JPH05343686A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to inhibit the generation of a punch through even if the channel length of a semiconductor device is shortened and to make it possible to realize the stable operation of an element. CONSTITUTION:A buried oxide film 3 is formed in the surface of a P-type silicon substrate 2. A silicon layer 4 is formed on the surface of the film 3. The layer 4 is constituted of a channel formation region 4a and one pair of source and drain regions 4b, which are formed holding the region 4a between them. A gate electrode 6 is formed on the surface of the region 4a via a gate dielectric thin film 5. Moreover, a substrate gate electrode 1 is formed under the region 4a and in the surface of the substrate 2 via the film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS (Metal Oxide Semiconductor) formed in a semiconductor layer on an insulating substrate.
inductor) field effect transistor (hereinafter, referred to as SOI-
The present invention relates to a semiconductor device including a MOSFET) and a manufacturing method thereof.

[0002]

2. Description of the Related Art First, the structure of a conventional SOI-MOSFET will be described.

FIG. 12 is a plan view schematically showing the structure of a conventional SOI-MOSFET. 13 is a sectional view taken along the line CC of FIG. 12, and FIG.
It is sectional drawing which follows the D line.

Mainly referring to FIGS. 12 and 13A, a buried oxide film (Si) is formed on the surface of silicon substrate 102.
O ₂ ) 103 is formed. This buried oxide film 103
A silicon layer 104 is formed in an island shape on the surface of the. A channel formation region 104 is formed in the silicon layer 104.
a and a pair of source / drain regions 104b are formed. The pair of source / drain regions 104b are formed with a space therebetween so as to sandwich the channel formation region 104a. The channel formation region 104a is
For example, it has a relatively low p-type impurity concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ . The source and drain regions 104b has, for example, a relatively high n-type impurity concentration of ^{10 1 9 ~10 2 1 / cm} 3. A gate electrode 106 is formed on the channel formation region 104a via a gate dielectric thin film 105. These silicon layer 104, gate dielectric thin film 105, and gate electrode 10
6 forms a transistor. An interlayer insulating film 107 is formed on the surface of the buried oxide film 103 so as to cover the transistor. A contact hole 107a is formed in the interlayer insulating film 107. From the contact hole 107a, the source / drain region 1
A part of the surface of 04b is exposed. A low-resistance wiring layer 108 is formed on the surface of the interlayer insulating film 107 so as to be in contact with the exposed surface of the source / drain region.

Referring to FIGS. 12 and 13B, gate electrode 106 is formed on the surface of buried oxide film 103 so as to vertically traverse silicon layer 104 formed in an island shape. Interlayer insulating film 107 is formed on the surface of buried oxide film 103 so as to cover silicon layer 104 and gate electrode 106. A contact hole 107b is formed in the interlayer insulating film 107. A part of the surface of the gate electrode 106 is exposed from the contact hole 107b. A low-resistance wiring layer 109 is formed in contact with the exposed surface of the gate electrode 106.

Next, the operating principle of the MOSFET will be described.

With reference to FIG. 13A, the gate electrode 10
A positive voltage is applied to 6. At this time, n-type carriers (electrons) are induced in the upper layer portion of the channel forming region 104a composed of the p-type region. That is, the channel formation region 1
The surface of 04a is inverted and the source / drain region 104b is formed.
And the same electric form. This allows a current to flow between the source / drain regions. Further, the n-type carrier concentration induced in the upper layer portion of the channel formation region 104a changes depending on the voltage applied to the gate electrode 105. Therefore, the amount of current flowing through the source / drain region 104b can be controlled by the voltage applied to the gate electrode 105. The MOSFET operates in this way.

In the SOI-MOSFET in which this MOSFET is formed on the SOI substrate, the distance between the wiring layer 108 and the silicon substrate 102 is increased by the thickness of the buried oxide film 103. Therefore, the capacitance between the wiring and the substrate, that is, the so-called wiring capacitance is reduced, and the operation speed of the circuit is increased. Further, the MOS transistor is completely insulated from other transistors by the insulating film. Therefore, it is possible to obtain a highly reliable device in which soft errors and latch-up are suppressed. These are SOI-MOSFETs
Is a feature and an advantage over a transistor formed on ordinary bulk silicon.

[0009]

[Problems to be Solved by the Invention] Conventional SOI-MOS
Since the FET is configured as described above, punch-through phenomenon occurs when the channel length becomes submicron. The punch-through phenomenon is a phenomenon in which the drain depletion layer largely penetrates below the gate electrode, and the charge of the depletion layer below the gate electrode cannot be controlled by the force of the gate electrode. When this punch-through phenomenon occurs, current flows between the source and drain even in the off state where the gate is closed, and normal transistor operation cannot be maintained.

SOI capable of suppressing this punch-through phenomenon
-The structure of the MOSFET is IEEE, IEDM199
1, pp. 683-686. The structure and manufacturing method of the SOI-MOSFET shown in this prior art document will be described below.

FIG. 14 shows S shown in the above-mentioned prior art document.
It is a top view which shows schematic structure of OI-MOSFET. Further, FIG. 15A is a sectional view taken along the line EE of FIG.
FIG.15 (b) is sectional drawing which follows the FF line.

Referring mainly to FIGS. 14 and 15A, a buried oxide film 203 is formed on the surface of silicon substrate 202. The buried oxide film 203 is the oxide film 203.
a and the second gate dielectric thin film 203b.
In the buried oxide film 203, the second gate electrode 201 is formed.
Are formed. A silicon layer 204 is formed in an island shape on the surface of the buried oxide film 203. In this silicon layer 204, a channel formation region 204a and a pair of source / drain regions 204b are formed. The pair of source / drain regions 204b are formed so as to be spaced from each other with the channel formation region 204a interposed therebetween. The channel forming region 204a is formed, for example, of 10 ¹⁵
It has a relatively low p-type impurity concentration of -10 ¹⁷ / cm ³ . The source and drain regions 204b has, for example, a relatively high n-type impurity concentration of ^{10 1 9 ~10 2 1 / cm} 3. On the surface of the silicon layer 204, the first gate electrode 20 is provided via the first gate dielectric thin film 205 so as to face the channel formation region 204a.
6 is formed. An interlayer insulating film 207 is formed so as to cover the silicon layer 204 and the first gate electrode 206. A contact hole 207a is formed in the interlayer insulating film 207. A part of the surface of the source / drain region 204b is exposed from the contact hole 207a. The low resistance semiconductor layer 2 is in contact with the exposed surface of the source / drain region 204b.
08 is formed on the surface of the interlayer insulating film 207.

Referring to FIGS. 14 and 15B, the second gate electrode 201 extends under the island-shaped silicon layer 204 via the second gate dielectric thin film 203b. Further, the first gate electrode 206 extends so as to extend vertically on the surface of the silicon layer 204 via the first dielectric thin film 205. The first gate electrode 201 and the second gate electrode 206 are in direct contact with each other. Therefore, the first gate electrode 201 and the second gate electrode 206 are electrically connected. An interlayer insulating film 207 is formed so as to cover the second gate electrode 206 and the silicon layer 204. In the interlayer insulating film 207, the contact hole 20
7b is formed. This contact hole 207b
From, a part of the surface of the first gate electrode 206 is exposed. A wiring layer 209 having a low resistance is formed on the surface of the interlayer insulating film 207 so as to be in contact with the exposed surface of the first gate electrode 206.

Next, a method of manufacturing this SOI-MOSFET will be described.

16 to 24 show the above SOI-MOS.
It is a schematic sectional drawing which follows the EE line of FIG. 14 which shows the manufacturing method of FET in process order.

Referring to FIG. 16, a second gate dielectric thin film 203b is formed relatively thin on the surface of silicon substrate 204. This second gate dielectric thin film 203b
A second gate 201 is formed on the surface of the.

Referring to FIG. 17, the second gate dielectric thin film 203b is formed so as to cover the second gate electrode 201.
An oxide film 203a is formed on the surface of the.

Referring to FIG. 18, the stepped surface of oxide film 203a is planarized by polishing. The flattened oxide film 203a and the second gate dielectric thin film 203
The buried oxide film 203 is formed by b.

Referring to FIG. 19, the silicon substrate 20 is formed on the surface of the buried oxide film 203 by bonding the wafers.
2 are pasted together.

Referring to FIG. 20, the bonded wafer is turned over.

With reference to FIG. 21, by this inversion, the silicon layer 204 which has become the upper surface is thinned by polishing.

Referring to FIG. 22, silicon layer 204 is formed in an island shape. This island-shaped silicon layer 20
A first dielectric thin film 205 is formed on the surface of No. 4. A first gate electrode 206 is formed on the surface of the first dielectric thin film 205 at a position facing the second gate electrode 201. Impurities are implanted into the silicon layer 204 using the first gate electrode 206 as a mask. By this implantation, a pair of source / drain regions 204b having a space therebetween are formed in the silicon layer 204. A channel formation region 204a is formed between the pair of source / drain regions 204b.

Referring to FIG. 23, buried oxide film 2 is formed so as to cover silicon layer 204 and first gate electrode 206.
An interlayer insulating film 207 is formed on the surface of 03. A contact hole 207a is formed in the interlayer insulating film 207. A part of the surface of the source / drain region 204 is exposed from the contact hole 207a.

Referring to FIG. 24, the interlayer insulating film 2 is contacted with the exposed surface of the source / drain region 204b.
A low resistance wiring layer 208 is formed on the surface of 07.

As described above, the SOI-MOSFET shown in the above-mentioned prior art document is manufactured.

SOI-MO shown in the above-mentioned prior art documents
The SFET has a double gate structure of a first gate electrode 206 and a second gate electrode 201. The advantages of the SOI-MOSFET having this double gate structure will be described below.

Referring to FIG. 13, in the case where there is only one gate for the pair of source / drain regions 104b, when the channel becomes short, the channel forming region 104a is deep (near the interface with the buried oxide film 103). At this point, the depletion layer due to the drain electric field extends and the potential rises. As a result, a current flows between the source and the drain even when the gate voltage is in the off state, and the controllability of the gate electrode 105 is lost, so-called punch-through phenomenon easily occurs. On the other hand, in the SOI-MOSFET having the double gate structure as shown in FIG. 15, the lower layer of the silicon layer 204 can be turned off by the second gate electrode 201 when the gate is off. Thus, by providing the lower electrode 201, the controllability of the lower layer of the channel formation region 204a can be significantly improved. Therefore, punch-through can be controlled even if the channel becomes short, and stable operation becomes possible.

Further, in the double gate structure, inversion layers can be formed on both upper and lower surfaces of the channel forming region 204a.
Therefore, the amount of current that can flow between the source and the drain is almost doubled, and the current driving capability is doubled. This also has a feature that the operating speed of the MOS transistor is improved.

However, the SOI-MOSFET having the double gate structure shown in FIG. 15 has the following drawbacks. Referring to FIG. 15, in general, M
The OS device can be regarded as a resistor whose resistance is changed by the gate voltage. That is, in the MOS device, power of P = IV is consumed. Since the consumed power is mainly heat, heat is generated in the MOS device. In bulk devices, the heat generated in MOS devices quickly escapes to the silicon substrate. Therefore, the temperature rise of the MOS device itself is slight. On the other hand, in the case of the SOI device, the element is completely covered with the insulating film. Therefore, the heat generated by the MOS device is less likely to be dissipated. If the heat is difficult to dissipate, the heat will scatter the carriers and reduce the mobility. As described above, if the heat is difficult to dissipate, the current driving capability may be reduced and the operating speed of the device may be reduced.

Further, in the method of manufacturing an SOI-MOSFET having a double gate shown in FIG. 15, after forming the second gate electrode 201, an insulating layer 203a is deposited and then planarized by a polishing process, and further a silicon layer is formed. It becomes a very complicated method of pasting.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to suppress the punch-through phenomenon even if the channel length becomes short and to realize stable element operation. Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[0032]

The semiconductor device of the present invention comprises:
The semiconductor substrate includes a semiconductor substrate, a first insulating layer, a semiconductor layer, a pair of source / drain regions, a gate electrode, and a conductive region. The semiconductor substrate has a main surface and is of the first conductivity type. The first insulating layer is formed on the main surface of the semiconductor substrate. The semiconductor layer is formed on the first insulating layer and has a first main surface facing the first insulating layer and a second main surface facing the first main surface. A pair of sauces
The drain regions are formed in the semiconductor layer so as to be spaced from each other with the channel region formed on the second main surface of the semiconductor layer interposed therebetween. The gate electrode is formed on the channel region with the second insulating layer interposed. The conductive region is formed on the main surface of the semiconductor substrate with the first insulating layer interposed below the region of the first main surface of the semiconductor layer facing the channel region. The conductive region is of the second conductivity type.

In the method of manufacturing a semiconductor device of the present invention, the first insulating layer is formed on the main surface of the first conductivity type semiconductor substrate. A semiconductor layer having a first main surface facing the first insulating layer and a second main surface facing the first main surface is formed on the first insulating layer. A conductive region of the second conductivity type is formed on the main surface of the semiconductor substrate. A second insulating layer is formed on the second main surface of the semiconductor layer. A gate electrode is formed on the second insulating layer so as to face the conductive region. A pair of source / drain regions are formed in the semiconductor layer so as to be spaced from each other with the region of the semiconductor layer facing the gate electrode interposed therebetween.

[0034]

The semiconductor device of the present invention has the gate electrode and the conductive region. The gate electrode and the conductive region are formed above and below the region sandwiched by the pair of source / drain regions. That is, it has a double gate structure. Therefore, the controllability of both the upper and lower surfaces of the region sandwiched by the pair of source / drain regions is significantly improved. Therefore, the punch through phenomenon can be suppressed.

The conductive region is formed on the main surface of the semiconductor substrate. Generally, a semiconductor substrate is made of silicon or the like, and its thermal conductivity is higher than that of an insulating film. Therefore, the heat generated by the device is dissipated relatively well through the first insulating film. Therefore, carrier scattering is suppressed, and a decrease in mobility is prevented. Therefore,
The current driving capability is also improved, and the influence on the operating speed of the device is relatively small.

In the method of manufacturing the semiconductor device of the present invention, the conductive region is formed on the main surface of the semiconductor substrate by, for example, the ion implantation method. Therefore, compared with the conventional process of forming an SOI-MOSFET having a double-gate structure having a structure in which a lower electrode is formed in an insulating film, complicated processes such as polishing and sticking of a silicon layer are unnecessary. Becomes Therefore, it is possible to greatly simplify the manufacturing process.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows S in the first embodiment of the present invention.
It is a top view which shows the structure of OI-MOSFET roughly. 2A is a sectional view taken along the line AA of FIG.
FIG. 2B is a sectional view taken along the line BB.

First, referring to FIGS. 1 and 2A, a buried oxide film 3 is formed on the surface of a p-type silicon substrate 2. A silicon layer 4 is formed as a semiconductor layer on the surface of the buried oxide film 3. This structure is an SOI structure, and typical thicknesses of the silicon layer 4 and the buried oxide film 3 are 100 nm and 500 nm, respectively. Also, as transistors are miniaturized, these film pressures become thinner,
For example, the 0.1 μm design rule requires the silicon layer 4 to have a thickness of about 20 nm or less. In the silicon layer 4, a channel forming region 4a and a pair of sources
The drain region 4b is formed. The pair of source / drain regions 4b are formed so as to be spaced from each other with the channel forming region 4a interposed therebetween. The channel forming region 4a has, for example, 10 ¹⁶ to 10 ¹⁷ / cm.
^{It has} a relatively low p-type impurity concentration of ³ . Further, the source / drain region 4b has, for example, 10 ¹⁹ to 10 ⁹
It has a relatively high n-type impurity concentration of ^{2 1} / cm ^3. A gate electrode 6 is formed on the surface of the channel forming region 4a via a gate dielectric thin film 5. An interlayer insulating film 7 is formed on the surface of buried oxide film 3 so as to cover the surfaces of gate electrode 6 and silicon layer 4. The interlayer insulating film 7 has a contact hole 7a.
Are formed. From this contact hole 7a,
Part of the surface of the source / drain region 7a is exposed.
A wiring layer 8 made of a metal layer such as aluminum (Al) is formed so as to be in contact with the exposed surface of the source / drain region 7a.

The above construction is the same as the above-mentioned conventional example, and the present example is different from the above-mentioned conventional example in the following points.
In the SOI-MOSFET according to the first embodiment of the present invention, the substrate gate electrode 1 is formed on the surface of the silicon substrate 2. The substrate gate electrode 1 is formed at a position facing the channel forming region 4a. Substrate gate electrode 1 has an n-type impurity concentration of, for example, 10 ¹⁶ to 10 ²⁰ / cm ³ .

With reference to FIGS. 1 and 2B, the substrate gate electrode 1 is formed so as to extend vertically below the island-shaped silicon layer 4. Further, the gate electrode 6 is formed so as to cross the silicon layer 4 vertically. An interlayer insulating film 7 is formed so as to cover the surfaces of the gate electrode 6 and the silicon layer 4. The substrate gate electrode 1 and the gate electrode 6 are electrically connected by the gate wiring layer 9 provided so as to penetrate the buried oxide film 3, the gate electrode 6 and the interlayer insulating film 7. Due to the gate wiring layer 9, a bias to the gate electrode 6 is simultaneously applied to the substrate gate electrode 1.

Since the n-type substrate gate electrode 1 has a conductivity type opposite to that of the p-type silicon substrate 1 and a positive bias is applied, the n-type substrate gate electrode 1 always has a reverse bias with respect to the silicon substrate 1. Therefore, the regions of the substrate gate electrode 1 and the silicon substrate 2 are p
-N will be separated. Therefore, the substrate gate electrode 1 and the silicon substrate 2 are electrically completely separated. The substrate gate electrode 1 can form a channel below the channel formation region 4a in synchronization with the gate electrode 6.

Next, a manufacturing method according to the first embodiment of the present invention will be described.

FIGS. 3 to 7 are sectional views (a) taken along the line AA of FIG. 1 showing a method for manufacturing an SOI-MOSFET in the first embodiment of the present invention in the order of steps, and BB of FIG. It is sectional drawing (b) which follows the line. First, referring to FIGS. 3A and 3B, oxygen ions are implanted into the surface of the silicon substrate 2,
Next, SI that recovers the crystallinity by high temperature annealing treatment
The SOI substrate is formed by the MOX method. As conditions, oxygen ions are set to 200 keV, 4 × 10 ¹⁷ / cm ²
And then heat-treated at 1300 ℃, it is about 800Å
Buried oxide film 3 and a silicon layer 4 of about 4000 Å are formed. Next, the silicon layer 4 is thinned to a thickness of about 500Å. In addition, when the wafer direct bonding method is used,
It is also possible to form the embedded oxide film 3 having an extremely thin thickness of about 0Å.
After forming the SOI substrate, the substrate gate electrode 1 is formed by, for example, the ion implantation method. When the bonding method is used, it is possible to previously form the substrate gate electrode 1 before bonding and then bond them.

Referring to FIGS. 4A and 4B, the silicon layer 4 is processed into an island shape. Silicon layer 4 by thermal oxidation
A gate dielectric thin film 5 is formed on the surface of the. Reduced pressure C
Polysilicon containing phosphorus is deposited on the entire surface by the VD method. Photolithography and anisotropic etching are performed on the deposited polysilicon. As a result, the gate electrode 6 made of polysilicon is formed. A pair of source / drain regions 4b are formed in the silicon layer 4 by an ion implantation method using the gate electrode 6 as a mask.
A channel formation region 4a is formed in a region sandwiched by the pair of source / drain regions 4b. The channel formation region 4a is located between the substrate gate electrode 1 and the gate electrode 6.

Referring to FIGS. 5A and 5B, an interlayer insulating film 7 is formed on the surface of buried oxide film 3 so as to cover the surfaces of gate electrode 6 and silicon layer 4. A resist 11 is applied on the surface of the interlayer insulating film 7. The resist 11 has a contact pattern 1 formed by exposure processing.
1a is formed. Using this resist 11 as a mask,
The interlayer insulating film 7 is etched. By this etching, the contact hole 7a is formed in the interlayer insulating film 7. A part of the surface of the source / drain region 4b is exposed from the contact hole 7a.

Referring to FIGS. 6A and 6B, the photoresist 11 is removed. Then, the photoresist 12 is applied to the entire surface. A contact hole forming pattern 12a is formed on the photoresist 12 by an exposure process. Using this resist 12 as a mask, the interlayer insulating film 7, the gate electrode 6 and the buried oxide film 3 are successively subjected to etching treatment. As a result, a contact hole 15 is formed so as to penetrate through the interlayer insulating film 7, the gate electrode 6 and the buried oxide film 3. A part of the surface of the substrate gate electrode 1 is exposed from the contact hole 15.

Referring to FIGS. 7 (a) and 7 (b), wiring layers 8 and 9 of low resistance metal made of aluminum (Al) or the like are formed so as to come into contact with the exposed surfaces through contact holes 7a and 15, respectively. It is formed.

The SOI-MOSFET according to the first embodiment of the present invention is manufactured as described above.

Next, the SO in the first embodiment of the present invention
The current driving capability of the I-MOSFET will be described.

FIG. 8A shows the drain voltage V _D -drain current I _D characteristics of the conventional transistor having the single-sided gate structure shown in FIG. Also, FIG.
(B), the drain voltage V _D of the transistor in the first embodiment of the present invention - illustrates the drain current I _D characteristics. The experimental condition is that the channel length is 0.3μ.
m, the channel width is 10 μm, and the gate is 1 to 5 V
It was measured by applying a voltage V _{G in} the range. As is apparent from FIGS. 8A and 8B, in the conventional example, when the short channel of 0.3 μm is used, the operating breakdown voltage deteriorates due to the punch-through phenomenon, and unstable transistor operation is realized. .. On the other hand, in this example, it is understood that punch-through is suppressed even when the channel becomes a short channel of 0.3 μm, and the current driving capability is also doubled.

As described above, in the SOI-MOSFET according to the first embodiment of the present invention, it is possible to improve the current driving capability and to operate the element stably.

Further, in the manufacturing method, complicated steps are unnecessary, and the manufacturing can be easily performed.

The SOI-MOSFET of the present invention is not limited to the configuration of the first embodiment, but may be any of those shown in FIGS. 9, 10 and 1.
The structure shown in the second, third and fourth embodiments shown in FIG.

The second, third and fourth embodiments will be described below.

FIG. 9 shows S in the second embodiment of the present invention.
It is sectional drawing which follows the BB line of FIG. 1 which shows schematic structure of OI-MOSFET. Referring to FIG. 9, S of the second embodiment
The structure of the OI-MOSFET is almost the same as that of the first embodiment. However, substrate gate electrode 1 and gate electrode 2
6 and the wiring layer 28 have different contact configurations. That is, the substrate gate electrode 1 is formed on the surface of the silicon substrate 2. A buried oxide film 3 is formed on the surface of the silicon substrate 2. A gate contact hole 27a is formed in this buried oxide film 3. A part of the surface of the substrate gate electrode 1 is exposed from the gate contact hole 27a. On the surface of the buried oxide film 3,
A silicon layer 4 is formed. The gate electrode 26 is formed so as to extend vertically over the silicon layer 4 through the gate dielectric thin film 5 and to be in contact with the exposed substrate gate electrode 1.
Are formed. Interlayer insulating film 7 is formed so as to cover gate electrode 26 and silicon layer 4.
The gate contact hole 27b is formed in the interlayer insulating film 7.
Are formed. This gate contact hole 27b
From, part of the surface of the gate electrode 26 is exposed. A wiring layer 28 is formed so as to be in contact with the exposed surface of the gate electrode 26.

Next, SO in the third embodiment of the present invention
The configuration of the I-MOSFET will be described.

FIG. 10 is a sectional view taken along the line BB of FIG. 1 showing a schematic structure of the SOI-MOSFET in the third embodiment of the present invention. Referring to FIG. 10, the structure of the SOI-MOSFET in the third embodiment is almost the same as that of the first embodiment. However, the contact configurations of the substrate gate electrode 1, the gate electrode 36, and the wiring layer 38 are different. That is, the substrate gate electrode 1 is formed on the surface of the silicon substrate 2. A buried oxide film 3 is formed on the surface of the silicon substrate 2. A silicon layer 4 is formed on the surface of the buried oxide film 3. A gate electrode 36 is formed through the gate dielectric thin film 5 so as to extend vertically on the silicon layer 4. This gate electrode 3
An interlayer insulating film 7 is formed so as to cover 6 and the silicon layer 4. From the interlayer insulating film 7 to the buried oxide film 3,
A gate contact hole 37 is formed. A part of the surface of the substrate gate electrode 1 is exposed from the gate contact hole 37. The gate contact hole 37 is composed of a first contact hole 37a formed in the buried oxide film 3 and a second contact hole 37b formed in the interlayer insulating film 7. A part of the surface of the gate electrode 36 is exposed from the second contact hole 37b. A first contact hole 37a is formed along the exposed side surface of the gate electrode 36. Substrate gate electrode 1 exposed from this contact hole 37
Wiring layer 38 is formed so as to be in contact with the surface of.

Next, SO in the fourth embodiment of the present invention
The configuration of the I-MOSFET will be described.

FIG. 11 is a sectional view taken along the line BB of FIG. 1 showing the schematic structure of the SOI-MOSFET in the fourth embodiment of the present invention. Referring to FIG. 11, the fourth embodiment of the present invention
The configuration of the SOI-MOSFET in the embodiment of
This is almost the same as the embodiment described above. However, the substrate gate electrode 1,
The contact configurations with the gate electrode 6 and the wiring layer 48 are different. That is, the substrate gate electrode 1 is formed on the surface of the silicon substrate 2. Also silicon substrate 2
A buried oxide film 3 is formed on the surface of the. A silicon layer 4 is formed on the surface of the buried oxide film 3. A gate electrode 6 is formed on the surface of the silicon layer 4 so as to vertically cross the silicon layer 4 via a gate dielectric thin film 5. An interlayer insulating film 7 is formed so as to cover the gate electrode 6 and the silicon layer 4. A gate contact hole 15 is provided so as to penetrate through interlayer insulating film 7, gate electrode 6 and buried oxide film 3. A part of the surface of the substrate gate electrode 1 is exposed from the gate contact hole 15. As described above, in order to expose the surface of the substrate gate electrode 1, it is necessary to penetrate the three layers of the buried oxide film 3, the gate electrode 6 and the interlayer insulating film 7. Therefore, the depth of the gate contact hole 15 becomes relatively deep. Therefore, when the wiring layer is formed by the sputtering method or the like, the wiring layer may be broken on the side surface of the gate contact hole 15. If such a disconnection occurs, the transistor may not operate. Therefore, the gate contact hole 15 is filled with the selective tungsten 50 or the like. As a result, the connection between the layers becomes good, and the performance of the transistor can be improved. In addition to the selective tungsten or the epitaxial silicon that selectively grows on the surface of silicon (Si), a film is formed on the entire surface by the CVD method and then only the gate contact hole 15 remains in the burying. There is a method to etch back. The wiring layer 48 is formed so as to be electrically connected to the selective tungsten 50 thus formed.

In the first to fourth embodiments, the NMOS-FET formed on the p-type substrate has been described.
It goes without saying that the PMOS-FET also has the same effect if it is formed on the n-type substrate so that the conductivity type is opposite to that of the NMOS. Further, the same effect can be obtained by providing a well instead of the substrate and fixing the voltage.

Further, even in the CMOS structure in which the NMOS and the PMOS are mixed, the same effect can be obtained if at least one of the NMOS and the PMOS has the structure of this embodiment.

Although silicon is used as the semiconductor in the above embodiment, germanium (Ge) and gallium arsenide (GaA) are used.
It goes without saying that the same effect can be obtained by using other semiconductor materials such as s).

[0064]

The semiconductor device of the present invention has a gate electrode and a conductive region. The gate electrode and the conductive area are
It is formed above and below the channel formation region sandwiched between the pair of source / drain regions. That is, it has a double gate structure. Therefore, it is possible to control the upper layer and the lower layer of the channel formation region. Therefore, it is possible to suppress the punch-through phenomenon and also to improve the current driving capability.

The conductive region is formed on the main surface of the semiconductor substrate. Generally, a semiconductor substrate is made of silicon or the like, and its thermal conductivity is higher than that of an insulating film. Therefore, the heat generated by the device is dissipated relatively well through the first insulating film. Therefore, the current driving capability is improved, and the influence on the operating speed of the device is relatively small.

In the method of manufacturing the semiconductor device of the present invention, the conductive region is formed on the main surface of the semiconductor substrate by, for example, the ion implantation method. Therefore, complicated steps such as polishing and sticking of a silicon layer can be omitted. Therefore, the manufacturing method can be simplified.

[Brief description of drawings]

FIG. 1 is an SOI-MOS according to a first embodiment of the present invention.
It is a top view which shows the structure of FET schematically.

2 is a cross-sectional view (a) taken along line AA of FIG. 1, B of FIG.
It is sectional drawing (b) which follows the -B line.

FIG. 3 is an SOI-MOS according to a first embodiment of the present invention.
A- in FIG. 1 schematically showing a first step of the method for manufacturing the FET.
It is sectional drawing (a) which follows the A line, and sectional drawing (b) which follows the BB line.

FIG. 4 is a SOI-MOS according to a first embodiment of the present invention.
A- of FIG. 1 schematically showing a second step of the method for manufacturing the FET.
It is sectional drawing (a) which follows the A line, and sectional drawing (b) which follows the BB line.

FIG. 5 is an SOI-MOS according to the first embodiment of the present invention.
A- of FIG. 1 schematically showing a third step of the method for manufacturing the FET.
It is sectional drawing (a) which follows the A line, and sectional drawing (b) which follows the BB line.

FIG. 6 is an SOI-MOS according to the first embodiment of the present invention.
A- in FIG. 1 schematically showing a fourth step of the method for manufacturing the FET.
It is sectional drawing (a) which follows the A line, and sectional drawing (b) which follows the BB line.

FIG. 7 is an SOI-MOS according to the first embodiment of the present invention.
A- in FIG. 1 schematically showing a fifth step of the method for manufacturing the FET.
It is sectional drawing (a) which follows the A line, and sectional drawing (b) which follows the BB line.

FIG. 8 is a diagram showing a relationship between a drain voltage V _D and a drain current I _D in a conventional example (a) having a single-sided gate structure and a first example (b) of the present invention having a double gate structure.

FIG. 9 is an SOI-MOS according to a second embodiment of the present invention.
It is sectional drawing which follows the BB line of FIG. 1 which shows the structure of FET roughly.

FIG. 10 is an SOI-MO according to a third embodiment of the present invention.
It is sectional drawing which follows the BB line of FIG. 1 which shows the structure of SFET roughly.

FIG. 11 is an SOI-MO according to a fourth embodiment of the present invention.
It is sectional drawing which follows the BB line of FIG. 1 which shows the structure of SFET roughly.

FIG. 12 is a plan view schematically showing a configuration of a conventional SOI-MOSFET.

13 is a cross-sectional view (a) taken along the line CC of FIG. 12, FIG.
It is sectional drawing (b) which follows the DD line of FIG.

FIG. 14: SOI-MOSFE shown in the prior art document
It is a top view which shows the structure of T roughly.

15 is a sectional view (a) taken along the line EE of FIG. 14, FIG.
4 is a sectional view (b) taken along line FF of FIG.

FIG. 16: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing the first step of the manufacturing method of T.
It is sectional drawing which follows the line.

FIG. 17: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing the second step of the manufacturing method of T.
It is sectional drawing which follows the line.

FIG. 18: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing a third step of the manufacturing method of T.
It is sectional drawing which follows the line.

FIG. 19: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing a fourth step of the manufacturing method of T
It is sectional drawing which follows the line.

FIG. 20: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing a fifth step of the manufacturing method of T.
It is sectional drawing which follows the line.

FIG. 21: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing a sixth step of the manufacturing method of T
It is sectional drawing which follows the line.

FIG. 22: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing the seventh step of the method for manufacturing T.
It is sectional drawing which follows the line.

FIG. 23: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing an eighth step of the manufacturing method of T.
It is sectional drawing which follows the line.

FIG. 24: SOI-MOSFE shown in the prior art document
FF of FIG. 14 schematically showing a ninth step of the manufacturing method of T
It is sectional drawing which follows the line.

[Explanation of symbols]

 1 substrate gate electrode 2 silicon substrate 3 buried oxide film 4 silicon layer 4a channel formation region 4b source / drain region 5 gate dielectric thin film 6 gate electrode

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type having a main surface, a first insulating layer formed on the main surface of the semiconductor substrate, and a first insulating layer formed on the first insulating layer, A semiconductor layer having a first main surface facing the first insulating layer, a second main surface facing the first main surface, and a channel region formed on the second main surface of the semiconductor layer. A pair of source / drain regions formed in the semiconductor layer so as to have a space therebetween, a gate electrode formed on the channel region with a second insulating layer interposed therebetween, and in the channel region. A semiconductor device, comprising: a second conductive type conductive region formed on the main surface of the semiconductor substrate with the first insulating layer interposed below the region of the first main surface of the semiconductor layer facing each other. .. 2. A step of forming a first insulating layer on a main surface of a semiconductor substrate of a first conductivity type, and a first surface facing the first insulating layer on the first insulating layer. Forming a semiconductor layer having a main surface of the semiconductor substrate and a second main surface opposite to the first main surface of the semiconductor substrate; forming a conductive region of a second conductivity type on the main surface of the semiconductor substrate; Forming a second insulating layer on the second main surface of the layer; forming a gate electrode on the second insulating layer so as to face the conductive region; Forming a pair of source / drain regions in the semiconductor layer so as to be spaced from each other with the region of the semiconductor layer facing each other sandwiched therebetween.