JP2003078141A - Semiconductor device and its manufacturing method as well as portable electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a drive current of a field effect transistor by utilizing a substrate bias effect without using a DTMOS in which a gate current flows at an on time. SOLUTION: A semiconductor device comprises a first conductivity type deep well region 121 formed on a semiconductor substrate 111, a second conductivity type shallow well region 123 formed on the deep well region, a semiconductor film formed on the shallow region via a first insulating film 142, a gate electrode 143 formed on the semiconductor film via a second insulating film 141, and an element isolation region 131 having a deeper depth than the depth of a junction between the deep well region and the shallow well region. A channel region 161 is formed on a part covered with a gate electrode of the semiconductor film, a first conductivity type source region 151 and drain region 152 are formed on a part not covered with a gate electrode, and the shallow well region is electrically connected to the gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a portable electronic device. More specifically,
The present invention relates to a semiconductor device including a field effect transistor that increases a drive current by utilizing a substrate bias effect, a manufacturing method thereof, and a portable electronic device using the semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a MOSFE capable of low voltage driving, low power consumption, and high speed operation utilizing the substrate bias effect generated by changing the bias of a well region.
T (Metal Oxide Semiconductor Field Effect Transis
As a technology, a dynamic threshold operating transistor (hereinafter referred to as DTMOS) using a bulk substrate has been proposed (JP-A-10-22462, Novel Bulk Thr).
eshold Voltage MOSFET (B-DTMOS) with Advanced Isola
tion (SITOS) and Gate to Shallow Well Contact (SSS-
C) Processes for Ultra Low Power Dual Gate CMOS,
H. Kotaki et al., IEDM Tech. Dig., P459, 1996).

The operating principle of the N-channel type DTMOS will be described below with reference to FIG. In addition, P-channel type DTM
The OS performs the same operation by reversing the polarity. Figure 1
2, 911 is a silicon substrate, 921 is an N-type deep well region, 923 is a P-type shallow well region, 931 is an element isolation region, 951 is a source region, 952 is a drain region, 941 is a gate insulating film, and 943 is 943. It is a gate electrode. Although not shown, the DTMOS has a gate electrode 943 and P
The feature is that it is electrically connected to the shallow well region 923 of the mold.

In the N-type MOSFET, when the potential of the gate electrode 943 is at the low level (when off), the potential of the P-type shallow well region 923 is also at the low level, and the effective threshold value of the normal MOSFET is It is no different from the case Therefore, the off-current value (off-leakage) is the same as in the case of a normal MOSFET.

On the other hand, when the potential of the gate electrode is at a high level (when ON), the potential of the P-type shallow well region 923 also becomes a high level, the effective threshold value is lowered by the substrate bias effect, and the drive current is reduced. It is increased as compared with the case of a normal MOSFET. Therefore, a large drive current can be obtained while maintaining a low leak current with a low power supply voltage. Therefore, a MOSFET with low power consumption and low power consumption is realized.

[0006]

However, in the above-mentioned conventional DTMOS, since the gate electrode and the well region are electrically connected, a problem peculiar to the DTMOS is that a gate current flows when turned on. was there.

The influence of the gate current will be considered with reference to FIG. FIG. 13 is a diagram showing the characteristics of the drain current (Id) (vertical axis left side) and the gate current (Ig) (vertical axis right side) versus gate voltage (Vg) (horizontal axis) of the N-channel type DTMOS. It can be seen that as the gate voltage increases, the gate current increases exponentially. In the example of the N-channel type DTMOS shown in FIG. 13, the gate current at a gate voltage of 0.5 V is comparable to the off current (Id at Vg = 0 V). Due to this gate current, the upper limit of the power supply voltage of the CMOS circuit using the DTMOS is limited to about 0.6 V at most. Therefore, the magnitude of the substrate bias effect to be obtained is also limited, which hinders further increase in drive current.

The present invention has been made to solve the above problems, and an object thereof is to increase the substrate bias effect while suppressing the gate current within an allowable range to obtain a high driving current, which enables high speed operation. It is to provide a semiconductor device and a manufacturing method thereof. Further, it is an object of the present invention to provide a portable information device having such a semiconductor device.

[0009]

In order to achieve the above object, a semiconductor device according to a first invention is a semiconductor device, a deep well region of a first conductivity type formed on the semiconductor substrate, and a first well of the first conductivity type. The second formed on the deep well region of the conductivity type
A conductive type shallow well region, a semiconductor film formed on the second conductive type shallow well region via a first insulating film, and a semiconductor film formed on the semiconductor film via a second insulating film. A gate electrode; an element isolation region having a depth deeper than a junction depth between the first-conductivity-type deep well region and the second-conductivity-type shallow well region; A channel region is formed in a portion covered with a gate electrode, and a source region and a drain region of a first conductivity type are formed in a portion of the semiconductor film not covered by the gate electrode. The well region and the gate electrode are electrically connected.

In this specification, the first conductivity type means P type or N type. The second conductivity type means N type when the first conductivity type is P type and P type when the first conductivity type is N type.

According to the above structure, a part of the semiconductor film becomes the channel region by being sandwiched between the gate electrode and the second well shallow region of the second conductivity type with the insulating film interposed therebetween. The gate electrode and the shallow well region of the second conductivity type are electrically connected. Therefore, the potential applied to the gate electrode to turn on the element is also transmitted to the shallow well region of the second conductivity type and lowers the potential of the channel region. Therefore, the substrate bias effect can be generated only when the device is in the ON state, and the effective threshold value can be lowered. Furthermore, since the second conductivity type shallow well region and the first conductivity type source region and drain region are separated by the first insulating film, almost no gate current flows. Therefore, the upper limit of the voltage value applied to the gate electrode can be significantly increased, and a larger substrate bias effect can be obtained to increase the drive current. Therefore, a semiconductor device that can operate at high speed is provided.

In one embodiment, the thickness of the semiconductor film sandwiched between the first insulating film and the second insulating film is 2-1.
It is characterized in that it is not more than 00 nm.

According to the above embodiment, the channel region is completely depleted even when the device is off. Therefore, the substrate bias effect works even in the subthreshold region below the threshold, and the subthreshold characteristic is improved. Therefore, the threshold value can be lowered without increasing the off-state current of the element, so that the power supply voltage can be lowered and power consumption can be reduced.

Further, one embodiment is characterized in that the potential is fixed in the deep well region of the first conductivity type.

According to the above-described embodiment, by fixing the potential of the deep well region, the potential of the deep well region changes with the change of the potential of the shallow well region, and the potential of the deep well region becomes unstable. Can be prevented. Therefore, it may affect the potential of other shallow well regions,
Punch-through between shallow well regions can be prevented.

Further, one embodiment is characterized in that the semiconductor film contains a metal element that promotes crystallization of an amorphous semiconductor by annealing.

According to the above embodiment, since the semiconductor film contains a metal element that promotes crystallization of the amorphous semiconductor by annealing, when the semiconductor film is crystallized by annealing, The direction of grain boundaries and the size of crystal grains can be controlled. Therefore, it is possible to easily suppress off-leakage or prevent deterioration of the drive current. In addition, if the size of the crystal grains is made sufficiently larger than the size of the device, a channel region substantially composed of a single crystal film can be realized, so that excellent characteristics such as low off-leakage and high drive current can be easily achieved at the same time. be able to.

The metal element is preferably at least one of nickel, cobalt, palladium and platinum. By specifically identifying these metal elements, the crystallization of the amorphous semiconductor and the control of the grain boundary direction can be efficiently performed.

A method of manufacturing a semiconductor device according to a second invention is the method of manufacturing a semiconductor device according to the first invention, wherein after the step of forming a second insulating film on the shallow well region of the second conductivity type is performed. Depositing a substantially amorphous semiconductor film on the entire surface of the semiconductor substrate, and selectively introducing a metal element that promotes crystallization of the amorphous semiconductor film into a part of the amorphous semiconductor film. And a step of crystallizing the amorphous semiconductor film into a polycrystalline semiconductor film or a substantially single crystal semiconductor film in at least a peripheral portion of a region into which the metal element is selectively introduced by annealing. Is characterized by.

According to the above procedure, the semiconductor film to be the channel region is formed by the step of depositing the amorphous semiconductor film, so that the film thickness can be easily made uniform.
Therefore, a double gate type field effect transistor having a small variation in characteristics is provided.

Furthermore, after selectively introducing a metal element that promotes crystallization of the amorphous semiconductor film into a part of the amorphous semiconductor film, the amorphous semiconductor film is crystallized by annealing. Therefore, it is possible to control the direction of grain boundaries and the size of crystal grains. Therefore, it is possible to easily suppress off-leakage or prevent deterioration of the drive current. In addition, if the size of the crystal grains is made sufficiently larger than the size of the device, a channel region substantially composed of a single crystal film can be realized, so that excellent characteristics such as low off-leakage and high drive current can be easily achieved at the same time. be able to.

In the semiconductor device manufacturing method of the second invention, it is preferable that the metal element that promotes crystallization of the amorphous semiconductor is at least one of nickel, cobalt, palladium and platinum. By specifically identifying these metal elements, the crystallization of the amorphous semiconductor and the control of the grain boundary direction can be efficiently performed.

Further, in one embodiment, in the semiconductor device of the first invention, a part of the source region and the drain region has a raised structure above a surface formed by the second insulating film. Is characterized by.

According to the above embodiment, the source region and the drain region have a raised structure, and the silicide formation is easy, so that the parasitic resistance of the source region and the drain region can be reduced. Therefore, it is possible to increase the drive current of the element and operate at high speed.

The portable electronic equipment of the third invention is characterized by including the above semiconductor device.

According to the third aspect, the LSI section of the portable electronic device can be speeded up, so that a highly functional portable electronic device is provided.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings.

The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Further, the semiconductor substrate may have a P-type or N-type conductivity. In each of the embodiments, an N-channel type element is mainly described, but a P-channel type element can be formed by reversing the conductivity types of impurities.
Of course, both conductivity type elements may be formed on the same substrate. (Embodiment 1) In the semiconductor device of Embodiment 1, the source / drain regions and the channel region are formed in the semiconductor thin film, so that the potential change in the shallow well region is transmitted to the channel region through the insulating film. It is the one. The semiconductor device according to the first embodiment will be described with reference to FIGS. 1 is a plan view of the semiconductor device according to the first embodiment, FIG. 2 is a sectional view taken along the section line AA ′ of FIG. 1, and FIG. 3 is a section line BB ′ of FIG. It is sectional drawing seen. The interlayer insulating film and the upper wiring are omitted in FIG. 1, and the upper wiring is omitted in FIGS. FIG. 4 is a conceptual diagram for explaining the operation principle of the semiconductor device according to the first embodiment. FIG. 5 and FIG. 6 explain the procedure for producing the semiconductor device according to the first embodiment.

First, the structure of the semiconductor device according to the first embodiment will be described with reference to FIGS.

An N type deep well region 121 is formed on the silicon substrate 111. A P-type shallow well region 123 is formed on the N-type deep well region 121. In the P-type shallow well region 123, an element isolation region 131 made of a silicon oxide film is formed around the entire periphery of the element and electrically isolated for each element.

On the P-type shallow well region 123, the first
A silicon oxide film 142 serving as an insulating film is formed. A gate electrode 143 is formed on the silicon oxide film 142 with a silicon film and a gate oxide film 141 serving as a second insulating film interposed therebetween. The silicon film is preferably a substantially single crystal silicon film or a polycrystalline silicon film having a very low grain boundary density, of which the part covered with the gate electrode 143 becomes the channel region 161, and the other part is the source. The region 151 or the drain region 152 is formed. The channel region 161 has a P-type conductivity type or is intrinsic.
The source region 151 and the drain region 152 are composed of n ⁺ diffusion layers.

As can be seen from FIGS. 1 and 3, a hole is opened in the gate-well connection region 144 in the gate electrode 143, and the P-type shallow well region 123 is exposed. A gate electrode contact hole 174 (not shown, metal is buried in the contact hole) is formed in the interlayer insulating film 171 so as to extend over the gate-well connection region 144 and the gate electrode. 143 and the P-type shallow well region 123 are electrically connected. Therefore, the potential applied to the gate electrode 143 is also transmitted to the P-type shallow well region 123, and the potential transmitted to the P-type shallow well region 123 changes the potential of the channel region 161 via the silicon oxide film 142. The substrate bias effect is generated.

Source region 151 and drain region 152
Contact holes 172 and 173 are provided on the top, respectively. Further, a P-type shallow well region 124 is formed on the P-type deep well region 121, and a well contact hole for fixing the potential of the P-type deep well region 121 is formed on the P-type shallow well region 124. 175 is provided.
By fixing the potential of the deep well region, it is possible to prevent the potential of the deep well region from changing and the potential of the deep well region becoming unstable due to the change of the potential of the shallow well region. Therefore, it is possible to affect the potential of the other shallow well regions and prevent punch-through between the shallow well regions. Although not shown, if the P-type shallow well region 124 is formed on the N-type deep well region,
A P-channel type element can be formed on the P-type shallow well region 124.

The operating principle of the semiconductor device of the first embodiment will be described with reference to FIG. FIG. 4 shows the section line C of FIG.
-C ', the gate electrode 143, the gate insulating film 141,
6 is an energy diagram of the channel region 161, the silicon oxide film 142, and the P-type shallow well region 124. FIG. 4A shows a state where the potential of the gate electrode is equal to the potential of the source region (OFF state).
(B) shows a state where a positive voltage is applied to the gate electrode (ON state). In FIG. 4, the influence of the drain electric field is not taken into consideration for simplicity.

When the transistor is in the off state shown in FIG. 4A, an electric field is generated due to the difference in work function between the gate electrode 143 and the channel region 161, and the channel region 161 is partially or entirely depleted. However, since there is almost no work function difference between the channel region 161 and the P-type shallow well region 123, there is almost no electric field.

On the other hand, when the transistor is in the ON state shown in FIG. 4B, the potential of the gate electrode 143 rises (moves downward in the energy diagram), so that the gate insulating film 141 in the channel region 161 is exposed. An inversion layer (channel) is formed in the contact area. Further, the potential of the P-type shallow well region 123 also rises, so that the potential (for electrons) of the channel region 161 is lowered. Therefore, the substrate bias effect occurs in the channel region 161, the threshold value of the transistor is substantially lowered, and the drive current is increased. When the potential of the P-type shallow well region 123 further rises, an inversion layer (channel) is also formed in the region of the channel region 161 in contact with the silicon oxide film 142. Therefore, two channels are formed in the channel region 161, and an operation similar to that of the double gate transistor is performed.

If a high dielectric material is used as the first insulating film instead of the silicon oxide film 142, the voltage applied to the first insulating film decreases, and the amount of decrease in the potential of the channel region 1261 increases correspondingly. Therefore, it is possible to more effectively generate the substrate bias and increase the drive current. As the high dielectric film, for example, an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a hafnium oxide film or the like can be used.

In the semiconductor device according to the first embodiment, the gate electrode and the shallow well region have the same potential as in the conventional DTMOS, so that the substrate bias effect is generated only when the transistor is in the ON state. Thus, the effective threshold value is lowered without increasing the off current. However, the semiconductor device according to the first embodiment affects the potential of the channel region through the insulating film (silicon oxide film 142) (the shallow well region and the channel region are capacitively coupled). Prior art DTMO
Different from S. Therefore, the gate electrode (ie,
No forward current flows from the shallow well region) to the source / drain regions. Therefore, it is possible to increase the power supply voltage (for example, 2 V) as compared with the case of the conventional DTMOS (0.6 V) and sufficiently increase the substrate bias effect. Therefore, a semiconductor device that can operate at high speed is provided.

By the way, the thickness of the channel region 161 is
It is preferable to make the channel region 161 sufficiently thin so that the channel region 161 is completely depleted even when the field effect transistor is off. In this case, the influence of the voltage applied to the gate electrode 143 and the P-type shallow well region 123 extends to the entire channel region even during the subthreshold operation of the field effect transistor. Therefore, the substrate bias effect works even in the subthreshold region below the threshold, and the subthreshold characteristic is improved. Specifically, the subthreshold coefficient (S value) at room temperature can obtain a value close to the theoretical limit of 60 mV / decade. In the field effect transistor having such an excellent S value, the threshold value can be lowered without increasing the off current, so that the power supply voltage can be lowered to reduce the power consumption. Further, even when the field effect transistor is off, the depletion layer derived from the gate electrode 143 and the P-type shallow well region 123 extends over the entire channel region, and the extension of the depletion layer derived from the drain region 152 is blocked. Therefore, the short channel effect is extremely effectively suppressed. When the field effect transistor is turned on, the potential of the central portion of the channel region further decreases (the substrate bias effect increases), so that a large drive current can be obtained. Therefore, it is possible to realize a field effect transistor in which a short channel effect is extremely effectively suppressed and a large drive current is obtained. Alternatively, the power supply voltage can be lowered to reduce the power consumption of the field effect transistor. When the field effect transistor is in the off state, the thickness of the depletion layer extending from the gate oxide film 141 side into the channel region 161 is, for example, about 100 n when the impurity concentration of the channel region 161 is 5 × 10 ¹⁶ cm ^−3.
m. Therefore, the thickness of the channel region 161 is 1
More preferably, it is not more than 00 nm. The thickness of the channel region 161 can be manufactured, and the thickness required for the channel region 161 to operate is 2 nm or more.

Next, the procedure for forming the semiconductor device of the first embodiment will be described with reference to FIGS. FIG. 5 and FIG. 6 are plan views of the element in the process of preparation as seen from above.

First, a deep well region 121 and shallow well regions 123, 12 are formed in the semiconductor substrate 111 by a known method.
4 and the element isolation region 131 are formed.

The depth of the junction between the shallow well region and the deep well region is determined by the implantation conditions for the shallow well region, the implantation conditions for the deep well region, and the thermal process performed thereafter. The depth of the element isolation region 131 is set so that the shallow well regions of adjacent elements are electrically isolated. That is, a trench is formed all around one element so as to surround the shallow well region so that the lower end of the deep element isolation region is deeper than the junction between the deep well region and the shallow well region, and a silicon oxide film is embedded in this trench. Alternatively, a silicon oxide film is formed to form an element isolation region.

Next, as shown in FIG. 5A, a silicon oxide film 142 is formed. The material of the silicon oxide film 142 is not particularly limited as long as it has an insulating property. Here, when a silicon substrate is used, a silicon oxide film, a silicon nitride film, or a laminated body thereof can be used. Further, a high dielectric film such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a hafnium oxide film, or a laminated film thereof can be used. Next, as shown in FIG. 5B, a CVD (Chemical Vapor)
The amorphous silicon thin film 181 is deposited to a desired thickness (for example, 10 nm to 200 nm) by the Deposition method. The material of the amorphous silicon thin film 181 is not particularly limited as long as it is a semiconductor, and may be a group IV semiconductor such as germanium or silicon germanium, or a group III-V compound semiconductor such as gallium arsenide. Next, as shown in FIG. 5C, a silicon oxide film or a silicon nitride film is deposited by the CVD method and patterned to form a mask 182.
At this time, a slit-shaped exposed region 183 is formed in the amorphous silicon thin film 181.

After the mask 182 is provided, for example, an aqueous solution of nickel acetate or nickel nitrate is applied to the entire surface of the substrate,
After that, it is dried to a uniform film thickness with a spinner. Instead of the nickel compound, a compound of cobalt, palladium or platinum may be used. In the region 183 where the amorphous silicon thin film 181 is exposed in a slit shape, the deposited nickel ions are in contact with each other, and a small amount of nickel is added to the amorphous silicon thin film 181. Next, the amorphous silicon thin film is crystallized by annealing at 580 ° C. for 16 hours in a hydrogen reducing atmosphere or an inert gas atmosphere.
At this time, crystallization proceeded in the direction of arrow 184 in FIG. 6D, very elongated crystal grains having grain boundaries running in the direction parallel to the arrow were formed, and a polycrystalline silicon film 185 was formed. Alternatively, a substantially single crystal silicon film having a larger grain boundary spacing than the device size was formed.

Next, as shown in FIG. 6E, the mask 1
After removing 82, the polycrystalline silicon film 185 was patterned.

When the distance between the grain boundaries of the polycrystalline silicon film 185 is equal to or smaller than the size of the device, the direction of the slit-shaped exposed region 183 and the source / drain of the field effect transistor formed later are formed. The device characteristics differ depending on whether the direction connecting the regions is parallel (almost the same direction) or vertical (intersecting direction). When the direction in which the region 183 exposed in the slit shape and the source / drain region are perpendicular to each other (or in the intersecting direction), the grain boundaries run in the direction parallel to the moving direction of the charges, so that the driving current is deteriorated due to the scattering of the charges. Is small,
Off leak increases. On the other hand, the slit-shaped exposed region 183 is parallel to the direction connecting the source / drain regions.
In the case of (or almost the same direction), the grain boundary runs in a direction perpendicular to the charge moving direction, so that the drive current is largely deteriorated due to the charge scattering, but the increase in off-leakage is suppressed.
Further, by forming a substantially single crystal silicon film in which the spacing between grain boundaries is larger than the device size, a device with a large drive current and a small off leak can be obtained.

Next, although not shown, the polycrystalline silicon film 1
Gate oxide film 1 by forming a silicon oxide film on the surface of 85
41 is formed. The material of the gate oxide film 141 is not particularly limited as long as it has an insulating property. Here, when a silicon substrate is used, a silicon oxide film, a silicon nitride film, or a laminated body thereof can be used. In addition, aluminum oxide film, titanium oxide film,
A high dielectric film such as a tantalum oxide film or a hafnium oxide film or a laminated film thereof can be used. After that, a gate electrode, a source / drain region, an upper wiring, etc. are formed by a known method to complete the semiconductor device.

The above procedure provides a specific method for manufacturing the semiconductor device of the first embodiment. According to the above procedure, since a small amount of nickel is added to part of the amorphous silicon film 182 and then crystallization is performed, the direction and density of the grain boundary can be controlled. Further, if the density of the grain boundaries is reduced, it is possible to form a substantially single crystal film.
Therefore, the characteristics of the field effect transistor can be improved.

Further, according to the above procedure, since the amorphous silicon film deposited by the CVD method is crystallized to form the channel region, the film thickness can be controlled very precisely. Therefore, variations in characteristics of the field effect transistor can be suppressed.

As is clear from the above description, in the semiconductor device of the present First Embodiment, the gate electrode and the shallow well region are electrically connected, and the shallow well region and the channel region are interposed by the insulating film. Because of the capacitive coupling, it is possible to cause the substrate bias effect only when the field effect transistor is in the ON state and lower the effective threshold value without increasing the OFF current. Moreover, since the shallow well region and the source / drain region are separated by the insulating film,
Almost no gate current flows. Therefore, a higher voltage can be applied to the gate electrode as compared with the conventional technique, and a larger substrate bias effect can be obtained to increase the drive current. Therefore, a semiconductor device that can operate at high speed is provided. (Second Embodiment) The semiconductor device of the second embodiment is the same as the semiconductor device of the first embodiment, except that the source region and the drain region have a raised structure. The semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 7 is a sectional view of the semiconductor device according to the second embodiment. Note that the upper wiring is omitted in FIG. 7. 8 and 9 illustrate a procedure for manufacturing the semiconductor device according to the second embodiment. FIG. 10 illustrates another procedure for manufacturing the semiconductor device according to the second embodiment.

In the semiconductor device of the first embodiment, since the source region and the drain region are thin silicon films, there is a problem that parasitic resistance is large and silicidation is difficult. In the semiconductor device of the second embodiment, since the source / drain regions have the raised structure, silicidation is facilitated and the parasitic resistance of the source / drain regions can be reduced.

In the semiconductor device of the second embodiment, the source region is composed of the raised structure portion 155 and the region 153 in which impurities are diffused in the crystallized silicon film. Similarly, the drain region is composed of a region 156 and a region 154. With such a configuration, the thickness of the source region and the drain region becomes sufficiently thick, so that the parasitic resistance can be significantly reduced. Further, since the junction between the source / drain region and the channel region is protected by a sufficiently thick silicon film, the silicided region 1 is formed on the surface of the source region, the drain region and the gate region.
48 can be easily formed. Therefore, it is possible to further reduce the parasitic resistance of the source region and the drain region.

Next, a procedure for forming the semiconductor device of the second embodiment will be described with reference to FIGS. 8 and 9. The well structure is omitted in FIGS. 8 and 9. Second Embodiment
The procedure of forming the semiconductor device of 1 is different from the procedure of forming the semiconductor device of the first embodiment after the formation of the gate electrode. That is, the procedure similar to that of the first embodiment may be performed up to the stage of FIG.

Next, as shown in FIG. 8A, a polycrystalline silicon film 187 to be a gate electrode and a silicon oxide film 188 are formed in this order by a CVD method. The polycrystalline silicon film 187 may be replaced with another conductive film as long as it has conductivity. Here, when a silicon substrate is used as the semiconductor substrate, single crystal silicon, aluminum, copper, and the like can be used in addition to polycrystalline silicon. The conductive film is
It preferably has a thickness of 0.1 to 0.4 μm. The conductive film can be formed by a method such as a CVD method or a vapor deposition method. The silicon oxide film 188 is 0.05 to 0.25.
It preferably has a thickness of μm. Silicon oxide film 18
8 can be formed by a method such as a CVD method, a sputtering method, or a thermal oxidation method.

Next, as shown in FIG. 8B, a gate electrode is formed. First, the polycrystalline silicon film 187 and the silicon oxide film 188 are patterned. To perform this pattern processing, the silicon oxide film 188 and the polycrystalline silicon film 187 may be etched using the patterned photoresist as a mask. Further, only the silicon oxide film 188 is etched using the photoresist as a mask, the photoresist is removed, and then the silicon oxide film 18 is removed.
The polycrystalline silicon film 187 may be etched by using 8 as a mask. As a result, the gate electrode 143 is formed. Next, after depositing a silicon nitride film on the entire surface by the CVD method, etching back is performed to form a gate sidewall insulating film 145.

Next, as shown in FIG. 9C, a sidewall 189 of polycrystalline silicon is formed. In order to form the sidewalls 189 of polycrystalline silicon, etching back may be performed after depositing polycrystalline silicon on the entire surface. At this time, in addition to polycrystalline silicon, a semiconductor such as amorphous silicon or a conductive material can be used.

Next, the silicon oxide film 188 is removed by etching. Then, using the photoresist as a mask, the gate electrode 143 and part of the polycrystalline silicon sidewall 189 are removed by anisotropic etching. By this anisotropic etching, a part of the gate electrode 143 surrounded by the gate sidewall insulating film 145 can be removed to form a gate-well connection region. In addition, the polycrystalline silicon sidewall 189 is divided into a plurality of regions, and after impurity implantation and impurity diffusion, each constitutes a source region or a drain region.

Next, as shown in FIG. 9D, impurity ions are implanted into the gate electrode and the sidewalls 189 of polycrystalline silicon, and annealing for activating the impurities is performed. Thereby, the source region and the drain region are formed. The ion implantation of the source region and the drain region is, for example, 10 to 140 KeV as the implantation energy and 1 as the implantation amount when ⁷⁵ As ⁺ is used as the impurity ions.
When the ion implantation energy is ³¹ P ⁺ , the implantation energy is 5 to 8 × 10 ^{15 to} 2 × 10 ¹⁶ cm ^-2.
0 KeV, injection amount 1 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ^-2
Or when ¹¹ B ⁺ ions are used as impurity ions, the implantation energy can be 5 to 30 KeV and the implantation amount can be 1 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ^-2 .

After that, a silicidation process is performed by a known method to form upper wiring and the like to complete the semiconductor device.

Another method for forming the source / drain regions in the raised structure will be described with reference to FIG. In this method, the raised structure portion of the source / drain region is formed by the selective epitaxial growth method. Figure 8
From the state of (b), silicon is deposited by the CVD method. At this time, the silicon film 199 reflecting the underlying silicon crystal orientation is epitaxially grown only on the polycrystalline silicon film 185, and the silicon is not deposited on other regions (FIG. 10). After that, impurity ions are implanted into the gate electrode and the silicon film 199, and annealing for activating the impurities is performed, whereby the source / drain regions of the rise structure can be formed. According to the other method for making the source / drain regions have the raised structure described above, the silicon film 199 is formed in such a manner that a portion to be a source region in the future and a portion to be a drain region are separated in advance. Therefore, it is not necessary to separate them later.

According to the semiconductor device of the second embodiment, the source region and the drain region have a raised structure, and since silicidation is easy, the parasitic resistance of the source region and the drain region should be reduced. You can Therefore, the drive current of the element is increased, and a semiconductor device that operates at high speed is provided. (Embodiment 3) The semiconductor device of Embodiment 1 or 2 can be used in a battery-driven portable electronic device, particularly a portable information terminal. Examples of mobile electronic devices include personal digital assistants, mobile phones, and game devices.

FIG. 11 shows an example of a mobile phone. The semiconductor device of the present invention is incorporated in the control circuit 211. The control circuit 211 may be composed of an LSI (large scale integrated circuit) in which a logic circuit including the semiconductor device of the present invention and a memory are mounted together. 212 is a battery,
213 is an RF (radio frequency) circuit section, 214 is a display section,
215 is an antenna section, 216 is a signal line, and 217 is a power line.

By using the semiconductor device of the present invention in a portable electronic device, the operating speed of the LSI section can be increased, so that the portable electronic device can be operated as compared with the case where the conventional integrated circuit made of DTMOS is provided. It becomes possible to make the function sophisticated.

[0064]

As is apparent from the above, according to the semiconductor device of the first invention, a part of the semiconductor film is formed on the gate electrode and the shallow well region of the second conductivity type respectively. Sandwiched between the above to become the above channel region,
The gate electrode and the shallow well region of the second conductivity type are electrically connected. Therefore, the potential applied to the gate electrode to turn on the element is also transmitted to the shallow well region of the second conductivity type and lowers the potential of the channel region. Therefore, the substrate bias effect can be generated only when the device is in the ON state, and the effective threshold value can be lowered. Furthermore, since the second conductivity type shallow well region and the first conductivity type source region and drain region are separated by the first insulating film, almost no gate current flows. Therefore, the upper limit of the voltage value applied to the gate electrode can be significantly increased, and a larger substrate bias effect can be obtained to increase the drive current. Therefore, a semiconductor device that can operate at high speed is provided.

According to one embodiment, the channel region is completely depleted even when the device is off. Therefore, the substrate bias effect works even in the subthreshold region below the threshold, and the subthreshold characteristic is improved. Therefore, the threshold value can be lowered without increasing the off-state current of the element, so that the power supply voltage can be lowered and power consumption can be reduced.

Further, according to one embodiment, since the semiconductor film contains a metal element that promotes crystallization of the amorphous semiconductor by annealing, when the semiconductor film is crystallized by annealing. In addition, the direction of grain boundaries and the size of crystal grains can be controlled. Therefore, it is possible to easily suppress off-leakage or prevent deterioration of the drive current. In addition, if the size of the crystal grains is made sufficiently larger than the size of the device, a channel region substantially composed of a single crystal film can be realized, so that excellent characteristics such as low off-leakage and high drive current can be easily achieved at the same time. be able to.

Further, one embodiment specifically specifies a metal element that promotes crystallization of the amorphous semiconductor, and efficiently controls crystallization of the amorphous semiconductor and control of grain boundary direction. Can be done.

According to the method of manufacturing the semiconductor device of the second invention, the semiconductor film to be the channel region is formed by the step of depositing the amorphous semiconductor film, so that the film thickness is easily made uniform. I can do it. Therefore, a double gate type field effect transistor having a small variation in characteristics is provided.

Furthermore, after a metal element that promotes crystallization of the amorphous semiconductor film is selectively introduced into a part of the amorphous semiconductor film, the amorphous semiconductor film is crystallized by annealing. Therefore, it is possible to control the direction of grain boundaries and the size of crystal grains. Therefore, it is possible to easily suppress off-leakage or prevent deterioration of the drive current. In addition, if the size of the crystal grains is made sufficiently larger than the size of the device, a channel region substantially composed of a single crystal film can be realized, so that excellent characteristics such as low off-leakage and high drive current can be easily achieved at the same time. be able to.

One embodiment specifically specifies a metal element that promotes crystallization of the amorphous semiconductor,
Crystallization of the amorphous semiconductor and control of the grain boundary direction can be efficiently performed.

Further, according to one embodiment, since the source region and the drain region have a raised structure and the silicidation is easy, the parasitic resistance of the source region and the drain region can be reduced. it can. Therefore, it is possible to increase the drive current of the element and operate at high speed.

Since the portable electronic equipment of the third invention comprises the above semiconductor device, the LSI of the portable electronic equipment is
A high-performance portable electronic device having a high speed part is provided.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the section line AA ′ of FIG.

3 is a cross-sectional view taken along the section line BB ′ of FIG.

FIG. 4 is a conceptual diagram illustrating an operating principle of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a procedure for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a diagram illustrating a procedure for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a diagram illustrating another procedure for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a configuration diagram of a mobile electronic device according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view of a conventional semiconductor device.

FIG. 13 is a graph showing the electrical characteristics of an N-channel type DTMOS, for explaining the problems of the conventional technique.

[Explanation of symbols]

111 ... Semiconductor substrate 121 ... Deep well region 123 ... Shallow well region 142 ... First insulating film 141 ... Second insulating film 161 ... Channel area 151 ... Source area 152 ... Drain region 143 ... Gate electrode 131 ... Element isolation region 172 ... Contact hole 173 ... Contact hole 181 ... Amorphous silicon thin film 155 ... rised structure part

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/08 331 H01L 21/76 D 27/092 29/44 Z 29/41 27/08 321B 321D 29 / 78 626C (72) Inventor Seizo Kakimoto 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture F-term in Sharp Co., Ltd. (reference) 4M104 EE02 EE12 EE16 EE17 FF31 GG20 5F032 AA11 AA35 AA44 AB03 BB01 CA16 CA23 DA43 A08 AB0148F0148 AB03 AC04 BA14 BA15 BA16 BB01 BB04 BB05 BB11 BC05 BE02 BE09 BF06 BF15 BF17 BG01 BG13 DA27 5F052 AA12 DA02 DA03 DA05 DB01 FA06 JA01 JA10 5F110 AA01 AA03 AA06EEEE EE30 EE05 EE05 EE05 EE05 DD32 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD11 DD12 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD11 DD12 DD22 DD22 DD22 DD11 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD11 DD12 DD12 DD22 DD22 DD22 DD22 DD22 DD11 DD12 DD22 DD22 DD22 DD12 DD22 DD22 DD22 DD22 DD22 DD22 DD22 DD25 FF02 FF03 FF09 GG01 GG02 GG03 GG04 GG13 GG25 GG35 HK09 HK14 HK16 HK25 HK27 HK32 HK34 HK39 HK40 HM02 PP01 PP13 PP23 PP34 QQ03

Claims (7)

[Claims] 1. A semiconductor substrate, a deep well region of a first conductivity type formed on the semiconductor substrate, and a shallow well region of a second conductivity type formed on the deep well region of the first conductivity type. A semiconductor film formed on the second conductivity type shallow well region via a first insulating film; a gate electrode formed on the semiconductor film via a second insulating film; An element isolation region having a depth deeper than a junction depth between a conductivity type deep well region and the second conductivity type shallow well region is provided, and a channel is formed in a portion of the semiconductor film covered with the gate electrode. A region is formed, and a first conductivity type source region and a drain region are formed in a portion of the semiconductor film which is not covered with the gate electrode. The second conductivity type shallow well region and the gate electrode are formed. Specially connected electrically Semiconductor device to collect. 2. The semiconductor device according to claim 1, wherein the thickness of the semiconductor film sandwiched between the first insulating film and the second insulating film is 100 nm or less. . 3. The semiconductor device according to claim 1, wherein the deep well region of the first conductivity type has a fixed potential. 4. The semiconductor device according to claim 1, wherein the semiconductor film contains a metal element that promotes crystallization of an amorphous semiconductor by annealing. 5. The method of manufacturing a semiconductor device according to claim 4, wherein after the step of forming the first insulating film on the shallow well region of the second conductivity type, substantially all over the semiconductor substrate. Depositing an amorphous semiconductor film, selectively introducing a metal element that promotes crystallization of the amorphous semiconductor film into a part of the amorphous semiconductor film, and annealing at least the metal element And a step of crystallizing the amorphous semiconductor film in the peripheral portion of the region into which is selectively introduced into a polycrystalline semiconductor film or a substantially single crystal semiconductor film. . 6. The semiconductor device according to claim 1, wherein a part of the source region and the drain region has a raised structure that is present above a surface formed by the second insulating film. A semiconductor device characterized by: 7. A portable electronic device comprising the semiconductor device according to claim 1. Description: