JP2000340795A - Semiconductor logic element and logic circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of elements constituting a logic circuit and the area of the circuit by arranging first and second gate thresholds, such that a semiconductor logic element is turned on, when one of first and second input signals is high and turned off when both input signals are low. SOLUTION: A semiconductor logic element 1 has a second front-side gate electrode 7 formed at a location which is on a front-side gate insulating film 5 and which is counterposed to a second back-side gate electrode 5. While leaving a resist pattern used as an etching mask for the electrode 7 as is, the element 1 is implanted with ions, thereby doping prescribed impurities into a semiconductor active layer 4. Then, the element 1 is annealed for activation to form source/drain impurity regions 4a and 4b. It is arranged, such that the thresholds of the electrodes 5 and 7 allow the element 1 to be turned on, when one of first and second input signals is high, and to be turned off when both input signals are low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic device capable of performing, for example, a logical sum or a logical product with a single device,
The present invention relates to a logic circuit using the same.

[0002]

2. Description of the Related Art Conventionally, a single gate M
The unit logic circuit (logic gate circuit) is constituted by the OSFET.

For example, the NOR gate circuit shown in FIG. 11B has two single-gate PMOS transistors Mp1 and Mp2 and two single-gate NMOS transistors Mn1 and Mn2. That is, the PMOS transistors Mp1 and Mp2 are connected in series to a predetermined bias voltage + VB supply line,
An NMO is connected between the MOS transistor Mp2 and the ground potential.
The S transistors Mn1 and Mn2 are connected in parallel with each other. The gates of the PMOS transistor Mp1 and the NMOS transistor Mn1 are commonly connected to form a first input terminal, and the gates of the PMOS transistor Mp2 and the NMOS transistor Mn2 are commonly connected to form a second input terminal. An output is taken from the drain of the PMOS transistor Mp2.

A NAND gate circuit shown in FIG. 12B has two single gate PMOS transistors M.
p1 and Mp2 and two single-gate NMOS transistors Mn1 and Mn2. That is,
NMOS transistors Mn2 and Mn1 are connected to the ground potential line.
Are connected in series with each other, and a PMOS is connected between the NMOS transistor Mn1 and a supply line of a predetermined bias voltage + VB.
The transistors Mp1 and Mp2 are connected in parallel with each other. The gates of the PMOS transistor Mp1 and the NMOS transistor Mn1 are commonly connected to form a first input terminal, and the gates of the PMOS transistor Mp2 and the NMOS transistor Mn2 are commonly connected to form a second input terminal. An output is taken from the drain of the NMOS transistor Mn1.

Incidentally, a so-called dual gate (dual gate) is used.
gate) As a kind of MOS transistor, SOI (Silicon On Insulator, or, S
2. Description of the Related Art A semiconductor element having a structure in which two gate electrodes are opposed to each other on both sides in a thickness direction of a semiconductor (on insulator) layer via a gate insulating film is known. This semiconductor element
This is a variable threshold element that can change the threshold value of the gate electrode (front gate) on the opposed surface side according to the potential of the gate electrode (back gate) on the support substrate side embedded in the insulating layer.

When this variable threshold element is applied to a logic circuit, it may be used by being inserted between a logic circuit block and a power supply voltage or ground potential supply line. In this case, the switching element is used as a high-performance power supply switching element that can lower the threshold value during conduction to increase current driving capability and increase the threshold value during non-conduction to reduce off-leakage current. Further, even when used in the logic circuit itself, by replacing the individual single-gate MOS transistors shown in FIG. 11B or FIG. 12B, the current driving capability at the time of operation is improved and the leakage current at the time of cutoff is improved. It was used for the purpose of achieving a balance with reduction.

[0007]

However, although the conventional variable threshold element has the advantage of improving the performance of the element itself, it is inevitable that the manufacturing process becomes complicated. The benefits to applying were not too great.

An object of the present invention is to propose a method of using a variable threshold element in a new logic circuit, thereby improving the performance, reducing the number of elements of the logic circuit and reducing the circuit area. I do.

[0009]

The semiconductor logic element according to the first aspect of the present invention is preferably applied to an OR (OR) gate circuit or the like as an element having an n-type channel conductivity type. That is, a semiconductor layer supported on a substrate, a source and a drain formed apart from each other in the semiconductor layer, and an insulating film on each side of the semiconductor layer located between the source and the drain in the thickness direction. A first and second gates formed through the first and second gates, the first and second gates being applied with a first input signal and the second input signal being applied with a threshold value of the first gate. The threshold value of the second gate is such that when at least one of the first and second input signals is at a high level, the semiconductor logic element is turned on and when both input signals are at a low level, the semiconductor logic element is turned off. It is set to be. Preferably, the threshold value of one of the first and second gates is set so as to be 1/3 or less of the power supply voltage when the signal input to the other gate takes a low level.

The semiconductor logic element according to the second aspect of the present invention is preferably applied to an AND gate circuit or the like as an element having an n-type channel conductivity. That is, a semiconductor layer supported on a substrate, a source and a drain formed apart from each other in the semiconductor layer, and an insulating film on each side of the semiconductor layer located between the source and the drain in the thickness direction. A first and second gates formed through the first and second gates, the first and second gates being applied with a first input signal and the second input signal being applied with a threshold value of the first gate. The threshold value of the second gate is such that the semiconductor logic element becomes conductive when both the first and second input signals are at a high level, and becomes non-conductive when at least one input signal is at a low level. It is set to be. Preferably, when the potential of the second gate is equal to or lower than the threshold value of the second gate, the threshold value of the first gate is higher than the high level of the first input signal, and the potential of the second gate is higher than the high level of the first input signal. When the input signal is at a high level, the threshold value of the first gate is the first threshold value.
When the potential of the first gate is higher than the low level of the input signal and the potential of the first gate is the low level of the first input signal, the threshold value of the second gate is higher than the high level of the second input signal. When the potential is at the high level of the first input signal, the threshold value of the second gate is not more than 1/3 of the power supply voltage.

The semiconductor logic device according to the third aspect of the present invention is preferably applied to a logical sum (OR) gate circuit or the like as a device having a p-type channel conductivity type. That is, a semiconductor layer supported on a substrate, a source and a drain formed apart from each other in the semiconductor layer, and an insulating film on each side of the semiconductor layer located between the source and the drain in the thickness direction. A first and second gates formed through the first and second gates, the first and second gates being applied with a first input signal and the second input signal being applied with a threshold value of the first gate. The threshold value of the second gate is such that when at least one of the first and second input signals is at a low level, the semiconductor logic element is turned on and when both input signals are at a high level, the semiconductor logic element is turned off. It is set to be. Preferably, the first
Alternatively, one threshold value of the second gate is set to 1 of the power supply voltage when a signal input to the other gate takes a high level.
/ 3 or less.

The semiconductor logic device according to a fourth aspect of the present invention is preferably applied to a logical product (AND) gate circuit or the like as a device having a p-type channel conductivity type. That is, a semiconductor layer supported on a substrate, a source and a drain formed apart from each other in the semiconductor layer, and an insulating film on each side of the semiconductor layer located between the source and the drain in the thickness direction. A first and second gates formed via the first and second gates, wherein a threshold of the first gate to which a first input signal is applied and a second input signal are applied. The threshold value of the second gate is such that when both the first and second input signals are at a low level, the semiconductor logic element becomes conductive, and when at least one of the input signals is at a high level, the semiconductor logic element becomes non-conductive. It is set to be. Preferably, when the potential of the second gate is higher than or equal to the threshold of the second gate, the threshold of the first gate is lower than the low level of the first input signal, and the potential of the second gate is lower than the low level of the first input signal. When the input signal is at a low level, the threshold value of the first gate is the first threshold value.
When the potential of the first gate is lower than the high level of the input signal and the potential of the first gate is high, the threshold value of the second gate is lower than the low level of the second input signal. When the potential is at the low level of the first input signal, the threshold value of the second gate is higher than one third of the power supply voltage.

In the semiconductor logic device according to the first and third aspects, the threshold values of the first and second gates are the same, and the input signals applied to both gates are not equal. The structural parameters are set so that the element does not conduct only at the active level. Therefore, an OR gate circuit having two inputs of the first and second gates can be constituted by a single element. In addition, when conducting, the threshold value is reduced and the current driving capability is improved. When not conducting, the threshold value is improved and the off-leak current is reduced.

In the semiconductor logic elements according to the second and third aspects, the change widths of the threshold values of the first and second gates are different, and the element can be obtained only by applying the active level of the input signal to one of the gates. Are set to be non-conducting and conducting only when both gates are at the active level. Therefore, an AND gate circuit having two inputs of the first and second gates can be constituted by a single element.
In addition, when conducting, the threshold value is reduced and the current driving capability is improved. When not conducting, the threshold value is improved and the off-leak current is reduced.

A logic circuit according to the present invention includes a semiconductor layer supported on a substrate, a source and a drain formed in the semiconductor layer so as to be separated from each other, and a thickness of a semiconductor layer portion located between the source and the drain. A semiconductor logic element having first and second gates formed on both sides in the direction via an insulating film and facing each other, wherein the first and second gates of the semiconductor logic element are respectively signal input terminals. It is connected to the. Preferably, the semiconductor logic element is any of the semiconductor logic elements of the above four aspects.

[0016]

FIG. 1 is a diagram showing a circuit symbol of a semiconductor logic element according to an embodiment of the present invention. The semiconductor logic device according to the present embodiment has a dual gate (dual gate) having two gates and a common source and drain.
e) type insulated gate field effect transistor. FIG.
Semiconductor logic elements NMOS1 and NM shown in FIGS.
In OS3, the conductivity type of the channel is n-type. FIG.
Semiconductor logic elements PMOS2 and PM shown in (B) and (D)
In OS4, the conductivity type of the channel is p-type.

Of the semiconductor logic elements NMOS1 and PMOS2 shown in FIGS. 1A and 1B, one gate is used as a control terminal and the other is used as a control terminal. The threshold value and the manner of changing the threshold value have symmetrical characteristics.
That. In the present embodiment, one symmetrical logic element constitutes an OR gate for calculating a logical sum.

On the other hand, in the semiconductor logic elements NMOS2 and PMOS4 shown in FIGS. 1C and 1D, one gate is used as a control terminal and the other is used as a control terminal. , The threshold value and the manner of changing the threshold value have asymmetrical characteristics, and are hereinafter referred to as “asymmetrical logic element”. In the present embodiment, details will be described later, but 2
This asymmetry is realized by providing a thickness difference in the gate insulating film interposed between the two gate electrodes and the semiconductor active layer. In the circuit symbol, the thicker gate insulating film is hatched to distinguish it from a symmetrical logic element. In the present embodiment, an AND gate for calculating a logical product is constituted by one of the asymmetrical logic elements.

FIG. 2 shows an asymmetrical logic element as an example.
The structure of the semiconductor logic element according to the present embodiment is shown in a sectional view. In the logic element 1 shown in FIG. 2, the insulating layer 2 is formed on a support substrate via an adhesive layer, not particularly shown. A semiconductor active layer 4 is formed on the insulating layer 2 with a back gate insulating film 3 interposed. Semiconductor active layer 4 is made of, for example, single-crystal silicon having a thickness of about 25 nm, and has an impurity having a conductivity type opposite to the channel conductivity type introduced at a relatively low concentration. The back surface gate electrode 5 is embedded in the insulating layer 2. A surface gate electrode 7 is formed on the surface of the semiconductor active layer 4 with a surface gate insulating film 6 interposed therebetween. The back gate electrode 5 and the front gate electrode 7 are made of, for example, doped polysilicon (doped polysilicon).
stalline silicon) or doped metal silicide
(doped metal silicide) and face each other via the semiconductor active layer 4 and the gate insulating films 3 and 6. Gate insulating films 3 and 6 are made of, for example, silicon oxide or silicon nitride oxide. The thickness of the back gate insulating film 3 is, for example, about 10 nm, and the thickness of the front gate insulating film 6 is, for example, about 5 nm.

Impurities of the same conductivity type as the channel are introduced at a relatively high concentration into the semiconductor active layer outside the gate electrodes 5 and 7, thereby forming a source impurity region 4a and a drain impurity region 4b. . From the source / drain impurity regions 4a and 4b, a source terminal or a drain terminal is led out to the element outer surface by a conductive layer (not shown). Also, the back gate electrode 5
, And a first signal input terminal from the surface gate electrode 7 are respectively drawn to the outer surface of the device.

3 to 9 are cross-sectional views of a semiconductor logic element in a manufacturing process. In FIG. 3, a substrate 10 to be polished made of, for example, a single crystal silicon wafer or the like is prepared, a resist pattern R1 is formed thereon, and the surface of substrate 10 to be polished is etched using this as a mask (eg, RIE).
(Reactive Ion Etching)), thereby forming a convex portion 10a to be a semiconductor active layer later. The step of the projection 10a is, for example, about 25 nm.

After the resist pattern R1 is removed, a back gate insulating film 3 made of silicon oxide is formed to a thickness of about 10 nm on the surface of the substrate 10 to be polished, on which the projections 10a are formed, for example, by thermal oxidation as shown in FIG. I do. This thermal oxidation is performed, for example, using a vertical oxidation furnace at normal pressure, under the conditions of an introduced gas H ₂ : O ₂ = 1: 1 and a furnace temperature of 950 ° C.

In FIG. 5, for example, doped polysilicon or doped tungsten silicide (doped WSi _x ) serving as a back gate electrode is deposited to a thickness of about 150 nm. A resist pattern (not shown) is formed on the film serving as the back gate electrode, and the underlying film is etched (eg, RIE) using the resist pattern as a mask. As a result, the back gate electrode 5 is formed on the projection 10 a of the substrate 10 to be polished via the back gate insulating film 3.

In FIG. 6, for example, insulating layer 2 made of silicon oxide is deposited relatively thickly, and back gate electrode 5 is embedded in the insulating layer. Further, for example, polysilicon is deposited on the insulating layer 2 and the surface is polished to form the adhesive layer 11.

In FIG. 7, for example, the substrate 10 to be polished is bonded to a support substrate 20 made of a silicon wafer or the like prepared from the flattened surface side of the adhesive layer 11 and heat-treated. The heat treatment at this time is performed, for example, in an electric furnace in an oxygen atmosphere at 1100 ° C. for 60 minutes.

The bonded SOI thus formed
Edge grindin
g), grinding is performed from the back side of the substrate 10 to be polished, and polishing (for example, CMP (Chemical Mechanical Polling)) is performed.
ishing). In the CMP, the convex portions 10 of the substrate 10 to be polished are
When the back gate insulating film 3 is exposed between “a”, this functions as a stopper. Therefore, the polishing does not proceed much thereafter, and the end point of the polishing is detected. The convex portions 10a of the substrate 10 to be polished are separated from each other by this selective polishing. Then, for the separated convex portion 10a,
A predetermined impurity is introduced in a required amount by, for example, an ion implantation method. In the case where the PMOS transistor and the NMOS transistor coexist, the formation of the resist pattern and the ion implantation are repeated twice to separate different ion species. By the subsequent activation annealing, a semiconductor active layer 4 is formed as shown in FIG.

In FIG. 9, for example, the surface of semiconductor active layer 4 is thermally oxidized to form surface gate insulating film 6 having a thickness of about 5 nm. On the surface gate insulating film 6, doped polysilicon or doped tungsten silicide serving as a surface gate electrode is deposited to a thickness of about 150 nm. A resist pattern (not shown) is formed on the film serving as the surface gate electrode, and the underlying film is etched (eg, RIE) using the resist pattern as a mask. As a result, the front gate electrode 7 is located on the front gate insulating film 6 at a position facing the back gate electrode 5.
Is formed.

Thereafter, ion implantation is carried out while leaving the resist pattern used as an etching mask for the surface gate electrode, a predetermined impurity is introduced into the semiconductor active layer 4, and activation annealing is carried out. The source shown in
Drain impurity regions 4a and 4b are formed. In addition, a protective oxide film (not shown) is deposited to a thickness of, for example, about 500 nm, and a conductive layer for extracting an electrode is appropriately formed, whereby the semiconductor logic element 1 is completed.

The present invention can also be applied to a semiconductor device having a so-called bulk type back gate as shown in FIG. That is, in FIG. 10, a well 31 separated from the semiconductor substrate 30 by a pn junction is provided on the substrate surface, an electrode 32 is brought into ohmic contact with the well 31, and according to the voltage value of an input signal applied to the electrode 32, The threshold value of a transistor having the surface gate electrode 7 as a control electrode is controlled. Further, in the SOI type isolation structure of FIG. 2, the source / drain impurity regions 4a and 4b are formed from the surface of the semiconductor active layer 4 to the middle of the thickness, and the semiconductor active layer is replaced with the back gate electrode embedded in the insulating layer. An electrode may be brought into ohmic contact with the layer 4 and this electrode may be used as a second signal input electrode.

However, in these ohmic contact type control electrodes, a reactive current flows and power consumption increases, and channel controllability is poor. Therefore, an insulated gate type control electrode as shown in FIG. The back gate electrode 5 is desirable. Although the insulated gate back gate electrode 5 can be partially depleted depending on device parameters such as the thickness of the semiconductor active layer, the semiconductor active layer is directly controlled by an electric field and has high controllability. A fully depleted type that operates by depleting the entire layer thickness is desirable.

Next, a setting condition such as a threshold value will be described by taking a fully depleted type logic element as an example. The threshold value of the fully depleted dual gate MOSFET is expressed by the following equations (1) and (2).

[0032]

(Equation 1)

(Equation 2)

Here, φs and φsb are the surface potential and the back surface potential of the silicon active layer (semiconductor active layer 4), VFB and VFBb are the flat band voltages of the front and back surfaces of the silicon active layer, and Cox, Coxb, and Csi are the front surfaces, respectively. Gate, back gate or capacitance of silicon active layer, Tox, T
oxb and Tsi are the surface gate oxide film (front gate insulating film 6), the back gate oxide film (back gate insulating film 3), the thickness of the silicon active layer, Qsi is the impurity amount in the silicon active layer, and Vg and Vgb are The voltages applied to the front gate electrode and the rear gate electrode, and Vth and Vthb indicate the threshold values of the front channel MOSFET and the rear channel MOSFET, respectively.

From the above equations (1) and (2), the variation ΔVth of the threshold value of the surface channel MOSFET with respect to the variation ΔVgb of the voltage applied to the back gate electrode is expressed by the following equation (3). Of applied voltage Δ
The change amount ΔVthb of the threshold value of the back channel MOSFET with respect to Vg is expressed by the following equation (4).

[0035]

(Equation 3)

(Equation 4)

The rate of change of the threshold value in equation (4) can be obtained by replacing the front gate insulating film thickness Tox and the back gate insulating film thickness Toxb in the threshold value change equation in equation (3). Therefore, a symmetric logic element is
This can be realized by making both gate insulating film thicknesses the same.

On the other hand, for example, a logic element for calculating a logical product (AND) cannot be realized when both gate insulating film thicknesses are the same.

In order to realize the function of the AND gate using an asymmetrical logic element, if the voltage value of the input signal applied to the gate electrode of one MOSFET is at a level that turns off the channel, the channel of the other MOSFET is turned off. On,
It is necessary that a channel is not always formed regardless of the voltage value of the input signal for turning off. Therefore,
One M for the gate applied voltage of the other MOSFET
The amount of change in the threshold value of the OSFET is
Needs to be sufficiently larger than the change amount of the threshold voltage of the other MOSFET with respect to the gate applied voltage. As a result, the other MOSFE for which the amount of change in the threshold
It is necessary to set the gate insulating film thickness of T to be larger. Dual gate MOSFET 1 having the structure shown in FIG.
In this example, the thickness of the back gate insulating film 3 on the buried gate side, which is difficult to be reduced in thickness due to the influence of heating at the time of bonding the substrates, is set to be thicker, so that Toxb> Tox.

Now, the high level of the input signal is changed to the power supply voltage V
_{When DD} and the low level are set to the ground potential of 0 V, the threshold condition of the backside channel MOSFET is expressed by the following equation (5-1) and
(5-2). The condition of the threshold value of the surface channel MOSFET is expressed by the following equation (5-3).

[0040]

(Equation 5)

Here, the suffix "0" indicates that the voltage applied to the opposing gate is 0V. The above formula (5-
2) specifies the optimum range of the threshold value during the operation of the backside channel MOSFET from the viewpoint of the current driving capability and the off-leak current.

Hereinafter, specifically, when the silicon active layer thickness Tsi is 2
Back gate insulating film thickness Toxb and surface channel MO when 5 nm and front gate insulating film thickness Tox are 5 nm
An optimum range of the initial threshold value of the SFET is obtained. Now, the threshold change rate of the backside channel MOSFET is 0.7 to
When the back gate insulating film thickness Toxb is determined from the rate of change in the above equation (4) and 0.8 V, the following equation (6) is obtained.

[0043]

(Equation 6)

By substituting the value of Toxb for the rate of change in the above equation (3), the range of the rate of change of the threshold value of the surface channel MOSFET is obtained as in the following equation (7).

[0045]

Tox / (0.333 × Tsi + Toxb) = 5 / (8.325 + 10.7) to 5 / (8.325 + 9.3) = 0.26 to 0.28 (7)

Using the above equations (5-2) and (5-3), a relational expression is obtained with respect to the threshold value Vth of the surface channel MOSFET. 8) is obtained.

[0047]

Vth = Vth0− (0.26 to 0.28) × (0.2 to 0.3) × V _DD > V _DD = Vth0− (0.052 to 0.084) × V _DD > V _DD Vth0> (1.06-1.09) × V _DD (8)

Table 1 summarizes the gate insulating film thickness and the silicon active layer thickness for symmetric and asymmetric logic elements. The impurity concentration of the silicon active layer where the channel is formed is 5 × 1 for both the p-channel type and the n-channel type.
0 ¹⁴ / cm ³ , and the gate electrode material was doped polysilicon or doped metal silicide. The following Table 2 summarizes the shift amount of the Fermi level due to the gate electrode material and the impurity addition.

[0049]

[Table 1]

[Table 2]

When the power supply voltage V _DD is 1 V, the threshold value of the symmetrical logic element (dual gate MOSFET) manufactured under such conditions is shown in Table 3 below. The values are summarized in Table 4 below.

[0051]

[Table 3]

[Table 4]

The logical operation of the symmetrical logic element shown in Table 3 will be described using an NMOSFET as an example.
Assuming that the low level of the input signal is ground potential 0V and the high level is 0.18V, when both input signals are low level, both the front and back channels are turned off.
When one of the input signals is at the low level and the other is at the high level, only the channel to which the low level is applied to the gate is turned on. Further, when both input signals are at the high level, only the surface channel is turned on. Therefore, only when both input signals are at the low level, non-conduction is achieved, and when at least one of the input signals is at the high level, conduction is achieved, thereby realizing an OR gate. In this case, for example, in the NMOSFET of Table 3, the initial threshold value Vth0 and the operating V
th differs by 50 mV, and the off-leak current is reduced by 0.5 digit or more.

On the other hand, in the asymmetric logic element shown in Table 4, in the case of an NMOSFET, for example, the low level of the input signal is set to the ground potential 0 V, and the high level is set to the power supply voltage V _DD (1
V), when both input signals are at a low level, both the front and back channels are turned off, and when both are at a high level, both channels are turned on. Also,
When one of the input signals is at a low level and the other is at a high level, both channels remain off. Therefore, only when both input signals are at a high level,
If at least one of them takes a low level, it becomes non-conductive, whereby an AND gate can be realized. In this case, the initial threshold V
Since th0 and Vthb0 can be made large, the off-leakage current becomes 7
Significantly reduced by more than an order of magnitude.

The NOR gate circuit shown by the circuit symbol in FIG. 11A conventionally has two PMOS transistors Mp1 and Mp2 and two NMOs as shown in FIG. 11B.
It consisted of S transistors Mn1 and Mn2.
In other words, the PMOS is connected to the predetermined bias voltage + VB supply line.
Transistors Mp1 and Mp2 are connected in series with each other, and between PMOS transistor Mp2 and ground potential,
NMOS transistors Mn1 and Mn2 are connected in parallel with each other. PMOS transistor Mp1 and NMOS
The gates of the transistors Mn1 are commonly connected to form a first input terminal, and the gates of the PMOS transistor Mp2 and the NMOS transistor Mn2 are commonly connected to form a second input terminal. An output is taken from the drain of the PMOS transistor Mp2.

In this embodiment, a circuit having the same function is provided by a dual-gate PMOS transistor PMOS4 (FIG. 1).
(D)) and a dual gate NMOS transistor NMO
It is composed of two elements S1 (FIG. 1A). That is, an asymmetric dual-gate PMOS transistor PMOS4 and a symmetric dual-gate NMOS transistor NMOS1 are connected in series between a predetermined bias voltage + VB supply line and the ground potential. For example, the surface gate electrodes are commonly connected. To form a first input terminal, and the back gate electrodes are commonly connected to form a second input terminal. The output is obtained from the connection point of the dual gate MOS transistor.

A NAND gate circuit shown by a circuit symbol in FIG. 12A conventionally has two PMOS transistors Mp1 and Mp2 and two NMs as shown in FIG.
OS transistors Mn1 and Mn2. That is, the NMOS transistor Mn2 is connected to the ground potential line.
And Mn1 are connected in series with each other, and PMOS transistors Mp1 and Mp2 are connected in parallel with each other between the NMOS transistor Mn1 and a supply line of a predetermined bias voltage + VB. PMOS transistors Mp1 and NM
The gates of the OS transistors Mn1 are connected in common and the first
No input terminal, PMOS transistor Mp2 and NMO
The gates of the S transistors Mn2 are commonly connected to form a second input terminal. An output is taken from the drain of the NMOS transistor Mn1.

In this embodiment, a circuit having the same function is provided by a dual gate PMOS transistor PMOS2 (FIG. 1).
(B)) and dual gate NMOS transistor NMO
It is composed of two elements S3 (FIG. 1C). That is, a symmetrical dual-gate PMOS transistor P is connected between a predetermined bias voltage + VB supply line and the ground potential.
MOS2 and an asymmetric dual-gate NMOS transistor NMOS3 are connected in series. For example, front gate electrodes are commonly connected to form a first input terminal, and back gate electrodes are commonly connected to form a second input terminal. The output is obtained from the connection point of the dual gate MOS transistor.

The logic circuit having such a configuration is, for example, X
In addition to the OR gate, a multi-input logic gate may be used.
When the number of inputs is even, the number of elements is halved compared to the conventional case.
When the number of inputs is odd, the number of elements is reduced to (half + 1) as compared with the conventional case. In any case, by burying the back gate electrode, the circuit occupation area can be reduced by almost half compared to the conventional case. With these advantages,
Without changing the conventional circuit design technology, the number of elements constituting the logic circuit can be reduced, and high integration can be achieved. Further, the off-leakage current can be reduced without adding an additional circuit due to the variable threshold characteristics.

[0059]

According to the semiconductor logic device and the logic circuit of the present invention, a basic logic gate such as an OR gate or an AND gate, which has conventionally been constituted by two devices, is replaced by a single variable threshold device. And the number of elements is reduced accordingly. In addition, the circuit occupied area has been greatly reduced,
The integration degree of the logic circuit can be easily improved. Since the current driving capability of each transistor is improved and the off-leak current is reduced, the circuit characteristics themselves are also improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit symbol of a semiconductor logic element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of a semiconductor logic element according to the embodiment, taking an asymmetric logic element as an example.

FIG. 3 is a cross-sectional view showing a state after a convex portion of a substrate to be polished is formed in the manufacture of the semiconductor logic element.

FIG. 4 is a cross-sectional view subsequent to FIG. 3, showing a state after a back gate insulating film is formed.

FIG. 5 is a cross-sectional view showing a state after the formation of the back surface gate electrode, following FIG. 4;

FIG. 6 is a cross-sectional view subsequent to FIG. 5, illustrating a state after the adhesive layer is flattened.

FIG. 7 is a cross-sectional view following FIG.

FIG. 8 is a cross-sectional view subsequent to FIG. 7, illustrating a state after polishing of the substrate to be polished;

FIG. 9 is a cross-sectional view showing a state after the formation of the surface gate electrode, following FIG. 8;

FIG. 10 is a cross-sectional view of a semiconductor element having a so-called bulk type back gate, showing another structural example to which the present invention can be applied.

FIG. 11 is a diagram showing a symbol and a configuration of a NOR gate circuit of the present invention together with a configuration of a conventional circuit.

FIG. 12 is a diagram showing a symbol and a configuration of a NAND gate circuit of the present invention together with a configuration of a conventional circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Dual gate MOS transistor (semiconductor logic element), 2 ... Substrate to be polished, 3 ... Back gate insulating film, 4 ... Silicon active layer (semiconductor active layer), 4a, 31a ... Source impurity region, 4b, 31b ... Drain impurity Area, 5 ...
Back gate electrode, 6 front gate insulating film, 7 front gate electrode, 10 polished substrate, 10a convex portion, 11 adhesive layer, 20 support substrate, 30 semiconductor substrate, 31 well, 32 electrode .., NMOS1, PMOS2... Symmetrical logic elements, NMOS3, PMOS4... Asymmetrical logic elements, R1.

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Claims (15)

[Claims] A semiconductor layer supported on a substrate, a source and a drain formed in the semiconductor layer so as to be separated from each other, and a semiconductor layer portion located between the source and the drain on both sides in a thickness direction. A semiconductor logic element having first and second gates formed through an insulating film and facing each other, wherein a threshold value of the first gate to which a first input signal is applied and a second input signal are applied. The threshold value of the second gate is such that when at least one of the first and second input signals is at a high level, the semiconductor logic element is turned on and when both input signals are at a low level, the semiconductor logic element is turned on. A semiconductor logic element that is set to be non-conductive. 2. A threshold value of one of the first and second gates is set so that when a signal inputted to the other gate takes a low level, the threshold value is one third or less of a power supply voltage. The semiconductor logic device according to claim 1. 3. A semiconductor layer supported by a substrate, a source and a drain formed apart from each other in the semiconductor layer, and a semiconductor layer portion located between the source and the drain on both sides in the thickness direction. A semiconductor logic element having first and second gates formed through an insulating film and facing each other, wherein a threshold value of the first gate to which a first input signal is applied and a second input signal are applied. The threshold value of the second gate is such that when both the first and second input signals are at a high level, the semiconductor logic element is turned on and when at least one input signal is at a low level, the semiconductor logic element is turned on. A semiconductor logic element that is set to be non-conductive. 4. When the potential of the second gate is equal to or lower than the threshold value of the second gate, the threshold value of the first gate is higher than the high level of the first input signal. Is higher than the second input signal, the threshold value of the first gate is higher than the low level of the first input signal, and when the potential of the first gate is the low level of the first input signal, The threshold value of the second gate is higher than the high level of the second input signal. When the potential of the first gate is at the high level of the first input signal, the threshold value of the second gate is 1 / the power supply voltage. 4. The semiconductor logic device according to claim 3, wherein the number is 3 or less. 5. A semiconductor layer supported by a substrate, a source and a drain formed apart from each other in the semiconductor layer, and a surface on both sides in a thickness direction of a semiconductor layer portion located between the source and the drain. A semiconductor logic element having first and second gates formed through an insulating film and facing each other, wherein a threshold value of the first gate to which a first input signal is applied and a second input signal are applied. The threshold value of the second gate is such that when at least one of the first and second input signals is at a low level, the semiconductor logic element is turned on and when both input signals are at a high level, the semiconductor logic element is turned on. A semiconductor logic element that is set to be non-conductive. 6. A threshold value of one of the first and second gates is set so that when a signal input to the other gate takes a high level, the threshold value is one third or less of a power supply voltage. The semiconductor logic device according to claim 5. 7. A semiconductor layer supported by a substrate, a source and a drain formed apart from each other in the semiconductor layer, and a surface on both sides in a thickness direction of a semiconductor layer portion located between the source and the drain. A semiconductor logic element having first and second gates formed through an insulating film and facing each other, wherein a threshold value of the first gate to which a first input signal is applied and a second input signal are applied. The threshold value of the second gate is such that when both the first and second input signals are at a low level, the semiconductor logic element is turned on and when at least one input signal is at a high level, the semiconductor logic element is turned on. A semiconductor logic element that is set to be non-conductive. 8. When the potential of the second gate is equal to or higher than the threshold value of the second gate, the threshold value of the first gate is lower than the low level of the first input signal. When the second input signal is low level, the threshold value of the first gate is lower than the high level of the first input signal. When the potential of the first gate is high level of the first input signal, The threshold value of the second gate is lower than the low level of the second input signal. When the potential of the first gate is at the low level of the first input signal, the threshold value of the second gate is 1 / the power supply voltage. 8. The semiconductor logic device according to claim 7, which is higher than 3. 9. A semiconductor layer supported by a substrate, a source and a drain formed apart from each other in the semiconductor layer, and a surface on both sides in a thickness direction of a semiconductor layer portion located between the source and the drain. A logic circuit comprising a semiconductor logic element having first and second gates respectively formed with an insulating film interposed therebetween, wherein the first and second gates of the semiconductor logic element are respectively connected to signal input terminals circuit. 10. The threshold of said first gate to which a first input signal is applied and said second gate to which a second input signal is applied.
The threshold value of the gate is such that the semiconductor logic element is conductive when at least one of the first and second input signals is at a high level, and the semiconductor logic element is non-conductive when both input signals are at a low level. Claim 9 which is set to
The logic circuit according to the above. 11. The threshold value of the first gate to which a first input signal is applied and the second threshold voltage to which a second input signal is applied.
The threshold value of the gate is such that the semiconductor logic element becomes conductive when both the first and second input signals are at a high level, and becomes non-conductive when at least one of the input signals is at a low level. Claim 9 which is set to
The logic circuit according to the above. 12. The threshold of said first gate to which a first input signal is applied and said second threshold to which a second input signal is applied.
The threshold value of the gate is such that when at least one of the first and second input signals is at a low level, the semiconductor logic element becomes conductive, and when both input signals are at a high level, the semiconductor logic element becomes non-conductive. Claim 9 which is set to
The logic circuit according to the above. 13. The threshold value of the first gate to which a first input signal is applied and the second threshold voltage to which a second input signal is applied.
The threshold value of the gate is such that the semiconductor logic element becomes conductive when both the first and second input signals are at a low level, and becomes non-conductive when at least one input signal is at a high level. Claim 9
The logic circuit according to the above. 14. The logic circuit according to claim 9, wherein said semiconductor logic element independently constitutes an OR operation circuit. 15. The logic circuit according to claim 9, wherein said semiconductor logic element independently constitutes an AND operation circuit.