JPH09162417A - Cmos integrated circuit formed on silicon-on-insulator substrate, and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reconcile the structure of a CMOS integrated circuit with an already-existing CMOS process technique an to obtain the optimum threshold voltage control of the integrated circuit which is actuated in a low voltage. SOLUTION: This integrated circuit is constituted of N-MOS FETs 104 and P-MOS FETs 102, which are respectively formed on selected regions on a silicon surface layer, and two back gate electrodes 150 and 152, which are respectively formed of heairly doped region in the surface of a silicon substrate 114 which is adjacent to an insulating layer 116 and is located under the lower side of the layer 116. At this time, the electrode 150 is extended under the lower sides of one group of the FETs 102, the electrode 152 is extended under the lower sides of one group of the electrodes 104, each back gate electrode has a contact part for applying a bias voltage to each MOS FET and the threshold voltage of the individual groups of the MOS FETs is controlled by this contact parts by applying the bias voltage to the individual back gate electrodes to correspond to the MOS FETs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit on a silicon-on-insulator substrate and a method for forming an integrated circuit on a silicon-on-insulator substrate. The present invention relates to the realization of improved threshold voltage control.

[0002]

2. Description of the Related Art A conventional complementary metal oxide film (CMO)
In the S) technology, a MOS field effect transistor (MO
SFETs) are embedded in the surface of a bulk silicon substrate wafer and are formed in distributed semiconductor well regions.
The threshold voltage of the MOSFET is, for example, S.M. M. Sze,
"Physics of semconductorD
It has been known in the past that the voltage can be adjusted and controlled by applying a bias between the power supply junction of the MOSFET and the well, as described in "Devices", 2nd.ed., p.442.

This technique of threshold voltage control is often referred to as "backgating." Normally, a reverse bias is applied between the power supply and the well to make the threshold voltage of the n-channel transistor more positive and p-
Be more negative than the threshold voltage of the channel device.

However, it is also possible to apply a small forward bias to the power supply / substrate junction to make the n-channel threshold more negative and the p-channel threshold more positive. Forward bias is typically about 0.4
It is not greater than V, and the power supply / well junction begins to conduct sufficiently, affecting circuit operation.

Low power CMOS integrated circuits have been reported which operate at supply voltages of 1 V or less. A supply voltage on the order of 1 V will be used in the future with transistor gate lengths of ~ 0.1 μm and below to minimize the "hot carrier" effect associated with energetic electrons accelerated by high electric fields in the device. It is also required for CMOS technology. MOSFE for operation from 1V power supply
It is required to control the T threshold voltage in a very narrow range as compared with that required in the case of a circuit that operates with a normal 5V power supply. The requirement for the MOSFET to be less conductive when its input gate is zero biased to its power supply is that the threshold voltage of the n-channel transistor is greater than about 0.3V and that the p-channel transistor is Threshold voltage of less than about -0.3V.

In order to allow the threshold voltage to change according to the temperature and the processing conditions, it is necessary to add a certain margin to the above (threshold voltage) value. Since the ability of a MOSFET to supply current in a circuit is usually determined by the difference between the power supply voltage and the threshold voltage,
The operation of integrated circuits with supply voltages below 1 V is strongly affected by variations in transistor threshold voltage.

Recently, J. Burr and J. Shott is
"200 mV using Stanford ultra low power CMOS
Self Test Encoder / Decoder ", 1994I
A technical digest of the EEE Solid State Circuit Conference, p84, demonstrates a technique of backgating for adjusting the threshold voltage of transistors in CMOS integrated circuits operating at very low (<1V) supply voltage.

The above techniques allow analog and digital CMOS integrated circuits to operate with supply voltages as low as 0.2V by incorporating additional circuitry to control the bias applied between the power supply and the well of each transistor. It has been shown that there is a possibility. Not only does threshold adjustment by backgating allow process variations, but it can also be done dynamically during circuit operation, allowing the threshold voltage to change in response to changes in temperature and other conditions. Will give you.

By properly designing the structure of the device, the use of a silicon-on-insulator (SOI) substrate allows the use of a conventional "bulk" CMOS, ie a CM formed on a conventional bulk silicon substrate.
It offers considerable advantages over OS circuits. S
OI substrates are beneficial for low power integrated circuits operating at low supply voltages. In particular, the capacitance between the power and drain region and the substrate is greatly reduced, eliminating the power and drain coupling leakage current.

The use of SOI substrates for the production of CMOS integrated circuits has been extensively studied. The SOI substrate is formed of a thin film of crystalline silicon overlying a buried oxide layer formed in or on the crystalline silicon wafer. Various techniques for forming an SOI substrate are
For example, Wolf by Silicon Pro
cessing for the VLSI Era:
Vol. 2 Process Integrati
n, p. p. 66-76, (Lattice Pres
S., Sunset Beach CA, 1990).

A known technique for forming SOI substrates is high dose and high energy implantation of oxygen into a bulk silicon wafer, which is then described, for example, in T.W. W. MacElwee, I .; D. Calde
r, R. A. Bruce and F.F. R. Shepher
d, "High performance fully
depleted silicon-on-insul
attor transistors ”, IEEE Tr
ans. Electron. Devices. ED-3
7, 1444 (1990), and US Pat.
4,804,633 by high temperature annealing. SO made in this way
The I substrate is SIMOX (separation by i).
It has become known as a plant of oxygen material.

The SOI substrate may also be a zero-melt recrystallization of an amorphous or polycrystalline silicon film deposited on an oxide layer, or an oxide silicon wafer may be electrostatically bonded to a carrier substrate and then chemically It can be manufactured by removing all but the thin film of the original wafer using a mechanical polishing method.

In a variation of the CMOS on SOI technology known to improve circuit performance,
The silicon film that forms the MOSFET channel is completely depleted of free carriers when no gate bias is applied, as described, for example, in the reference to MacElwee et al., Supra. These "fully depleted" techniques provide high transconductance because changes in gate voltage are almost completely absorbed by changes in mobile carrier concentration in the channel below the gate.

In contrast, normal MO at gate voltage
The portion corresponding to the SFET is absorbed by the change in charge in the depletion region below the channel and does not contribute to the current between the source and the drain. A fully depleted MOSFET is also defined as a small value of the subthreshold swing S (S = dV _G / dlog101 _D , where V _G is the gate voltage and I _D is the drain current). The threshold voltage of the MOSFET can be set to a value close to zero if the quasi-threshold swing is small, which is especially important for circuits operating at low supply voltages. This means
Moreover, it provides a large difference between the supply voltage and the threshold voltage, improving the current drive of the MOSFET.

In a well-depleted MOSFET formed on an SOI substrate, the threshold voltage is highly dependent on the thickness of thin film silicon and the doping level within the thin film. At present, it is considered difficult to control the thickness of a silicon thin film with sufficient accuracy to control the threshold voltage well (B. Davari,
short course notes on low
-Power CMOS integrated ci
rcuits, IEDM '93). As a result, the threshold voltage must be set to a fairly high value to allow for process variations, and thus loses many of the advantages of the small quasi-threshold swing S of a fully depleted device.

Some MOSs using SOI substrate in which the gate electrode is arranged both above and below the silicon thin film
FET structures are known. This type of device has become known as a "double gate" MOSFET. These gates are separated from the channel by an oxide layer and also from the substrate by another oxide layer. The "double gate" structure is based on the F.S. Ba
lestra, S.R. Cristoloveanu, M .;
Benachir, J .; Brini and T.W. El
by ewa, "Double-gate sili
con-on-insulator transist
or with volume inversion:
a new device with greatl
y enhanced performance ”, I
EEE Electron Device Letter
It was first proposed in 1987 as a theoretical study in rs EDL-8,410 (1987).

In this work, the use of two gate electrodes was used to form the silicon channel forming the MOSFET channel.
It is known to allow conductive regions to be formed on both the top and bottom surfaces of the film, increasing transconductance and, more commonly, increasing the current drive capability of the MOSFET. Balestra et al. Proposed that the lower electrode could be made by performing two oxygen implants at different energies during the SIMOX substrate preparation to form two buried oxide layers after high temperature annealing. It was This structure was later realized in experiments.

T. Ohno, S .; Matsumoto,
And K.K. Izumi (NTT) is an Electron
ics Letters 25, p. 1071 (198
9) mentions the use of the lower electrode as a shielding electrode for high power circuits. MOSFE
Another example of a double gate having a lower electrode formed in a trench located under the T channel is described in US Pat. 5,188,973.

Regarding the double gate structure, T.W. Ta
naka, K .; Suzuki, H .; Horie and T.W. 11 by Sugii (Fujitsu) of VLSI Technology 1994 Symposium Digest Technical Record
As described on the page, "P ⁺ -n ⁺ double gate M
Reported in a paper entitled "Ultrafast Low Power Operation of OSFETs", which has been implemented using a complex process.

In this process, the wafer is exposed to normal CMO.
It is transferred to the polysilicon gate patterning step of the S processing step. This wafer is then electrostatically bonded to the carrier substrate, leaving a residual silicon thickness of 0.1.
The material is removed from the backside until it is on the order of μm. At this stage, the gate oxide is grown on the backside and the polysilicon gate is formed with the source and drain regions to complete the MOSFET structure. Tanak
a et al. to enable its use in low power integrated circuits M
Report on fabricating upper and lower gate electrodes of opposite doping type (ie top electrode doped p ⁺ and bottom electrode n ⁺ ) to achieve low threshold voltage of OSFET. doing.

"Silicon on insulator
Philips Wi titled "or device"
U.S. Patent No. 4,8
64, 377 also describe another structure formed by a heavily doped contact zone formed inside the silicon layer below the channel region of a MOS transistor formed on an SOI substrate. .

US Pat. No. 5,103,277, Cavi
glia et al., Sensing circuit and n-MOSFET
And a method for compensating for changes in threshold voltage due to radiation damage using an operational amplifier off-chip that generates a bias voltage applied to a substrate forming a back gate electrode for a p-MOSFET. There is.

The substrate forms the back gate of the p-MOSFET therein, and the back gate electrode is formed below the channel region of the n-MOSFET formed on the SOI substrate to form p- and n-MOSFETs. Another structure has been suggested in which a separate gate bias is applied to. 1 formed on an n-type substrate
In one example, the p-type back gate electrode is n-FE
Formed on the surface of the substrate below the channel region of Ts,
The substrate itself forms the back gate of the p-FET.

A bias is applied to the substrate and the substrate is maintained more positive than the bias on the p-type back gate electrode so that the resulting reverse biased diode has a current flowing in each back gate source. Stop flowing through. In order to overcome the constraint of maintaining a specific relationship between the back gate bias level and the substrate, the back gate electrode of the n-FET is provided by a metal layer formed in the insulating layer below the channel region. Another proposed structure has been proposed. In the latter structure, the electrodes are completely isolated within the insulating layer. Nevertheless, Cavilia does not provide any suggestion as to how to actually make these gate electrode structures.

Various alternative methods have been devised to implement threshold voltage control in MOSFETs on SOI substrates. For example, threshold optimization for SOI transistors is described by Doyle et al. (Digital Equipm).
ent Corp. US Patent No. 5,38
This is accomplished by forming a charge layer in the gate oxide as described in 7,530.

US Pat. No. 4,968,967 to Houston et al. Of Texas Instruments. 5,18
5,280, "A method of manufacturing an SOI transistor by pocket implant and body source BTS contact" is described. Localized'pocket 'implants were used to enhance the back gate threshold voltage. Vinal (Thunderbird Techn
U.S. Pat. 5,151,759
And discloses a "Fermi threshold SOI transistor" that makes the threshold voltage independent of gate oxide thickness, channel length, and drain voltage by setting the threshold voltage to twice the Fermi potential. There is.

[0027]

Thus, although various back gate MOSFET structures are known, many of these structures are laborious to fabricate, and these structures and existing CMOS process technology are not compatible. There was a problem that it was not easy to make them compatible.

The present invention has been made in view of the above, and facilitates the manufacture of a CMOS integrated circuit, makes these structures compatible with the existing CMOS process technology, and optimizes the integrated circuit operating at a low voltage. CMO on silicon-on-insulator substrate that can obtain various threshold voltage control
It is an object to provide a method for forming an integrated circuit on an S integrated circuit and a silicon-on-insulator substrate.

[0029]

To achieve the above object, a CMOS integrated circuit according to the present invention comprises a semiconductor substrate layer, a buried insulating dielectric layer, and a silicon surface layer above the semiconductor substrate layer. In a CMOS integrated circuit on a silicon-on-insulator substrate, a plurality of n-MOSFETs and p-MOSFETs formed in selected regions of the silicon surface layer using fully depleted CMOS technology and the isolation At least two back gate electrodes formed by heavily doped regions of the surface of the lower semiconductor substrate layer adjacent to the dielectric layer, the first back gate electrode being a set. Of the second p-MOSFET of the second
Back gate electrodes extend below the set of n-MOSFETs, and each back gate electrode is connected to each MOSF.
A contact portion for applying a bias voltage to ET is provided, and the threshold voltage of each MOSFET of each set is controlled by the contact portion by applying a bias to the corresponding back gate electrode.

In the CMOS integrated circuit according to the second aspect, each set is composed of individual MOSFETs,
A separate back gate electrode is provided for each individual MOSFET.

In the CMOS integrated circuit according to the third aspect, one set is composed of a plurality of n-MOSFET groups, and another set is composed of a plurality of p-MOSFET groups. A separate back gate electrode is provided for the -MOSFET group and each n-MOSFET group.

According to a fourth aspect of the present invention, in the CMOS integrated circuit, the substrate is the first conductive type, and
The gate electrode is constituted by heavily doped conductive regions of opposite conductivity type.

According to a fifth aspect of the present invention, in the CMOS integrated circuit, the substrate is of the first conductivity type and includes well regions of the second conductivity type formed therein. The gate electrode is constituted by a heavily doped conductive region of the first conductivity type formed inside the well region.

In the CMOS integrated circuit according to the present invention, the back gate electrode is provided by a heavily doped region of a doping type opposite to the doping type of the semiconductor substrate, and the back gate electrode is provided. A structure in which a bias is applied to the gate electrode so that the back gate electrode is junction-insulated from the substrate.

The CMOS integrated circuit according to claim 7 also includes at least one electrically conductive contact to each back gate electrode through the conductive interconnect metallization layer of the integrated circuit. This is the structure provided.

Further, the CMOS integrated circuit according to the eighth aspect of the invention is such that the individual MOSFs formed in the silicon surface layer.
The ET is insulated by a field oxide layer, and the contact with the back gate electrode is realized by a through structure extending through the field oxide layer.

According to a ninth aspect of the present invention, in the CMOS integrated circuit, the integrated circuit operates at a voltage of 1 V or less, and the circuit operates while the n-MOSFET and the p-type MOSFET are being operated.
A means for generating the back gate bias in response to changes in MOSFET parameters.

In the CMOS integrated circuit according to the tenth aspect of the present invention, the back gate bias is formed in the silicon surface layer, and the back gate bias is applied to the back gate electrode via a metal interconnection line. It is generated by a portion of the integrated circuit that includes means for transmitting a bias.

A CMOS integrated circuit according to the eleventh aspect of the present invention includes a charge pumping means for providing the back gate bias.

The method according to claim 12 is the back
In a method of forming an integrated circuit on a silicon-on-insulator substrate including a MOSFET constituted by a gate electrode, a semiconductor substrate layer of a first conductivity type,
Providing a silicon-on-insulator substrate having a buried insulating layer and a silicon surface layer on top of it, and forming a heavily doped conductive region in the substrate layer to provide the silicon surface Forming a buried back gate electrode by selectively doping a certain region of the substrate layer by high energy ion implantation through the layer and further through the buried insulating layer; MOSFET in the silicon surface layer extending above the gate electrode
And a step of forming an electrical contact with the terminal of the MOSFET constituted by the lower back gate electrode of the MOSFET.

Also, in the method according to the thirteenth aspect, the step of forming the back gate electrode includes the step of forming a heavily doped region of a conductivity type opposite to the substrate layer.

In the method according to claim 14, the step of forming the back gate electrode forms a well region of a second conductivity type in the substrate, and then, the back region is formed in the well region. Forming a gate electrode, said back gate electrode being provided by a selectively doped region of a first conductivity type insulated in said well region; said well region and said back region. Providing electrical contact to the gate electrode.

According to a fifteenth aspect of the present invention, in the step of forming the buried back gate electrode, the high energy of the dopant to the inside of the substrate layer is passed through the silicon surface layer and further through the buried insulating layer. Selectively doping the substrate by implantation to provide a heavily doped region in a region of the substrate adjacent to the insulating layer, and annealing the implant to adjoin the substrate layer to the insulating layer. And forming a conductive region on the surface region of which the electrode is provided.

The method according to claim 16 includes at least a step of forming first and second back gate electrodes, which is subsequently performed on the silicon surface layer above the first back gate electrode. Expanding set of n-MOSFETs
And a set of p-MOSFETs extending above the second back gate electrode, the threshold voltages of the n-MOSFET set and the p-MOSFET set are independently set. For the purpose of controlling, including at least one contact to each of the first and second gate electrodes to apply a bias, the n-
It includes the step of contacting the terminals of the MOSFET and the p-MOSFET.

The method according to claim 17 is a method of forming a CMOS integrated circuit including an n-MOSFET and a p-MOSFET on a silicon-on-insulator substrate, wherein the semiconductor substrate layer of the first conductivity type is provided. And a step of providing a substrate composed of a buried insulating layer on the upper side thereof and a crystalline silicon layer on the upper side thereof, and in the substrate layer, a certain region of the substrate layer is selectively selected by ion implantation. Forming a plurality of buried back gate electrodes by heavily doping to form conductive regions of a second conductivity type, thereby junction-insulating the electrodes from the substrate, and the silicon surface. A set of p-MOSFETs and a set of n-MOSFETs on each back gate electrode in the layer
So that the threshold voltage of each p-MOSFET and each n-MOSFET of each set can be independently controlled by applying a bias to the corresponding back gate electrode. Process,
Is included.

[0046]

DETAILED DESCRIPTION OF THE INVENTION The silicon according to the present invention will be described below.
Embodiments of a CMOS integrated circuit on an on-insulator substrate and a method of forming an integrated circuit on a silicon-on-insulator substrate will be described in detail with reference to the drawings.

(Embodiment 1) First, Embodiment 1 will be described. A cross-sectional view of an integrated circuit 10 including a MOSFET 20 according to the known prior art on an SOI substrate 12 is shown in FIG. The SOI substrate 12 has a silicon substrate ware 14 on which an insulating layer 16 of silicon dioxide is formed.
And has a thin crystalline silicon surface layer 18. SOI
Substrate 12 may be formed using any of the methods described above, and is preferably formed by the SIMOX process.

The heavily doped n-type source and drain regions 22 of the MOSFET are formed in a conventional manner by selectively doping a portion of the crystalline silicon surface layer 18, ie, ion implantation. It is formed by the method of.

The normal polysilicon gate electrode 24 is M
Formed on the thin gate oxide layer 26 over the lightly doped p-type channel region 28 of the OSFET. Below this channel region 28, a second gate electrode 30, or "back gate," is formed within the insulating layer 16, that is, within the insulating layer 16 of silicon dioxide. The first gate electrode (polysilicon gate electrode) 24 and the second gate electrode 30 are therefore
As shown in FIG. 2, the thin silicon thin film forming the channel of the MOSFET 20 is formed above and below the channel region 28.

The first gate electrode 24 is separated from the channel region 28 by a gate oxide layer 26. The back gate (second gate electrode 30) is separated from the channel region 28 by a portion 32 of the insulating layer 16 and is separated from the underlying silicon substrate wear (semiconductor layer) 14 by a portion 34 of the insulating layer 16. ing. This type of device is known as a "double gate" MOSFET.

P formed on a silicon-on-insulator substrate composed of a semiconductor substrate 44, an insulating layer 46, and a thin silicon surface layer 62 having transistor source, drain and channel regions formed therein. FIG. 2 shows a cross-sectional view of another CMOS integrated circuit 40 including a -channel MOSFET 41 and an n-channel MOSFET 42.

This FIG. 2 shows the source 5 of the MOSFET 41.
2, drain 54 and channel 50, and MOSFE
Source 58, drain 60 and channel 5 of T42
6 and 6 are shown. Lower silicon surface layer (insulating layer) 6
A portion of 2 constitutes the gate oxide of the transistors under gates 64 and 66. In n-doped substrate 44, electrode 70 is p-doped and n-MOSFET
The back gate electrode of 42 is formed and the contact 72 applies a bias to the electrode 70.

Another contact 68 is provided on the substrate forming the back gate electrode of the p-MOSFET 41. In this way, the threshold voltage of the n- and p-MOSFETs can be adjusted by applying a bias to the substrate and the electrode 70, the electrode 70 being junction isolated from the substrate and the substrate being more positive than the electrode 70.・
Maintained at bias.

Next, the p-channel MOSFET formed on the SOI substrate 112 according to the first embodiment.
A cross-sectional view of a CMOS integrated circuit 100 composed of 102 and an n-channel MOSFET 104 is shown in FIG.

The SOI substrate 112 (see FIG. 4) comprises a starting silicon substrate 114 which is a lightly doped n-type wafer, further comprising a layer of silicon dioxide forming a buried insulating layer 116. 114
A thin silicon surface layer 118 that is separated from the layers of. The SOI substrate 112 is preferably SIMOX
Formed by the technique.

As shown in FIG. 3, the silicon surface layer 1
18 is selectively doped to form n-well regions 120 and p
-Well regions 122 are formed in which the individual MOSFETs 102 and 104 are formed respectively. These well regions are electrically isolated by the regions of field oxide 124 formed by the fully oxidized portion of the thin silicon surface layer 118 (see FIG. 4) in these regions. The surface region of the n-well is selectively doped in the usual way, with heavily doped p-type source region 130 and drain region 132, and a lightly doped channel region 134 in between. P-channel MOSF constructed
It forms ET102. Also, the gate oxide layer 13
6 and a polysilicon gate electrode 138 are formed thereon in a conventional manner.

Correspondingly, the n-channel MOSFET 104 having the source region 140, the drain region 142, the channel region 144, the gate oxide 146, and the gate electrode 148 corresponds to the silicon surface layer 118 (FIG. 4).
Reference p) well portion 122. Each MO
SFETs 102 and 104 also have back gate electrodes 150 and 152, respectively, which extend downward.

The back gate electrode 150 is formed in the n-type substrate layer 114 and is a p-channel MOSFE.
Heavily doped p- extending below the ET 102
It is formed by the type region. And correspondingly, another heavily doped n-channel MOSF.
The back gate electrode 152 is formed by the p-type region extending under the ET 104. Metal interconnect lines, such as 154 and 156, provide electrical contact to the source, drain and gate regions of the transistor, respectively, in the conventional manner.

Still another metal interconnect line 160 and 162 extending through the field oxide layer 124 provides electrical contact to the back gate electrodes 150 and 152, respectively. These contacts allow biasing of the back gate electrode and / or connection to other parts of the completed integrated circuit.

Preferably, the back gate electrodes 150, 15
Since 2 has the opposite conductivity to the substrate and is more heavily doped than the substrate, they are the upper MOSFETs 102 and 1 formed in the thin silicon surface layer 118.
Not heavily depleted when biased against a 04 source junction. This is important in minimizing the effect of the back gate electrode on threshold voltage control.

As is well known, an MO formed on an SOI substrate by applying a substrate bias.
The threshold voltage V _{t of the} SFET can be shifted.
The integrated circuit structure shown in FIG. 3 has n-MOSFETs and p-types.
Providing a separate back gate electrode for the MOSFET, each electrode being junction insulated from each other electrode. Therefore, the threshold voltage of each device can be individually optimized, ie each back gate can be selectively biased.

Conveniently, the bias circuit is incorporated on-chip using the charge pumping method. Charge pumping can provide a back gate bias of about twice the supply voltage, which allows a reasonable range of V _t regulation. Not only does this circuit allow control of biasing to optimize circuit performance, but it can also compensate during operation, for example to adjust bias in response to changes in temperature during operation. It has the effect of enabling it and eliminating the need for multiple power supplies.

Control of the threshold voltage by back gate biasing depends on sufficient depletion of the thin silicon film within which the MOSFET is built. Therefore, in the manufacture of MOSFET, M
A well-depleted CMOS technology with controlled doping levels of silicon film to form OSFETs is provided.

For example, in an n-channel FET, sufficient depletion means that most of the carrier concentration in the silicon film forming the active channel of the device is ionized everywhere when no bias is applied. It means less than half of the dopant concentration.

In an integrated circuit according to another embodiment of the present invention (not shown), the first back gate electrode is provided for one set of a plurality of n-MOSFETs, The second gate electrode has another set of p-M
It is provided for the OSFET. In this way, individual back gate electrodes can selectively control a single MOSFET or group of MOSFETs, and different biases can be applied to groups of transistors or individual groups of transistors as needed. It becomes possible to selectively apply to the transistor. As a result, the threshold voltage of individual transistors or groups of transistors can be controlled and circuit performance can be optimized.

As mentioned above, in fully depleted CMOS technology, the threshold voltage is basically determined by the thickness of the thin silicon surface layer. It can be difficult to control during manufacturing. As mentioned above,
Better control of the threshold voltage of individual transistors, or groups of transistors, allows compensation for these process variations. Therefore,
The advantages of fully depleted MOSFET high transconductance and small quasi-threshold swing can be exploited in low voltage circuit devices.

Next, in the method of manufacturing the integrated circuit structure, a preferred method of forming the SOI substrate as shown in FIG. 4 is, for example, the SIMOX method as described in the above-mentioned MacElwee et al. Preferably, commercially available SOI substrate ware is used. For example, in a typical SIMOX process, a normal n-type silicon wafer having a crystal orientation (100) is used to perform phosphorus (n-type) doping of about 10 ¹⁵ cm ⁻³ , and × 10 ¹⁸ cm ^-2 dose, about 150
Oxygen is implanted with an energy of about keV, and the wafer is maintained at a temperature of about 550 ° C.

This wafer was annealed at a temperature of about 1350 ° C. for about 6 hours to give a thickness of 300 nm below the remaining silicon substrate 114, as shown in FIG.
A buried oxide (insulating) layer 116 having a thickness of about 100 nm and a thin single-crystal silicon surface layer 118 having a thickness of about 150 nm that extends above the buried oxide layer 116 are formed (see FIG. 4).

As shown in FIG. 5, after the SIMOX substrate is provided, the thickness of the thin silicon surface layer 118 is reduced to about 80 nm by using a sacrificial oxide layer. This sacrificial layer is etched away. Next, the thickness is 25
A pad oxide 170 of about nm thickness is grown over the entire surface, and a thermally deposited layer of silicon nitride 172 is deposited on the pad oxide 170 with a thickness of about 100 nm. This layer of silicon nitride 172 and pad oxide 170 is photolithographically patterned and selectively removed by etching from field regions 174 intended to provide isolation between active transistors.

Next, the exposed field region 174
Are oxidized in a water vapor containing atmosphere until the thin silicon surface layer 118 in these regions is completely consumed, thereby forming a field oxide layer 124 (see FIG. 6). This latter procedure, which is an example of a Local Oxidation of Silicon (LOCOS) technique known in the prior art, leaves a field oxide layer 124 of approximately 0.2 μm thickness in the unprotected regions. The silicon surface layer 118 remains in the areas protected from oxidation by the layer of silicon nitride 172. This layer of silicon nitride 172 and pad oxide 170 is then etched from the wear surface, leaving the structure shown in FIG.

The structure is then coated with a photoresist mask 176 and patterned to expose the remaining areas of the thin silicon surface layer 118 where the p-channel transistor will be formed, as shown in FIG. Let Phosphorus dose of about 3 × 10 ¹¹ cm ^-2 and 30 ke
Implanted through the photoresist mask 176 with an ion energy of the order of V and n is applied to the surface silicon layer.
Forming the well region 120.

To form the back gate electrode 150 for a p-channel transistor, relatively high energy boron, ie boron having an energy on the order of 200 keV, at a dose of 10 ¹³ cm ^-2 , n-.
Implanted through the same photoresist mask 176 used to form the well region 120. The much higher energy implant penetrates the buried insulating layer 116 to reach the substrate under the back gate electrode 150.

Thicker photoresist is used to determine which areas of the wafer will receive the back gate electrode implant and which will not. In this way there is provided a substrate with a plurality of insulated electrodes provided in the area where the individual transistors are to be formed, or one back gate electrode common to two or more transistors. Can be formed.

According to the result of the simulation using SUPREM3, a small part of the boron ions are n-well region 1.
It has been shown to stay in the thin silicon forming 20 and to some extent compensate for the phosphorus implanted in the previous step. However, most of the implanted boron ions are below the buried oxide as shown in the graph of FIG.

Optionally, n-well region 120
Photoresist mask 1 used to form
76 is removed and then a second photoresist (not shown) is reapplied and patterned to expose only the active channel regions 134 of the transistor, leaving only those regions in the n-well region 120 behind. As a result, the circuit performance can be slightly improved. In that case, the back gate electrode implant would be done through this second photoresist mask.

Such process modifications can optimize the implant regions for the channel and back gate electrodes, respectively, and reduce the capacitance between the source and drain regions of the transistor and the back gate electrode. However, the cost of adding the photolithography process must be paid.

After stripping the photoresist mask (layer) 176, the photoresist is again used to pattern to expose the p-well region 122 in which the n-channel transistor will be formed. These p
The well region 122 is formed by implanting boron with an energy of about 20 keV and a dose of about 3 × 10 ¹¹ cm ⁻² . Next, the back gate electrode 152 for the n-channel has energy of about 200 keV and 10
It is formed by implanting in the exposed area with a dose of ¹³ cm ^-2 .

In order to simplify the process, one method is to use the same photoresist mask used to form the p-well region 122 as a back mask.
There are methods of performing the gate electrode implant. Optionally, as mentioned above, a new photoresist mask is formed by exposing only in the p-well region where active transistor channel region 134 is located (rather than the source and drain regions). And improved circuit performance is obtained.

To enable electrical connection to the back gate electrode implant, photoresist is applied and patterned to form mask 180 (see FIG. 8), then field oxide layer 124 is formed. Openings 182 are created through etching to expose the underlying substrate at specific areas 184 within the back gate electrode implant area where electrical contact is made, as shown in FIG. .

With the photoresist still in place, energy about 20 keV, dose about 3 × 10 ¹⁵ cm ^-2.
Severe boron implant at p ⁺ region 15
1, 153 are produced, where the surface dopant concentration of a portion of the surface area of the back gate electrode implant area 150 is about 10 ²⁰ cm ⁻³ . This latter implant provides a low resistance ohmic contact to the back gate electrode. Each region of the p-type back gate electrode implant is provided with at least one contact for electrical interconnection. At this stage, all photoresist is stripped from the wafer surface, and a 100 nm thick oxide capping layer is blanket deposited.

The implant forming the well region and back gate electrode is then annealed, for example at a temperature of 1000 ° C. for 60 minutes. The anneal cycle should be long enough to allow the thin silicon surface layer 118 n- and p-
-It is important to anneal at a temperature high enough to evenly spread the dopant through the well.

The anneal also contributes to increasing the boron concentration at the interface between the back gate electrode and the buried oxide by up diffusion from the buried implant peak as shown in FIG. This is because the MOS existing on the thin silicon surface layer (film) described above.
Increases the effectiveness of the back gate electrode in controlling the threshold voltage of the FET.

The subsequent process for completing the integrated circuit is the same as the conventional process. The 100 nm thick capping oxide deposited to seal the silicon surface prior to the well and back gate electrode implant anneal is etched away. 20 nm thickness
A degree of gate oxide is thermally grown on the surface of the thin silicon film in each well region.

Next, a thickness of 0.
An undoped polysilicon film of the order of 35 μm is deposited and patterned using photolithography to form the gate electrode for the active transistors. This gate electrode is then doped by implantation as described below (see Figure 8).

Various prior art methods are known for forming source and drain regions for MOSFETs. For example, the straightforward method is
It includes the following steps. Photoresist is applied and patterned to expose only p-channel transistors. Energy about 10 keV, dose about 3 × 1
The p ⁺ source region 130 and drain region 132 are formed using a 0 ¹⁵ cm ^-2 boron implant, and a polysilicon gate electrode 138 for these transistors is formed.
Heavily doped.

The photoresist mask is then removed and a new photoresist layer is applied and patterned to expose only the n-channel transistor. An n ⁺ source region 140 and a drain region 142 are formed for these transistors using a phosphorus implant with an energy of about 20 kev and a dose of about 4 × 10 ¹⁵ cm ⁻² , and n−
The gate electrode 148 of the channel transistor is heavily doped.

After removing this photoresist, the implants used to dope the source, drain and gate regions are activated and the implant damage is subjected to a rapid thermal anneal at a temperature of, for example, about 1050 ° C. for about 30 seconds. Get rid of by.

The remaining steps in this process sequence are to form metal contacts and interconnects for the transistors in the usual manner. As an example,
A layer of silicon oxide film having a thickness of about 100 nm is deposited by a low temperature method, and then a layer of borophosphosilicate glass having a thickness of about 1 μm is formed. After selective masking, openings are made through the oxide and glass to expose the silicon surface where contacts are made to the source, drain, gate and back gate electronic regions.

The photoresist is stripped to a thickness of about 1
A μm aluminum layer is deposited, then photoresist is applied and patterned, and the aluminum layer is etched to remove, for example, first level metal interconnect lines including metal interconnect lines 154, 156, 160 and 162. The connection is formed (see FIG. 2). In this way, contact to the buried electrode can be easily achieved by the interconnect metallization layer used to provide contact to the terminals of the MOSFET.

Optionally, there are also higher level metallization schemes, including, for example, self-aligned silicidation contacts to the source, drain and gate regions of the transistor. If desired, additional dielectric and metallization layers can be subsequently deposited and patterned in known manner, and multilevel interconnect metallization schemes can also be utilized.

The processing steps described above are special for n-type starting substrates. Alternatively,
A lightly doped p-type starting substrate may be used. In the latter case, the process steps described above can also be used to fabricate the back gate electrode structure, provided that the n-type implant, ie phosphorus, is of the order of 500 keV to form the back gate electrode. Energy of 10 ¹³ cm ^-2 is used.

By properly selecting the thicknesses of the buried oxide layer and the silicon surface layer (film), using the back gate electrode structure disclosed herein,
Any known technique for manufacturing an SOI substrate as described above can be used.

The first embodiment described above is a simple n-MOSFET and p-MOS having a back gate electrode.
It includes a FET structure. The process parameters and implant doses and energies are given as examples and many variations of this embodiment are feasible.

Furthermore, this electrode structure is compatible with other known methods of forming MOSFETs, since the back gate electrode is formed during the first stage of processing, ie during the formation of the well region. . The anneal required to disperse the back gate electrode is completed before the implant required for the MOSFET source, drain and gate implants. As a result, there are few process constraints in subsequent steps to form the active device.

Further, the above description relates to the straight forward metallization method. Including self-aligned silicidized contacts to transistor source / drain and gate electrodes, and multilevel interconnects,
Other metallization schemes are also compatible (or compatible) with the structures and processes described above.

In forming the source and drain regions of a transistor according to another embodiment of the present invention, in order to achieve improved performance, if desired,
More advanced techniques are used, for example, incorporating lightly doped drain regions and / or oxide sidewall spacers on the polysilicon gate.

(Second Embodiment) Next, a second embodiment will be described. A part of the integrated circuit according to the second embodiment is shown in FIG. 10, and as in the case of the first embodiment, n
A type semiconductor substrate layer 214, a buried silicon oxide insulating layer 216 and a thin silicon surface layer 218 above it.
And the SOI substrate 212.

This structure is different from the first embodiment in that the p-well region of the substrate 251 is formed, and the n-type back gate electrode 252 is formed inside the p-well region of the substrate 251. Is different. M of the first embodiment
As with OSFET 104, an n-MOSFET 204 is provided that includes source region 240, drain region 242 and channel region 244, gate oxide 246 and polysilicon gate 248.

For example, when implementing a back gate for a MOSFET having a 0.5 μm gate length structure, the thickness of the silicon surface layer 218 is about 50 nm and the thickness of the buried silicon oxide insulating layer 216 is 200 nm.
It is desirable to set it to about nm. The use of such a thin film allows for the implantation of isolated n-type phosphorous back gate electrodes within deeper boron implanted wells, as shown in FIG.

Although only one MOSFET is shown in FIG. 10, this integrated circuit has a corresponding back gate electrode each formed by an n-doped region isolated within the p-well region. Set of n-MOS
It includes a FET and a p-MOSFET. Contact is made to each back gate electrode and p-well region.

Such a structure is advantageous when designing a charge pump circuit for providing a back gate bias to the back gate electrode 252, because the pump is not loaded with the capacitance of the entire substrate. During operation, the substrate is grounded. The p-well is charge pumped to the maximum negative voltage possible. As a result, the back gate electrode can be biased to any positive voltage, or to a negative voltage equal to or less than the intensity applied to the p-well.

In the method of manufacturing the structure of the second embodiment (see FIG. 9), the SOI substrate 212 is formed on the semiconductor substrate layer 2.
14, a buried silicon oxide insulating layer 216 and a silicon surface layer 218 are provided. Embodiment 2
Is advantageous for gate devices of half a micron or less in length that require the relatively thin silicon and buried oxide layers mentioned in the description of the structure according to the second embodiment.

As described above, the p-well region has a high energy p to the substrate layer through the silicon surface layer and the buried insulating layer, as in the case of forming the buried electrode of the first embodiment. -Type implant, i.e. formed by boron. Next, the back gate electrode inside the p-well region is formed by a second high energy ion plant, namely phosphorus, which is an n-type dopant. A contact opening for the back gate electrode and an additional opening for contacting the p-well region is provided through the field oxide insulating layer as described above with respect to Embodiment 1 so that p- A bias can be applied individually to the well region and the back gate electrode.

In a subsequent step, a series of n-channel and p-channel MOS transistors are formed by conventional methods, as described above. Also in this case, since the processing step of forming the well region and the buried electrode is performed before the other steps of active device formation, there are few restrictions in the subsequent processing steps.

Threshold voltage control is well known "double gate"
A method of forming an electrode on the surface of a substrate semiconductor layer, which is provided by a back gate electrode in a similar manner to a CMOS / SOI structure, but extends below the insulating layer is described in the design and manufacture of active devices for integrated circuits. Increases flexibility in. Separate back gate electrodes can be provided to selectively control the threshold voltage of individual transistors or groups of transistors to optimize performance and to compensate for process variations and temperature changes during operation. .

Thus, a particularly advantageous improved control of the threshold voltage can be provided for low voltage (~ 1V) integrated circuit devices. Moreover, the ion-implanted back gate electrode as described above is much easier to manufacture than other known double gate MOSFET structures.

As described above, in the CMOS integrated circuit according to the present invention, the back gate electrode is provided internally in the substrate layer immediately below the n-MOSFET and p-MOSFET below the insulating layer. A CMOS integrated circuit including a MOSFET on a silicon-on-insulator substrate is provided, and fully depleted CMOS technology is used. The individual back gate electrodes are
It may be provided on an individual MOSFET or on a set of MOSFETs to selectively apply different biases to the back gates of the SFETs or groups of MOSFETs. At least different bias is n-MOSFE
Applied to the back gates of T and p-MOSFETs.
In this way, the circuit performance can be optimized by controlling the threshold voltage of individual transistors or groups of transistors. In addition, process variations and other effects that may result in changes in threshold voltage, including changes in temperature during operation, can be compensated for.

Each back gate electrode is provided by a conductive region formed by a heavily doped region in the silicon substrate below the buried insulating layer, ie below the oxide layer. Preferably, each back gate electrode is of opposite doping type to the substrate,
The electrodes can be isolated and bonded from the substrate and from other back gate electrodes on the substrate. As a result, the threshold voltage of one set of MOSFETs formed in the underlying thin silicon film makes an appropriate bias independent of the bias applied to the other set of MOSFETs by making electrical contact to the back gate electrode. Can be controlled by applying. Thus, for example, in a CMOS integrated circuit, one back gate electrode is a set of n-MOSFE.
T can be controlled and the other back gate electrode can control a set of p-MOSFETs. Also,
It is also possible to form individual back gate electrodes for each MOSFET. Thus, individual MOSFE
The threshold voltage of T, or a group of MOSFETs, can be adjusted as needed to optimize circuit performance. This capability is especially beneficial for low power integrated circuits operating at supply voltages below 1V.

It is preferably done in on-chip circuitry, eg by charge pumping or other means, to allow control of the threshold voltage to compensate for factors including process variations and temperature changes during operation. Become. Thus, this structure allows individual control of the threshold voltage of fully depleted MOSFETs formed in CMOS technology using SOI substrates for low voltage devices.

The back gate electrode of this structure is formed on the surface of the starting silicon substrate, that is, the substrate layer directly below the buried insulator layer. This structure therefore differs from the "double gate" SOI MOSFET known in the prior art, in which the back gate is located in the thin silicon surface layer where the source / drain and channel regions of the MOSFET are formed, M
The back gate electrode is provided by a polysilicon layer located inside the insulating layer below the OSFET and is also distinguished from the starting substrate.

Electrical contacts are made to the individual sets of MOSFETs.
Back gate bias can be adjusted,
Each back gate electrode is provided with an electrical contact so that the individual back gate electrodes can be biased, preferably by other parts of the integrated circuit formed in the silicon surface layer. Field isolation in CMOS technology using SIMOX substrates is usually provided by selective oxidation of portions of the silicon thin film using a patterned silicon nitride mask. silicon·
The film is fully oxidized, providing electrical insulation between the areas surrounding the active transistor. The contact to the back gate electrode is usually suitably formed in the selected region through the field oxide layer.

As an option, deep, submicron
In order to form a MOSFET having a gate length, the back gate electrode is formed by greatly reducing the thickness of the silicon layer and the lower buried layer. It is possible to consider the ion plantation of the well region into the substrate underlying the MOSFET. For example, in an n substrate, a p-well region is formed by boron ion implantation, and then an n-type back gate electrode is formed in the p-well region by implantation of an n-dopant, ie phosphorus. To be done. When using such a structure, the substrate is polished and each p-well is pumped to the most negative potential possible. Preferably, when biasing the back gate electrode with charge pumping, the pump circuit is not carried by the capacitance of the entire substrate, but by the capacitance of the p-well.

Further, in the method of forming an integrated circuit on a substrate according to the present invention, it is preferable that the back gate electrode structure is formed at an early stage of manufacturing via the device well region and the buried insulating layer. High energy of dopant
Formed by ion implantation, MOSFE
A heavily doped region is created that extends below the region where the T channel region is to be formed. After annealing to activate the dopant, each heavily doped region provides a conductive region forming a back gate electrode. Next, a MOSFET is formed on the silicon surface layer by a conventional process. Also,
In addition to the usual electrical contacts to the MOSFET source, drain and gate terminals, contacts are also provided to each back gate electrode.

Preferably, the back gate electrode is on the substrate,
It is formed early in the process, prior to the formation of active devices, or MOSFETs.

A thicker photoresist mask is used to determine which areas of the wafer will receive the back gate electrode implants and which will not. It is therefore possible to provide a substrate with a plurality of insulated electrodes formed in the area where each individual transistor is to be formed, or to form one back gate electrode common to two or more transistors. It will be possible.

Since the implanted doped regions are either n-type or p-type, but actually have a conductivity type opposite to the starting silicon substrate, the back gate electrode is from the substrate, and It is insulated and joined from other back gate electrodes formed on the same substrate.

In order to form a deep transistor having a submicron channel length, the silicon layer and the buried insulating layer are sufficiently thin, that is, the silicon layer is formed to a thickness of 20 nm or less and the buried oxide layer is formed to a thickness of 200 nm or less. Therefore, it is practical to ion implant the p-well region of the semiconductor substrate layer and form the n-type buried electrode therein as described above. That is, the well region is formed with a high energy boron implant, and then the phosphorus implant is used to form an n-type gate electrode inside the p-well on the substrate surface. Contact is made to both the back gate electrode and the well region.

In addition, a CMOS on another substrate according to the present invention may be used.
A method of forming an integrated circuit is to form a MOSFET and then provide an appropriately selected back gate bias to individual transistors or groups of transistors to optimize their performance in any circuit application. can do. For example, at least a different bias is applied to the lower back gate electrode implant of the n-channel transistor rather than the lower back gate electrode of the p-channel transistor. Contact to the electrodes is typically conveniently provided from the surface via a conductive bias by a conventional interconnect metallization layer.

A back gate electrode structure placed in the starting silicon substrate and formed by high energy implantation as disclosed herein, comprises:
It is much simpler to manufacture than other known "double gate" structures where the back gate electrode is formed on an insulating layer or a surface silicon layer. Furthermore, since the processing of the back gate electrode is completed at an early stage of the processing step, there are few restrictions in the subsequent processing steps, and M on the SOI substrate is reduced.
Improves compatibility with known CMOS process technology for forming OSFETs.

[Brief description of the drawings]

1 a "double gate" S according to the known prior art
It is sectional drawing which shows a part of structure of the integrated circuit comprised by OI MOSFET structure.

FIG. 2 is a cross-sectional view showing a part of the structure of an integrated circuit according to another known prior art structure.

FIG. 3 is a cross-sectional view showing a part of the structure of the integrated circuit having the MOSFET formed on the SOI substrate and manufactured according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a series of manufacturing steps of the integrated circuit shown in FIG.

FIG. 5 is a cross-sectional view showing a series of manufacturing steps of the integrated circuit shown in FIG.

6 is a cross-sectional view showing a series of manufacturing steps of the integrated circuit shown in FIG.

7 is a cross-sectional view showing a series of manufacturing steps of the integrated circuit shown in FIG.

FIG. 8 is a cross-sectional view showing a series of manufacturing steps of the integrated circuit shown in FIG.

FIG. 9 is a MOSFET manufactured according to the first embodiment.
Produced by high energy ion implantation forming the back gate electrode of
It is a graph which shows the characteristic of dopant boron on a substrate.

FIG. 10 is a cross-sectional view showing a part of the structure of the integrated circuit according to the second embodiment.

[Explanation of symbols]

100 integrated circuit 102 p-MOSFET 104 n-MOSFET 112 SOI substrate 114 silicon substrate 116 buried insulating layer 120 n-well region 122 p-well region 124 field oxide layer 130,140 source region 132,142 drain region 134,144 channel Regions 136,146 Gate Oxide Layers 138,148 Gate Electrodes 150,152 Back Gate Electrodes 151,153 p ⁺ Regions 154,156,160,162 Metal Interconnect Lines 170 Pat Oxide 172 Silicon Nitride 174 Field Regions 176 Photoresist -Mask 204 n-MOSFET 212 SOI substrate 214 Semiconductor substrate layer 216 Buried oxide layer 218 Silicon surface layer 240 Source region 242 Drain region 244 Channel region 246 Gate oxide 248 Polysilicon gate 215 Substrate 252 Back gate electrode

Claims (17)

[Claims] 1. A CMOS integrated circuit on a silicon-on-insulator substrate, comprising a semiconductor substrate layer, a buried insulating dielectric layer, and a silicon surface layer above it, using fully depleted CMOS technology. , A plurality of n formed in selected regions of the silicon surface layer
-MOSFET and p-MOSFET, and at least two back gate electrodes formed by heavily doped regions of the surface of the lower semiconductor substrate layer adjacent to the insulating dielectric layer. One back gate electrode is a pair of p-MOSF
Extends underneath ET and the second back gate electrode extends underneath a set of n-MOSFETs, each back gate electrode applying a bias voltage to each MOSFET. CMOS integrated circuit characterized in that the threshold voltage of each MOSFET of each set is controlled by applying a bias to the corresponding back gate electrode. 2. The CMOS integrated circuit according to claim 1, wherein each set is constituted by an individual MOSFET, and a separate back gate electrode is provided for each individual MOSFET. 3. One set is composed of a group of a plurality of n-MOSFETs, and another set is a plurality of p-MOSFs.
Each p-MOSF consists of ET groups.
The CMOS integrated circuit according to claim 1, wherein a separate back gate electrode is provided for the ET group and each n-MOSFET group. 4. The substrate is of a first conductivity type,
The CMOS integrated circuit of claim 1, wherein each back gate electrode is constituted by a heavily doped conductive region of opposite conductivity type. 5. The substrate is of a first conductivity type,
A second conductive type well region formed therein, wherein each back gate electrode is formed by a first conductive type, heavily doped conductive region formed within the well region. The CMOS integrated circuit according to claim 1, wherein the CMOS integrated circuit is configured. 6. The back gate electrode is provided by a heavily doped region of a doping type opposite to the doping type of the semiconductor substrate, biasing the back gate electrode, 2. The CMOS integrated circuit according to claim 1, wherein the CMOS integrated circuit has a structure in which the back gate electrode is junction-insulated from the substrate. 7. A structure having at least one electrically conductive contact on each back gate electrode through a conductive interconnect metallization layer of the integrated circuit. The COMS integrated circuit according to claim 1. 8. An individual MOSFET formed in the silicon surface layer is insulated by a field oxide layer, and a contact to the back gate electrode extends through the field oxide layer. The CMOS integrated circuit according to claim 1, which is realized. 9. The integrated circuit operates at a voltage of 1 V or less, and the circuit operates the n-MOS during operation of the integrated circuit.
2. The CMO of claim 1, including means for generating the back gate bias in response to changes in FET and p-MOSFET parameters.
S integrated circuit. 10. The back gate bias is formed in the silicon surface layer to a back gate electrode to the back gate electrode via a metal interconnect line.
A CMOS integrated circuit according to claim 9, characterized in that it is generated by a part of said integrated circuit which comprises means for transmitting a bias. 11. The CMOS integrated circuit of claim 10, including charge pumping means for providing the back gate bias. 12. A method of forming an integrated circuit on a silicon-on-insulator substrate including a MOSFET constituted by a back gate electrode, comprising: a semiconductor substrate layer of a first conductivity type; a buried insulating layer; Providing a silicon-on-insulator substrate having a silicon surface layer on the upper side, and forming a heavily-doped conductive region in the substrate layer, through the silicon surface layer, Forming a buried back gate electrode by selectively doping a certain region of the substrate layer by high-energy ion implantation through the buried insulating layer; and spreading over the back gate electrode. Forming a MOSFET in the silicon surface layer, and a bottom side of the MOSFET Method characterized by comprising the steps of forming an electrical contact to Tsu of the MOSFET is constituted by click gate electrode terminal. 13. The method of claim 12, wherein the step of forming the back gate electrode includes the step of forming a heavily doped region of a conductivity type opposite that of the substrate layer. the method of. 14. The step of forming the back gate electrode includes forming a well region of a second conductivity type in the substrate,
Next, forming the back gate electrode in the well region, the back gate electrode being provided in the well region by an insulated first conductivity type selectively doped region. 13. The method of claim 12 including the steps of: providing electrical contact to the well region and the back gate electrode. 15. The step of forming the buried back gate electrode comprises selecting the substrate by high energy implantation of a dopant into the substrate layer through the silicon surface layer and further through the buried insulating layer. Electrically doping and providing a heavily doped region in a region of the substrate adjacent to the insulating layer, and annealing the implant to provide an electrode in a surface region of the substrate layer adjacent to the insulating layer. 13. The method of claim 12 including the step of forming a sexual region. 16. At least forming first and second back gate electrodes, followed by a set of n-MOSFETs extending above said first back gate electrodes in said silicon surface layer. And, forming a set of p-MOSFETs extending above the second back gate electrode, independently controlling the threshold voltages of the n-MOSFET set and the p-MOSFET set. For the purpose of applying a bias, including at least one contact to each of the first and second gate electrodes,
13. The method of claim 12 including the step of contacting the terminals of the -MOSFET and the p-MOSFET. 17. A method of forming a CMOS integrated circuit including an n-MOSFET and a p-MOSFET on a silicon-on-insulator substrate, wherein a semiconductor substrate layer of a first conductivity type and a buried insulating layer above the semiconductor substrate layer. And a step of providing a substrate composed of the crystalline silicon layer on the upper side thereof, and in the substrate layer, by selectively heavily doping a certain region of the substrate layer by ion implantation, Forming a plurality of buried back gate electrodes and forming conductive regions of a second conductivity type,
Thereby junction insulating the electrodes from the substrate, and forming a set of p-MOSFETs and a set of n-MOSFETs on each back gate electrode in the silicon surface layer, whereby each of the Enabling each of the threshold voltages of the p-MOSFETs of the set and the n-MOSFETs of each set to be controlled independently by applying a bias to the corresponding back gate electrode. And how to.