KR100395159B1 - Method of manufacturing a BICMOS device using Si-Ge - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bismos device in which bipolar transistors and CMOS transistors are formed on the same substrate. A method of fabricating a bismos device using silicon germanium is disclosed by forming a base of a bipolar transistor to form a base of a bipolar transistor.

Description

Method for manufacturing a bismos device using silicon germanium {Method of manufacturing a BICMOS device using Si-Ge}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bisMOS device manufacturing method using silicon germanium, and more particularly, to a bipolar transistor based on an epitaxial layer containing germanium (Ge) on a semiconductor substrate and a silicon using germanium to form a CMOS transistor. It relates to a CMOS device manufacturing method.

The BICMOS device, which consists of a bipolar transistor with a fast operating speed and a low-power CMOS transistor, enables the circuit to perform better than using only one type of transistor.

A number of methods are already known for manufacturing BICMOS devices, and most of them are divided into A-type and B-type depending on the number of times polycrystalline silicon is deposited.

1A to 1E are cross-sectional views for explaining a conventional bi-MOS device manufacturing method.

The method of manufacturing the bi-MOSMOS device shown in FIGS. 1A to 1E is A-type, and the gate and the bipolar transistor emitters of the CMOS are formed of polycrystalline silicon through one deposition process and a patterning process. It is done as follows.

Referring to FIG. 1A, an n ⁺ type bipolar buried layer 12 having arsenic (As) implanted into a first region of a P-type semiconductor substrate 11 is formed through a predetermined photolithography process and an ion implantation process. P ⁺ type NMOS buried layer 13 implanted with boron (B) is formed in the second region where the NMOS transistor is to be formed, and n ⁺ type implanted with phosphorus (P) in the third region where the PMOS transistor is to be formed. The PMOS buried layer 14 is formed.

Thereafter, a silicon epitaxial layer (not shown) is deposited to a thickness of about 1000 nm, and a pad oxide film (not shown) and a silicon nitride film (not shown) are sequentially deposited thereon. After depositing the silicon nitride film, a silicon nitride film pattern (not shown) is formed through a predetermined photolithography / etch process. The silicon nitride film pattern remains only in the active region where the device is to be formed and serves to protect the active region from oxidation.

Thereafter, a thermal oxide film 15 having a thickness of about 600 nm is formed in a predetermined region of the semiconductor substrate 11 through a conventional process such as a thermal oxidation process, and the silicon nitride film pattern is removed by wet etching.

After removing the silicon nitride film pattern as described above, the N-type collector 16, the n-well 17, the N ⁺ type collector connection (Plug; 18), and the p-well (19) through a predetermined photolithography process and an ion implantation process ) And P ⁺ type intrinsic base 20. The N-type collector 16, the n-well 17, the N ⁺ type collector connection 18, the p-well 19 and the P ⁺ type intrinsic base 20 are ordered according to the photolithography process and the ion implantation process. It can be formed by changing, and mask sharing using the mask can also be used depending on the conductivity type.

The pad oxide layer is removed by wet etching, and the gate oxide layer 21 is formed through a thermal oxidation process.

On the other hand, ion implantation is performed while the pad oxide film is formed as described above, whereby the N-type collector 16, the n-well 17, the N ⁺ type collector connection 18, the p-well 19, and P ⁺ Unlike the method of forming the intrinsic base 20, the gate oxide film 21 is first formed, followed by a photolithography process and ion implantation to perform the N-type collector 16, the n-well 17, and the N ^+. It is also possible to form the type collector connection 18, the p-well 19 and the P ⁺ type intrinsic base 20. In addition, an ion implantation process for forming the wells 17 and 19 may be performed, followed by an ion implantation process for adjusting the CMOS threshold voltage (V _T ).

Referring to FIG. 1B, a photolithography process and an etching process remove a predetermined region on the P ⁺ -type intrinsic base 20 and a gate oxide layer 21 on the N ⁺ -type collector connection 18 to remove the active region and the polycrystal of the bipolar. Determine the area where silicon will contact.

Referring to FIG. 1C, after the polycrystalline silicon is deposited on the entire surface, the polycrystalline silicon is partially removed through a photolithography / dry etching process, the region where the gate oxide layer 21 is removed, and the n-well 17 and p− The bipolar emitter 23, the bipolar collector electrode 24, the NMOS gate 25 and the PMOS gate 26 are formed by remaining only in a predetermined region above the well 19, respectively.

In this case, a method of making polysilicon into a conductor is an in-situ doping method in which a dopant is injected in a state in which polycrystalline silicon is deposited, or a dopant is injected and heat treated after the deposition of polycrystalline silicon. Method and the like.

Subsequently, phosphorus (P) or arsenic (As) is ion-implanted in the p-well 19 to form an N-type LDD (Lightly Doped Drain) 28a, and boron (B) ions in the n-well 17 region. Is injected to form the P-type LDD 29a.

Referring to FIG. 1D, a low-temperature oxide film is deposited to a thickness of about 200 nm on the entire upper side, and then, by dry etching, the emitter 23 and the collector electrode 24 of the bipolar transistor, the gate 25 of the NMOS, and the PMOS An insulating film 27 is formed on the sidewall of the gate 26. Thereafter, a high concentration of phosphorus or arsenic ions are implanted into the p-well 19 to form an N-type source / drain 28 formed with the N-type LDD 28a, and the n-well 17 and the P ⁺ type. High concentrations of boron are ion-implanted in the intrinsic base 20 to form a P-type source / drain 29 and an extrinsic base 30 formed with the P-type LDD 29a.

After all ion implantation processes have been performed, heat treatment is performed to activate the dopant, in which the emitter 23 and collector electrode 24 of the bipolar transistor, the gate 25 of the NMOS and the gate 26 of the PMOS are formed. The parasitic oxide film 31 is grown to a thickness of about 20 nm.

Referring to FIG. 1E, the parasitic oxide layer 31 is removed by wet etching, and the bipolar emitter 23, the bipolar collector electrode 24, the NMOS gate 25, and the PMOS gate ( 26), the silicide layer 32 is formed on the surfaces of the N-type source / drain 28, the P-type source / drain 29, and the outer base 30. Subsequent back-end processes result in the production of silicon BICMOS devices.

2A to 2E are cross-sectional views illustrating another exemplary embodiment of a conventional bismos device manufacturing method.

The method of manufacturing the bi-MOSMOS device shown in FIGS. 2A to 2E is type B, which forms the gate of the CMOS and the emitter of the bipolar transistor with polycrystalline silicon through two deposition and patterning processes. Is as follows.

FIG. 2A is the same view as FIG. 1A, and the same process steps described with reference to FIG. 1A are equally applied. Therefore, the description of the process steps with respect to FIG. 2A will be omitted. In addition, the same reference numerals will be applied to elements corresponding to FIGS. 1A to 1E.

Referring to FIG. 2A, as in FIG. 1A, an N-type collector 16, an n-well 17, and an N ⁺ -type collector are formed through a photolithography process and an ion implantation process before or after forming the gate oxide film 21. It is possible to form the connection portion 18, the p-well 19 and the P ⁺ type intrinsic base 20, and also to perform the ion implantation process for forming the wells 17 and 19, and then to implant the CMOS threshold voltage. The process may be further performed.

Referring to FIG. 2B, polycrystalline silicon is first deposited on the entire upper part, and then partially removed polycrystalline silicon through a photolithography / dry etching process, and a predetermined region on the n-well 17 and the p-well 19. Only the gates 25 of the NMOS and the gate 26 of the PMOS are formed.

Thereafter, phosphorus or arsenic is ion-implanted in the p-well 19 region to form an N-type LDD, and boron is ion-implanted in the n-well 17 region to form a P-type LDD.

Again, the low-temperature oxide film is deposited to a thickness of about 200 nm on the entire upper side, and then the sidewall insulating layer 27 is formed on the sidewalls of the gate 25 of the NMOS and the gate 26 of the PMOS through dry etching. Subsequently, a high concentration of phosphorus or arsenic is ion-implanted in the p-well 19 to form an N-type source / drain 28 formed with an N-type LDD, and an n-well 17 and a P ⁺ -type intrinsic base ( 20) A high concentration of boron is ion-implanted to form a P-type source / drain 29 and an outer base 30 formed with a P-type LDD.

After the ion implantation process is performed, heat treatment is performed to activate the dopant. At this time, the parasitic oxide layer 31 is grown to a thickness of about 20 nm on the gate 25 of the NMOS and the gate 26 of the PMOS. do.

Referring to FIG. 2C, a predetermined region on the P ⁺ -type intrinsic base 20 and a gate oxide layer 21 on the N ⁺ -type collector connection 18 are removed by a photolithography process and an etching process to remove the active region and the polycrystal of the bipolar. Determine the area where silicon will contact. Thereafter, the secondary polycrystalline silicon layer 33 is formed on the entire top.

Referring to FIG. 2D, a portion of the upper portion of the P ⁺ type intrinsic base 20 where the secondary polycrystalline silicon layer 33 is partially removed through the photolithography / dry etching process and the gate oxide film 21 is removed, and N is removed. ^The secondary polycrystalline silicon layer 33 is left only on the ⁺ type collector connection 18 to form the bipolar emitter 23 and the bipolar collector electrode 24.

Again, a low-temperature oxide film is deposited to a thickness of about 200 nm on the entire upper side, and a sidewall insulating layer 27 is formed on sidewalls of the bipolar emitter 23 and the bipolar collector electrode 24 through dry etching. The parasitic oxide film 31 is simultaneously removed along with the gate oxide film 21 exposed to the n-well and p-well in the front surface etching process for forming the sidewall insulating film 27.

Referring to FIG. 2E, the bipolar emitter 23, the bipolar collector electrode 24, the NMOS gate 25 and the PMOS gate 26, the N-type source / drain 28, through a predetermined process, The silicide layer 32 is formed on the surfaces of the P-type source / drain 29 and the outer base 30. Subsequent back-end processes result in the production of silicon BICMOS devices.

By using the BICMOS device composed of a bipolar transistor having a fast operation speed characteristics and a CMOS transistor having a low power consumption characteristic as described above, it is possible to easily implement a high-performance electronic circuit compared to the case of using one type of transistor.

However, the type B process deposits polycrystalline silicon twice, forms bipolar emitters and CMOS gates by two photolithography processes and dry etching, and performs sidewall forming twice. There exists a problem that productivity falls compared with the case of using a process. On the other hand, the A-type process is simpler than the B-type process, but since the emitter-base junction of bipolar is formed before the source-drain heat treatment of CMOS, it is difficult to control the electric specific control of an independent bipolar transistor due to the effect of heat treatment. There is a problem.

In addition, in order to manufacture a high frequency (RF) integrated circuit, a bipolar transistor constituting a BICMOS device must operate according to a high frequency signal. The manufacturing technology of a silicon bipolar transistor operating in a frequency range of several GHz has reached a technical limit. to be.

Therefore, in order to solve the above problems, the base of the bipolar transistor is formed by depositing a silicon germanium epitaxial layer having a higher carrier mobility than silicon by chemical vapor deposition (CVD) or molecular beam deposition (MBE) on the lower collector. Accordingly, an object of the present invention is to provide a bismos device manufacturing method using silicon germanium, which can solve the above disadvantages.

According to the bismos device manufacturing method using silicon germanium according to the present invention for achieving the above object is a device isolation film, a bipolar collector, a collector connection, n-well and p-well are formed on the semiconductor substrate through a predetermined process, respectively Forming a gate oxide film on the n-well and p-well semiconductor substrates in a state, sequentially forming an epitaxial layer containing germanium and a low temperature oxide film on the whole, and a predetermined region of the collector and a collector connection portion removing the low temperature oxide film on the n-well and p-well, removing the epitaxial layer of the collector connection, and then forming a conductive layer on the entire upper surface, and forming the conductive layer on the n-well and p-well. By simultaneously patterning the epitaxial layer, an emitter is formed on a predetermined region of the collector, an electrode is formed on the collector connection, and a gate is formed on the predetermined region of the n-well and p-well. Removing the exposed gate oxides on the n-well and p-wells, and implanting impurities into the epitaxial layer through an impurity ion implantation process to the outer region of the remaining region of the collector where no emitter is formed. Forming a low concentration impurity region in the n-well and the p-well,

Forming an insulating film on the sidewalls of the conductive layer, leaving only the epitaxial layers in the upper and peripheral regions of the collector to form an external base electrode consisting of an epitaxial layer, and source of LDD structures in the n-well and p-well / Forming a drain.

In addition, according to another embodiment of the method for manufacturing a bismos device using silicon germanium according to the present invention, a device isolation film, a bipolar collector, a collector connection part, an n-well, and a p-well are respectively formed on a semiconductor substrate through a predetermined process. Forming an oxide film on the bipolar collector, the collector connection, the n-well and p-well semiconductor substrates, forming a PMOS transistor in the n-well, forming an NMOS transistor in the p-well, the collector and Removing the oxide film on the collector connection, forming a base consisting of an epitaxial layer containing germanium in the peripheral region including the upper part of the collector, depositing a low temperature oxide film on the entire upper surface, and then a predetermined region and the collector of the base. Removing the low temperature oxide layer on the connection portion, forming a conductive layer on the entire upper surface, and then patterning the bay to remove the low temperature oxide layer An emitter is formed on a predetermined region of the electrode, and an electrode is formed on the collector connection portion; an external base is formed on the collector of the region in which the emitter is not formed by removing impurity ions after removing the low temperature oxide film; And forming a sidewall insulating film on the sidewalls of the electrodes on the emitter and collector connections.

The epitaxial layer is formed of a silicon germanium mixture, and further comprising forming a silicide layer on the gate and the source and drain of the transistor, the conductive layer and the base after forming the sidewall insulating film. It is done.

1A to 1E are cross-sectional views illustrating a conventional bi-sMOS device manufacturing method.

2A to 2E are cross-sectional views illustrating another embodiment of a conventional bi-sMOS device manufacturing method.

3A to 3I are cross-sectional views of a device for explaining a bismos device manufacturing method using silicon germanium according to the present invention.

4A to 4I are cross-sectional views of devices for explaining another embodiment of a bismos device manufacturing method using silicon germanium according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 41, 71: semiconductor substrate 12, 42, 72: n ⁺ type bipolar buried layer

13, 43, 73: NMOS buried layer of p ⁺ type 14, 44, 74: n ⁺ type buried layer of the PMOS

15, 45, 75, 84: thermal oxide film 16, 46, 76: N-type collector

17, 47, 77: n-well 18, 48, 78: N ⁺ type collector connection

19, 49, 79: p-well 20: P ⁺ type intrinsic base

21, 50, 80: gate oxide film 23, 54, 91: bipolar emitter

24, 55, 92: bipolar collector electrode

25, 56, 82: gate of NMOS 26, 57, 83: gate of PMOS

27, 61, 87, 94: sidewall insulating films 28a, 58a, 85a: N-type LDD

28, 58, 85: N-type source / drain 29a, 59a, 86a: P-type LDD

29, 59, 86: P-type source / drain 30, 60, 93: External base

31: parasitic oxide film 32, 63, 95: silicide layer

33: 2nd polycrystalline silicon layer 51, 51a, 88: silicon germanium epitaxial layer

52, 89: low temperature oxide film 53: polycrystalline silicon layer

62, 88a: external base electrode 81: first polycrystalline silicon layer

In order to implement a high frequency (RF) integrated circuit, a bipolar transistor constituting a BICMOS device must operate according to a high frequency signal. However, the current technology of manufacturing silicon bipolar transistors operating in the frequency range of several GHz has reached technical limits. The solution to this problem is to use materials such as compound semiconductors or silicon germanium of the III-V group, which have higher carrier mobility than silicon.

Germanium has electrical characteristics with a smaller energy band gap than silicon, and the lattice constant of germanium is similar to that of silicon, and it is possible to mix the two materials in an appropriate ratio while maintaining crystallinity. Therefore, silicon germanium, which is a mixture of silicon and germanium, has a smaller energy band gap than silicon and maintains crystallinity when grown on a silicon substrate. When the silicon germanium is used as the base of the bipolar transistor, it is possible to manufacture a bipolar transistor having a faster operating speed and a larger current gain than the conventional silicon bipolar transistor.

Silicon germanium bipolar is easy to produce carriers due to small energy band gaps, and the mobility of carriers is increased by additionally generated electric fields according to energy band gaps that change in proportion to the silicon-germanium mixture ratio, thereby providing excellent electrical characteristics. Have Accordingly, silicon germanium BICMOS devices including silicon germanium bipolar enable the implementation of high frequency (RF) integrated circuits as compared to silicon BICMOS devices.

In addition, the silicon germanium BICMOS device can be manufactured by applying a conventional silicon semiconductor process unlike other compound semiconductors in terms of the manufacturing process, and the BICMOS device is manufactured with a minimum process change that adds a silicon germanium epitaxial growth process. It has the advantage to do it. In order to fabricate the silicon germanium BICMOS device having the above characteristics, a silicon germanium epitaxial layer is deposited separately on the lower collector by chemical vapor deposition (CVD) or molecular beam deposition (MBE) to form a base of a bipolar transistor. In addition, the doping of the thin layer of silicon germanium uses a method of implanting dopants at the same time as deposition, not ion implantation. Since the silicon germanium layer serves as a base and must be electrically insulated from other parts, a pattern is formed through a photolithography process and dry etching.

Meanwhile, the conventional silicon BICMOS fabrication technique, as shown in FIGS. 1A-1E and 2A-2E, injects a P-type dopant into an N-type epitaxial layer to form an intrinsic base. However, when germanium is added to a silicon layer already formed and doped by the conventional ion implantation method to form an intrinsic base, it is difficult to add germanium at a high concentration, and it is impossible to control the germanium concentration within a thin thickness base. Accordingly, the present invention provides a method for fabricating a BICMOS device in which a single crystal silicon germanium epitaxial layer is grown from a silicon collector and used as a base, but does not cause a change in CMOS characteristics.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3I are cross-sectional views of a device for explaining a bismos device manufacturing method using silicon germanium according to the present invention, which is a cross-sectional view illustrating a continuous manufacturing step of a silicon germanium BICMOS device using one type of polycrystalline silicon layer. to be.

Referring to FIG. 3A, a thermal oxide film (not shown) is formed on the P-type semiconductor substrate 41 to a thickness of about 40 nm, and then the P-type semiconductor substrate 41 is formed through a predetermined photolithography process and an ion implantation process. An n ⁺ type bipolar buried layer 42 in which arsenic (As) is implanted is formed in the first region, and a p ⁺ type NMOS buried layer 43 in which boron (B) is implanted in the second region where the NMOS transistor is to be formed. ), And an n ⁺ type PMOS buried layer 44 implanted with phosphorus (P) is formed in the third region where the PMOS transistor is to be formed.

Thereafter, heat treatment is performed for about 120 minutes at a temperature of about 1000 ^° C. to activate dopants injected into the buried layers 42, 43, and 44 and diffuse over a wide area (drive-in process).

After the heat treatment, the thermal oxide film is removed by wet etching, a silicon epitaxial layer (not shown) is deposited, and a pad oxide film (not shown) is formed on the epitaxial layer surface with a thickness of about 40 nm. After performing a photolithography process and implanting boron or BF ₂ to form a P ⁺ type isolation region (Isolation and channel stop (not shown)) at a predetermined depth of the semiconductor substrate 41 except the active region, A silicon nitride film (not shown) to a thickness of about 160 nm. After depositing the silicon nitride film, a photolithography / dry etching process is performed to form a nitride film pattern for determining a region in which the device isolation film is to be formed.The thermal oxide film 45, which is a device isolation film, has a thickness of about 600 nm through a thermal oxidation process. After forming, the nitride layer pattern is removed by wet etching.

After the silicon nitride film pattern is removed, an N-type collector 46, an n-well 47, an N ⁺ type collector connection (Plug 48), and a p-well 49 are formed through a predetermined photolithography process and an ion implantation process. do. The N-type collector 46, the n-well 47, the N ⁺ type collector connection portion 48 and the p-well 49 may be formed by changing the order according to the photolithography process and the ion implantation process. In some cases, mask sharing using duplicate masks is possible. In the ion implantation process, arsenic or phosphorus for N-type and boron or BF ₂ for P-type are implanted.

It is also possible to perform all or part of the above photolithography process and ion implantation process before the silicon nitride film deposition. That is, a pad oxide film (not shown) is formed to a thickness of about 40 nm, a photolithography process and an ion implantation process are performed, and a nitride film pattern is formed to a thickness of about 160 nm, and the thermal oxide film 45 is formed to a thickness of about 600 nm. After forming, the photolithography process and the ion implantation process may be performed while the nitride film pattern is removed by wet etching. When the process is performed in the above-described order, the dopants implanted with ion prior to the thermal oxide film 46 are appropriately drive-in during the thermal oxidation process.

In addition, in the case where an ion implantation process for forming the wells 47 and 49 is performed, the pad oxide layer is removed by wet etching after performing the CMOS implant voltage adjustment process, and the gate oxide layer 50 is removed through a thermal oxidation process. Form.

3A differs from the conventional FIGS. 1A and 2A in that the intrinsic base of P ⁺ type formed by ion implantation is not formed in the present invention.

Referring to FIG. 3B, only the N-type collector 46 and the N ⁺ type collector connection portion 48 are exposed through a photolithography process, and then the gate oxide layer 50 is removed by performing dry etching or wet etching.

Referring to FIG. 3C, a silicon germanium epitaxial layer 51 having a thickness of 50 to 200 nm is formed on the whole by CVD or MBE. The germanium concentration in the silicon germanium epitaxial layer 51 has an arbitrary value between 0% and 100%, and is adjusted according to the position. The silicon germanium epitaxial layer 51 has an N-type collector because boron is doped at the same time as the deposition. (46) Form a true base of P ⁺ conductivity at the top. A low temperature oxide film 52 is deposited on the silicon germanium epitaxial layer 51 by CVD.

Referring to Figure 3d, the photolithography process and remove the N-type collector 46 is given in the upper region and the N ⁺ type collector connection 48 of the upper low-temperature oxide film (52) through the dry etching process, the emitter and collector electrodes Confirm the area to be formed. At this time, the low temperature oxide film 52 formed in the n-well 47 and the p-well 49, which are active regions of the CMOS, is also removed.

Thereafter, the silicon germanium epitaxial layer 51 formed on the N ⁺ type collector connection part 48 is removed through a photolithography process and a dry etching process.

Referring to FIG. 3E, the polysilicon layer 53 is formed to a thickness of about 150 to 400 nm. In the process of depositing polycrystalline silicon, a dopant is implanted or ion implantation is performed after deposition to make the polycrystalline silicon layer 53 a conductor layer.

Referring to FIG. 3F, a portion of the polycrystalline silicon layer 53 and the silicon germanium epitaxial layer 51 are removed through a photolithography process and dry etching, and the exposed low-temperature oxide film 52 and the gate oxide film 50 are continuously exposed. Some are removed by dry etching to form the bipolar emitter 54, the bipolar collector electrode 55, the NMOS gate 56 and the PMOS gate 57. Since the low-temperature oxide film that previously existed in the active region of the CMOS was removed, the silicon germanium epitaxial layer 51 covering the active region of the CMOS was simultaneously removed during the dry etching process of the polycrystalline silicon layer 53 and the NMOS. And only under the PNOS gate electrodes 56 and 57. Although the work function of the gate electrodes 56 and 57 is changed by the silicon germanium epitaxial layer 51 and doped boron is diffused through the gate oxide film, the threshold voltage of the CMOS device may be changed. By adjusting the ion implantation conditions for adjusting the threshold voltage of the desired threshold voltage can be obtained.

The silicon germanium epitaxial layer 51 in the bipolar transistor region is protected from the dry etching of the polycrystalline silicon layer 53 because the low temperature oxide film 52 is present thereon. The thermal oxide film 45 is protected from dry etching of the low temperature oxide film 52 by the silicon germanium epitaxial layer 51.

Thereafter, the N-type LDD 58a, the P-type LDD 59a, and the outer base 60 are formed through the photolithography process and the ion implantation process. At the same time as the external base 60 is formed, a dopant is ion-implanted into the part of the silicon germanium epitaxial layer 51a to serve as an external base electrode after a subsequent process.

The order of the photolithography process and the ion implantation process can be changed, and the mask can be shared depending on the conductivity type. In the ion implantation process, arsenic or phosphorus for N-type and boron or BF ₂ for P-type are used. In order to prevent channeling and damage of the thin film due to ion implantation, a low temperature buffer oxide layer may be deposited before ion implantation to a thickness of about 40 nm.

Referring to FIG. 3G, a low-temperature oxide film having a thickness of about 200 nm is deposited by CVD and subjected to dry etching, so that the bipolar emitter 54, the bipolar collector electrode 55, the NMOS gate 56, and the PMOS gate ( A sidewall insulating film 61 is formed on the sidewall of 57. Thereafter, the silicon germanium epitaxial layer on the thermal oxide layer 45 is removed through a photolithography process and dry etching, and only the silicon germanium epitaxial layer on the upper and peripheral regions of the collector 46 is left, thereby forming a silicon germanium epitaxial layer. The external base electrode 62 is formed. Again, phosphorus or arsenic is ion implanted into the p-well 49 through a photolithography / ion implantation process to form an N-type source-drain 58, and the n-well 47 is implanted with boron or BF ₂ . Thus, the P-type source-drain 59 is formed.

Referring to FIG. 3H, after all ion implantation processes are performed, heat treatment is performed to activate the dopant. Subsequently, wet etching is performed to remove the parasitic oxide layer, and then Ti / TiN (not shown) is deposited, and the first heat treatment is performed to emitter 54 of bipolar, collector electrode 55 of bipolar, and gate 56 of NMOS. ), High-resistance Ti silicide having a specific resistance of about 60 to 70 uΩcm is formed on the surfaces of the gate 57 and the external base electrode 62 of the PMOS. Thereafter, the Ti / TiN remaining unreacted on the oxide film is removed by wet etching, and the second heat treatment is performed to form a low-resistance Ti silicide layer 63 having a resistivity of about 15 to 20 µΩcm.

Although not shown in the drawing, a back-end process of forming a contact, a metal layer, and a pad finally results in a silicon germanium BICMOS device.

The fabrication of the silicon germanium BICMOS device in the above-described manner has the advantage of simplifying the process, but since source-drain heat treatment is performed after the emitter is formed, the dopants of the emitter and the base diffuse during heat treatment, thereby deteriorating the characteristics of the bipolar transistor. Can be.

On the other hand, if the bipolar transistor is manufactured by performing a source-drain heat treatment and depositing a silicon germanium epitaxial layer, the process becomes complicated, but it is possible to prevent a change in the characteristics of the bipolar transistor.

Hereinafter, a bismos device manufacturing method using silicon germanium according to the above method will be described in detail.

4A to 4I are cross-sectional views of devices for explaining another embodiment of a bisMOS device manufacturing method using silicon germanium according to the present invention.

Referring to FIG. 4A, FIG. 4A is a cross-sectional view of the same device as that of FIG. 3A, and the process steps described with reference to FIG. 3A are equally applied. Therefore, the description of the process steps with respect to FIG. 4A will be omitted.

Referring to FIG. 4B, a first polycrystalline silicon layer 81 for forming a gate is formed on the gate oxide film 80 to a thickness of 150 to 400 nm.

Referring to FIG. 4C, the first polycrystalline silicon layer 81 is etched through a photolithography process and dry etching to form a gate 82 of the NMOS on the p-well 79 and the n-well 77. The gate 83 of the PMOS is formed. On the surfaces of the gates 82 and 83, thermal oxide films 84 are formed to a thickness of about 10 nm to remove damages and impurities on the silicon surface generated during dry etching.

Subsequently, phosphorus or arsenic is ion-implanted into the p-well 79 to form an N-type LDD 85a through photolithography, and boron or BF ₂ is ion-implanted to the n-well 77 to form a P-type LDD ( 86a).

Referring to FIG. 4D, a low temperature oxide film is deposited to a thickness of about 200 nm through a CVD process, followed by dry etching to form sidewall insulating layers 87 on sidewalls of the gates 82 and 83. Thereafter, a thermal oxide film (not shown) is again formed on the entire upper portion with a thickness of about 10 nm to supplement the thickness of the etched gate oxide film 80. P-well 79 is ion-implanted with phosphorus or arsenic to form an N-type source / drain 85 through photolithography, and P-type source is ion-implanted with boron or BF ₂ in the n-well 77. After forming / drain 86, heat treatment is performed to activate the dopant of the source-drain. In this way, a CMOS transistor is manufactured.

Referring to FIG. 4E, a photolithography process is performed and the gate oxide layer on the N-type collector 76 and the N ⁺ -type collector connection 78, which are active regions of the bipolar transistor, is removed by dry etching or wet etching, and the entire upper portion is removed. The silicon germanium epitaxial layer 88 is formed in a method such as CVD or MBE. The silicon germanium epitaxial layer 88 on the N-type collector 76 serves as a base as a P ⁺ type conductor.

Referring to FIG. 4F, the silicon germanium epitaxial layer 88 is left in the peripheral region including the upper portion of the collector 76 through a photolithography process and dry etching to determine the base region as the silicon germanium epitaxial layer 88. Thereafter, the low temperature oxide film 89 is deposited on the entire surface using CVD, and the low temperature oxide film on the N ⁺ type collector connection portion 78 and the predetermined region on the N type collector 76 is removed through a photolithography process and dry etching. To determine the area where the emitter and collector electrodes are to be formed.

Referring to FIG. 4G, a second polycrystalline silicon layer is formed on the whole with a thickness of 150 to 400 nm. In the process of forming the second polycrystalline silicon layer, the dopant is implanted or the dopant is ion implanted after deposition to make the second polycrystalline silicon layer a conductor. Thereafter, the second polycrystalline silicon layer is left only on the predetermined region and the N ⁺ type collector connection portion 78 above the N-type collector 76 through a photolithography process and dry etching, and the low-temperature oxide film 89 is continuously subjected to dry etching. Is removed to form the emitter 91 and collector electrode 92 composed of the second polycrystalline silicon layer. Thereafter, a photolithography process is performed and boron or BF ₂ is injected to simultaneously form the external base electrode 88a and the external base 93.

Referring to FIG. 4H, a low-temperature oxide film having a thickness of about 200 nm is deposited on the entire surface by a CVD method, and dry etching is performed to form a sidewall insulating film 94 on the emitter 91 and the collector electrode 92. At this time, in the process of performing dry etching to form the sidewall insulating film 94, the thermal oxide film 84 on the gates 82 and 83 is also simultaneously removed.

Compared with FIG. 4H and FIG. 3H, the process is almost similar, but in this process, there is a feature that a silicon germanium epitaxial layer does not exist below the gate electrodes 82 and 83.

Referring to FIG. 4I, Ti / TiN (not shown) is deposited and subjected to a first heat treatment to emitter 91 of bipolar, collector electrode 92 of bipolar, gate 82 of NMOS, and gate 83 of PMOS. And a high resistance Ti silicide having a specific resistance of about 60 to 70 uΩcm on the surface of the external base electrode 88a. After that, the Ti / TiN remaining unreacted on the oxide film is removed by wet etching, and the second heat treatment is performed to form a low-resistance Ti silicide layer 95 having a specific resistance of about 15 to 20 µΩcm.

Although not shown in the drawing, a back-end process of forming a contact, a metal layer, and a pad finally results in a silicon germanium BICMOS device.

As described above, the present invention has the effect of increasing the operation speed of the bipolar transistor included in the BICMOS device by manufacturing the BICMOS device using silicon germanium having high carrier mobility as a base layer. The introduction of this new base layer does not cause changes in the characteristics of conventional CMOS transistors. Accordingly, the present invention enables the implementation of high frequency (RF) integrated circuits operating in the high frequency region by maintaining the inherent characteristics of the CMOS transistor included in the BICMOS device and improving the performance of the bipolar transistor.

Claims (6)

Forming a gate oxide film on the n-well and p-well semiconductor substrates in a state in which a device isolation film, a bipolar collector, a collector connection part, n-wells and p-wells are formed on the semiconductor substrate through a predetermined process; , Sequentially forming an epitaxial layer and a low temperature oxide film including germanium on the entire upper portion; Removing the low temperature oxide film on a predetermined region of the collector, the collector connection, the n-well and the p-well; Removing the epitaxial layer of the collector connection and then forming a conductive layer on the entire upper surface; By simultaneously patterning the conductive layer and the epitaxial layer formed on the n-well and the p-well, an emitter is formed on a predetermined region of the collector, an electrode is formed on the collector connection, and the n-well and p -Forming a gate in a predetermined region of the well, Removing the exposed gate oxide layer on the n-well and p-well, Implanting impurities into the epitaxial layer through an impurity ion implantation process to form an external base in the remaining region of the collector where the emitter is not formed, and forming a low concentration impurity region in the n-well and p-well Wow, Forming an insulating film on sidewalls of the conductive layer; Leaving only the epitaxial layer in the upper and peripheral regions of the collector to form an external base electrode comprising the epitaxial layer; And forming a source / drain of an LDD structure in the n-well and p-well. The method of claim 1 And forming a silicide layer on the conductive layer and the epitaxial layer after the source / drain of the LDD structure is formed. The semiconductor substrate of the bipolar collector, the collector connecting portion, the n-well and p-well in a state in which a device isolation film, a bipolar collector, a collector connection part, an n-well and a p-well are formed on a semiconductor substrate through a predetermined process, respectively. Forming an oxide film on the substrate, Forming a PMOS transistor in the n-well and forming an NMOS transistor in the p-well; Removing the oxide film on the collector and the collector connection, Forming a base composed of an epitaxial layer containing germanium in a peripheral region including an upper portion of the collector; Depositing a low temperature oxide film on the entire upper surface, and then removing the low temperature oxide film on a predetermined region of the base and the collector connection portion; Forming a conductive layer on the entire upper surface and then patterning the emitter on a predetermined region of the base from which the low temperature oxide film is removed, and forming an electrode on the collector connection; Forming an external base on the collector of the region where the emitter is not formed by removing impurity ions and removing the low temperature oxide film, and forming an external base electrode on the exposed base; And forming a sidewall insulating film on the sidewalls of the electrodes on the emitter and collector connections. The method according to claim 1 or 3, The epitaxial layer is a bismos device manufacturing method using silicon germanium, characterized in that consisting of a silicon germanium mixture. The method of claim 3, wherein A sidewall insulating film is formed on the sidewalls of the electrodes on the emitter and collector connections, and the thermal oxide film on the gate of the NMOS transistor and the PMOS transistor is simultaneously removed. The method of claim 3, wherein And forming a silicide layer on the gate and the source / drain, the conductive layer, and the base of the transistor after the sidewall insulating film is formed.