KR930010118B1 - Making method of semiconductor device - Google Patents

Abstract

The semiconductor device is mfd. by (a) forming an epitaxial layer on the semiconductor substrate, and then forming an active region of a bipolar transistor and an well of a MOSFET on the surface, (b) forming an impurity diffusing region by additionally implanting a first conductive impurity into an emitter-forming region in the active region of the bipolar transistor, (c) diffusing the impurity by the heat oxidation process, (d) forming a base region by implanting a second impurity into the active region, and (e) removing the impurity diffusing region contacted with a bottom boundary of the base region. The semiconductor device has an improved high frenquency characteristic and current driving power.

Description

Manufacturing Method of Semiconductor Device

1A to 1C are cross-sectional views showing a BICMOS fabrication method having a second buried layer in a bipolar portion.

2 is a vertical sectional view showing a BICMOS in which an impurity concentration is increased by an ion implantation method in a region where a base region and a collector region are in contact with each other.

3A to 3J are cross-sectional views showing a BICMOS manufacturing method according to the present invention.

4A to 4B are graphs showing a profile of impurity concentrations depending on the depth of the epitaxial layer.

5 is a graph showing changes in bratedown voltage, current driving force, and cutoff frequency according to the depth of the epitaxial layer.

* Explanation of symbols for main parts of the drawings

10: semiconductor substrate 42: Well

44 P well 26 emitter area

300: impurity diffusion region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a bipolar transistor and a MOS field effect transistor are formed on the same semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor device capable of realizing a high performance bipolar transistor and a MOS field effect transistor.

Semiconductor integrated circuit devices (hereinafter referred to as BICMOS LSIs) that form other semiconductor devices on one semiconductor substrate, for example, bipolar transistors (BJTs) and complementary MOS transistors (CMOS), have been tried since 1969. (IEEE, Trans, Electron Devices, Vol.DE-16, No. 11, P945-951, 1969, 11)

The advantage of BICMOS LSI is that the advantages of high speed, high driving ability, high performance analog circuit of bipolar integrated circuit and low power consumption, high integration of CMOS integrated circuit can be realized on the same board. It is accepted as technology.

In order to best realize the above advantages of the BICMOS LSI, it is designed to take full advantage of its components, but without sacrificing the advantages of other components in order to take advantage of some of the components. You must design. In general, when an event that acts as an advantage and an event that acts as a disadvantage exists at the same time, the facts are adjusted to an appropriate state, and the facts and disadvantages of the events are excessively shifted to one side by the fact. In order to avoid the hitting, the overall effect can be obtained. In this case, the adjustment process is referred to as "trade off". For example, in BICMOS, bipolar transistors and MOS field effect transistors can be applied to the above mentioned events.

In BICMOS, in which bipolar transistors and MOS field effect transistors are formed on one substrate, a method of improving the characteristics of bipolar transistors without degrading the performance of MOS field effect transistors is proposed as a method for manufacturing high performance BICMOS, which is a bipolar transistor. It is possible by changing the thickness and impurity concentration of the collector region among the three regions of the transistor, that is, the emitter, base and collector regions.

The present invention describes the production of high performance BICMOS by the above two methods, namely, the method of changing the thickness of the collector region of the bipolar transistor and the method of changing the impurity concentration of the collector region.

The above two equations describe the electrical characteristics of the NPN bipolar transistor and relate to the device propagation time of the carrier and the electric field in the base region. In Equation (1), τt is the device travel time of the carrier, Dn is the diffusion coefficient of electrons, and Wb is the thickness of the base region. In Equation (2), ε (xn) is the electric field of the base region. (xn is the arbitrary distance between the base region in contact with the emitter region and the base region in contact with the collector region), K is the Boltzmann constant, T is the absolute temperature, q is the charge amount, a is Is the number of acceptors in contact with the emitter area, N (Wb) is the number of acceptors in contact with the collector area), and Wb is the thickness of the base area.

Looking at the above equations (1) and (2), it can be seen that the device travel time of the carrier is proportional to the square of the thickness of the base area, and the electric field of the base area is inversely proportional to the thickness of the base area. The inverse determines the high frequency characteristics of the bipolar transistor, and the magnitude of the electric field is related to the current driving force of the bipolar transistor. In the above two equations, it can be seen that as the thickness Wb of the base region decreases, the high frequency characteristics and current driving force of the bipolar transistor are improved.

The thickness of the base area must be maintained at a suitable thickness by various factors, such as breakdown voltage, punchthrough, capacitance between the emitter and the base, and capacitance between the base and the collector. Even if the device is manufactured with a predetermined thickness off), there is a case where the predetermined thickness is expanded by a base pushout phenomenon.

The base push-out occurs when the density of the multiple carriers injected from the base region to the collector region is comparable with the impurity concentration of the collector when the bipolar transistor is electrically conducting by applying a specific voltage to the bipolar transistor. The electric field region acting between and the collector region is diffused toward the collector region, which induces high-level injection (HLI) of electrons and holes into the collector region.

(Kirk effect)

Jc = qVs (Nc + 2εsVc / qWc ² ) --------------------- (3)

Equation (3) relates to the critical current density (Jc) that causes the base expansion phenomenon due to the high injection of electrons and holes, where Wc is the thickness of the effective epitaxial layer, that is, the N ⁺ buried layer in the base-collector junction. It is up to the thickness. In order to increase the critical current density Jc in the above Equation (3), it may be estimated that the thickness of Wc, that is, the effective epitaxial layer, or the concentration of impurities in the Nc, the collector region, should be increased.

5 shows the high frequency characteristics, current driving force, and breakdown voltage characteristics of the bipolar transistor according to the thickness change of the effective epitaxial layer, and as the thickness of the epitaxial layer is thinned, the high frequency characteristic (current gain bandwidth f _T ) and the current driving force are shown. It can be seen that (I _K ) can be improved. Therefore, in order to manufacture a high performance bipolar transistor, the impurity concentration of the collector region is determined so that the minimum base region thickness is determined under a breakdown voltage and the thickness of the determined base region is not expanded by the above-described HLI (high injection of electrons and holes). And the thickness of the effective epitaxial layer.

In this case, the impurity concentration and the thickness of the effective epitaxial layer should be a value that is not traded off against the capacitance, resistance and breakdown voltage of the collector region as well as HLI.

In the case of the BICMOS in which the bipolar transistor and the MOS field effect transistor are formed on the same substrate, a series of requirements for manufacturing the high-performance bipolar transistor described above are subject to various restrictions in the manufacturing method, which impurity concentration in the collector region. This is because the increase and the decrease in the thickness of the effective epitaxial layer increase the substrate effect and the S / D (source / drain) capacitance in the MOS field effect transistor, leading to deterioration of the characteristics thereof.

1A-1C and 2 relate to a high performance BICMOS fabricated in a manner that accommodates a series of requirements for improving the electrical properties of a bipolar transistor while not degrading the properties of a MOS field effect transistor.

First, FIGS. 1A to 1C show a method of reducing the thickness of the effective epitaxial layer of the bipolar portion, and refer to the application of Hitachi, Japan, in 1983 (priority recommendation 1983. 3. 28, 83) -53077) will be described.

FIG. 1A shows a first N tongue buried layer (surface concentration 10 ¹⁹ / cm 3) 12 having high concentration by antimony (As) on one surface of P-type semiconductor substrate 10, and P type by boron B A buried layer (surface concentration 10 ¹⁸ / cm 3) 14 is selectively formed. Subsequently, a thin oxide film 16 (thickness 1000Å) is formed, and then a phosphorus (P) ion is implanted into the vertical lower end of the emitter region of the bipolar transistor using the photoresist film 18 as a mask. An N-type buried layer 100a is formed. At this time, the phosphorus ion is injected at a concentration of 1 × 10 ¹⁴ / cm 2 with energy of 100KeV.

Referring to FIG. 1B, after the ion implantation, heat treatment is performed at 1000 ° C. for 30 minutes, and the N-type epitaxial layer 40 is formed to a thickness of 2.5 μm, and the P-type well layer 20 is formed again. As shown in the figure, the impurity concentration of the epitaxial layer 40 is 5 × 10 ¹⁵ cm 2, and the formation of the P well layer 20 is 1 × 10 ¹⁶ / cm 3 by implantation of boron (B) ions. .

FIG. 1C shows the BICMOS completed through the formation of the epitaxial layer 40 and the P well layer 20, followed by a conventional CMOS forming process and a bipolar transistor having an epitaxial process using the polycrystalline silicon 84. The heat treatment of the entire process after the textural growth is about 70 minutes at 1000 ° C, and the second N-type buried layer 100a diffuses upward from the first N-type buried layer 12 by this heat treatment. The diffusion coefficient of antimony and phosphorus at a substrate temperature of 1000 ° C. differs from the former by 3 × 10 ⁻² (μm / hr ^1/2) and the latter by 1 × 10 (μm / hr ^1/2 ).

Therefore, the depth of the second N-type buried layer 100 by phosphorus (P) is about 1 탆 shallow by the first N-type buried layer 12 by antimony (As), and the depth from the surface is 0.6. It becomes micrometer. Since the result f _T can be confirmed that the increase in the 3.5GHz to 5.0GHz, the thickness of the epitaxial layer portion of the MOS transistor is an NPN bipolar transistor as the MOS transistor due to the increase of junction capacitance due to the reduced thickness of the epitaxial layer The frequency characteristics and current driving power of bipolar transistors can be improved without deterioration of the characteristics, enabling high performance BICMOS.

In FIGS. 1A to 1C, the unexplained symbols are omitted because they are not essential in describing the method, but they are obviously understood by those skilled in the art. Do.

FIG. 2 is a vertical sectional view of a BICMOS in which an impurity region having a high concentration (rather than an N well impurity concentration) is formed between the base region and the collector region constituting the bipolar portion, which is to be improved.

As can be seen from the above equations (1) and (2), in order to improve the high frequency characteristics and current driving force of the bipolar transistor, it is preferable to reduce the thickness (Wb) of the base region, and the reduced base thickness is extended by the HLI. It is clear that the impurity concentration in the collector region must be increased in order not to be. However, in BICMOS where different devices are formed on one substrate, increasing the impurity concentration of the N well to prevent the HLI increases the substrate effect and source / drain capacitance in the MOS transistor. Problems are caused, resulting in deterioration of the characteristics.

2 illustrates a method of improving the performance of a bipolar transistor without deteriorating the characteristics of the MOS transistor. The purpose of the present invention is to introduce a selective ion-implanted collector (hereinafter referred to as SIC) process. do.

The SIC process (see Reprinted with permission from 19th Conference Solid-State Devices and Meterials, pp. 331-334, 1987) forms a source region in a well for forming a bipolar transistor, and then forms an emitter region. Since the impurity injection window is short, and impurity is injected through the window, the impurity region 200 is formed by a super self-aligned process technology (SST).

The method of forming the impurity region 200 by the SIC is easy to form an impurity layer having a desired concentration in a desired region by controlling the implantation energy of implanted ions, but the ion implantation technology is a high-level technique and A high cost is required, and since the impurity region 200 formed between the source region and the collector region is very thin, breakdown is liable to occur and leakage due to the destruction of the crystal structure that may occur during the ion implantation process. Current problems can also occur, reducing the device's electrical characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, comprising forming an active region of a well of a MOS transistor and a bipolar transistor by BICMOS technology, and then doping impurities to a specific portion of the bipolar transistor. .

A semiconductor device manufacturing method for achieving the above object of the present invention is a semiconductor device in which a bipolar transistor and a MOS field effect transistor are formed on the same semiconductor substrate, wherein a well and a bipolar transistor of a MOS field effect transistor are formed on the semiconductor substrate. After the active region is formed, an impurity is further doped in the region where the emitter region of the bipolar transistor is to be formed.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3A to 3J are cross-sectional views illustrating a BICMOS manufacturing method according to the present invention.

First, referring to FIG. 3A, a process of doping impurities to form an active region of a bipolar transistor and a well of a PMOS transistor in an epitaxial layer is illustrated. 10) after the self-aligned high concentration of the buried layers 12 and 14 are formed by the Local Oxidation of Silicon (LOCOS) method, the N ^_ epitaxial layer 40 is formed, for example, at a concentration of about 1.7 SE14 electrons / cm 2. It is formed on the semiconductor substrate 10 in which the buried layers having a high concentration of -3㎛. The high concentration buried layers 12 and 14 are formed such that N ⁺ buried layers 12 are surrounded by P buried layers 14, which is N in the region where N ⁺ buried layer 12 is to be formed. As the impurity, for example, As ions are implanted at a dose of 10 ¹⁵ electrons / cm 2, and then the surface (the surface of the region where the N ⁺ buried layer is to be formed) is oxidized to form an oxide film, and the oxide film is used as a mask. In the region where the P buried layer 14 is to be formed, for example, B ion is implanted at a dose of 10 ¹³ electrons / cm 2 as a P-type impurity. According to the above-described process for forming the buried layer, since the oxide film etches the surface of the N ⁺ buried layer as much as the depth penetrating the substrate, the N ⁺ buried layer is formed as a shape that is smaller than the surface of the P buried layer. This is negligible because the effect on the overall device characteristics is minimal.

Subsequently, an entire surface of the epitaxial layer 40 is surface oxidized to form an oxide film (SiO ₂ ) 16, and a nitride film such as a Si ₃ N ₄ (18) film is laminated on the oxide film, and then the N ⁺ buried layer The Si ₃ N ₄ film is partially removed by using a mask sizing the mask pattern used to form (12), thereby forming an impurity doped window for forming an active region of a bipolar transistor and a well region of a PMOS transistor. Form. The active region and the well region are formed to correspond to the N ⁺ buried layer 12 by N-type impurities such as P (Phosphorus) ions implanted through the dope window.

Referring to FIG. 3B, a step of forming the impurity diffusion region 300a is shown. After the photoresist is applied to the entire surface of the epitaxial layer 40 doped with N-type impurities, the emitter region may be small. Since the photoresist is patterned to form a window having a size including a photoresist, a photoresist pattern 90a for forming an impurity diffusion region is formed, and an N-type impurity is implanted into the entire surface of the substrate as a mask of the photoresist pattern. do.

At this time, the concentration of the N-type impurities, as described above, the concentration such that base pushout (Hi; High-Level Injection) does not occur (for example, 180KeV, 7E12 electron / ㎠) In the present invention, the impurity diffusion region 300a has a concentration of 5E16 electrons / cm 3 so that the concentration of the impurity diffusion region (see FIG. 3D, 300), which is finally determined by two thermal processes, is 5E16 electrons / cm 3. Was determined. The concentration is not limited to this, and can be expanded to a concentration (variable by concentration of epitaxial layer, concentration of N region 42a and various conditions) in which base expansion phenomenon by high injection does not occur. It is apparent that this is possible by those skilled in the art.

The impurity diffusion region 300 formed by FIG. 3b is not only easy to manufacture, but also easy to manufacture because of its difficulty in processing than in the ion implantation technique of the conventional method (see FIG. 2). Since the risk of breakdown due to the thin impurity region (200 in FIG. 2) as described above is small, high reliability device manufacturing is easy.

Referring to FIG. 3C, a process of forming a region in which the P wells and the bipolar portion and the MOS portion of the NMOS transistor are electrically insulated using the LOCOS range is shown. The Si ₃ N ₄ film 18 Is formed as a mask to protect the epitaxial layer against thermal oxidation, and then an oxide film (SiO ₂ ) 19 is formed on the surface of the N region 42a, and then the Si ₃ N ₄ film 18 is removed, and the Si ₃ N _4, where the film has been removed to the window for impurity injection implanting P-type impurity, for example B (Boron) ions, so to form a self-aligned manner to the P region (44a). At this time, the N region and the impurity diffusion region (42a and 300a in FIG. 3b) are reshaped (42a and 300a in FIG. 3c) in a form diffused toward the N ⁺ buried layer, which is applied to the thermal energy supplied during the thermal oxidation process. As a result of the diffusion of impurity ions, it is an important shape necessary to achieve the object of the present invention.

Referring to FIG. 3D, a process of forming the device isolation layer 35, the N wells, and the P wells, and a mask for protecting the epitaxial layer against thermal oxidation in regions other than the region where the device isolation layer is to be formed, is illustrated. After forming a Si ₃ N ₄ film in order to play a role, the thermal oxidation process is performed, and an isolation device for isolation (SiO) having a thickness of, for example, about 5000 μs in a region other than the active region (the region where the device isolation film is to be formed) is formed. ₂ ) 35.

Since the process for forming the device isolation film 35 is performed after the oxide film 19 is removed, the process is performed on a slightly curved surface (the same principle as that described in FIG. 3A) by removing the oxide film. Its negligible effect on device characteristics is negligible. In addition, the thermal energy supplied to the substrate during the thermal oxidation process for forming the device isolation film supplies active energy to the impurity ions in the N region 42a, the P region 44a, and the impurity diffusion region 300a to diffuse them. N wells, P wells, and impurity diffusion regions 300 are thereby reformed.

Two thermal oxidation processes for forming the oxide film 19 and the device isolation film 35 are important processes required for the purpose of the present invention, and the impurity diffusion region 300 is formed by the two thermal oxidation processes. The concentration of impurities and their depth can be adjusted.

Referring to FIG. 3E, a process of forming a high concentration impurity region 22 for resistive contact of a collector electrode is shown. After the photoresist is applied to the entire epitaxial layer in which the device isolation layer 35 is formed, And partially removing the photoresist on the region where the collector electrode is to be formed to form a photoresist pattern 90b, and using the photoresist pattern as a mask as an N-type impurity on the entire epitaxial layer, for example, P ion. Is injected at a high concentration to form the high concentration impurity region 22. At this time, the impurity concentration of the impurity region is about 1E ¹⁹ electrons / cm 2, and is formed for the purpose of improving the electrical characteristics of the device by reducing the series resistance of the collector.

Referring to FIG. 3F, a process of forming the low concentration source and drain impurity regions 30a of the gate electrode 80 and the NMOS transistor is shown. The photoresist pattern 90b is formed on the entire surface of the epitaxial layer from which the photoresist pattern 90b is removed. The gate oxide film (SiO ₂ ) 36 was formed to a thickness of about 300 kV, and then a polycrystalline silicon layer doped with impurities was deposited on the entire surface of the gate oxide film, followed by an etching process, to form the gate oxide film. Forming a photoresist pattern (90c) by forming a photoresist (80), applying a photoresist on the entire epitaxial layer where the gate electrode is formed, and then removing the photoresist on a region where an NMOS transistor is to be formed; Since the photoresist pattern 90c is used as a mask, the N-type impurities such as P ions are doped at low concentration, so that the low concentration source and drain impurity regions 30a are formed. Sung.

Referring to FIG. 3G, a process of forming a spacer 81 for forming an LDD structure of an NMOS transistor, a high concentration impurity region 24a for resistive contact of a base region, and a source and drain impurity region 28 of a PMOS transistor As shown in FIG. 6, a thin oxide film is formed on the entire surface of the epitaxial layer on which the gate electrode 80 is formed. Then, an anisotropic etching process is performed to form a spacer 81 on the sidewall of the gate electrode. An NMOS transistor is formed on the resultant. After forming a photoresist pattern in which a window is formed to expose the negative epitaxial layer (not shown), an N-type impurity is implanted using the pattern as a mask to complete the LDD structure of the NMOS transistor. Subsequently, a photoresist pattern 90d having a window is formed on the resultant so that the PMOS transistor portion and the epitaxial layer of the region where the base region is to be formed are formed on the resultant, and then the base region is implanted with, for example, BF ₂ ions with P-type impurities. The high concentration impurity region 24a and the source and drain impurity region 28 of the PMOS transistor are formed for the ohmic contact.

Referring to FIG. 3H, a process of forming the base region 24 is illustrated. After applying photoresist to the entire surface of the resultant, the photoresist pattern is partially removed by removing the photoresist on the region where the base region is to be formed. 90e is formed and the base region 24 is completed by doping B (Boron) ions, for example, with P-type impurities using the photoresist pattern as a mask. At this time, it is obvious that the depth of the base region (relative to the surface) should be shallower than the impurity diffusion region 300.

Referring to FIG. 3I, a process of forming an emitter electrode is shown. A high temperature oxide (HTO) 37 is thinly formed on the entire epitaxial layer on which the base region 24 is formed, and the emitter region is formed. Since the HTO on the region to be formed is removed, an impurity doped window for forming an emitter region is formed, and then a polysilicon layer is laminated and a photolithography process is performed to form the emitter electrode 84. Subsequently, a photoresist pattern 90f having a dope window formed to expose the emitter electrode is formed on the resultant material, and then doped with N-type impurities through the window to complete the emitter region 26.

Referring to FIG. 3J, a process of forming the electrodes of the MOS transistor and the bipolar transistor is illustrated, and HTO and BSPG (BoroPhos phorous Silicate Glass) are formed on the entire epitaxial layer on which the emitter electrode 84 is formed. After stacking, the collector electrode 50a, the emitter electrode 50c and the base electrode 50b in the region in which the electrodes are to be formed, that is, the source electrodes 60a and 70a and the drain electrode 60c and the bipolar transistor, respectively. 70c) and the HTO and BPSG films on the region where the gate electrodes 60b and 70b are to be formed to form a window for contact, and a conductive material is deposited on the front surface of the BPSG to be completely patterned and then patterned. By completing the electrodes, a bipolar transistor and a MOS field effect transistor complete the BICMOS formed on one substrate.

4A to 4B are graphs showing profiles of impurity concentrations depending on the depth of the epitaxial layer, in which FIG. 4A is a case in which an impurity diffusion region 300 is not formed, and in FIG. 4B is an impurity diffusion region 300. ) Is formed.

According to the present invention as described above, it is possible to improve the frequency characteristics and current driving range of the device because it prevents the base pushout of the base region due to the high injection generated in the bipolar transistor without damaging the MOS transistor. In addition, it is possible to prevent the deterioration of the electrical characteristics of the device due to the expensive cost and the breakdown voltage that have been a problem in the conventional method.

It is apparent that many modifications are possible to those skilled in the art within the technical spirit of the present invention without being limited to the above embodiments of the present invention.

Claims (6)

A method for manufacturing a semiconductor device in which a bipolar transistor and a MOS field effect transistor are formed on the same semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate and then the active region of the bipolar transistor and the well of the MOS field effect transistor are formed. Forming an impurity diffusion region by further implanting a first conductivity type impurity under the emitter formation region in the active region of the bipolar transistor; and forming the impurity diffusion region by a thermal oxidation process. Forming a diffused impurity diffusion region by diffusing, implanting a second conductivity type impurity into an active region of the bipolar transistor, and forming a base region to know the depth from the surface of the diffused impurity region; Leaving an impurity diffusion region in contact with the lower boundary of the A method for manufacturing a semiconductor device, comprising 2. The method of claim 1, wherein the first conductivity type impurity is an impurity of the same type as the collector region of the bipolar transistor. The method of manufacturing a semiconductor device according to claim 2, wherein the concentration of the first conductivity type impurity is such that a concentration of the Jay region is not increased due to high injection. 4. A method according to claim 3, wherein the concentration of the first conductivity type impurity is 5E16 electrons / cm < 2 >. The method of claim 2, wherein the first conductivity type impurity is deeper than the source region of the bipolar transistor. 6. The method of claim 5, wherein the first conductivity type impurity is diffused by thermal energy supplied during the thermal oxidation process.