JP3312691B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon On In)
(sulator) related to a structure semiconductor device.

[0002]

2. Description of the Related Art In a SOI substrate, SIMOX (Separation by IMplanted OXyge) in which oxygen is ion-implanted into a single-crystal silicon substrate and heat treatment is performed to form a buried insulating layer.
n) There is a bonded substrate where a silicon substrate with an oxide film formed on its surface and another silicon substrate are bonded together. As a semiconductor device having this SOI structure, for example, M
In an OS transistor, the parasitic capacitance can be reduced as compared with a conventional MOS transistor using a silicon substrate, so that a MOS transistor using an SOI substrate can perform high-speed operation and reduce power consumption.

[0003]

In a single-gate SOI MOS transistor having one gate electrode for one MOS transistor, if the element size is reduced for the purpose of miniaturization, the current drive in a saturated state is performed. The performance is almost the same as that of a MOS transistor using a conventional silicon substrate. In the SOI, since the elements are completely separated by the insulating layer, the substrate potential is not fixed. Therefore, since the substrate potential also changes with the change in the drain potential, when the gate length is reduced to about 0.05 μm, the short channel effect becomes disadvantageous as compared with the silicon substrate.

SUMMARY OF THE INVENTION The present invention overcomes the above-mentioned problems and provides a MOS having a structure capable of achieving high current driving capability and suppressing a short channel effect.
An object is to provide a transistor.

[0005]

In order to solve the above-mentioned problems, the present invention uses the following means. (1) In an SOI semiconductor device in which a main surface portion on which elements are formed is insulated and separated by a buried insulating layer formed in a semiconductor substrate, a MOS is formed on the buried insulating layer.
A buried insulating layer having a thickness in contact with the buried insulating layer in the depth direction around the MOS transistor; a buried electrode below the buried insulating layer; Wherein the polycrystalline silicon gate electrode and the buried electrode of the MOS transistor have a planar overlap. (2) A semiconductor device in which the gate electrode and the buried electrode are electrically connected. (3) An interlayer insulating film is provided on the previous MOS transistor, a metal wiring is provided on the previous interlayer insulating film, a contact hole is provided in the previous interlayer insulating film on the previous gate electrode, and the burying is performed. On the electrode, in a region having the previous element isolation region and the previous interlayer insulating film, a contact hole having a depth reaching the first buried electrode is provided, and the first gate electrode and the first buried electrode form the first contact hole. Semiconductor devices that are connected by the metal wiring. (4) A via hole having a depth reaching the buried electrode is formed on the buried electrode and in a region having the element isolation region and the interlayer insulating film. A semiconductor device which is connected via the via hole by polycrystalline silicon forming the gate electrode. (5) A semiconductor device in which the embedded electrode is an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate. (6) A semiconductor device in which the above-mentioned buried electrode is made of polycrystalline silicon different from the above-mentioned gate electrode, and has an insulating film between the above-mentioned buried electrode and the above-mentioned semiconductor substrate. (7) A semiconductor device in which the thickness of the buried insulating layer is equal to the thickness of the gate insulating film of the MOS transistor.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings, taking an N-type MOS transistor as an embodiment. First Embodiment FIG. 1 is a cross-sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention. The semiconductor substrate 101 in FIG. 1 is a P-type bonded SOI substrate,
The main surface of the semiconductor substrate 101 on which the element is formed is insulated from the back surface by the buried insulating layer 102. An N-type diffusion layer serving as a buried electrode 104 is provided below the buried insulating layer 102 on the back surface of the semiconductor substrate 101. At this time, the buried insulating layer 102 is
Work as a gate insulating film.

An N-type MOS is formed on the buried insulating layer 102.
A transistor is formed. This MOS transistor includes an N-type source region 107, a drain region 108, and a gate electrode 105 via a gate insulating film 106. This N-type MOS transistor is defined in a plane by the field insulating film 103. The buried electrode 104 is electrically connected to the gate electrode 105 by using, for example, buried polycrystalline silicon 109 as a wiring on the field insulating film in order to maintain electrical continuity.
Note that conduction may be obtained by a metal film.

When a gate voltage is applied to the MOS transistor, the buried electrode 104 and the gate electrode 105
Can be activated simultaneously. Therefore, a channel is formed vertically inside the element, and the current driving force increases. Further, since the substrate potential inside the device can be fixed by the buried electrode 104 and the gate electrode 105, the short channel effect can be suppressed.

Next, one embodiment of a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIGS. As shown in FIG. 3A, a P-type semiconductor substrate 301 made of single crystal silicon
Is patterned with a photoresist 302, and an N-type impurity, for example, arsenic is ion-implanted partially to form an N-type diffusion layer serving as the buried electrode 104. The concentration is about 1 × 10 ²⁰ / cm ³ . Then, the semiconductor substrate 3
01 is subjected to thermal oxidation to form an oxide film serving as the buried insulating layer 102 on the surface of the semiconductor substrate 301. Another P-type semiconductor substrate 303 is provided on the semiconductor substrate 301 on which the insulating layer 102 is formed.
Are bonded, polished and ground, and the SOI semiconductor substrate 10
Let it be 1. This state is shown in FIG. At this time, the thickness of the buried insulating layer 102 is about 10 nm to 100 nm. Here, the buried insulating layer 1 is embedded in the semiconductor substrate 301.
02 was formed, but of another of bonding semiconductor substrate 303
It is also possible to form an oxide film on the substrate to form the buried insulating layer 102.

After a field insulating film 103 is formed on the SOI substrate by using the LOCOS method, a silicon oxide film is formed as a gate insulating film 106 on the surface of the semiconductor substrate 101 by performing thermal oxidation. Here, the gate insulating film 106
Has a thickness of about 10 nm to 100 nm, which is the same as the thickness of the buried insulating layer 102. Then, the buried insulating layer 1
In order to establish electrical connection with the buried electrode 104 which is an N-type diffusion layer below the photoresist 02, as shown in FIG.
After applying the pattern at 01, etching is performed to form a groove 402 having an arbitrary shape. At this time, the etching is performed up to the buried insulating layer 102 and stopped after reaching the N-type diffusion layer.

In the trench 402 formed by etching, polycrystalline silicon 109 serving as a wiring for establishing conduction with the buried electrode 104 is buried, and further a polycrystalline silicon layer is deposited to form a gate electrode 105 above the element.
This state is shown in FIG. This polycrystalline silicon is pre-deposited with phosphorus to have conductivity. And FIG.
As shown in (d), apply a pattern with photoresist,
The gate electrode 105 is formed by etching.

Using the formed gate electrode 105 and field insulating film 103 as a mask, an N-type impurity such as arsenic is ion-implanted to form a source region 107 and a drain region 108. Thereafter, an interlayer insulating film (not shown) is deposited, a pattern is formed with a photoresist, etching is performed, a metal film is deposited in the formed groove, and a source region 10 is formed.
7. Make electrical connection with the drain region 108 and the gate electrode 105.

FIG. 5 is a cross-sectional view showing a main part of a semiconductor device according to another embodiment of the present invention. In FIG. 5, polycrystalline silicon covered with an insulating film 510 is buried under a buried insulating layer 502 on the back surface of a semiconductor substrate 501 which is a bonded SOI substrate, and this polycrystalline silicon is used as a buried electrode 504.

An N-type MOS is formed on the buried insulating layer 502.
Since a transistor is formed and has a structure in which gate electrodes are provided above and below the element as in Embodiment 1, current driving force is increased and a short channel effect can be suppressed. Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention shown in FIG. 5 will be described with reference to FIG.

P-type semiconductor substrate 6 made of single crystal silicon
A pattern is formed on the surface of the substrate No. 01 by using a photoresist, and etching is performed.
And a groove of about 0.5 μm is formed. This semiconductor substrate 6
01 is partially subjected to thermal oxidation to form an oxide film of about 30 nm serving as an insulating film 510 in the groove. After that, as shown in FIG.
04 is formed. At this time, pre-deposition of phosphorus is performed to impart conductivity to the polycrystalline silicon. Example 2
Then, another P-type semiconductor substrate 6 on the side where an element is formed
02 is thermally oxidized to form an oxide film to be a buried insulating layer 502 on the surface, and then bonded to a semiconductor substrate 601 in which a buried electrode 504 is buried, and polished and ground.
An I-type semiconductor substrate 501 was used.

Thereafter, similarly to the first embodiment, the N-type M
An OS transistor is formed. In this embodiment, an N-type MOS transistor has been described.
A similar configuration is possible for the S transistor.

[0017]

As described above, the effects obtained by the present invention are as follows. In the SOI semiconductor device, a double gate structure having an electrode also below the MOS transistor has an effect that a higher current driving force can be achieved. Further, according to the present invention, the short channel effect can be more effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2 in a process of a main part of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 2 in a process of a main part of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a process cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 SOI type semiconductor substrate 102 buried insulating layer 103 field insulating film 104 buried electrode 105 gate electrode 106 gate insulating film 107 source region 108 drain region 109 polycrystalline silicon 201 element internal region 301 P-type semiconductor substrate 302 photoresist 303 P-type semiconductor substrate Reference Signs List 401 Photoresist 402 Groove formed by etching 403 SOI type semiconductor substrate 502 Buried insulating layer 503 Field insulating film 504 Buried electrode 505 Gate electrode 506 Gate insulating film 507 Source region 508 Drain region 509 Polycrystalline silicon 510 Insulating film 601 P-type semiconductor substrate 602 P-type semiconductor substrate

Claims (2)

(57) [Claims] [1 claim: a first semiconductor substrate, said first recess formed in the semiconductor substrate surface, a buried electrode of polycrystalline silicon formed through an insulating film formed by thermal oxidation, the On the first semiconductor substrate surface and the embedded electrode,
A second semiconductor substrate formed via a buried insulating film having a thickness of 10 to 100 nm, a field insulating film formed on the second semiconductor substrate to define a semiconductor region, and the second semiconductor substrate Gate insulating film formed on the surface
And , on the gate insulating film and the field insulating film,
It is formed so as to have a planar overlap with the embedded electrode.
A gate electrode made of polycrystalline silicon, the field insulating film and the gate electrode as a mask, the source region and a drain region formed by implanting an impurity into the second semiconductor substrate, said field insulating film and the Formed in the buried insulating film
A connecting hole reaching the buried electrode, wherein embedded in the connection hole, the semiconductor device characterized by comprising a said of polycrystalline silicon connecting the embedded electrode and the gate electrode wiring. 2. The semiconductor device according to claim 1, wherein said buried insulating layer and said gate insulating film have the same thickness.