JP4789369B2 - Display device and electronic device - Google Patents

Display device and electronic device Download PDF

Info

Publication number
JP4789369B2
JP4789369B2 JP2001241463A JP2001241463A JP4789369B2 JP 4789369 B2 JP4789369 B2 JP 4789369B2 JP 2001241463 A JP2001241463 A JP 2001241463A JP 2001241463 A JP2001241463 A JP 2001241463A JP 4789369 B2 JP4789369 B2 JP 4789369B2
Authority
JP
Japan
Prior art keywords
signal line
gate signal
pixel
display device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2001241463A
Other languages
Japanese (ja)
Other versions
JP2003058075A5 (en
JP2003058075A (en
Inventor
潤 小山
舜平 山崎
Original Assignee
株式会社半導体エネルギー研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社半導体エネルギー研究所 filed Critical 株式会社半導体エネルギー研究所
Priority to JP2001241463A priority Critical patent/JP4789369B2/en
Publication of JP2003058075A publication Critical patent/JP2003058075A/en
Publication of JP2003058075A5 publication Critical patent/JP2003058075A5/ja
Application granted granted Critical
Publication of JP4789369B2 publication Critical patent/JP4789369B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3276Wiring lines
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13454Drivers integrated on the active matrix substrate
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F2001/13456Conductors connecting electrodes to cell terminals cell terminals on one side of the display only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2251/00Indexing scheme relating to organic semiconductor devices covered by group H01L51/00
    • H01L2251/50Organic light emitting devices
    • H01L2251/53Structure
    • H01L2251/5307Structure specially adapted for controlling the direction of light emission
    • H01L2251/5315Top emission

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device in which a plurality of pixels are provided on an insulating surface and display is performed by changing the luminance of each pixel. In particular, the present invention relates to a display device having a structure in which a driving circuit for controlling the luminance of each pixel is provided on the same surface as the insulating surface where the pixels are formed. The present invention also relates to an electronic device using the display device.
[0002]
[Prior art]
Display devices are incorporated and used in various electronic devices. In particular, in a display device used in a portable information device, in order to reduce the size and power consumption of the portable information device, the display device is required to be reduced in size and power consumption.
[0003]
As small-sized and low power consumption display devices, flat panel displays such as liquid crystal display devices and OLED display devices using OLED (Organic Light Emitting Diode) elements have attracted attention.
[0004]
Note that in this specification, the OLED element includes both light emission (fluorescence) from singlet excitons and light emission (phosphorescence) from triplet excitons.
[0005]
These flat panel displays have a plurality of matrix-like pixels formed on a substrate having an insulating surface. An image is expressed by selectively inputting a video signal to one pixel and changing the luminance of the pixel by a driving circuit.
[0006]
There are various methods for connecting the driving circuit and the pixel.
[0007]
There is a method in which a driver circuit for controlling the luminance of a pixel is formed over another substrate such as a single crystal IC substrate, and attached to a substrate having an insulating surface on which the pixel is formed to be connected to the pixel. In this case, a large area is required when the single crystal IC substrate is bonded to the substrate having an insulating surface on which pixels are formed. In addition, the wiring resistance between the driving circuit and the pixel is large. Therefore, it is difficult to provide a small display device with low power consumption.
[0008]
On the other hand, there is a method in which a driver circuit is integrally formed on the same surface as the insulating surface on which the pixel is formed, and the pixel and the driver circuit are connected. A driving circuit is formed by a thin film transistor (TFT) on the same surface as the insulating surface on which the pixels are formed. Thus, a display device that can be reduced in size and power consumption is provided.
[0009]
FIG. 9 is a top view of a display device including a pixel region in which a plurality of pixels are formed in a matrix and a driver circuit formed around the pixel region.
[0010]
A source signal line driver circuit 902, gate signal line driver circuits 901 (901A and 901B), and a pixel region 903 are provided over a substrate 900 having an insulating surface. Signals input to each driving circuit (source signal line driving circuit 902 and gate signal line driving circuit 901) are input from the FPC board 904.
[0011]
When the display device is viewed from above, an area other than the pixel area 903 is referred to as a frame. That is, the frame in the display device corresponds to a portion where no image is displayed.
[0012]
In the liquid crystal display device, the luminance of each pixel is expressed by controlling the transmittance by controlling the orientation of the liquid crystal element. The liquid crystal element has a structure in which a liquid crystal material is disposed between two electrodes. One electrode of a liquid crystal element (hereinafter referred to as a pixel electrode) is formed on a substrate (hereinafter referred to as a pixel substrate) on which a drive circuit or the like is formed, and is provided on another substrate (hereinafter referred to as a counter substrate). The other electrode (counter electrode) of the liquid crystal element is formed. The pixel substrate and the counter substrate are attached so that the pixel electrode and the counter electrode face each other.
[0013]
On the pixel substrate, a sealing material is disposed so as to surround the pixel region and each driving circuit, and an opposing base plate is attached. A liquid crystal material is sealed in a region surrounded by the pixel substrate, the counter substrate, and the sealant. If the display device illustrated in FIG. 9 is a liquid crystal display device, a sealing material 906 is used when the pixel substrate 900 and the counter substrate are attached to each other. In FIG. 9, the counter substrate and the liquid crystal material are not shown.
[0014]
In the OLED display device, the luminance of each pixel is expressed by controlling the light emission of the OLED element. The OLED element is formed on the pixel substrate after the TFT constituting the drive circuit or the like is formed. Here, the OLED element has a property of being significantly deteriorated by oxygen, moisture or the like when exposed to the outside air. For this reason, the OLED display device has a structure in which after the OLED element is formed, a cover material is provided to block the OLED element from the outside air. The cover material is attached to the pixel substrate using a seal material.
[0015]
On the pixel substrate, a sealing material is disposed so as to surround the pixel region and each driving circuit, and a cover material is attached. The OLED element is sealed in a region surrounded by the pixel substrate, the cover material, and the seal material. If the display device shown in FIG. 9 is an OLED display device, the sealing material is 906. In FIG. 9, the cover material is not shown.
[0016]
In common with a display device such as a liquid crystal display device or an OLED display device, the pixel region 903 has x (x is a natural number) source signal lines S1 to Sx and source signal lines S1 to Sx arranged in parallel. The gate signal lines G1 to Gy of y (y is a natural number) arranged in parallel are formed in a direction perpendicular to. A pixel is selected by signals input to the source signal lines S1 to Sx and the gate signal lines G1 to Gy, and the luminance of the selected pixel is controlled.
[0017]
A pixel signal region 903 includes a source signal line driver circuit 902 that inputs signals to the plurality of source signal lines S1 to Sx and a gate signal line driver circuit 901 (901A and 901B) that inputs signals to the plurality of gate signal lines G1 to Gy. Is formed around.
[0018]
In the source signal line driver circuit 902 using a shift register or the like, signals are output in order according to the scanning direction indicated by an arrow in the drawing, and the output signals are input to the plurality of source signal lines S1 to Sx. Usually, the source signal line drive circuit 902 is arranged so that the scanning direction is perpendicular to the plurality of source signal lines S1 to Sx arranged in parallel. Similarly, the gate signal line driver circuit 901 using a shift register or the like sequentially outputs signals in accordance with the scanning direction indicated by the arrow in the drawing, and the output signals are input to the plurality of gate signal lines G1 to Gy. The Usually, the gate signal line drive circuit 901 is arranged so that the scanning direction is perpendicular to the plurality of gate signal lines G1 to Gy arranged in parallel.
[0019]
In FIG. 9, the gate signal line driver circuits 901 (901A and 901B) are formed on both sides of the pixel region, but may be arranged on one side.
[0020]
The scanning direction of the gate signal line driver circuit 901 arranged as described above is referred to as a row direction, and the scanning direction of the source signal line driver circuit 902 is referred to as a column direction.
[0021]
In FIG. 9, a source signal line driver circuit 902 is formed in parallel with one side of a pixel region 903 indicated by a rectangle. Further, gate signal line drive circuits 901A and 901B are formed in parallel on two sides which are different from the side where the source signal line drive circuit 902 is formed in parallel and which are not opposed to each other.
[0022]
In this specification, in the periphery of the four sides of the pixel region 903 on the pixel substrate 900, the side to which the FPC substrate 904 is connected is referred to as the upper side, and the side opposite to the side is referred to as the lower side.
[0023]
On the other hand, on the periphery of the four sides of the pixel region 903 on the pixel substrate 900, the side adjacent to the side to which the FPC substrate 904 is connected and the side of the opposite side are respectively left and right of the pixel region. I will call it part.
[0024]
Usually, the source signal line driver circuit is disposed at the closest distance from the portion where the FPC board is attached. Therefore, in general, a source signal line driver circuit 902 is disposed above the pixel region 903. On the other hand, gate signal line driving circuits 901 are arranged on the left and right sides of the pixel region 903 on the pixel substrate 900.
[0025]
Note that the source signal line driver circuit may be disposed around the four sides of the pixel region 903 on the pixel substrate 900 on the side facing the side to which the FPC substrate 904 is connected. At this time, the source signal line driver circuit is arranged below the pixel region.
[0026]
Note that the top, bottom, left and right of the pixel region 903 correspond to the top, bottom, left and right of the display device, respectively.
[0027]
[Problems to be solved by the invention]
In the case of a portable information device such as a cellular phone, a user is required to make a screen for displaying an image as large as possible and to make it easier to hold by reducing the width of the main body.
[0028]
In order to make the display screen as large as possible and make the width of the main body as small as possible, it is required to reduce the area of the frame of the display device incorporated in the main body.
[0029]
Here, in the display device having the structure illustrated in FIG. 9, the gate signal line driver circuits 901 </ b> A and 901 </ b> B are arranged on the left and right sides of the pixel region 903.
[0030]
Further, a sealing material 906 is further formed outside the gate signal line driver circuits 901A and 901B on the pixel substrate 900. Therefore, there is a problem that the area of the left and right frame of the display device cannot be reduced.
[0031]
Note that since the FPC board is connected in the vertical direction of the pixel region, there is a limit in reducing the area of the frame.
[0032]
Therefore, in a display device in which a driving circuit for controlling signals input to the plurality of pixels is formed on the same surface as the insulating surface on which the plurality of pixels are formed, the area of the horizontal frame of the display device is reduced. This is the issue.
[0033]
[Means for Solving the Problems]
In a display device in which a driving circuit (a source signal line driving circuit and a gate signal line driving circuit) that controls signals input to the plurality of pixels is formed on the same surface as the insulating surface on which the plurality of pixels are formed. A gate signal line driver circuit is provided in parallel with the source signal line driver circuit. That is, the gate signal line driver circuit is disposed above or below the pixel region.
[0034]
Thus, at least two of the four sides of the pixel region that are opposed to each other are configured such that no drive circuit is disposed.
[0035]
Here, making the gate signal line driving circuit and the source signal line driving circuit parallel means that the scanning direction of the gate signal line driving circuit is parallel to the scanning direction of the source signal line driving circuit.
[0036]
Note that in this specification, the scanning direction of the drive circuit indicates a direction in which circuits corresponding to a plurality of signal lines to which signals from the drive circuit are input are arranged in the drive circuit.
[0037]
In general, a signal output from the source signal line driver circuit is preferably input to the pixel region at a short distance. Therefore, when the source signal line driver circuit and the gate signal line driver circuit are formed on the same side of the pixel region, the source signal line driver circuit is disposed closer to the pixel region than the gate signal line driver circuit.
[0038]
Note that the gate signal line driver circuit may be arranged closer to the pixel region than the source signal line driver circuit.
[0039]
In addition, the source signal line driver circuit is disposed only in the upper or lower portion of the pixel region, and the gate signal line driver circuit is disposed only on the side of the pixel region opposite to the side on which the source signal line driver circuit is formed. The structure to do may be sufficient.
[0040]
As described above, when the source signal line driver circuit and the gate signal line driver circuit are arranged, the following configuration is used to sequentially scan the gate signal lines in the pixel region.
[0041]
As a first configuration, the gate signal line driving circuit outputs a signal to a routing gate signal line that is perpendicular to the gate signal line in the pixel region.
[0042]
Here, when the gate signal line driver circuit and the source signal line driver circuit are arranged on the same side of the pixel region, and the source signal line driver circuit is arranged closer to the pixel region than the gate signal line driver circuit, The routing gate signal line passes through the source signal line driving circuit provided between the gate signal line driving circuit and the pixel region, and is led around the pixel region.
[0043]
The routing gate signal line is connected to the corresponding gate signal line in the pixel region. Thus, the gate signal line driver circuit sequentially inputs signals to the gate signal lines in the pixel region.
[0044]
In the pixel region, the routing gate signal line connected to the gate signal line may be formed in the same layer as the gate signal line, or may be formed in a different layer.
[0045]
The routing gate signal line is formed in parallel with the source signal line and the like in the pixel region. By forming the routing gate signal line so as to overlap these parallel wirings, the aperture ratio can be increased.
[0046]
As a second configuration, the output of the gate signal line driving circuit is routed and input from the lateral direction of the pixel region.
[0047]
At this time, a sealing material can be disposed above the gate signal line. Thereby, the area of the frame in the horizontal direction of the display device due to the area occupied by the wiring can also be suppressed.
[0048]
With the above structure, the horizontal width of the display device in which the conventional gate signal line driving circuit is formed can be reduced by the amount of the gate signal line driving circuit, and a display device with a small horizontal frame area is provided. be able to.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
In a display device in which a driving circuit (a source signal line driving circuit and a gate signal line driving circuit) that controls signals input to the plurality of pixels is formed on the same surface as the insulating surface on which the plurality of pixels are formed. The gate signal line driver circuit is arranged on the same side as the source signal line driver circuit around the four sides of the pixel region. At this time, the source signal line driver circuit is disposed closer to the pixel region than the gate signal line driver circuit, and a signal from the gate signal line driver circuit is input to the pixel region through the source signal line driver circuit.
[0050]
The driving circuits (source signal line driving circuit and gate signal line driving circuit) are not arranged on the left and right sides of the pixel region.
[0051]
FIG. 1 shows the configuration of Embodiment 1 of the display device of the present invention.
[0052]
FIG. 1A is a top view illustrating a structure of a display device. In the display device, a pixel region 103, a source signal line driver circuit 102, a gate signal line driver circuit 101, an FPC substrate 104, and a seal material 106 are arranged on a pixel substrate 100.
[0053]
The source signal line driver circuit 102 is formed above the pixel region 103, and the gate signal line driver circuit 101 is formed above the pixel region 103 in parallel with the source signal line driver circuit 102.
[0054]
In FIG. 1A, a detailed configuration of a portion indicated by a region 110 is shown in FIG. 1B, and a detailed configuration of a portion indicated by a region 111 is shown in FIG.
[0055]
In FIG. 1B, reference numeral 101 a denotes a part of the gate signal line driver circuit 101. Reference numeral 102 a denotes a part of the source signal line driver circuit 102. Here, it is assumed that x (x is a natural number) source signal lines and y (y is a natural number) gate signal lines are arranged in the pixel region.
[0056]
In the region 110, the signal output from the gate signal line driving circuit 101a is output to the routing gate signal lines GDi−2 to GDi + 2 (i is a natural number of 3 or more). The routing gate signal lines GDi−2 to GDi + 2 are routed to the pixel region 103 through the source signal line driving circuit 102a. The source signal line driver circuit 102a outputs signals to the source signal lines Sj−2 to Sj + 2 (j is a natural number of 3 or more). The routing gate signal lines GDi−2 to GDi + 2 and the source signal lines Sj−2 to Sj + 2 are parallel to each other.
[0057]
Note that in this specification, the portion of the source signal line that is routed from the source signal line driver circuit to the pixel region is referred to as a routing source signal line, and can be distinguished from the source signal line in the pixel region. For the sake of explanation, both the source signal line in the pixel region and the source signal line in the pixel region are called source signal lines.
[0058]
In the region 111 shown in FIG. 1C, the routing gate signal lines GDi−2 to GDi + 2 routed to the pixel region 103 are connected to the gate signal lines Gi−2 to Gi + 2, respectively.
[0059]
Note that in FIG. 1C, source signal lines and the like are not illustrated.
[0060]
Similarly to the region 110, signals are input to all the routing gate signal lines GD1 to GDz (z is a natural number) from the entire gate signal line driving circuit 101, and signals are input to the pixel region. In addition, signals are input to the source signal lines S <b> 1 to Sx from the entire source signal line driver circuit 102, and signals are input to the pixel region 103. In the pixel region 103, as in the region 111, all the gate signal lines G1 to Gy are connected to the corresponding routing gate signal lines GD1 to GDz, respectively.
[0061]
Here, it is assumed that the number z of gate signal lines for routing is set to be the same as the number y of gate signal lines.
[0062]
At this time, the number x of source signal lines is generally different from the number y of gate signal lines. If the number x of source signal lines is larger than the number y of gate signal lines, the source signal lines and the routing gate signal lines are alternately routed to the pixel area, and only the source signal lines are in the pixel area. The state where the part drawn around is generated. Alternatively, the wiring interval between the routing gate signal lines is larger than the wiring interval between the source signal lines.
[0063]
The above state may cause variations in pixel luminance when the aperture ratio of the pixel becomes a problem in a transmissive display device. Therefore, the number z of the gate signal lines for routing is set to be the same as the number x of the source signal lines, and xy lines of the routing gate signal lines are not actually input to the gate signal lines. It is good also as a structure handled as wiring.
[0064]
As a first configuration of the first embodiment, a case where the extraction gate signal line is formed in the same layer as the gate signal line will be described as an example.
[0065]
FIG. 2 is a top view illustrating a configuration of part of the pixel region.
[0066]
In FIG. 2A, the routing gate signal lines GDi-1 to GDi + 1 and the gate signal lines Gi-1 to Gi + 1 are formed in the same layer. It is assumed that the gate signal line Gi and the routing gate signal line GDi are connected. On the other hand, the unconnected gate signal line Gi and the routing gate signal line GDj (j is a natural number equal to or less than y different from i) intersect via a wiring formed in a layer different from the gate signal line Gi. .
[0067]
Thus, the routing gate signal lines GD1 to GDy are connected to the gate signal lines G1 to Gy, respectively, in the entire pixel region.
[0068]
FIG. 2B shows an enlarged view of a portion indicated by a region 200 in FIG.
[0069]
The routing gate signal line GDi crosses the gate signal line Gi-1 via the wiring 201 formed in a layer different from the gate signal lines Gi, Gi-1 and the like. That is, before crossing the gate signal line Gi-1, the routing gate signal line GDi formed in the same layer as the gate signal line Gi-1 is connected to the wiring 201 through the contact hole 202a. Further, after crossing the gate signal line Gi-1, the wiring 201 is again connected to the routing gate signal line GDi formed in the same layer as the gate signal line Gi-1 by the contact hole 202b. Thus, the routing gate signal line GDi and the gate signal line Gi are connected.
[0070]
The configuration shown in FIG. 2 is effective for a display device of a type that visually recognizes light emitted without passing through a pixel substrate, such as a reflective liquid crystal display device or an upward emitting OLED display device.
[0071]
Next, as a second configuration of the first embodiment, an example in which the extraction gate signal line is formed in a layer different from the gate signal line will be described with reference to FIGS.
[0072]
5A to 5C are top views illustrating a part of the structure of the pixel region.
[0073]
As shown in FIG. 5A, the extraction gate signal lines GDi and GDi + 1 are formed in a different layer from the gate signal lines Gi and Gi + 1. Note that in FIG. 5A, wirings other than the gate signal line and the routing gate signal line are not illustrated.
[0074]
The routing gate signal line GDi and the gate signal line Gi are connected by a contact hole 501i. Similarly, the routing gate signal line GDi + 1 and the gate signal line Gi + 1 are connected by a contact hole 501i + 1.
[0075]
FIG. 5B shows an example in which the source signal lines Sj and Sj + 1 are arranged so as to overlap with the routing gate signal lines GDi and GDi + 1. At this time, the source signal lines Sj and Sj + 1, the gate signal lines Gi and Gi + 1, and the routing gate signal lines GDi and GDi + 1 are formed in different layers. One pixel is indicated by 500.
[0076]
The routing gate signal line GDi and the gate signal line Gi are connected by a contact hole 502i. Similarly, the routing gate signal line GDi + 1 and the gate signal line Gi + 1 are connected by a contact hole 502i + 1.
[0077]
In a structure in which the source signal line and the routing gate signal line are overlapped as shown in FIG. 5B, the aperture ratio of the pixel can be increased. The structure shown in FIG. 5B is effective for a display device that visually recognizes light emitted through the pixel substrate, such as a transmissive liquid crystal display device or a downward emission OLED display device.
[0078]
FIG. 5C shows an example in which the power supply lines Vi and Vi + 1 are arranged so as to overlap with the routing gate signal lines GDi and GDi + 1. At this time, the power supply lines Vi and Vi + 1, the gate signal lines Gi and Gi + 1, and the routing gate signal lines GDi and GDi + 1 are formed in different layers. Note that the power supply lines Vi and Vi + 1 and the source signal lines Sj and Sj + 1 may be formed in the same layer or in different layers. One pixel is indicated by 500.
[0079]
The routing gate signal line GDi and the gate signal line Gi are connected by a contact hole 503i. Similarly, the routing gate signal line GDi + 1 and the gate signal line Gi + 1 are connected by a contact hole 503i + 1.
[0080]
In the configuration in which the power supply line and the routing gate signal line are overlapped as shown in FIG. 5C, the aperture ratio of the pixel can be increased. The structure shown in FIG. 5C is effective for a display device that visually recognizes light emitted through the pixel substrate, such as a transmissive liquid crystal display device or a downward emitting OLED display device.
[0081]
In Embodiment 1, the gate signal line driver circuit is arranged above the source signal line driver circuit. That is, the source signal line driver circuit is disposed closer to the pixel region than the gate signal line driver circuit, but the gate signal line driver circuit is disposed closer to the pixel region than the source signal line driver circuit. It is also possible.
[0082]
In the display device shown in Embodiment Mode 1, the routing distance of the routing gate signal line can be shortened. Therefore, the first embodiment is effective for a display device in which the area of the pixel region is relatively large.
[0083]
In this embodiment mode, pixels driven by a driving circuit (source signal line driving circuit) for selecting a pixel column and a driving circuit (gate signal line driving circuit) for selecting a pixel row, such as a liquid crystal display device and an OLED display device, are used. It can be freely applied to display devices having any configuration.
[0084]
In addition, a pixel having a known configuration in which a signal line (source signal line) for selecting a pixel column and a signal line (gate signal line) for selecting a pixel row are wired to the pixel of the display device of this embodiment mode. It can be used freely. In addition, each driving circuit (a source signal line driving circuit and a gate signal line driving circuit) can freely use a driving circuit having a known configuration.
[0085]
For example, the gate signal line driver circuit may be of a type configured using a shift register or the like and outputting signals in order, or may be of a type configured by a decoder or the like and capable of outputting signals in any order.
[0086]
(Embodiment 2)
In Embodiment 2, a driver circuit (a source signal line driver circuit and a gate signal line driver circuit) that controls signals input to the plurality of pixels is formed on the same surface as the insulating surface on which the plurality of pixels are formed. In the display device, the gate signal line driving circuit is arranged in parallel with the source signal line driving circuit, and the signal output from the gate signal line driving circuit is routed around the source signal line driving circuit and the periphery of the pixel region. In this configuration, the signal is input to the gate signal line in the pixel region from the horizontal direction. A schematic view of the display device having the above-described configuration is shown in FIG.
[0087]
4, in the display device, a gate signal line driver circuit 301 (301 </ b> A and 301 </ b> B), a source signal line driver circuit 302, a pixel region 303, an FPC substrate 304, and a seal material 306 are arranged on a pixel substrate 300.
[0088]
The gate signal line driver circuit 301 (301A and 301B) is arranged above and below the pixel region 303 so as to be parallel to the source signal line driver circuit 302. An output signal from each gate signal line driver circuit is input to the gate signal line of the pixel region 303 from the left and right of the pixel region 303 by a wiring routed through the region indicated by 333 in the drawing.
[0089]
Note that the gate signal line driver circuit 301 may be disposed only on one side of the upper or lower portion of the pixel region 303.
[0090]
Here, the area of the horizontal frame of the display device can be further reduced by forming a sealing material so as to overlap with the gate signal lines routed to the left and right of the pixel region.
[0091]
Note that in Embodiment Mode 2, a portion of the gate signal line that is routed from the gate signal line driver circuit to the pixel region is referred to as a routing gate signal line, and can be distinguished from the gate signal line in the pixel region. However, for the sake of explanation, both the gate signal line in the pixel region and the gate signal line in the pixel region are called gate signal lines.
[0092]
FIG. 15 is a schematic diagram showing an example of a structure in which the routed gate signal line and the sealing material are arranged to overlap each other.
[0093]
FIG. 15A is a top view of a gate signal line routed to the left of the pixel region. Gate signal lines G <b> 1 to Gy ′ are arranged in parallel and routed to the pixel region 1510 at each location on the left side of the pixel region 1510. A seal material 1511 is formed on the gate signal lines G1 to Gy ′. FIG. 15B is a cross-sectional view of a portion indicated by A to A ′ in FIG. In FIG. 15B, the gate signal lines G1 to Gy ′ are formed on an insulating surface 1501 on the pixel substrate 1500, and a seal material 1511 is formed on the gate signal lines G1 to Gy ′.
[0094]
Further, as shown in FIGS. 15A and 15B, all of the gate signal lines G1 to Gy ′ arranged in parallel beside the pixel region 1510 are overlapped with the seal material 1511. Alternatively, a part of the gate signal lines G1 to Gy ′ arranged in parallel beside the pixel region 1510 may be arranged so as to overlap the sealing material 1511. FIG. 15C is a top view of a structure in which only a part of the gate signal lines G1 to Gy ′ arranged in parallel and routed on the lateral side of the pixel region 1510 is arranged so as to overlap the sealant 1511. Show. In addition, a cross-sectional view taken along B-B ′ in FIG. 15C is FIG. 15D. Note that in FIGS. 15C and 15D, the same portions as those in FIGS. 15A and 15B are denoted by the same reference numerals, and description thereof is omitted.
[0095]
Although FIG. 15 shows a structure in which the sealing material and the gate signal line are formed in contact with each other, the sealing material and the gate signal line may overlap with each other through an interlayer film or the like.
[0096]
Note that in the case where the display device illustrated in FIG. 15 is a liquid crystal display device, a counter substrate, an alignment film, a liquid crystal material, and the like are not illustrated. Further, when the display device shown in FIG. 15 is an OLED display device, a cover material and the like are not shown.
[0097]
The structure in which the gate signal lines in the routing portion are arranged so as to overlap with the sealant can reduce the frame area even when the number of gate signal lines is large.
[0098]
FIG. 3 shows an example of a specific configuration of the display device according to the second embodiment.
[0099]
3A, the same portions as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.
[0100]
The gate signal line driver circuit 301 </ b> A is disposed further above the source signal line driver circuit 302 above the pixel region 303. Further, the gate signal line driver circuit 301 </ b> B is also disposed below the pixel region 303.
[0101]
Output signals of the gate signal line driver circuits 301A and 301B are routed around the source signal line driver circuit 302 and the periphery of the pixel region 303 and input to the pixel region 303.
[0102]
One specific example of the routing of the gate signal lines until the output signals of the gate signal line driver circuits 301A and 301B are input to the pixel region will be described in detail with reference to FIGS. explain.
[0103]
Note that the number of gate signal lines arranged in the pixel region is y (y is a natural number). Here, for the sake of explanation, y is a multiple of 4, but the present invention is not limited to this.
[0104]
First, the gate signal line driver circuit 301A is divided into two blocks 301A_1 and 301A_2. The gate signal line driver circuit 301B is divided into two blocks 301B_1 and 301B_2. The gate signal line driver circuit 301 </ b> A_ <b> 1 is a circuit that inputs signals to the first to (y / 4) gate signal lines G <b> 1 to G (y / 4) arranged in the pixel region 303. A pixel region in which the gate signal lines G1 to G (y / 4) are arranged is denoted by 303_1. The gate signal line driver circuit 301A_2 outputs signals to the (y / 4) +1 to (y / 2) gate signal lines G (y / 4) +1 to G (y / 2) arranged in the pixel region 303. Is a circuit that inputs. A pixel region where the gate signal lines G (y / 4) +1 to G (y / 2) are arranged is denoted by 303_2. The gate signal line driver circuit 301B_1 outputs signals to the (y / 2) +1 to (3y / 4) gate signal lines G (y / 2) +1 to G (3y / 4) arranged in the pixel region 303. Is a circuit that inputs. A pixel region in which the gate signal lines G (y / 2) +1 to G (3y / 4) are arranged is denoted by 303_3. The gate signal line driver circuit 301B_2 is a circuit that inputs signals to the (3y / 4) + 1-th to y-th gate signal lines G (3y / 4) +1 to Gy arranged in the pixel region 303. A pixel region where the gate signal lines G (3y / 4) +1 to Gy are arranged is denoted by 303_4.
[0105]
First, a wiring for inputting an output signal from the gate signal line driver circuit 301A_1 to the region 303_1 is described in detail. 3B to 3D are detailed structures of regions indicated by 311a, 312a, and 313a in FIG. 3A, respectively.
[0106]
As shown in FIG. 3B, signals output from a part 301Aa of the gate signal line driver circuit 301A_1 are input to the gate signal lines Gi-2 to Gi + 2. The direction of the gate signal lines Gi-2 to Gi + 2 is changed between the gate signal line driving circuit 301Aa and a part 302a of the source signal line driving circuit 302. Thus, the signal output from the gate signal line driver circuit 301A_1 is passed through the gate signal lines G1 to G (y / 4) formed in parallel between the source signal line driver circuit 302 and the gate signal line driver circuit 301A_1. Thus, the source signal line driver circuit 302 is routed to the left end. When the gate signal lines G1 to G (y / 4) are routed to the left end of the source signal line driver circuit 302, the direction of the gate signal lines G1 to G (y / 4) is changed, and the region on the left side of the pixel region 303 overlapping with the sealant 306 extends to the left side of the region 303_1. Is routed and input to the area 303_1. FIG. 3C illustrates a part 306a of the sealant 306 and a part 303a of the region 303_1. Thus, as shown in FIG. 3D, signals are input to the gate signal lines Gi−2 to Gi + 2 formed perpendicular to the source signal line (denoted by S in the drawing) in the pixel region 303_1.
[0107]
Next, a wiring for inputting an output signal from the gate signal line driver circuit 301A_2 to the region 303_2 is described in detail. FIGS. 3E to 3G are detailed structures of the regions indicated by 311b, 312b, and 313b in FIG. 3A, respectively.
[0108]
As shown in FIG. 3E, signals output from the part 301Ab of the gate signal line driver circuit 301A_2 are input to the gate signal lines Gj−2 to Gj + 2. The direction of the gate signal lines Gj−2 to Gj + 2 is changed between the gate signal line driver circuit 301Ab and a part 302b of the source signal line driver circuit 302. Thus, signals output from the gate signal line driver circuit 301A_2 are gate signal lines G (y / 4) +1 to G (1) formed in parallel between the source signal line driver circuit 302 and the gate signal line driver circuit 301A_2. It is routed to the right end of the source signal line drive circuit 302 via y / 2). When the gate signal lines G1 to G (y / 4) are routed to the right end of the source signal line driver circuit 302, the direction of the gate signal lines G1 to G (y / 4) is changed, and the region on the right side of the pixel region 303 overlapping with the sealant 306 extends to the right side of the region 303_2. Is routed and input to the area 303_2. FIG. 3F illustrates a part 306b of the sealant 306 and a part 303b of the region 303_2. Thus, as shown in FIG. 3G, signals are input to the gate signal lines Gj−2 to Gj + 2 formed perpendicular to the source signal line (denoted by S in the drawing) in the pixel region 303_2.
[0109]
A wiring for inputting an output signal from the gate signal line driver circuit 301B_1 to the region 303_3 will be described in detail. 3H to 3J are detailed structures of the regions indicated by 311c, 312c, and 313c in FIG. 3A, respectively.
[0110]
As shown in FIG. 3H, signals output from part 301Ba of the gate signal line driver circuit 301B_1 are input to the gate signal lines Gk−2 to Gk + 2. The direction of the gate signal lines Gk−2 to Gk + 2 is changed between the gate signal line driver circuit 301Ba and a part 303c of the pixel region 303_4. Thus, signals output from the gate signal line driver circuit 301B_1 are gate signal lines G (y / 2) +1 to G (3y / 4) formed in parallel between the pixel region 303 and the gate signal line driver circuit 301B_1. ) To the left end of the pixel region 303. The gate signal lines G (y / 2) +1 to G (3y / 4) change direction when drawn to the left end of the pixel region 303, and the region on the left side of the pixel region 303 that overlaps with the sealant 306 is defined as region 303_3. And is input to the area 303_3. FIG. 3I illustrates a part 306c of the sealant 306 and a part 303c of the region 303_1. Thus, as shown in FIG. 3J, signals are input to the gate signal lines Gi−2 to Gi + 2 formed perpendicular to the source signal line (denoted by S in the drawing) in the pixel region 303_3.
[0111]
Similarly, although not illustrated, a signal output from the gate signal line driver circuit 301B_2 is routed between the gate signal line driver circuit 301B_2 and the pixel region 303_4 to the right end of the pixel region 303, and the direction thereof is changed. The region on the right side of the pixel region 303 that overlaps with the material 306 is drawn to the right end of the region 303_4 and input to the region 303_4.
[0112]
Here, the gate signal line driver circuits 301A_1, 301A_2, 301B_1, and 301B_2 are respectively scanned, and signals are sequentially output to the gate signal lines G1 to Gy, whereby signals are sequentially applied to the gate signal lines G1 to Gy in the pixel region 303. Can be entered.
[0113]
With the above-described configuration, the area of the frame in the horizontal direction of the pixel region can be further reduced by the absence of the gate signal line driver circuit on the side of the pixel region. In addition, the width of the left and right picture frames of the display device can be further reduced by forming the sealing material on the upper part of the gate signal lines routed to the left and right of these pixel regions.
[0114]
When the gate signal lines are routed from the four directions of the upper left, upper right, lower left, and lower right of the pixel area as in the above configuration, at most y / 4 gates on the left and right of the pixel area, respectively. Signal lines are arranged in parallel. If the gate signal line driving circuit is arranged only above the pixel region and the gate signal line is routed from one direction on the upper left of the pixel region, a maximum of y gate signal lines are arranged in parallel on the left of the pixel region. Will be placed.
[0115]
As in this embodiment mode, the number of wirings provided in parallel on the lateral side of the pixel region can be reduced by routing the gate signal line from a plurality of directions of the pixel region. In this way, it is possible to further reduce the horizontal frame area of the pixel region.
[0116]
In addition, a signal line or a power supply line that inputs a signal from the FPC substrate to each driving circuit (source signal line driving circuit 302 and gate signal line driving circuit 301) is a gate signal line routed around the pixel region 303. Form in different layers.
[0117]
In the second embodiment as compared with the first embodiment, it is necessary to route the signal output from the gate signal line driver circuit to the left and right of the pixel region 303. Therefore, especially in the case of a display device having a large pixel area, the routing distance of the gate signal lines G1 to Gy becomes long. However, since it is not necessary to dispose a routing gate signal line perpendicular to the gate signal line in the pixel region, the aperture ratio can be increased in the transmissive display device. In addition, since there is no need for the routing gate signal line to pass through the source signal line driving circuit, there are few restrictions on the layout of the source signal line driving circuit.
[0118]
Therefore, the second embodiment is effective for a display device having a relatively small pixel area.
[0119]
In this embodiment mode, pixels driven by a driving circuit (source signal line driving circuit) for selecting a pixel column and a driving circuit (gate signal line driving circuit) for selecting a pixel row, such as a liquid crystal display device and an OLED display device, are used. It can be freely applied to display devices having any configuration.
[0120]
In addition, a pixel having a known configuration in which a signal line (source signal line) for selecting a pixel column and a signal line (gate signal line) for selecting a pixel row are wired to the pixel of the display device of this embodiment mode. It can be used freely. In addition, each driving circuit (a source signal line driving circuit and a gate signal line driving circuit) can freely use a driving circuit having a known configuration.
[0121]
For example, the gate signal line driver circuit may be of a type configured using a shift register or the like and outputting signals in order, or may be of a type configured by a decoder or the like and capable of outputting signals in any order.
[0122]
【Example】
Example 1
In this example, an example of the liquid crystal display device having the structure illustrated in FIG. 5B is described as the second structure of Embodiment 1.
[0123]
FIG. 10 is a circuit diagram showing the configuration of the pixel of this embodiment.
[0124]
In FIG. 10, a source signal line 602_1, a gate signal line 603_1, a switching TFT 607, and a capacitor (retention capacitor) 608 are arranged in one pixel 600.
[0125]
Reference numerals 603_1 to 603_3 denote gate signal lines. Reference numerals 601_1 to 601_3 denote routing gate signal lines. Reference numerals 606_1 to 606_3 denote common lines.
[0126]
In this embodiment, the switching TFT 607 is a dual-gate TFT having a first gate electrode and a second gate electrode. One of the first gate electrode and the second gate electrode of the switching TFT 607 has a potential V com And the other is connected to the gate signal line 603_1.
[0127]
One of a source region and a drain region of the switching TFT 607 is connected to the source signal line 602_1, and the other is connected to one electrode of the storage capacitor 608 and the liquid crystal element 609. The other electrode of the storage capacitor 608 is connected to the common line 606_1.
[0128]
The gate signal line 603_1 is connected to the routing gate signal line 601_1 through the contact hole 605_1. Similarly, the gate signal line 603_2 is connected to the routing gate signal line 601_2 through the contact hole 605_2. The gate signal line 603_3 is connected to the routing gate signal line 601_3 through the contact hole 605_3.
[0129]
FIG. 6 shows a top view and a cross-sectional view of a pixel of the liquid crystal display device having the configuration shown in FIG.
[0130]
In FIG. 6, the same parts as those in FIG.
In FIG. 6, only a pixel electrode is indicated by 609 as a liquid crystal element, and a counter substrate, a liquid crystal layer, an alignment film, and the like are not illustrated.
[0131]
FIG. 6A is a top view of the liquid crystal display device. 6A, the cross-sectional view of A to A ′ is FIG. 6B, the cross-sectional view of BB ′ is FIG. 6C, and the cross-sectional view of C to C ′ is FIG. 6D. is there.
[0132]
As shown in FIG. 6B, one of the source region and the drain region 668a of the switching TFT 607 formed over the pixel substrate 666 is connected to the source signal line 602_1, and the other 668c is connected through the wiring 612. The storage capacitor 608 is connected to one electrode 613 and the pixel electrode 609. Here, the storage capacitor 608 has a structure in which an insulating film 669 is interposed between an electrode 613 formed of a semiconductor layer and a common line 606_1. Here, 670 is an interlayer film.
[0133]
The switching TFT 607 has a first gate electrode 603_1a that is in contact with the channel portion 668b via the insulating film 669 and a second gate electrode 610a that is in contact with the channel portion 668b via the insulating film 667a. It is. Here, the first gate electrode 603_1a corresponds to part of the gate signal line 603_1. The second gate electrode 610a has a potential V com Corresponds to part of the wiring 610 to which is given.
[0134]
The routing gate signal line 601_1 is formed so as to overlap with the source signal line 602_1.
[0135]
As shown in FIG. 6C, the potential V is applied to the second gate electrode 610a of the switching TFT 607. com Is connected to the wiring 614 through the contact hole 611 and is routed over the routing gate signal line 601_2.
[0136]
As shown in FIG. 6D, the routing gate signal line 601_2 is connected to the gate signal line 603_2 through the contact hole 605_2.
[0137]
When the TFT arranged in each pixel is a dual gate type TFT as in the above configuration, a gate signal line is connected to the layer of one of the gate electrodes formed in different layers of the TFT. Then, a routing gate signal line can be formed in the layer in which the other gate electrode is formed.
[0138]
(Example 2)
In this example, an example of the OLED display device having the structure illustrated in FIG. 5C is shown as the second structure in Embodiment 1.
[0139]
FIG. 11 is a circuit diagram showing the configuration of the pixel of this embodiment.
[0140]
In FIG. 11, in one pixel 700, a source signal line 704_1, a gate signal line 703_1, a power supply line 702_2, a switching TFT 706, a driving TFT 707, and a capacitor (retention capacitor) 708 are arranged.
[0141]
Reference numerals 703_1 to 703_3 denote gate signal lines. Reference numerals 701_1 to 701_3 denote routing gate signal lines. 704_1 to 704_3 are source signal lines. Reference numerals 702_1 to 702_3 denote power supply lines.
[0142]
Note that in this embodiment, the switching TFT 706 is a dual-gate TFT having a first gate electrode and a second gate electrode. One of the first gate electrode and the second gate electrode of the switching TFT 706 has a potential V com And the other is connected to the gate signal line 703_1.
[0143]
The driving TFT 707 is also a dual-gate TFT having a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode of the driving TFT 707 are connected.
[0144]
By making the TFT a dual gate type, it is possible to reduce variations in TFT characteristics. In particular, the driving TFT 707 needs to reduce variation in characteristics. Therefore, it is an effective means to make the driving TFT 707 a dual gate type.
[0145]
One of a source region and a drain region of the switching TFT 706 is connected to the source signal line 704_1, and the other is one electrode of the storage capacitor 708 and a gate electrode of the driving TFT 707 (first gate electrode and second gate). Electrode). The other electrode of the storage capacitor 708 is connected to the power supply line 702_2. One of a source region and a drain region of the driving TFT 707 is connected to the power supply line 702_2, and the other is connected to one electrode (pixel electrode) of the OLED element 709.
[0146]
The gate signal line 703_1 is connected to the routing gate signal line 701_1 through the contact hole 705_1. Similarly, the gate signal line 703_2 is connected to the routing gate signal line 701_2 through the contact hole 705_2. The gate signal line 703_3 is connected to the routing gate signal line 701_3 through the contact hole 705_3.
[0147]
FIG. 7 shows a top view and a cross-sectional view of a pixel of the OLED display device having the configuration shown in FIG.
[0148]
In FIG. 7, the same parts as those in FIG. In FIG. 6, only the pixel electrode is indicated by 709 as the OLED element, and the OLED layer, the cover material, etc. are not shown.
[0149]
FIG. 7A is a top view of the OLED display device. 7A, the cross-sectional view of A to A ′ is FIG. 7B, the cross-sectional view of BB ′ is FIG. 7C, and the cross-sectional view of C to C ′ is FIG. 7D. A cross-sectional view of D to D ′ is FIG.
[0150]
As shown in FIG. 7B, one of the source region and the drain region 779a of the switching TFT 706 formed over the pixel substrate 777 is connected to the source signal line 704_1, and the other 779c is connected through the wiring 712. The wiring 715 and the wiring 716 are connected. Reference numeral 781 denotes an interlayer film.
[0151]
The switching TFT 706 includes a first gate electrode 703_1a that is in contact with the channel portion 779b via the insulating film 780 and a second gate electrode 710a that is in contact with the channel portion 779b via the insulating film 778. It is. Here, the first gate electrode 703_1a corresponds to part of the gate signal line 703_1. The second gate electrode 710a has a potential V com Corresponds to a part of the wiring 710.
[0152]
The routing gate signal line 701_1 is formed so as to overlap with the power supply line 702_1.
[0153]
As shown in FIG. 7C, one of the source region and the drain region 782a of the driving TFT 707 is connected to the pixel electrode 709 through a wiring 717, and the other 782c is connected to the power supply line 702_2. Further, the routing gate signal line 701_2 and the power supply line 702_2 are formed to overlap each other.
[0154]
The driving TFT 707 includes a first gate electrode 715a in contact with the channel portion 782b through the insulating film 780 and a dual gate TFT having a second gate electrode 716a in contact with the channel portion 782b through the insulating film 778. It is. Here, the first gate electrode 715 a corresponds to part of the wiring 715. The second gate electrode 716 a corresponds to part of the wiring 716. Note that the wiring 715 and the wiring 716 are connected (see FIG. 7D).
[0155]
As illustrated in FIG. 7D, the wiring 715 and the wiring 716 are connected. The wiring 715 corresponds to one electrode of the storage capacitor 708. The other electrode of the storage capacitor is 783 formed of a semiconductor layer, and 783 is connected to the power supply line 702_2 through a contact hole 784.
[0156]
Further, the routing gate signal line 701_2 is connected to the gate signal line 703_2 through the contact hole 705_2.
[0157]
As shown in FIG. 7E, the potential V is applied to the second gate electrode 710a of the switching TFT 706. com Is connected to the wiring 714 through the contact hole 711 and is routed on the routing gate signal line 701_2.
[0158]
When the TFT arranged in each pixel is a dual gate type TFT as in the above configuration, a gate signal line is connected to the layer of one of the gate electrodes formed in different layers of the TFT. Then, a routing gate signal line can be formed in the layer in which the other gate electrode is formed.
[0159]
(Example 3)
In this example, as the second structure of the first embodiment, an example of the OLED display device having the structure shown in FIG.
[0160]
FIG. 12 is a circuit diagram showing the configuration of the pixel of this embodiment. In FIG. 12, the same parts as those in FIG. 11 are denoted by the same reference numerals.
[0161]
In FIG. 12, each pixel 724 includes a source signal line 704_1, a gate signal line 703_1, a power supply line 702_2, a switching TFT 706, a driving TFT 707, an erasing TFT 722, and a capacitor (retention capacitor) 708. It is arranged.
[0162]
Reference numerals 703_1 to 703_3 denote gate signal lines. Reference numerals 701_1 to 701_3 denote routing gate signal lines. Reference numerals 721_1 to 721_3 denote erase gate signal lines. Reference numerals 720_1 to 720_3 denote routing erase gate signal lines. 704_1 to 704_3 are source signal lines. Reference numerals 702_1 to 702_3 denote power supply lines.
[0163]
Note that in this embodiment, the switching TFT 706 is a dual-gate TFT having a first gate electrode and a second gate electrode. One of the first gate electrode and the second gate electrode of the switching TFT 706 has a potential V com And the other is connected to the gate signal line 703_1.
[0164]
The driving TFT 707 is also a dual-gate TFT having a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode of the driving TFT 707 are connected.
[0165]
Further, it is assumed that the erasing TFT 722 is also a dual gate TFT having a first gate electrode and a second gate electrode. One of the first gate electrode and the second gate electrode of the erasing TFT 722 has a potential V com The other is connected to the erasing gate signal line 721_1.
[0166]
One of a source region and a drain region of the switching TFT 706 is connected to the source signal line 704_1, and the other is one electrode of the storage capacitor 708 and a gate electrode of the driving TFT 707 (first gate electrode and second gate). Electrode). The other electrode of the storage capacitor 708 is connected to the power supply line 702_2. One of a source region and a drain region of the driving TFT 707 is connected to the power supply line 702_2, and the other is connected to one electrode (pixel electrode) of the OLED element 709.
[0167]
One of a source region and a drain region of the erasing TFT 722 is connected to the power supply line 702_2, and the other is connected to a gate electrode (first gate electrode and second gate electrode) of the driving TFT 707.
[0168]
The gate signal line 703_1 is connected to the routing gate signal line 701_1 through the contact hole 705_1. Similarly, the gate signal line 703_2 is connected to the routing gate signal line 701_2 through the contact hole 705_2. The gate signal line 703_3 is connected to the routing gate signal line 701_3 through the contact hole 705_3.
[0169]
The erase gate signal line 721_1 is connected to the routing erase gate signal line 720_1 through a contact hole 723_1. Similarly, the erasing gate signal line 721_2 is connected to the routing erasing gate signal line 720_2 through the contact hole 723_2. The erasing gate signal line 721_3 is connected to the routing erasing gate signal line 720_3 through the contact hole 723_3.
[0170]
FIG. 8 shows a top view and a cross-sectional view of a pixel of the OLED display device having the configuration shown in FIG.
[0171]
In FIG. 8, the same parts as those in FIG. In FIG. 8, only the pixel electrode 709 is shown as the OLED element, and the OLED layer, the cover material, etc. are not shown.
[0172]
FIG. 8A is a top view of the OLED display device. 8A, the cross-sectional view of A to A ′ is FIG. 8B, the cross-sectional view of C to C ′ is FIG. 8C, and the cross-sectional view of E to E ′ is FIG. A cross-sectional view of D to D ′ is FIG. Note that in FIG. 8A, the cross-sectional views of B to B ′ are the same as those in FIG.
[0173]
As shown in FIG. 8B, one of the source region and the drain region 779a of the switching TFT 706 formed over the pixel substrate 777 is connected to the source signal line 704_1, and the other 779c is connected through the wiring 712. The wiring 715 and the wiring 716 are connected. Reference numeral 781 denotes an interlayer film.
[0174]
The switching TFT 706 includes a first gate electrode 703_1a that is in contact with the channel portion 779b via the insulating film 780 and a second gate electrode 710a that is in contact with the channel portion 779b via the insulating film 778. It is. Here, the first gate electrode 703_1a corresponds to part of the gate signal line 703_1. The second gate electrode 710a has a potential V com Corresponds to a part of the wiring 710.
[0175]
The routing gate signal line 701_1 is formed so as to overlap with the power supply line 702_1. The lead-out erase gate signal line 720_1 is formed so as to overlap with the source signal line 704_1.
[0176]
As illustrated in FIG. 7C, the wiring 715 and the wiring 716 are connected. The wiring 715 corresponds to one electrode of the storage capacitor 708. The other electrode of the storage capacitor is 783 formed of a semiconductor layer, and 783 is connected to the power supply line 702_2 through a contact hole 784.
[0177]
Further, the routing gate signal line 701_2 is connected to the gate signal line 703_2 through the contact hole 705_2.
[0178]
As shown in FIG. 8D, one of the source region and the drain region 799a of the erasing TFT 722 is connected to the wiring 715, and the other 799c is connected to the power supply line 702_2.
[0179]
The erasing TFT 722 includes a first gate electrode 721_1a that is in contact with the channel portion 799b through the insulating film 780 and a second gate electrode 710a that is in contact with the channel portion 799b through the insulating film 778. It is. Here, the first gate electrode 721_1a corresponds to part of the erasing gate signal line 721_1. The second gate electrode 710a has a potential V com Corresponds to a part of the wiring 710.
[0180]
The routing erasing gate signal line 720_1 is formed so as to overlap with the source signal line 704_1. The leading erasing gate signal line 720_1 is connected to the erasing gate signal line 721_1 through a contact hole 723_1.
[0181]
As shown in FIG. 7E, the potential V is applied to the second gate electrode of the switching TFT 706T and the second gate electrode 710a of the erasing TFT 722. com Is connected to the wiring 714 through the contact hole 711, and is routed over the routing gate signal line 701_2 and the routing erase gate signal line 720_1.
[0182]
In the case where the TFT arranged in each pixel is a dual gate type TFT as in the above configuration, among the gate electrodes formed in different layers of the TFT, the gate signal line and the gate signal line are formed on the layer where one gate electrode is formed. An erasing gate signal line can be formed, and a routing gate signal line and a routing erasing gate signal line can be formed in the layer where the other gate electrode is formed.
[0183]
Example 4
In this example, as a specific example of the display device having the structure shown in FIG. 4 in Embodiment Mode 2, an example different from the example shown in FIG. 3 is shown.
[0184]
FIG. 13 shows the configuration of the display device of this embodiment. Note that the same portions as those in FIG. 3 shown in Embodiment Mode 2 are denoted by the same reference numerals.
[0185]
FIG. 13A is a top view of the display device. On the pixel substrate 300, a gate signal line driver circuit 1301 (1301A and 1301B), a source signal line driver circuit 302, a pixel region 303, an FPC substrate 304, and a sealant 306 are arranged.
[0186]
Output signals of the gate signal line driver circuits 1301A and 1301B are routed around the periphery of the source signal line driver circuit 302 and the periphery of the pixel region 303 and input to the pixel region 303.
[0187]
One specific example of the routing of the gate signal lines until the output signals of the gate signal line driver circuits 1301A and 1301B are input to the pixel region 303 will be described in detail with reference to FIGS. 13B to 13F. Explained.
[0188]
Note that the number of gate signal lines arranged in the pixel region is y (y is a natural number). Here, for the sake of explanation, y is a multiple of 4, but the present invention is not limited to this.
[0189]
First, the gate signal line driver circuit 1301A is divided into two blocks 1301A_1 and 1301A_2. The gate signal line driver circuit 1301B is divided into two blocks 1301B_1 and 1301B_2.
[0190]
The gate signal line driver circuit 1301A_1 inputs a signal to even-numbered gate signal lines among the first to (y / 2) gate signal lines G1 to G (y / 2) arranged in the pixel region 303. Suppose that it is a circuit. The gate signal line driver circuit 1301A_2 inputs a signal to an odd-numbered gate signal line among the first to (y / 2) gate signal lines G1 to G (y / 2) arranged in the pixel region 303. Suppose that it is a circuit. A pixel region 303 in which the gate signal lines G1 to G (y / 2) to which signals output from the gate signal line driver circuits 1301A_1 and 1301A_2 are input is denoted by 303_A.
[0191]
Similarly, the gate signal line driver circuit 1301B_1 includes an even-numbered gate signal line among the (y / 2) +1 to y gate signal lines G (y / 2) +1 to Gy arranged in the pixel region 303. It is assumed that this is a circuit that inputs a signal to. The gate signal line driver circuit 1301B_2 sends signals to odd-numbered gate signal lines among (y / 2) +1 to y gate signal lines G (y / 2) +1 to Gy arranged in the pixel region 303. It is assumed that the circuit is an input circuit. A pixel region 303 in which gate signal lines G (y / 2) +1 to Gy to which signals output from the gate signal line driver circuits 1301B_1 and 1301B_2 are input is denoted by 303_B.
[0192]
First, wiring for inputting an output signal from the gate signal line driver circuit 1301A_1 to the region 303_A is described in detail. FIGS. 13B and 13C are detailed structures of the regions indicated by 1311a and 1312a in FIG. 13A, respectively.
[0193]
As shown in FIG. 13B, the signal output from the part 1301Aa of the gate signal line driver circuit 1301A_1 is input to the gate signal lines Gi-4, Gi-2, Gi, Gi + 2, and Gi + 4. The direction of the gate signal lines Gi-4, Gi-2, Gi, Gi + 2, and Gi + 4 is changed between the gate signal line driving circuit 1301Aa and a part 302a of the source signal line driving circuit 302. Thus, the signal output from the gate signal line driver circuit 1301A_1 is selected from the gate signal lines G1 to G (y / 2) formed in parallel between the source signal line driver circuit 302 and the gate signal line driver circuit 1301A_1. Are routed to the left end of the source signal line driving circuit 302 through the even-numbered gate signal lines. When the gate signal line is routed to the left end of the source signal line driver circuit 302, the direction is changed, and the region on the left side of the pixel region 303 that overlaps with the sealant 306 is routed to the left side of the region 303_A and is input to the region 303_A. Is done. FIG. 13C illustrates a part 306a of the sealant 306 and a part 303a of the region 303_A.
[0194]
Next, a wiring for inputting an output signal from the gate signal line driver circuit 1301A_2 to the region 303_A will be described in detail. FIGS. 13D and 13E are detailed structures of regions indicated by 1311b and 1312b in FIG. 13A, respectively.
[0195]
As shown in FIG. 13D, the signal output from the part 1301Ab of the gate signal line driver circuit 1301A_2 is input to the gate signal lines Gi-5, Gi-3, Gi-1, Gi + 1, Gi + 3. The direction of the gate signal lines Gi-5, Gi-3, Gi-1, Gi + 1, Gi + 3 is changed between the gate signal line driver circuit 1301Ab and a part 302b of the source signal line driver circuit 302. Thus, the signal output from the gate signal line driver circuit 1301A_2 is the gate signal line G1 to G (y / 2) formed in parallel between the source signal line driver circuit 302 and the gate signal line driver circuit 1301A_2. Are routed to the right end of the source signal line driving circuit 302 through the odd-numbered gate signal lines. When the gate signal line is routed to the right end of the source signal line driver circuit 302, the direction is changed, and the region on the right side of the pixel region 303 that overlaps with the sealant 306 is routed to the right side of the region 303_A and input to the region 303_A. Is done. FIG. 13E illustrates a part 306b of the sealant 306 and a part 303b of the region 303_A.
[0196]
As shown in FIG. 13F, with the above structure, signals are transmitted to the gate signal lines Gi-5 to Gi + 4 formed perpendicular to the source signal line (denoted as S in the drawing) in the part 1313ab of the pixel region 303_A. Entered.
[0197]
Similarly, gate signal lines are drawn from the gate signal line driver circuits 1301B_1 and 1301B_2, and connected to the gate signal lines in the pixel region 303_B.
[0198]
Thus, the signals of the gate signal line driver circuits 1301A and 1301B are input to the gate signal lines G1 to Gy in the pixel region 303.
[0199]
In addition, a signal line or a power supply line that inputs a signal from the FPC substrate to each driving circuit (source signal line driving circuit 302 and gate signal line driving circuit 1301) is a gate signal line routed around the pixel region 303. Form in different layers.
[0200]
The present embodiment includes a pixel driven by a driving circuit (source signal line driving circuit) for selecting a pixel column and a driving circuit (gate signal line driving circuit) for selecting a pixel row, such as a liquid crystal display device or an OLED display device. It can be freely applied to display devices of any configuration.
[0201]
In addition, a pixel having a known configuration in which a signal line (source signal line) for selecting a pixel column and a signal line (gate signal line) for selecting a pixel row are wired to the pixel of the display device of this embodiment can be freely used. Can be used. In addition, each driving circuit (a source signal line driving circuit and a gate signal line driving circuit) can freely use a driving circuit having a known configuration.
[0202]
For example, the gate signal line driver circuit may be of a type configured using a shift register or the like and outputting signals in order, or may be of a type configured by a decoder or the like and capable of outputting signals in any order.
[0203]
(Example 5)
In this embodiment, an example in which the display device of the present invention is applied to an OLED display device is shown.
[0204]
FIG. 16 is a cross-sectional view illustrating a configuration of a pixel of the OLED display device of the present invention. In the present embodiment, only the driving TFT that allows a drain current to flow through the OLED element and the OLED element are shown as elements constituting the pixel of the OLED display device.
[0205]
In this specification, the OLED element indicates an element having a structure in which an OLED layer that emits light by an electroluminescence effect when an electric field is generated is sandwiched between an anode and a cathode.
[0206]
Note that in this specification, the OLED element means light emission (fluorescence) when transitioning from a singlet exciton to a ground state and light emission (phosphorescence) when transitioning from a triplet exciton to a ground state. ) Are both used.
[0207]
Examples of the OLED layer include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. The OLED element is basically shown in a structure in which anode / light-emitting layer / cathode is stacked in this order, but in addition to this, a structure in which anode / hole injection layer / light-emitting layer / electron injection layer / cathode is stacked in order. And an anode / hole injection layer / hole transport layer / light-emitting layer / electron transport layer / electron injection layer / cathode layer.
[0208]
In FIG. 16A, a driving TFT 1601 is formed over a pixel substrate 1600. The driving TFT 1601 includes a first gate electrode 1603a, a second gate electrode 1603b, and a channel formation sandwiched between the first electrode and the second gate electrode with the insulating film 1602 and the insulating film 1605 interposed therebetween. This is a dual-gate TFT having a region 1604. One of the source region and the drain region of the driving TFT 1601 is 1604a, and the other is 1604c. After the driving TFT 1601 is formed, an interlayer film 1606 is formed.
[0209]
Note that the driving TFT 1601 is not limited to the structure shown in the drawing, and a TFT having a known structure can be freely used.
[0210]
Next, a transparent conductive film typified by ITO or the like is formed and patterned into a desired shape to form a pixel electrode 1608. Here, the pixel electrode 1608 is an anode. Contact holes reaching the source and drain regions of the driving TFT, 1604a and 1604c are formed in the interlayer film 1606, and a laminated film made of Al and Ti containing Ti and Ti is formed and patterned into a desired shape. A wiring 1607 and a wiring 1609 are formed. The wiring 1609 is brought into conduction by being in contact with the pixel electrode 1608.
[0211]
Subsequently, an insulating film made of an organic resin material such as acrylic is formed, and an opening is formed at a position corresponding to the pixel electrode 1608 of the OLED element 1614 to form the insulating film 1610. Here, in order to avoid problems such as deterioration of the OLED layer and step breakage due to the step of the side wall of the opening, the opening is formed to have a sufficiently gentle tapered side wall.
[0212]
Next, after the OLED layer 1611 is formed, the counter electrode (cathode) 1612 of the OLED element 1614 is formed with a cesium (Cs) film having a thickness of 2 [nm] or less and silver (Ag) having a thickness of 10 [nm] or less. ) It is formed by a laminated film in which films are sequentially formed. By making the thickness of the counter electrode 1612 of the OLED element 1614 extremely small, light generated in the OLED layer 1611 passes through the counter electrode 1612 and is emitted in a direction opposite to that of the pixel substrate 1600. Next, a protective film 1613 is formed for the purpose of protecting the OLED element 1614.
[0213]
As described above, in the case of a display device that emits light in the direction opposite to that of the pixel substrate 1600, with respect to the OLED element 1614, elements such as the driving TFT 1601 formed on the pixel substrate 1600 side are used. Since it is not necessary to visually recognize the light emission of the OLED element 1614, the aperture ratio can be increased.
[0214]
Note that TiN or the like is used as a material for the pixel electrode 1608, the pixel electrode is used as a cathode, and the counter electrode 1612 is formed using a transparent conductive film typified by ITO or the like as an anode. In this manner, the light emitted from the OLED layer 1611 may be emitted from the anode side in the direction opposite to the pixel substrate 1600.
[0215]
FIG. 16B is a cross-sectional view illustrating a structure of a pixel having an OLED element having a structure different from that in FIG.
[0216]
In FIG. 16B, the same portions as those in FIG. 16A are described using the same reference numerals.
[0217]
In FIG. 16B, until the driver TFT 1601 is formed and the interlayer film 1606 is formed, it can be formed in the same manner as the structure shown in FIG.
[0218]
Next, contact holes reaching the source and drain regions 1604 a and 1604 c of the driving TFT are formed in the interlayer film 1606. Thereafter, a laminated film made of Ti and Al containing Ti and Ti is formed, and then a transparent conductive film typified by ITO or the like is formed. A laminated film composed of Ti, Ti containing Ti and Ti, and a transparent conductive film typified by TO or the like are patterned into a desired shape to form a wiring 1621 composed of 1617 and 1618b, a wiring 1619, and a pixel An electrode 1620 is formed. The pixel electrode 1620 corresponds to the anode of the OLED element 1624.
[0219]
Subsequently, an insulating film made of an organic resin material such as acrylic is formed, and an opening is formed at a position corresponding to the pixel electrode 1620 of the OLED element 1624 to form the insulating film 1610. Here, in order to avoid problems such as deterioration of the OLED layer and step breakage due to the step of the side wall of the opening, the opening is formed to have a sufficiently gentle tapered side wall.
[0220]
Next, after the OLED layer 1611 is formed, the counter electrode (cathode) 1612 of the OLED element 1624 is formed with a cesium (Cs) film having a thickness of 2 [nm] or less and silver (Ag) having a thickness of 10 [nm] or less. ) It is formed by a laminated film in which films are sequentially formed. By making the thickness of the counter electrode 1612 of the OLED element 1624 extremely small, light generated in the OLED layer 1611 passes through the counter electrode 1612 and is emitted in a direction opposite to that of the pixel substrate 1600. Next, a protective film 1613 is formed for the purpose of protecting the OLED element 1624.
[0221]
As described above, in the case of a display device that emits light in a direction opposite to that of the pixel substrate 1600, the OLED element 1624 is formed on the pixel substrate 1600 side through elements such as the driving TFT 1601. Since it is not necessary to visually recognize the light emission of the OLED element 1624, the aperture ratio can be increased.
[0222]
Note that as a material of the pixel electrode 1620 and the wiring 1621, TiN or the like is used, the pixel electrode is used as a cathode, and the counter electrode 1612 is formed using a transparent conductive film typified by ITO or the like to be an anode. In this manner, the light emitted from the OLED layer 1611 may be emitted from the anode side in the direction opposite to the pixel substrate 1600.
[0223]
The pixel having the structure illustrated in FIG. 16B includes a wiring 1619 connected to the source region or the drain region of the driving TFT and a pixel electrode 1620 as compared with the pixel having the structure illustrated in FIG. Since patterning can be performed using a common photomask, it is possible to reduce the number of photomasks required in the manufacturing process and simplify the process.
[0224]
This embodiment can be implemented by freely combining with Embodiments 1 to 4.
[0225]
(Example 6)
In this embodiment, the display device of the present invention can be used for an electronic device.
[0226]
An example of an electronic device using the display device of the present invention is shown in FIG.
[0227]
FIG. 14A illustrates a portable information terminal. The portable information terminal includes a main body 1400, a display unit 1401, a power switch 1402, an operation key 1403, an external connection port 1404, an audio output unit 1405, an audio input unit 1406, a camera unit 1407, and the like. The display device of the present invention can be used for the display portion 1401. As a result, the frame width W1 around the display screen of the display portion 1401 shown in FIG. 14A can be reduced, so that the width W2 of the main body of the portable information device can be reduced.
[0228]
Thus, a portable information device that is convenient to carry is provided.
[0229]
FIG. 14B illustrates a mobile phone. A cellular phone includes a main body 1410, a display portion 1411, a power switch 1412, operation keys 1413, an external input port 1414, an audio output portion 1415, an audio input portion 1416, an antenna 1417, and the like. The display device of the present invention can be used for the display portion 1411. As a result, the width W3 of the frame of the display screen of the display unit shown by 14 (B) in the figure can be reduced, so that the width W4 of the main body of the mobile phone can be reduced.
[0230]
Thus, a mobile phone that is convenient to carry is provided.
[0231]
The display device of the present invention is not limited to the above, and can be used for various electronic devices.
[0232]
This embodiment can be implemented by freely combining with Embodiments 1 to 4.
[0233]
【The invention's effect】
As described above, the present invention provides a driver circuit (a source signal line driver circuit and a gate signal line driver circuit) that controls signals input to a plurality of pixels on the same surface as the insulating surface on which the pixels are formed. In the display device in which the gate signal line driving circuit is formed, the gate signal line driving circuit is arranged in parallel with the source signal line driving circuit. Thus, the area of the horizontal frame of the display device can be reduced.
[Brief description of the drawings]
FIG. 1 shows a structure of a display device of the present invention.
FIG. 2 is a diagram showing a wiring structure of a pixel of a display device of the present invention.
FIG. 3 shows a structure of a display device of the present invention.
FIG. 4 is a schematic diagram showing a configuration of a display device of the present invention.
FIG. 5 is a diagram showing a wiring structure of a pixel of a display device of the present invention.
6 is a diagram showing a structure of a pixel of a liquid crystal display device of the present invention. FIG.
FIG. 7 is a diagram showing a pixel configuration of an OLED display device of the present invention.
FIG. 8 is a diagram showing a configuration of a pixel of an OLED display device of the present invention.
FIG. 9 is a diagram showing a configuration of a conventional display device.
FIG. 10 is a circuit diagram illustrating a structure of a pixel of a liquid crystal display device of the present invention.
FIG. 11 is a circuit diagram showing a configuration of a pixel of the OLED display device of the present invention.
FIG. 12 is a circuit diagram showing a configuration of a pixel of the OLED display device of the present invention.
FIG. 13 shows a structure of a display device of the present invention.
FIG 14 is a diagram showing an electronic device using the display device of the invention.
FIG. 15 is a diagram showing a configuration of a routing member between a sealing material and a gate signal line of a display device of the present invention.
FIG. 16 is a cross-sectional view showing the structure of a pixel of an OLED display device of the present invention.

Claims (5)

  1. A pixel region having a plurality of pixels arranged in a matrix, a plurality of first wirings and a plurality of second wirings electrically connected to the plurality of pixels, and a plurality of routing wirings ;
    A first driving circuit for inputting a signal through the lead wirings to each of the plurality of first wires,
    A second drive circuit for inputting a signal to the plurality of second wirings,
    The pixel region, the first drive circuit, and the second drive circuit are formed on the same substrate,
    The first driving circuit and the second driving circuit are arranged in the same one of four directions of upper, lower, left and right of the pixel region,
    The number of the second wiring is larger than the number of the first wiring,
    The number of the routing wirings is the same as the number of the second wirings.
  2. In claim 1,
    The display device, wherein the plurality of second wirings are parallel to the routing wiring.
  3. In claim 1 or claim 2 ,
    The first driving circuit is a gate signal line driving circuit, and the second driving circuit is a source signal line driving circuit;
    The display device, wherein the second driving circuit is disposed at a position closer to the pixel region than the first driving circuit.
  4. In any one of Claim 1 thru | or 3 ,
    The display device is a transmissive type.
  5. In any one of Claims 1 thru | or 4 ,
    An electronic apparatus using the display device.
JP2001241463A 2001-08-08 2001-08-08 Display device and electronic device Active JP4789369B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001241463A JP4789369B2 (en) 2001-08-08 2001-08-08 Display device and electronic device

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP2001241463A JP4789369B2 (en) 2001-08-08 2001-08-08 Display device and electronic device
TW091116752A TW546597B (en) 2001-08-08 2002-07-26 Display device
US10/211,294 US6862008B2 (en) 2001-08-08 2002-08-05 Display device
KR1020020046259A KR100935415B1 (en) 2001-08-08 2002-08-06 A display device
CN2009101795791A CN101666951B (en) 2001-08-08 2002-08-08 Display device
CNB021437408A CN100565311C (en) 2001-08-08 2002-08-08 Display device
US11/041,454 US7573469B2 (en) 2001-08-08 2005-01-25 Display device
US12/535,734 US9972670B2 (en) 2001-08-08 2009-08-05 Display device
US13/594,944 US9105594B2 (en) 2001-08-08 2012-08-27 Display device

Publications (3)

Publication Number Publication Date
JP2003058075A JP2003058075A (en) 2003-02-28
JP2003058075A5 JP2003058075A5 (en) 2007-12-06
JP4789369B2 true JP4789369B2 (en) 2011-10-12

Family

ID=19071901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001241463A Active JP4789369B2 (en) 2001-08-08 2001-08-08 Display device and electronic device

Country Status (5)

Country Link
US (4) US6862008B2 (en)
JP (1) JP4789369B2 (en)
KR (1) KR100935415B1 (en)
CN (2) CN100565311C (en)
TW (1) TW546597B (en)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4789369B2 (en) 2001-08-08 2011-10-12 株式会社半導体エネルギー研究所 Display device and electronic device
US7078322B2 (en) 2001-11-29 2006-07-18 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor
EP1326273B1 (en) * 2001-12-28 2012-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4011344B2 (en) * 2001-12-28 2007-11-21 株式会社半導体エネルギー研究所 A method for manufacturing a semiconductor device
US6933527B2 (en) * 2001-12-28 2005-08-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US6841797B2 (en) * 2002-01-17 2005-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device formed over a surface with a drepession portion and a projection portion
US6847050B2 (en) 2002-03-15 2005-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and semiconductor device comprising the same
DE10308515B4 (en) 2003-02-26 2007-01-25 Schott Ag A process for producing organic light-emitting diodes and organic light-emitting diode
US7250720B2 (en) 2003-04-25 2007-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device
JP4689188B2 (en) * 2003-04-25 2011-05-25 株式会社半導体エネルギー研究所 Display device
JP3947848B2 (en) 2003-06-12 2007-07-25 セイコーエプソン株式会社 Electro-optical device and electronic equipment
JP2005005227A (en) * 2003-06-16 2005-01-06 Hitachi Displays Ltd Organic el light-emitting display device
KR100551046B1 (en) * 2003-08-28 2006-02-09 삼성에스디아이 주식회사 Organic EL device
EP1750622B1 (en) * 2004-05-05 2013-02-27 Direct Flow Medical, Inc. Unstented heart valve with formed in place support structure
KR100601324B1 (en) * 2004-07-27 2006-07-14 엘지전자 주식회사 Organic electroluminescent device
US20060054889A1 (en) * 2004-09-16 2006-03-16 Jang-Soo Kim Thin film transistor array panel
US7532187B2 (en) * 2004-09-28 2009-05-12 Sharp Laboratories Of America, Inc. Dual-gate transistor display
US8619007B2 (en) 2005-03-31 2013-12-31 Lg Display Co., Ltd. Electro-luminescence display device for implementing compact panel and driving method thereof
DE102006014873B4 (en) * 2005-03-31 2019-01-03 Lg Display Co., Ltd. Driving method for an electroluminescent display device
EP1717789B1 (en) * 2005-04-26 2016-04-13 LG Display Co., Ltd. Electro luminescence display device
KR101149936B1 (en) * 2005-04-26 2012-05-30 엘지디스플레이 주식회사 Organic light emitting panel
KR100624314B1 (en) * 2005-06-22 2006-09-07 삼성에스디아이 주식회사 Light emission display device and thin film transistor
KR101227134B1 (en) * 2005-07-05 2013-01-28 엘지디스플레이 주식회사 Organic electroluminescent device
TWI330726B (en) * 2005-09-05 2010-09-21 Au Optronics Corp Display apparatus, thin-film-transistor discharge method and electrical driving method therefor
KR101240648B1 (en) * 2006-01-10 2013-03-08 삼성디스플레이 주식회사 Organic light emitting diode display and method for manufacturing the same
JP4911983B2 (en) * 2006-02-08 2012-04-04 パナソニック液晶ディスプレイ株式会社 Display device
TWI336945B (en) 2006-06-15 2011-02-01 Au Optronics Corp Dual-gate transistor and pixel structure using the same
KR20080009889A (en) * 2006-07-25 2008-01-30 삼성전자주식회사 Liquid crystal display
KR101274037B1 (en) * 2006-09-25 2013-06-12 삼성디스플레이 주식회사 Display apparatus
JP5282372B2 (en) * 2007-05-11 2013-09-04 ソニー株式会社 Display device and electronic device
JP2008292654A (en) * 2007-05-23 2008-12-04 Funai Electric Co Ltd Liquid crystal module
JP2011509498A (en) * 2007-12-14 2011-03-24 イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニーE.I.Du Pont De Nemours And Company Backplane structure for electronic devices
JP5207885B2 (en) * 2008-09-03 2013-06-12 キヤノン株式会社 Pixel circuit, light emitting display device and driving method thereof
JP2010157493A (en) * 2008-12-02 2010-07-15 Sony Corp Display device and method of manufacturing the same
JP5298862B2 (en) * 2009-01-07 2013-09-25 株式会社ジャパンディスプレイ Liquid Crystal Display
TWI393947B (en) * 2009-06-12 2013-04-21 Au Optronics Corp Display device
US20110058770A1 (en) * 2009-09-10 2011-03-10 E. I. Du Pont De Nemours And Company Sub-surface engraving of oled substrates for improved optical outcoupling
JP5532797B2 (en) * 2009-09-29 2014-06-25 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
JP2011112724A (en) * 2009-11-24 2011-06-09 Sony Corp Display device, method of driving the same and electronic equipment
JP2011112723A (en) * 2009-11-24 2011-06-09 Sony Corp Display device, method of driving the same and electronic equipment
CN102439652B (en) * 2010-04-05 2015-05-06 松下电器产业株式会社 Organic el display device and method for controlling same
TWI408472B (en) * 2010-04-12 2013-09-11 Wintek Corp Active device array substrate
KR101142752B1 (en) * 2010-04-13 2012-05-03 삼성모바일디스플레이주식회사 Flat Panel Display Device
CN102403320B (en) * 2010-09-16 2015-05-20 上海天马微电子有限公司 Array substrate, fabricating method for same and liquid crystal display panel
CN102466931B (en) * 2010-11-03 2015-01-21 上海天马微电子有限公司 Array substrate, manufacture method thereof and liquid crystal panel
TWI407406B (en) * 2010-12-30 2013-09-01 Au Optronics Corp Pixel driving circuit of an organic light emitting diode
KR20120089123A (en) * 2011-02-01 2012-08-09 삼성디스플레이 주식회사 Organic light emitting display apparatus
CN102891163B (en) * 2011-07-19 2016-09-07 群创光电股份有限公司 Organic electroluminescent display device
TWI467756B (en) * 2011-07-19 2015-01-01 Chimei Innolux Corp Organic light emitting display
JP5832399B2 (en) 2011-09-16 2015-12-16 株式会社半導体エネルギー研究所 Light emitting device
US20130083080A1 (en) * 2011-09-30 2013-04-04 Apple Inc. Optical system and method to mimic zero-border display
KR101910340B1 (en) 2011-10-12 2018-10-23 삼성디스플레이 주식회사 Liquid crystal display having narrow bezel
KR102004710B1 (en) * 2011-11-04 2019-07-30 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
KR101873723B1 (en) 2012-02-02 2018-07-04 삼성디스플레이 주식회사 Organic electro luminescence display device
CN104737218B (en) * 2012-11-16 2017-03-01 夏普株式会社 Driving module, a display device and a multi-display apparatus
KR101906248B1 (en) * 2012-12-13 2018-10-11 엘지디스플레이 주식회사 Liquid crystal display device
WO2014117144A1 (en) * 2013-01-28 2014-07-31 Motorola Mobility Llc A symmetrical flat panel display
JP5526265B2 (en) * 2013-05-31 2014-06-18 株式会社ジャパンディスプレイ Liquid crystal display
TWI653755B (en) 2013-09-12 2019-03-11 日商新力股份有限公司 Display device, method of manufacturing the same, and electronic device
GB2519085B (en) * 2013-10-08 2018-09-26 Flexenable Ltd Transistor array routing
CN103941500B (en) * 2013-12-11 2017-10-24 上海天马微电子有限公司 A panel in a display device and a display
KR20150078645A (en) * 2013-12-31 2015-07-08 삼성디스플레이 주식회사 Display panel and display apparatus having them
US9336709B2 (en) 2014-04-25 2016-05-10 Apple Inc. Displays with overlapping light-emitting diodes and gate drivers
CN103985371B (en) 2014-05-31 2017-03-15 深圳市华星光电技术有限公司 The flexible display device splicing
CN104253147B (en) 2014-09-18 2017-03-15 京东方科技集团股份有限公司 An array substrate and manufacturing method, a display apparatus
JP2016071082A (en) 2014-09-29 2016-05-09 パナソニック液晶ディスプレイ株式会社 Display device
JP2016071083A (en) 2014-09-29 2016-05-09 パナソニック液晶ディスプレイ株式会社 Display device and drive circuit
US9293102B1 (en) * 2014-10-01 2016-03-22 Apple, Inc. Display having vertical gate line extensions and minimized borders
CN104360558A (en) * 2014-12-08 2015-02-18 重庆京东方光电科技有限公司 Array substrate, display panel and display device
CN104503177A (en) * 2014-12-23 2015-04-08 上海天马微电子有限公司 Array substrate and manufacturing method thereof, and display panel
CN104485349B (en) * 2014-12-26 2017-08-25 昆山工研院新型平板显示技术中心有限公司 Borderless display device
KR20170137822A (en) * 2015-04-20 2017-12-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor devices and electronic devices
CN104865737B (en) * 2015-06-15 2017-07-25 京东方科技集团股份有限公司 Species display panel driving method and a display device
CN104934458A (en) * 2015-06-29 2015-09-23 合肥京东方光电科技有限公司 Display substrate, manufacturing method for display substrate and display apparatus
KR20170010141A (en) * 2015-07-15 2017-01-26 삼성디스플레이 주식회사 Organic light emitting display device
KR20170020661A (en) * 2015-08-13 2017-02-23 삼성디스플레이 주식회사 Organic light emitting display device
KR20170080861A (en) * 2015-12-30 2017-07-11 삼성디스플레이 주식회사 Liquid display device and method for manufacturing the same
US20190025660A1 (en) * 2016-01-04 2019-01-24 Sharp Kabushiki Kaisha Display device
CN106024838B (en) * 2016-06-21 2019-04-30 武汉华星光电技术有限公司 Display element based on mixing TFT structure
CN106504689A (en) * 2016-11-08 2017-03-15 深圳市华星光电技术有限公司 Display driving circuit and display panel
CN108172174A (en) * 2016-12-07 2018-06-15 元太科技工业股份有限公司 Pixel array substrate
CN107481666A (en) * 2017-08-16 2017-12-15 深圳市华星光电半导体显示技术有限公司 Organic light-emitting diode display

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148301A (en) 1990-02-27 1992-09-15 Casio Computer Co., Ltd. Liquid crystal display device having a driving circuit inside the seal boundary
EP0603420B1 (en) * 1992-07-15 2001-06-13 Kabushiki Kaisha Toshiba Liquid crystal display
JPH06202124A (en) * 1992-12-26 1994-07-22 Nippondenso Co Ltd Liquid crystal display device
US5694061A (en) 1995-03-27 1997-12-02 Casio Computer Co., Ltd. Semiconductor device having same conductive type MIS transistors, a simple circuit design, and a high productivity
JP2939865B2 (en) * 1995-07-03 1999-08-25 カシオ計算機株式会社 A thin film semiconductor device and a display device using the same
JPH0982978A (en) * 1995-09-20 1997-03-28 Hitachi Ltd Semiconductor device and liquid-crystal display using semiconductor device
US5739880A (en) * 1995-12-01 1998-04-14 Hitachi, Ltd. Liquid crystal display device having a shielding film for shielding light from a light source
JP3737176B2 (en) 1995-12-21 2006-01-18 株式会社半導体エネルギー研究所 The liquid crystal display device
JP3511861B2 (en) * 1996-10-04 2004-03-29 セイコーエプソン株式会社 The liquid crystal display panel and method thereof testing, and manufacturing method of a liquid crystal display panel
KR100235589B1 (en) * 1997-01-08 1999-12-15 구본준 Driving method of tft-lcd device
KR100235590B1 (en) * 1997-01-08 1999-12-15 구본준 Driving method of tft-lcd device
KR100204909B1 (en) * 1997-02-28 1999-06-15 구본준 Liquid crystal display source driver
US6465268B2 (en) 1997-05-22 2002-10-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an electro-optical device
JP3998755B2 (en) * 1997-05-22 2007-10-31 株式会社半導体エネルギー研究所 Semiconductor display device
TWI224221B (en) * 1998-01-30 2004-11-21 Seiko Epson Corp Electro-optic apparatus, electronic apparatus using the same, and its manufacturing method
GB9803764D0 (en) * 1998-02-23 1998-04-15 Cambridge Display Tech Ltd Display devices
GB9803763D0 (en) * 1998-02-23 1998-04-15 Cambridge Display Tech Ltd Display devices
TW561292B (en) * 1998-04-01 2003-11-11 Seiko Epson Corp Liquid crystal device, method for manufacturing the liquid crystal device, and electronic apparatus
JPH11288001A (en) 1998-04-01 1999-10-19 Citizen Watch Co Ltd Liquid crystal display device
JPH11305681A (en) * 1998-04-17 1999-11-05 Casio Comput Co Ltd Display device
JPH11305743A (en) * 1998-04-23 1999-11-05 Semiconductor Energy Lab Co Ltd Liquid crystal display device
JP3640527B2 (en) * 1998-05-19 2005-04-20 富士通株式会社 The plasma display device
US6177301B1 (en) * 1998-06-09 2001-01-23 Lg.Philips Lcd Co., Ltd. Method of fabricating thin film transistors for a liquid crystal display
KR100505525B1 (en) * 1998-07-27 2005-08-04 세이코 엡슨 가부시키가이샤 Electro-optical device, method of manufacture thereof, projection display, and electronic device
JP4069991B2 (en) * 1998-08-10 2008-04-02 株式会社 日立ディスプレイズ The liquid crystal display device
JP2000148096A (en) * 1998-11-10 2000-05-26 Hitachi Ltd Liquid crystal display device with built-in peripheral circuit corresponding to digital image signal input
US7697052B1 (en) * 1999-02-17 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Electronic view finder utilizing an organic electroluminescence display
US6894758B1 (en) 1999-03-08 2005-05-17 Seiko Epson Corporation Liquid crystal device and manufacturing method thereof
US6475836B1 (en) * 1999-03-29 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP3312691B2 (en) * 1999-04-19 2002-08-12 セイコーインスツルメンツ株式会社 Semiconductor device
JP2001222017A (en) * 1999-05-24 2001-08-17 Fujitsu Ltd Liquid crystal display device and its manufacturing method
US6930745B1 (en) * 1999-06-11 2005-08-16 Seiko Epson Corporation LCD and method of manufacture thereof
JP4092857B2 (en) * 1999-06-17 2008-05-28 ソニー株式会社 Image display device
KR100319098B1 (en) * 1999-06-28 2001-12-29 김순택 Method and Apparatus for driving a plasma display panel with a function of automatic power control
JP2001075075A (en) 1999-06-29 2001-03-23 Seiko Epson Corp Liquid crystal device and electronic apparatus
US6590553B1 (en) * 1999-07-23 2003-07-08 Nec Corporation Liquid crystal display device and method for driving the same
JP3592205B2 (en) 1999-07-23 2004-11-24 日本電気株式会社 Method for driving a liquid crystal display device
JP3746925B2 (en) * 1999-08-27 2006-02-22 セイコーエプソン株式会社 A liquid crystal device and an electronic apparatus
JP4906017B2 (en) * 1999-09-24 2012-03-28 株式会社半導体エネルギー研究所 Display device
JP4718670B2 (en) * 1999-09-24 2011-07-06 株式会社半導体エネルギー研究所 El display device
US6641933B1 (en) 1999-09-24 2003-11-04 Semiconductor Energy Laboratory Co., Ltd. Light-emitting EL display device
TW540251B (en) 1999-09-24 2003-07-01 Semiconductor Energy Lab EL display device and method for driving the same
TW525122B (en) * 1999-11-29 2003-03-21 Semiconductor Energy Lab Electronic device
TW465122B (en) 1999-12-15 2001-11-21 Semiconductor Energy Lab Light-emitting device
US6922226B2 (en) * 1999-12-31 2005-07-26 Lg. Philips Lcd Co. Ltd. Liquid crystal display device implementing improved electrical lines and the fabricating method
JP2001194461A (en) * 2000-01-07 2001-07-19 Shimadzu Corp Two-dimensional array type radiation detector
TW480727B (en) 2000-01-11 2002-03-21 Semiconductor Energy Laboratro Semiconductor display device
US6611108B2 (en) * 2000-04-26 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Electronic device and driving method thereof
US6326913B1 (en) * 2000-04-27 2001-12-04 Century Semiconductor, Inc. Interpolating digital to analog converter and TFT-LCD source driver using the same
US6989805B2 (en) * 2000-05-08 2006-01-24 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
TW502236B (en) 2000-06-06 2002-09-11 Semiconductor Energy Lab Display device
JP3578110B2 (en) * 2000-06-15 2004-10-20 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
US7019718B2 (en) * 2000-07-25 2006-03-28 Semiconductor Energy Laboratory Co., Ltd. Display device
US6825820B2 (en) * 2000-08-10 2004-11-30 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
TW514854B (en) 2000-08-23 2002-12-21 Semiconductor Energy Lab Portable information apparatus and method of driving the same
JP2002123228A (en) * 2000-10-17 2002-04-26 Seiko Epson Corp Optoelectronic panel and its driving method and electronic equipment
US6693385B2 (en) 2001-03-22 2004-02-17 Semiconductor Energy Laboratory Co., Ltd. Method of driving a display device
JP4731718B2 (en) * 2001-04-27 2011-07-27 株式会社半導体エネルギー研究所 Display device
JP4789369B2 (en) * 2001-08-08 2011-10-12 株式会社半導体エネルギー研究所 Display device and electronic device
KR100480332B1 (en) * 2002-04-08 2005-04-06 엘지.필립스 엘시디 주식회사 Liquid Crystal Panel used for a Liquid Crystal Display Device
JP4001066B2 (en) * 2002-07-18 2007-10-31 セイコーエプソン株式会社 Electro-optical device, the wiring board and an electronic apparatus
KR20040062065A (en) * 2002-12-31 2004-07-07 엘지.필립스 엘시디 주식회사 active matrix organic electroluminescence display device
KR100769190B1 (en) * 2003-06-30 2007-10-23 엘지.필립스 엘시디 주식회사 Multi-domain liquid crystal display device and method of the same
KR101010162B1 (en) * 2004-12-28 2011-01-20 엘지디스플레이 주식회사 Apparatus for dispensing sealant of liquid crystal display device
KR101125252B1 (en) * 2004-12-31 2012-03-21 엘지디스플레이 주식회사 Poly Liquid Crystal Dispaly Panel and Method of Fabricating The Same
US7623097B2 (en) * 2005-08-17 2009-11-24 Samsung Mobile Display Co., Ltd. Emission control driver and organic light emitting display device having the same and a logical or circuit for an emission control driver for outputting an emission control signal
US20090153796A1 (en) * 2005-09-02 2009-06-18 Arthur Rabner Multi-functional optometric-ophthalmic system for testing diagnosing, or treating, vision or eyes of a subject, and methodologies thereof
KR20080023466A (en) * 2006-09-11 2008-03-14 삼성에스디아이 주식회사 Flat panel display device
US7796224B2 (en) * 2006-12-26 2010-09-14 Sony Corporation Liquid crystal display device
JP2008164787A (en) * 2006-12-27 2008-07-17 Epson Imaging Devices Corp Liquid crystal display device

Also Published As

Publication number Publication date
US9972670B2 (en) 2018-05-15
US6862008B2 (en) 2005-03-01
CN1407373A (en) 2003-04-02
US20050140578A1 (en) 2005-06-30
KR100935415B1 (en) 2010-01-06
US20030030381A1 (en) 2003-02-13
CN101666951B (en) 2012-03-21
KR20030014598A (en) 2003-02-19
US7573469B2 (en) 2009-08-11
TW546597B (en) 2003-08-11
CN100565311C (en) 2009-12-02
CN101666951A (en) 2010-03-10
JP2003058075A (en) 2003-02-28
US20100073272A1 (en) 2010-03-25
US9105594B2 (en) 2015-08-11
US20120313907A1 (en) 2012-12-13

Similar Documents

Publication Publication Date Title
KR100502747B1 (en) Display Module
US6392255B1 (en) Display device having a thin film transistor and electronic device having such display device
USRE42623E1 (en) Electro-optical apparatus, matrix substrate, and electronic unit
US6933574B2 (en) Organic electroluminescent display device and method of fabricating the same
US8766533B2 (en) Display device
TWI609212B (en) Display module and display module features of mobile phones and electronic devices
US7064482B2 (en) Organic electroluminescent display panel device and method of fabricating the same
US7012278B2 (en) Light-emitting apparatus driven with thin-film transistor and method of manufacturing light-emitting apparatus
CN100438119C (en) Dual panel-type organic electroluminescent device and method for fabricating the same
JP4549864B2 (en) Light-emitting device, an electronic device and a portable information terminal
US20040085504A1 (en) Liquid crystal display panel and method for manufacturing the same
JP4541936B2 (en) The flat panel display
JP4983766B2 (en) Display device
KR100537653B1 (en) Light emmision device and electronic apparatus
CN100356576C (en) Organic electroluminescent devcie and its producing method
CN102484123B (en) Tiled Display With Overlapping Flexible Substrates
US7211944B2 (en) Dual panel-type organic electroluminescent display device and method of fabricating the same
KR100830331B1 (en) Organic light emitting display device and method of manufacturing the same
US7173371B2 (en) Transmissive-type organic electroluminescent display device and fabricating method of the same
JP4039446B2 (en) Electro-optical device and electronic equipment
CN100511698C (en) Organic electroluminescence device and mfg. method thereof
JP4171258B2 (en) Organic el panel
CN100403576C (en) Dual panel-type organic electroluminescent display device and method for fabricating the same
KR100834346B1 (en) an active matrix organic electroluminescence display device
US7101729B2 (en) Method of manufacturing a semiconductor device having adjoining substrates

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071019

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071019

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100827

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101207

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110119

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110405

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110421

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110712

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110719

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140729

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140729

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250