46675 9 A7 B7 五、發明說明（1 ) 發明背景： 1 .發明領域： 本發明有關一種具有soi (絕緣體上之矽）結構的 半導體裝置。 2.相關技術之說明： 在SO I基質中，有下述幾區：S IMOX (利用植 入氧來分離）基質；一矽基質，其表面上形成一氧化物膜 ;—黏著基質等。在S I MOX基質中，氧係離子植入單 晶矽基質且經由熱處理埋入以形成一絕緣層。在黏著基質 中，個別的矽基質彼此黏附在一起。例如，在作爲具有此 S 0 I結構之半導體裝置的MO S型電晶體中，與使用傳 統矽結構之Μ 0 S電晶體相較下，可減少寄生電容。因此 ，使用S 0 I基質之Μ 0 S電晶體可以以高速操作且減少 電源消耗。 在相關於一 Μ 0 S電晶體之具有一個閘極的單閘 S〇I型Μ 0 S電晶體中，當一元件尺寸被減小以獲致一 微細結構時，與使用傳統矽基質之Μ 0 S電晶體相較下， 在一飽合狀態中沒有任何電流驅動能力係幾乎不同的。又 ，因爲元件係因S 0 I中之絕緣層而彼此完美地分開，沒 有任何基質之電位係固定的。因此，當汲極電位改變時， 基質之電位改變。因此，當一閘長度增加至約 ” . 0 5 ，與矽基質相較下，在短通道效應中是相反 地不利的。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) .'k.---— —-II 訂--------線' 經濟部智慧財產局員工消費合作社印製 -4- 46675 9 A7 _ B7 五、發明說明（2 ) 發明槪要： 爲解決上述問題，本發明的目的係提供一 Μ 0 S電晶 體’其有一結構，其中電流驅動能力增加且抑制短通道效 應。 本發明使用下列機構以解決上面問題。 (1 )設有一S 0 I型半導體裝置，其中形成一元件 之主表面部分係利用一埋設之絕緣層（形成於一半導體基 質內）而絕緣及彼此分離，此半導體裝置之特徵在於： MO S電晶體形成於埋設絕緣層上方，且一元件分離一絕 緣膜（其厚度可於深度方向中與埋設絕緣層接觸）係形成 於MO S電晶體周圍，且一埋設電極形成於埋設絕緣層下 面，且Μ 0 S電晶體之多晶矽閘極及埋設電極彼此於一平 面上重疊。 (2 )半導體裝置，其中閘極及埋設電極彼此係電連 接的。 (3)半導體裝置’其中一中間層絕緣膜係形成於 Μ 0 S電晶體上’且金屬配線形成於中間層絕緣膜，且一 接觸孔形成於閘極上之中間絕緣膜內，又一接觸孔（有一 深度抵達埋設電極）係形成於元件分離區或~具有於埋設 電極上之中間層絕緣膜的區域，且閘極及埋設電極利用穿 過接觸孔之金屬配線而彼此相連。 '* (4 )半導體裝置，其中一具有深度可抵達埋設電極 之經由孔（via hole )係形成於元件分離區域或一具有於埋 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先Μ讀背面之注意事項再填窝本頁)46675 9 A7 B7 V. Description of the invention (1) Background of the invention: 1. Field of the invention: The present invention relates to a semiconductor device having a soi (silicon on insulator) structure. 2. Description of related technology: In the SO I matrix, there are the following areas: S IMOX (separation by implanted oxygen) matrix; a silicon matrix, an oxide film is formed on its surface; an adhesive matrix and the like. In the SI MOX matrix, oxygen-based ions are implanted into the single crystal silicon matrix and buried by heat treatment to form an insulating layer. In the adhesive matrix, individual silicon matrices adhere to each other. For example, in the MO S-type transistor, which is a semiconductor device having this S 0 I structure, the parasitic capacitance can be reduced compared with the M 0 S transistor using a conventional silicon structure. Therefore, the M 0 S transistor using the S 0 I matrix can operate at high speed and reduce power consumption. In a single-gate SOI type M0S transistor with one gate, which is related to a M0S transistor, when a component size is reduced to obtain a fine structure, the M0S using a conventional silicon substrate Compared with the S transistor, in a saturated state, there is almost no current driving capability that is almost different. Also, because the elements are perfectly separated from each other by the insulating layer in S 0 I, no potential of any substrate is fixed. Therefore, when the drain potential changes, the potential of the substrate changes. Therefore, when the length of a gate is increased to about "0.5", compared with the silicon substrate, it is disadvantageous in the short channel effect. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) (Please read the notes on the back before filling out this page) .'k .----- —-II Order -------- Line 'Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economy -4- 46675 9 A7 _ B7 V. Description of the invention (2) Summary of the invention: In order to solve the above problems, the object of the present invention is to provide an M 0 S transistor which has a structure in which the current driving ability is increased and the short channel effect is suppressed. The following mechanisms are used to solve the above problems. (1) A S 0 I-type semiconductor device is provided, in which the main surface portion forming an element is insulated and separated from each other by using a buried insulating layer (formed in a semiconductor matrix). The semiconductor device is characterized in that: a MOS transistor is formed over the buried insulating layer, and an element separation and an insulating film (the thickness of which can be in contact with the buried insulating layer in the depth direction) is formed around the MOS transistor, and a buried electrode It is formed under the buried insulating layer, and the polycrystalline silicon gate and the buried electrode of the MOS transistor overlap each other on a plane. (2) A semiconductor device, wherein the gate and the buried electrode are electrically connected to each other. (3) Semiconductor device 'One of the interlayer insulating films is formed on the M 0 S transistor' and the metal wiring is formed on the interlayer insulating film, and a contact hole is formed in the intermediate insulating film on the gate, and another contact hole (a depth reaches the buried (Electrode) is formed in the element separation area or an area having an interlayer insulating film on the buried electrode, and the gate electrode and the buried electrode are connected to each other by a metal wiring passing through a contact hole. '* (4) a semiconductor device in which A via hole with a depth that can reach the buried electrode is formed in the component separation area or a paper with a standard of China National Standards (CNS) A4 (210 X 297 mm) is applied to the buried paper (please read the back first) (Notes to fill in this page again)
'农 ! i 訂 — I I--I 經濟部智慧財產局員工消費合作社印製 -5- A7 466759 ——____B7_____ 五、發明說明（3 ) 設電極上之中間層絕緣膜之區域，且閘極及埋設電極係利 用構成閘極之多晶矽經由該經由孔而彼此相連。 <請先閱讀背面之注意事項再填寫本頁) (5 )半導體裝置，其中埋設電極係一導電型雜質擴 散層，其與半導體基質之雜質擴散層反向。 (6 )半導體裝置，其中埋設電極係由與閘極之多晶 石夕不同之多晶矽構成，且一絕緣膜形成於埋設電極及半導 體基質之間。 (7 )半導體裝置，其中埋設絕緣層及MO S電晶體 之閘絕緣層之厚度彼此相等。 圓式簡單說明 圖1爲一橫剖面圖，示出本發明之一實施例之半導體 裝置之主要部分； 圖2係本發明之一實施例之半導體裝置之主要部分之 平面圖； 圖3 A - 3 D係延圖2之A - A '線取得之橫剖面圖 ，示出本發明之一實施例之半導體裝置之主要部分之形成 過程； 經濟部智慧財產局員工消費合作社印製 圖4A-4D係延圖2之線B_B/取得之橫剖面圖 ，示出本發明之一實施例之半導體裝置之主要部分之形成 過程； 圖5係一橫剖面圖，示出本發明之另一實施例之半導 體裝置之主要部分；及 圖6 A - 6 B係橫剖面圖，示出本發明之另一實施例 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -6 - 4 6 675 9 ΚΙ _Β7_五、發明說明（4 ) 之半導體裝置之主要部分之形成過程。 符號說明 經濟部智慧財產局員工消費合作社印製 1 0 1 半 導 體 基 質 1 0 2 埋 設 絕 緣 層 1 0 3 場 絕 緣 薄 膜 1 0 4 埋 設 電 極 1 0 5 閘 極 1 0 6 閘 絕 緣 膜 1 0 7 源 區 1 0 8 汲 極 區 1 0 9 埋 設 多 晶 矽 2 0 1 元 件 內 部 區 3 0 1 P 型 半 導 體 基質 3 0 2 光 阻材料 3 0 3 黏 半 導 體 基 質 4 0 1 光 阻材料 4 0 2 槽 5 0 1 半 導 體 基 質 5 0 2 埋 設 絕 緣 層 5 0 3 場 絕 緣 層 5 0 4 埋 設 電 極 5 0 5 閘 極 5 0 6 閘 絕 緣 薄 膜 (請先閲讀背面之注意事項再填寫本頁) 裝--------訂----------線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 6 6 7 5 9'Nong! I order — I I--I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -5- A7 466759 ——____ B7_____ V. Description of the invention (3) Set the area of the insulating film on the electrode and the gate And the buried electrode is connected to each other through the via hole using polycrystalline silicon constituting the gate. < Please read the precautions on the back before filling this page) (5) Semiconductor devices, where the buried electrode is a conductive impurity diffusion layer, which is opposite to the impurity diffusion layer of the semiconductor substrate. (6) A semiconductor device, wherein the buried electrode is made of polycrystalline silicon different from the polycrystalline silicon of the gate, and an insulating film is formed between the buried electrode and the semiconductor substrate. (7) A semiconductor device in which the thicknesses of the buried insulating layer and the gate insulating layer of the MOS transistor are equal to each other. Brief Description of the Circular Figure 1 is a cross-sectional view showing the main part of a semiconductor device according to an embodiment of the present invention; Figure 2 is a plan view of the main part of a semiconductor device according to an embodiment of the present invention; Figure 3 A-3 D is a cross-sectional view taken along line A-A 'in FIG. 2 and shows the forming process of the main part of the semiconductor device according to an embodiment of the present invention; Figures 4A-4D are printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A cross-sectional view taken along line B_B / obtained in FIG. 2 shows the formation process of the main part of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. The main part of the device; and Figs. 6A-6B are cross-sectional views showing another embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -6-4 6 675 9 ΚΙ_Β7_ V. The process of forming the main part of the semiconductor device of the invention description (4). Symbol description Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 0 1 Semiconductor substrate 1 0 2 Embedded insulating layer 1 0 3 Field insulating film 1 0 4 Embedded electrode 1 0 5 Gate 1 0 6 Gate insulating film 1 0 7 Source area 1 0 8 Drain region 1 0 9 Buried polycrystalline silicon 2 0 1 Element internal region 3 0 1 P-type semiconductor substrate 3 0 2 Photoresistive material 3 0 3 Sticky semiconductor substrate 4 0 1 Photoresistive material 4 0 2 Slot 5 0 1 Semiconductor Substrate 5 0 2 Embedded insulating layer 5 0 3 Field insulating layer 5 0 4 Embedded electrode 5 0 5 Gate 5 0 6 Gate insulating film (Please read the precautions on the back before filling this page) -Order ---------- Line- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 6 6 7 5 9
五、發明說明（5 ) 5〇7 源區 5 〇 8 汲極區 5 〇 9 埋設多晶砂 510 絕緣膜 6 〇 1 P型半導體基質 6〇2 P型半導體基質 較J圭實施例夕詳細說_明 參照所附圖形’於下將詳細說明做爲本發明之—實施 例的一N型Μ 0 S電晶體。 圖1係一橫剖面圖’顯示做爲一實施例1之本發明的 —實施例模式中之一半導體裝置的一主要部份，且圖2係 圖1中之半導體裝置的一主要部份之一平面圖。圖1之半 導體基質1Q 1係一 Ρ型黏著SO I基質，且半導體基質 1 0 1之一主表面係與其之後面（rear face )絕緣。經由 —埋設（buried )絕緣層102，在半導體基質1〇1之 主表面上形成一元件。做爲一埋設電極1 0 4之一 N型擴 散層，係被形成在此—半導體基質1 0 1之後面上的埋設 絕緣層120之下方。於此時，埋設絕緣層102係被操 作爲相關於埋設電極1 〇 4之一閘絕緣膜。 在埋設絕緣層1 〇 2之上方形成一 N型MO S電晶體 。此一 Μ 0 S電晶體一係由通過一 N型源區1 〇 7“，一汲 極（drain )區域1 〇 8 ’及一閘絕緣膜1 〇 6之閘極 1 0 5所構成。此一 N型MO S電晶體係由一場（field ) (請先閱讀背面之注意事項再填寫本頁) 裝 -----訂---------線： 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -8- 46675 9 A7 _ B7 五、發明說明（6 ) 絕緣膜1 〇 3規定在一平面上。例如，埋設電極1 〇 4係 以埋設多晶矽1 0 9爲配線而電連至在場絕緣膜上之閘極 1 〇 5，以執行一電導作業。亦可由一金屬膜執行電導作 業。 當一閘電壓被施加至此一 MO S電晶體時，埋設電極 1 〇 4與閘極1 0 5可被同時地操作。因而，在元件內直 立地形成通道，且增加了電流驅動能力。在元件內之基質 的電位可由埋設電極1 0 4與閘極1 〇 5所固定，因此， 短通道效應可被抑制。 於圖2中，一元件內部區域2 0 1包括一源極、通道 、及汲極，且閘電極1 0 5被形成在元件內部區域2 0 1 上。進一步的，連接埋設電極與閘極之一對多晶矽1 0 9 均被形成在閘極1 0 5之下方與元件內部區域2 0 1之外 部部份上。 經由參照圖3與4，於下將解釋圖1之半導體裝置的 一製造方法之實施例。圖3A至3 B均爲沿著圖2之線A —A /取得之橫剖面圖，且圖4A至4D均爲沿著圖2之 線B _ B —取得之橫剖面圖。 如不於圖3 A，一圖型（patterning )是由一在？_型半 導體基質301(由單晶矽構成）之表面上之光阻302 所完成的，且N型雜質（例如砷）局部離子植入P型半導 體基質3 0 1，使得形成一作爲埋設電極1 〇 4之‘N型擴 散層。在此情形下，砷之濃度設定爲約1 k 1 0 2 ° c 。之後，此半導體基質3 0 1被熱氧化且一作爲埋設絕緣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ! I I-1 I 訂·！！ — 經濟部智慧財產局員工消費合作社印製 4 6 6 7 5 9 A7 B7 五、發明說明（7 ) (請先閱讀背面之注意事項再填寫本頁> 層1 0 2之氧化膜形成於半導體基質3 ο 1之表面上’如 圖3 B所示。一個別的p型半導體基質3 0 3被黏附於半 導體基質301(其上形成有絕緣層1〇2)上’且被拋 光及硏磨和調整成一 S Ο I型半導體基質1 〇 1。此狀態 示於圖3 Β及圖4Α。在此時，埋設絕緣層1 〇 2約有自 1 0 nm至1 0 0 nm的厚度。此處，形成埋設絕緣層 1 〇 2在半導體基質3 0 1上。但是，一氧化膜可形成於 個別的黏著半導體基質3 0 3上，且也能調整成埋設絕緣 層 1 0 2。 經濟部智慧財產局員工消費合作社印製 在使用L 0 C 0 S方法形成一場絕緣膜1 0 3於此 S〇I基質中之後，場絕緣膜1 0 3被熱氧化，使得一氧 化矽膜（作爲閘絕緣膜1 0 6 )被形成於半導體基質 1 〇 1之表面上。此處，閘絕緣膜1 〇 6被安置成約有 1 0 nm至丄0 0 nm之厚度，以等於埋設絕緣層1 0 2 之厚度。此狀態示於圖3 C及圖4 B中。之後’如圖4 C 所示，利用一光阻4 0 1形成一圖型’以完成一導電作業 給埋設絕緣層1 0 2下面作爲N型擴散層之埋設電極 1 0 4。之後，實施蝕刻法使得一槽4 0 2形成任意形狀 。在此情形下，實施鈾刻直到埋設絕緣層1 0 2，且於蝕 刻作業實施直到N型擴散層之後停止蝕刻。 作爲配線之多晶矽1 0 9被埋入利用餓刻所形成之槽 4 0 2中，以完成一導電作業給埋設電極1 0 4。'文，一 多晶矽層被沉積以形成一閘極1 0 5於元件之上部分。此 狀態示於圖4 D。磷被預先沉積在此多晶矽中以提供一導 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -10- 46 675 9 A7 B7 五、發明說明（8 ) 電性質。如圖3 D所示，之後利用一光阻完成圖型，且利 用蝕刻形成閘極1 0 5。 N型雜質，如砷，與形成之閘極1 〇 5被離子植入， 且場絕緣膜1 〇 3作爲幕罩（masks )，使得形成一源極區 1 〇 7及一汲極區1 0 8。之後，一中間層絕緣膜（未示 出）被沉積，且利用一光阻完成一圖型，並實行鈾刻使得 一金屬膜被沉積於所形成之槽中。因此，源極區1 〇 7、 汲極區108及閘極105彼此電連接。 圖5是一橫剖面圖，示出本發明之另一實施例（實施 例2)之半導體裝置之主要部分。在圖5中，被覆蓋一絕 緣膜5 1 0之多晶矽被埋於半導體基質5 0 1 (作爲一黏 著S Ο I基質）之後表面上的埋設絕緣層5 0 2下面。此 多晶矽被調整成一埋設電極5 0 4。 —N型Μ 0 S電晶體形成於埋設絕緣層5 0 2上。類 似實施例1，一具有閘極於元件之上及下側之結構被形成 ，使得電流驅動力量增加且能抑制短通道效應。 圖5所示之本發明之另一實施例的半導體裝置之製造 方法將以圖6 Α — 6 Β加以說明。 利用一 P型半導體基質6 0 1 (由單晶矽構成）之表 面上的光阻完成圖型，且實行鈾刻以形成一槽，該槽於一 位置約有0 . l^m至〇 . 5//m之深度以形成一埋設電 極》此半導體基質6 0 1局部熱氧化且形成厚度約“ 30nm之氧化膜，作爲槽中之絕緣膜510。之後，如 圖6 A所示，多晶矽被埋入槽中以形成一埋設電極5 0 4 (請先閲讀背面之注*ί事項再填寫本頁) ..哀--------訂---------緣 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -11 - 46675 9 Δ7 Α7 ——_ Β7 五、發明說明（9 ) 。在此情形中，磷被預先沉積以提供一導電性質給多晶矽 。在此實施例2中，在側面上形成一元件之個別P型半導 體基質6 0 2被熱氧化，且一作爲埋設絕緣層5 0 2之氧 化膜形成於基質表面，如圖6 B所示。之後’ P型半導體 基質6 0 2被黏著於半導體基質6 0 1而將埋設電極 5 0 4埋入其內。其些基質之後被拋光及硏磨以調整成.一 SOI型半導體基質501。 之後，類似上述之實施例1 ，形成一 N型Μ 0 S電晶 體。在此實施例中，已有相關於Ν型MO S電晶體之說明 ，但是相關於Ρ型M〇S電晶體類似結構也能形成。 如上所述，本發明可獲致下列之效果。即，在S 0 I 型半導體裝置中，藉由形成一雙閘結構（其中一電極也形 成於一 Μ〇S電晶體下面），可增加電流驅動能力。又， 使用本發明，可更有效抑制短通道效應。 (請先閱讀背面之注意事項再填寫本頁) 裝！ —訂·！-線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复） -12-V. Description of the invention (5) 507 Source region 5 08 Drain region 5 009 Buried polycrystalline sand 510 Insulation film 6 〇1 P-type semiconductor substrate 602 P-type semiconductor substrate _Referring to the attached figure ', the N-type M 0 S transistor as an embodiment of the present invention will be described in detail below. FIG. 1 is a cross-sectional view 'showing a main part of a semiconductor device in an embodiment mode of the present invention as an embodiment 1 and FIG. 2 is a main part of a semiconductor device in FIG. 1 A floor plan. The semiconductor substrate 1Q 1 of FIG. 1 is a P-type adhesive SO I substrate, and one of the main surfaces of the semiconductor substrate 101 is insulated from its rear face. An element is formed on the main surface of the semiconductor substrate 101 via a buried insulating layer 102. An N-type diffusion layer, which is one of the buried electrodes 104, is formed below the buried insulating layer 120 on the rear surface of the semiconductor substrate 101. At this time, the buried insulating layer 102 is operated as a gate insulating film related to one of the buried electrodes 104. An N-type MOS transistor is formed over the buried insulating layer 102. The M 0 S transistor is composed of a gate electrode 105 passing through an N-type source region 107, a drain region 108, and a gate insulating film 106. A N-type MO S transistor system consists of a field (please read the precautions on the back before filling out this page). -------- Order --------- Line: Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperatives applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -8- 46675 9 A7 _ B7 V. Description of the invention (6) The insulating film 1 03 is specified on a plane. For example The buried electrode 104 is electrically connected to the gate electrode 105 on the field insulating film by using the buried polycrystalline silicon 109 as a wiring to perform a conductance operation. The conductance operation may also be performed by a metal film. When a gate voltage When applied to this MOS transistor, the buried electrode 104 and the gate electrode 105 can be operated simultaneously. Therefore, a channel is formed upright in the element, and the current driving capability is increased. The potential can be fixed by the buried electrode 104 and the gate electrode 105, so the short channel effect can be suppressed. A device internal region 2 0 1 includes a source electrode, a channel, and a drain electrode, and a gate electrode 105 is formed on the device internal region 2 0 1. Further, a pair of polysilicon 1 is connected to one of the buried electrode and the gate electrode. 0 9 are both formed below the gate electrode 105 and on the outer part of the device internal region 201. With reference to FIGS. 3 and 4, an embodiment of a method of manufacturing the semiconductor device of FIG. 1 will be explained below. 3A to 3B are cross-sectional views taken along line A-A / of Fig. 2, and Figs. 4A to 4D are cross-sectional views taken along line B_B- of Fig. 2. If not in the figure 3 A, a patterning is completed by a photoresist 302 on the surface of a? -Type semiconductor substrate 301 (consisting of single crystal silicon), and N-type impurities (such as arsenic) are partially ion-implanted P Type semiconductor substrate 3 0 1 so that an 'N-type diffusion layer is formed as the buried electrode 104. In this case, the concentration of arsenic is set to about 1 k 1 0 2 ° c. Thereafter, the semiconductor substrate 3 0 1 It is thermally oxidized and used as a buried insulation. The size of this paper applies to China National Standard (CNS) A4 (210 X 297 mm) (please first Read the notes on the reverse side and fill out this page)! I I-1 I Order !!! — Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 6 7 5 9 A7 B7 V. Description of Invention (7) (Please read first Note on the back side Please fill in this page again> The oxide film of the layer 102 is formed on the surface of the semiconductor substrate 3 ο 'as shown in FIG. 3B. Another p-type semiconductor substrate 3 0 3 is adhered to a semiconductor substrate 301 (with an insulating layer 102 formed thereon) 'and is polished and honed and adjusted to a S 0 I-type semiconductor substrate 101. This state is shown in Figs. 3B and 4A. At this time, the buried insulating layer 102 has a thickness of about 10 nm to 100 nm. Here, a buried insulating layer 102 is formed on the semiconductor substrate 301. However, an oxide film can be formed on the individual adhesive semiconductor substrate 3 0 3 and can also be adjusted to embed the insulating layer 10 2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. After using the L 0 C 0 S method to form a field of insulating film 103 in this SOI matrix, the field insulating film 103 was thermally oxidized, making the silicon monoxide film ( A gate insulating film 10 6) is formed on the surface of the semiconductor substrate 100. Here, the gate insulating film 106 is disposed to have a thickness of about 10 nm to about 100 nm, so as to be equal to the thickness of the buried insulating layer 10 2. This state is shown in Fig. 3C and Fig. 4B. After that, as shown in FIG. 4C, a pattern is formed using a photoresist 401 to complete a conductive operation. A buried electrode 104 is used as the N-type diffusion layer under the buried insulating layer 102. After that, an etching method is performed to form a groove 4 2 in an arbitrary shape. In this case, uranium etching is performed until the insulating layer 102 is buried, and etching is stopped after the etching operation is performed until the N-type diffusion layer. Polycrystalline silicon 10 9 as a wiring is buried in a groove 4 2 formed by using a engraving to complete a conductive operation for the buried electrode 104. In this case, a polycrystalline silicon layer is deposited to form a gate 105 on the device. This state is shown in Figure 4D. Phosphorus is pre-deposited in this polycrystalline silicon to provide a guide. The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -10- 46 675 9 A7 B7 V. Description of the invention (8) Electrical properties. As shown in FIG. 3D, a photoresist is used to complete the pattern, and the gate electrode 105 is formed by etching. N-type impurities, such as arsenic, are ion-implanted with the formed gate electrode 105, and the field insulating film 103 is used as masks, so that a source region 107 and a drain region 10 are formed. 8. After that, an interlayer insulating film (not shown) is deposited, and a pattern is completed using a photoresist, and uranium etching is performed so that a metal film is deposited in the formed groove. Therefore, the source region 107, the drain region 108, and the gate electrode 105 are electrically connected to each other. Fig. 5 is a cross-sectional view showing a main part of a semiconductor device according to another embodiment (Embodiment 2) of the present invention. In FIG. 5, polycrystalline silicon covered with an insulating film 5 10 is buried under a buried insulating layer 50 2 on the surface of the semiconductor substrate 5 0 1 (as an adhesive S 0 I substrate). The polycrystalline silicon is adjusted to a buried electrode 504. An N-type M 0 S transistor is formed on the buried insulating layer 50 2. Similar to Embodiment 1, a structure having gates above and below the element is formed so that the current driving force is increased and the short channel effect can be suppressed. A method of manufacturing a semiconductor device according to another embodiment of the present invention shown in Fig. 5 will be described with reference to Figs. 6A-6B. L ^ m 至 〇. The pattern is completed using a photoresist on the surface of a P-type semiconductor substrate 6 0 1 (consisting of single crystal silicon), and uranium engraving is performed to form a groove, which has a position of about 0.1 μm to 0. The semiconductor substrate 601 is locally thermally oxidized and an oxide film with a thickness of about 30 nm is formed as an insulating film 510 in the trench. Then, as shown in FIG. 6A, the polycrystalline silicon is Buried in the trench to form a buried electrode 5 0 4 (please read the note on the back before filling in this page). The consumer property cooperation of the Ministry of Intellectual Property Bureau Du printed the paper standard applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -11-46675 9 Δ7 Α7 ——_ Β7 V. Description of the invention (9). In the case, phosphorus is previously deposited to provide a conductive property to polycrystalline silicon. In this embodiment 2, an individual P-type semiconductor substrate 6 0 2 forming an element on the side is thermally oxidized, and one is used as a buried insulating layer 5 0 2 An oxide film is formed on the surface of the substrate, as shown in FIG. 6B. Then, the P-type semiconductor substrate 6 0 2 is adhered to the semiconductor substrate 6 0 1 The buried electrode 504 is buried therein. Some substrates are then polished and honed to adjust to a SOI-type semiconductor substrate 501. Thereafter, similar to the above-mentioned Example 1, an N-type M 0 S transistor is formed. In this embodiment, there has been a description regarding the N-type MO S transistor, but a similar structure can be formed with respect to the P-type MOS transistor. As described above, the present invention can achieve the following effects. That is, in In the S 0 I type semiconductor device, by forming a double-gate structure (one of the electrodes is also formed under a MOS transistor), the current driving capability can be increased. Furthermore, the present invention can more effectively suppress the short channel effect (Please read the precautions on the back before filling out this page) Pack! —Order ·!-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297) ) -12-