JP4880150B2 - MIS field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit having an SOI structure. In particular, a low-cost pseudo SOI substrate is formed on a semiconductor substrate (bulk wafer) by an easy manufacturing process, and high speed, low power, high reliability is formed on the pseudo SOI substrate. In addition, the present invention relates to forming a semiconductor device including a highly integrated short channel MIS field effect transistor.
Conventionally, as for a semiconductor device having an SOI structure, a semiconductor integrated circuit using a so-called bonded SOI wafer in which a semiconductor substrate having a uniform single crystal is bonded to another semiconductor substrate through an oxide film is being put into practical use. The disadvantage is that the yield is poor due to the use of two semiconductor substrates and the need to form an extremely thin SOI substrate in order to completely deplete, and the commercially available bonded SOI wafer is extremely expensive. There is.
In addition, in the formation of an SOI substrate by the so-called SIMOX method in which oxygen ions are implanted into a normal semiconductor substrate (bulk wafer) and an oxide film is formed inside the bulk wafer by high-temperature heat treatment, an expensive high-dose ion implantation machine is purchased. However, there are disadvantages such as high costs due to a long manufacturing process and instability of characteristics in the use of a large-diameter wafer.
At present, ignoring the problem of high cost, it has been put into practical use only for portable devices and analog / digital mixed system LSIs that require extremely high speed and low power consumption, both of which are conventional using SOI wafers. An LDD-structured short channel MIS field-effect transistor using a sidewall is formed on an SOI substrate separated by an insulating film. The speed is increased by reducing junction capacitance, depletion layer capacitance, threshold voltage, etc. It is designed to reduce power consumption, but on the other hand, since it is formed on a thin-film SOI substrate, the contact resistance of the source / drain region is increased and the resistance of each element is not reduced. However, there was a drawback that speeding up was not achieved. Further, when a voltage different from the voltage applied to the gate electrode is applied to the conductor (semiconductor substrate or lower layer wiring) under the SOI substrate, a minute back channel leak generated at the bottom of the SOI substrate cannot be prevented. There was also a drawback that reliability was not achieved.
Therefore, an SOI structure can be formed by a low-cost and easy process that enables the manufacture of a semiconductor integrated circuit for high-speed and large-capacity communication or a portable information terminal, and further high integration, high speed, low power, and high performance are achieved. There is a need for means capable of forming short channel MIS field effect transistors that can be achieved.
[0002]
[Prior art]
FIG. 22 is a schematic cross-sectional side view of a conventional semiconductor device, showing a part of a semiconductor integrated circuit including an N-channel MIS field effect transistor having an SOI structure formed by using a bonded SOI wafer. Type silicon substrate, 52 a bonding oxide film, 53 a p-type SOI substrate, 54 an element isolation region forming trench and a buried oxide film, 55 an n-type source / drain region, and 56 an n-type ⁺ Type source / drain region 57 is a gate oxide film (SiO ₂ ), 58 is a gate electrode (WSi / PolySi), 59 is a base oxide film, and 60 is a side wall (SiO 2). ₂ ), 61 is an oxide film for impurity blocking, 62 is a BPSG film, 63 is a barrier metal (Ti / TiN), 64 is a plug (W), 65 is a barrier metal (Ti / TiN), 66 is an AlCu wiring, and 67 is a barrier Metal (Ti / TiN) is shown.
In the figure, a thin film p-type SOI substrate 53 bonded to a p-type silicon substrate 51 via an oxide film 52 and insulated and isolated in an island shape by a trench for forming an element isolation region and a buried oxide film 54. In this p-type SOI substrate 53, an N-channel LDD MIS field effect transistor is formed.
Accordingly, the junction capacitance can be reduced by forming a source / drain region surrounded by an insulating film, the depletion layer capacitance can be reduced by completely depleting the SOI substrate, and the threshold voltage can be reduced by improving the subthreshold characteristics. Compared with a semiconductor integrated circuit formed of a MIS field effect transistor formed on a normal bulk wafer by removing the contact region to the semiconductor substrate, it is possible to increase the speed, reduce the power, and increase the integration.
However, since it is formed on a thin SOI substrate, the contact resistance in the source / drain region increases and the resistance of each element has not been reduced. There was a drawback.
Further, when a voltage different from the voltage applied to the gate electrode is applied to the conductor (semiconductor substrate or lower layer wiring) under the SOI substrate, a minute back channel leak generated at the bottom of the SOI substrate cannot be prevented. There was also a drawback that reliability was not achieved.
Furthermore, in order to create such an SOI structure, it is necessary to purchase a bonded SOI wafer that is commercially available, and even if it depends on the cost reduction technology of the wafer manufacturer, it is three times higher than the bulk wafer in the mass production stage. There was a drawback that the cost was extremely high, about 5 times.
Further, as another means for creating an SOI structure, even if a bulk wafer is used, an oxide film is formed inside the bulk wafer by injecting oxygen ions and performing high-temperature heat treatment, so-called SIMOX method of forming an SOI substrate, High cost due to having to purchase a very expensive high dose ion implantation machine and requiring a long manufacturing process to implant high doses of oxygen, or as large as 10 to 12 inches There are drawbacks such as instability of characteristics due to repair of crystal defects by oxygen ion implantation in the use of a diameter wafer.
[0003]
[Problems to be solved by the invention]
The problem to be solved by the present invention is that, as shown in the prior art, in order to obtain a MIS field effect transistor with improved high speed, a fully depleted thin film SOI substrate is required. Since the source / drain region is formed in the SOI substrate, it is inevitable that the SOI substrate forming the source / drain region is over-etched when the interlayer insulating film for forming the conductive plug is etched. Although contact can be made, the contact resistance of the source / drain region increases, and although the capacitance can be reduced, the resistance of the thin source / drain region and the resistance of the gate electrode cannot be reduced, etc. High speed could not be achieved, when forming C-MOS or applied to gate electrode under SOI substrate When there is a lower layer wiring to which a voltage different from the voltage is applied, high reliability due to the inability to prevent back channel leakage was not obtained, and even when a bonded SOI wafer was used to form an SOI structure Alternatively, even if an SOI substrate is formed by the SIMOX method, the current technology increases the cost considerably, so it can be used only for high value-added special-purpose products, and the technology applicable to inexpensive general-purpose products is scarce. That is.
[0004]
[Means for Solving the Problems]
The above problem is that a semiconductor substrate, a semiconductor layer selectively stacked on the semiconductor substrate, and a pair of opposing conductive films provided in contact with part of two opposing side surfaces of the semiconductor layer ( Part of source / drain region) And the conductive film ( Part of source / drain region) Impurities provided in the semiconductor layer in contact with each other Source drain A region, a gate electrode provided on at least one remaining side surface of the semiconductor layer via a gate insulating film, the semiconductor layer, the conductive film ( Part of source / drain region) And an insulating film provided around the remaining side surface and bottom surface of the gate electrode. A side surface where the semiconductor layer and the conductive film (a part of the source / drain region) are in contact with each other, and the insulating layer provided immediately below the semiconductor layer and the conductive film (a part of the source / drain region). The insulating film provided on the side surface of the semiconductor layer, the conductive film (a part of the source / drain region), the side surface of the conductive film (a part of the source / drain region), The top surface of the gate electrode has the same height This is solved by the MIS field effect transistor of the present invention.
[0005]
[Operation]
That is, in the main MIS field effect transistor of the present invention, an epitaxial semiconductor layer is provided on the exposed portion of the semiconductor substrate selectively provided on the insulating film laminated on the semiconductor substrate, and the epitaxial semiconductor layer is opposed to the epitaxial semiconductor layer. A conductive film having a barrier metal (metal source / drain region), which is in contact with a part of the two side surfaces and embeds a pair of first openings provided in a part of the insulating film, is provided. High-concentration and low-concentration source / drain regions are provided in contact portions between the film and the epitaxial semiconductor layer, are in contact with a part of the remaining one side surface of the epitaxial semiconductor layer, are slightly wider than the epitaxial semiconductor layer, and the first opening portion Deeper, a gate insulating film is provided on the side surface and bottom surface of the second opening provided in a part of the insulating film, and the barrier is interposed through the gate insulating film. A gate electrode having a tar is embedded in the second opening portion flatly, and the barrier metal is formed through the remaining side surface of the epitaxial semiconductor layer, the bottom surface and the remaining side surface of the conductive film having the barrier metal, and the gate insulating film. Lateral pseudo SOI structure in which an insulating film is provided on the bottom surface and the remaining side surface of the gate electrode (which is not a conventional SOI structure in which islands are separated by an insulating film in the vertical direction, but a part thereof is directly connected to the substrate. A side-gate metal gate type MIS field effect transistor having a pseudo SOI structure that is insulated and isolated in the lateral direction and having almost no element characteristics) is formed.
Therefore, without forming an expensive SOI wafer or an SOI structure by SIMOX, a gate electrode is formed on one side with a gate oxide film and an insulating film is formed on the opposite side by a simple process on a semiconductor substrate. It is possible to form a lateral side operation MIS field effect transistor using a partially epitaxial semiconductor layer as a pseudo SOI substrate. Further, since the surface occupation area of the growing partial epitaxial semiconductor layer can be formed very minutely, a fully depleted pseudo SOI substrate and a short channel can be easily formed. Further, a sufficient channel width can be ensured with high integration by the thickness of the grown partial epitaxial silicon layer. In the epitaxial semiconductor layer, only the channel region, very minute high-concentration and low-concentration source / drain regions are formed, and most of the source / drain regions are not impurity regions, and the remaining side surfaces and bottom surfaces are surrounded by insulating films. In addition, since it can be formed of a low resistance conductive film (metal source / drain region), the junction capacitance and resistance of the source / drain region can be reduced. Ta with high dielectric constant ₂ O _Five Can be used as the gate oxide film, so that the gate oxide film can be thickened, and a slight current leakage between the gate electrode and the epitaxial semiconductor layer can be improved and the gate capacity can be reduced. In addition, since a source / drain region that requires high-temperature heat treatment to activate the impurity region can be formed before forming the gate electrode, a gate made of a low-resistance, low-melting-point metal can be used without using a polycrystalline silicon film as a semiconductor layer. Since the electrode can be formed, the resistance of the gate electrode wiring can be reduced. Further, since the gate structure is formed on the thin pseudo-SOI substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer and the substrate can be eliminated, and the gate made of metal. By using the electrode, the depletion layer capacitance at the gate electrode can also be removed, so that the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, and the subthreshold characteristic can be improved, so that the threshold voltage can be reduced, It is also possible to reduce power consumption. In addition, the insulating film in the element isolation region, the epitaxial semiconductor layer, the metal source / drain region, and the upper surface of the gate electrode portion can be formed on a continuous flat surface having no step, thereby forming an extremely reliable interlayer insulating film and wiring body. Is also possible. It is also possible to easily form a metal source / drain region and a connection to the gate electrode from the surface with a fine area.
That is, a lateral metal gate type MIS field effect transistor having a lateral pseudo-SOI structure using a partial epitaxial semiconductor layer that can form a semiconductor integrated circuit having high speed, low power, high reliability, high performance, and high integration can be obtained. .
[0006]
【Example】
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 is a schematic plan view of a first embodiment of the MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view of the first embodiment of the MIS field effect transistor of the present invention (cross-sectional view taken along the line pp). 3 is a schematic side sectional view of the first embodiment of the MIS field effect transistor according to the present invention (qq arrow sectional view), and FIG. 4 is a diagram of the first embodiment of the MIS field effect transistor according to the present invention. FIG. 5 is a schematic plan view of a second embodiment of the MIS field effect transistor of the present invention, and FIG. 6 is a second embodiment of the MIS field effect transistor of the present invention. FIG. 7 is a schematic plan view of a third embodiment of the MIS field effect transistor of the present invention, and FIG. 8 is a third plan view of the MIS field effect transistor of the present invention. Examples of FIG. 9 is a schematic plan view of a fourth embodiment of the MIS field effect transistor of the present invention, and FIG. 10 is a fourth embodiment of the MIS field effect transistor of the present invention. FIG. 11 is a schematic side sectional view of a fifth embodiment of the MIS field effect transistor of the present invention, and FIG. 12 is a schematic side sectional view of the MIS field effect transistor of the present invention. FIG. 13 is a schematic plan view of a seventh embodiment of the MIS field effect transistor of the present invention, and FIG. 14 is a schematic side view of the seventh embodiment of the MIS field effect transistor of the present invention. FIG. 15 is a schematic side sectional view (qq arrow sectional view) of the seventh embodiment of the MIS field effect transistor of the present invention, and FIGS. MIS of the invention It is a process cross-sectional view of one embodiment of a manufacturing method in the field effect transistor.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the oblique lines in the side sectional view are shown only on the main insulating film, and the broken lines are added for easy understanding of the drawings, and represent objects slightly in front of or behind the paper in the direction perpendicular to the paper surface. Moreover, in order to show the principal part of invention, the size of the horizontal direction and the vertical direction does not show the exact dimension.
1 to 4 show a first embodiment of the MIS field effect transistor according to the present invention (FIG. 1 is a schematic plan view, FIG. 2 is a cross-sectional view taken along a line pp, FIG. 3 is a cross-sectional view taken along a line q-q, 4 is a cross-sectional view taken along the line r-r), and is a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor in which a partial epitaxial silicon layer grown on a p-type silicon substrate is formed as a pseudo SOI substrate. 1 is 10 ¹⁵ cm ^-3 P-type silicon substrate, 2 is an insulating film serving as an element isolation region, a metal source / drain region, and an insulating film (SiO 2 below the gate electrode) ₂ ) 3 is a rectangular p-type epitaxial silicon layer having a surface of about 100 nm in length and 120 nm in width, 4 is 10 ¹⁷ cm ^-3 N-type source / drain region, 5 is 10 ²⁰ cm ^-3 Degree n ⁺ Type source / drain region 6 is a barrier metal (TiN) of about 20 nm, 7 is a conductive film (metal source / drain region, W) having a depth of about 5 μm, and 8 is a gate oxide film (SiO 2) of about 12 nm. ₂ / Ta ₂ O _Five ), 9 is a barrier metal (TiN) of about 20 nm, 10 is a gate electrode (Al) having a gate length of about 120 nm, 11 is a phosphosilicate glass (PSG) film of about 600 nm, and 12 is a barrier metal (TiN) of about 20 nm. ), 13 is a conductive plug (W), 14 is a barrier metal (TiN) of about 50 nm, 15 is an AlCu wiring of about 500 nm, and 16 is a barrier metal (TiN) of about 50 nm.
In the figure, a p-type epitaxial silicon layer 3 is provided on an exposed portion of a p-type silicon substrate 1 selectively provided on an oxide film 2 stacked on a p-type silicon substrate 1. A conductive film (metal source / drain region) having a barrier metal (TiN) 6 embedded in a pair of first opening portions provided in a part of the insulating film 2 in contact with a part of two opposite side surfaces of the layer 3 , W) 7 is provided, and the contact portion between the conductive film 7 having the barrier metal 6 and the epitaxial silicon layer 3 is n ⁺ Type and n type source / drain regions (4, 5) are provided, in contact with a part of the remaining one side surface of the epitaxial silicon layer 3, slightly wider than the epitaxial silicon layer 3 and deeper than the first opening, A gate oxide film (SiO ₂ / Ta ₂ O _Five ) 8 is provided, and the gate electrode (Al) 10 having the barrier metal (TiN) 9 is flatly embedded in the second opening portion through the gate oxide film 8, and the remaining portion of the epitaxial silicon layer 3 is Lateral pseudo in which the oxide film 2 is provided around the side surface, the bottom surface of the conductive film 7 having the barrier metal 6 and the remaining side surface, and the bottom surface and the remaining side surface of the gate electrode 10 having the barrier metal 9 through the gate oxide film 8. An SOI-structure side metal gate type N-channel MIS field effect transistor is formed. Further, both the metal source / drain region and the electrode contact portion with the wiring body in the gate electrode are formed wider than the width of the epitaxial silicon layer. (The metal source / drain region in the present invention is a metal film or alloy film that does not include an impurity region unlike a conventional metal source / drain region made of a compound [salicide] of an impurity region and a metal film formed on a silicon semiconductor substrate. Only area.)
Therefore, without forming an expensive SOI wafer or an SOI structure by SIMOX, a gate electrode is formed on one side with a gate oxide film and an insulating film is formed on the opposite side by a simple process on a semiconductor substrate. A lateral side operation MIS field effect transistor using a partially epitaxial silicon layer as a pseudo SOI substrate can be formed. Further, since the surface occupation area of the growing partial epitaxial silicon layer can be formed very minutely, a fully depleted pseudo SOI substrate and a short channel can be easily formed. (One direction of the surface defines the channel length [strictly defined by the distance between the impurity source and drain regions], and the vertical direction defines the thickness of the SOI substrate that can be completely depleted.) It is possible to ensure a sufficient channel width with high integration by the stacking thickness. (The channel width is defined by the depth of the metal source / drain region, and is strictly defined by the depth of the impurity source / drain region.) The epitaxial silicon layer has a channel region, a very small high-concentration and low-concentration source. Since only the drain region is formed, most of the source / drain region can be formed not by the impurity region but by the low resistance conductive film (metal source / drain region) in which the remaining side and bottom surfaces are surrounded by an insulating film. The junction capacitance and resistance of the region can be reduced. Ta with high dielectric constant ₂ O _Five Can be used as the gate oxide film, so that the gate oxide film can be thickened, and a slight current leakage between the gate electrode and the epitaxial silicon layer can be improved and the gate capacity can be reduced. In addition, a source / drain region that requires high-temperature heat treatment to activate the impurity region can be formed before forming the gate electrode, so that a low-resistance low-melting-point metal (Al) can be used without using a polycrystalline silicon film as a semiconductor layer. Therefore, the resistance of the gate electrode wiring can be reduced. Further, since the gate structure is formed on the thin pseudo-SOI substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer and the substrate can be eliminated, and the gate made of metal. By using the electrode, the depletion layer capacitance at the gate electrode can also be removed, so that the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, and the subthreshold characteristic can be improved, so that the threshold voltage can be reduced, It is also possible to reduce power consumption. In addition, the insulating film in the element isolation region, the epitaxial silicon layer, the metal source / drain region, and the upper surface of the gate electrode portion can be formed on a continuous flat surface having no step, thereby forming an extremely reliable interlayer insulating film and wiring body. Is also possible. It is also possible to easily form a metal source / drain region and a connection to the gate electrode from the surface with a fine area.
As a result, high-speed, low-power, high-reliability, high-performance and high-integration can be achieved by using the partial epitaxial semiconductor layer formed on the semiconductor substrate as a pseudo SOI substrate without using an expensive SOI-structured semiconductor substrate. A lateral metal gate type MIS field effect transistor having a lateral pseudo SOI structure can be formed using a partially epitaxial semiconductor layer.
[0007]
5 and 6 show a second embodiment of the MIS field effect transistor of the present invention (FIG. 5 is a schematic plan view, and FIG. 6 is a cross-sectional view taken along the line qq), and a portion grown on a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor in which an epitaxial silicon layer is formed as a pseudo SOI substrate, and reference numerals 1 to 16 denote the same components as those in the first embodiment.
In the figure, the structure is the same as that of the first embodiment except that the gate electrode (Al) 10 having the barrier metal (TiN) 9 is provided on both sides of the epitaxial silicon layer 3 via the gate oxide film 8. A short-channel N-channel MIS field effect transistor is formed.
In this embodiment, the same effect as in the first embodiment can be obtained. In addition, a minute current leak due to the generation of a side channel on the opposite side surface (in the case of a MIS field effect transistor having a normal SOI structure, structural control is possible). Difficult, corresponding to a minute current leak due to the occurrence of a back channel) can be easily prevented, and a channel controlled by the gate electrode can be formed on both sides, so that more current can flow. High speed is possible.
[0008]
7 and 8 show a third embodiment of the MIS field effect transistor of the present invention (FIG. 7 is a schematic plan view and FIG. 8 is a cross-sectional view taken along the line qq), and a portion grown on a p-type silicon substrate. 1 shows a part of a C-MOS type semiconductor integrated circuit including short channel N-channel and P-channel MIS field effect transistors formed by using an epitaxial silicon layer as a pseudo SOI substrate. The same thing, 17 is an n-type epitaxial silicon layer, 18 is p ⁺ A type source / drain region is shown.
In this figure, a common gate electrode 10 having a barrier metal 9 is provided, and an N-channel MIS field effect transistor having the same structure as that of the first embodiment is partially formed on a p-type silicon substrate 1. A p-channel MIS field effect transistor having the same structure is partially formed on the p-type silicon substrate 1 except that the low-concentration source / drain region is removed. The n-type epitaxial silicon layer 17 is formed. Although not shown, gate electrodes may exist on both side surfaces of the p-type epitaxial silicon layer 3 and the n-type epitaxial silicon layer 17.
In the present embodiment, the same effect as that of the first embodiment can be obtained with respect to the C-MOS type semiconductor integrated circuit, and also compared with the conventional twin tab C-MOS type semiconductor integrated circuit formed on the semiconductor substrate. In addition, it can be formed with higher integration.
[0009]
9 and 10 show a fourth embodiment (FIG. 9 is a schematic plan view, FIG. 10 is a cross-sectional view taken along the line pp) of the MIS field-effect transistor of the present invention, and a portion grown on a p-type silicon substrate. 1 shows a part of a C-MOS type semiconductor integrated circuit including a short-channel N-channel and P-channel MIS field effect transistor in which an epitaxial silicon layer is formed as a pseudo SOI substrate. 7a indicates a metal drain region, and 7b indicates a metal source region.
In this figure, although the layout is different, not only N-channel and P-channel MIS field effect transistors having the same structure as the third embodiment are formed, but also an N-channel MIS field effect transistor and a P-channel MIS. An extremely highly integrated C-MOS basic circuit in which a common metal drain region 7a is formed between different channels without forming an element isolation region by an insulating film that separates a field effect transistor (effective for an inverter of a C-MOS, etc.) ) Is formed. Although not shown, gate electrodes may exist on both side surfaces of the p-type epitaxial silicon layer 3 and the n-type epitaxial silicon layer 17.
In the present embodiment, not only can the same effect as the first embodiment be obtained with respect to the C-MOS type semiconductor integrated circuit, but also an extremely highly integrated C-MOS type semiconductor integrated circuit can be obtained. Become.
[0010]
FIG. 11 is a schematic sectional side view of the fifth embodiment of the MIS field effect transistor according to the present invention. The short channel N channel and P are formed by forming a partial epitaxial silicon layer grown on a p-type silicon substrate as a pseudo SOI substrate. 1 shows a part of a C-MOS type semiconductor integrated circuit including a channel MIS field effect transistor, wherein 1 to 18 are the same as those of the first and third embodiments, 19 is a p-type impurity region, and 20 is an n-type A type impurity region is shown.
In the figure, an N-channel MIS electric field having the same structure as that of the first embodiment is formed on a p-type epitaxial silicon layer 3 formed on a p-type impurity region selectively provided on a p-type silicon substrate 1. Since the effect transistor is formed and the hot carrier effect does not occur in the n-type epitaxial silicon layer 17 formed on the n-type impurity region selectively provided on the p-type silicon substrate 1, the low concentration source / drain region is formed. A P-channel MIS field-effect transistor with the same structure is formed except for the removal, and a small amount of current leakage is caused by using the raised regions (19, 20) of the impurities when growing the epitaxial silicon layer as channel stoppers. It has been prevented. In this embodiment, the same effect as that of the first embodiment can be obtained with respect to the C-MOS type semiconductor integrated circuit, and a minute current leakage can be prevented, thereby enabling further high reliability. .
[0011]
FIG. 12 is a schematic sectional side view of a sixth embodiment of the MIS field effect transistor according to the present invention. A short channel N channel and a P channel formed by forming a partial epitaxial silicon layer grown on a p-type silicon substrate as a pseudo SOI substrate. A part of a C-MOS type semiconductor integrated circuit including a channel MIS field effect transistor is shown, and reference numerals 1 to 18 denote the same parts as in the first and third embodiments.
In the figure, an N-channel MIS field effect transistor having the same structure as that of the first embodiment is formed on a p-type epitaxial silicon layer 3 formed on a p-type silicon substrate 1, and a p-type silicon substrate is formed. Since no hot carrier effect occurs in the n-type epitaxial silicon layer 17 formed on 1, the metal source / drain region 7 and the p having the barrier metal 6 have the same structure except that the low-concentration source / drain region is removed. ⁺ A P-channel MIS field effect transistor in which the source / drain region 18 is formed deeply is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained with respect to the C-MOS type semiconductor integrated circuit, and the integration degree is lowered in the P-channel MIS field effect transistor having a low carrier mobility. Without increasing the channel width, it is possible to further increase the speed.
[0012]
13 to 15 show a seventh embodiment of the MIS field effect transistor of the present invention (FIG. 13 Is a schematic plan view, figure 14 Is a cross-sectional view of the pp arrow, figure 15 Is a cross-sectional view taken along the arrow q-q), and shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor in which a partial epitaxial silicon layer grown on a p-type silicon substrate is formed as a pseudo SOI substrate. 1 to 16 are the same as those in the first embodiment.
In the figure, a short circuit having the same structure as that of the second embodiment except that a gate electrode width is formed in a self-alignment with a p-type epitaxial silicon layer by a pair of metal source / drain regions 7 having a barrier metal 6. A channel N-channel MIS field effect transistor is formed.
In this embodiment, the same effect as in the first and second embodiments can be obtained, but the capacitance between the gate electrode and the metal source / drain region is slightly increased, but the gate electrode width and the metal source / drain region width are increased. Therefore, higher integration can be achieved.
[0013]
Next, an embodiment of a method for manufacturing a MIS field effect transistor according to the present invention will be described with reference to FIGS. However, here, only the manufacturing method relating to the formation of the MIS field effect transistor of the present invention is described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit. Is omitted.
FIG.
An oxide film (SiO 2) of about 6 μm is formed on the p-type silicon substrate 1 by chemical vapor deposition. ₂ ) Grow 2. Next, using an ordinary photolithography technique, an oxide film (SiO 2) is formed using the first resist (not shown) as a mask layer. ₂ 2) Selectively dry anisotropically about 5 μm. Next, the first resist (not shown) is left as it is to form a selectively opened second resist (not shown), and the first and second resists (not shown) are used as mask layers. The remaining oxide film (SiO ₂ ) 2 is selectively anisotropically etched by about 1 μm to expose a part of the p-type silicon substrate 1. Next, the first and second resists (not shown) are removed. Thus, an oxide film (SiO 2 having a two-stage structure) ₂ ) 2 is formed.
FIG.
Next, a p-type epitaxial silicon layer 3 is formed on the exposed p-type silicon substrate 1 with an oxide film (SiO 2). ₂ ) Grows so as to be higher than the upper surface of the upper stage of 2. Next, phosphorus is obliquely ion-implanted. Continuous oblique ion implantation of arsenic is performed. (At this time, boron ion implantation for controlling the threshold voltage may be performed.)
FIG.
Then oxide film (SiO ₂ ) Chemical mechanical polishing of the p-type epitaxial silicon layer 3 until the upper surface of 2 is slightly scraped ( C chemical M economic-al P (hereinafter abbreviated as CMP). (As impurities are introduced into the entire side surface and upper surface of the portion of the epitaxial silicon layer 3 protruding from the upper surface of the upper stage of the oxide film 2, the epitaxial silicon layer 3 is removed to such an extent that the impurity introduction region other than the two opposing side surfaces can be removed. Then, N at 800 ° C ₂ By applying annealing, the n-type source / drain regions 4 and n are diffused slightly in the lateral direction using the difference in diffusion coefficient. ⁺ A type source / drain region 5 is formed.
FIG.
Next, TiN 6 serving as a barrier metal is grown by sputtering to about 20 nm. Next, the tungsten film (W) 7 is grown by chemical vapor deposition to such an extent that the tungsten film (W) 7 can be sufficiently embedded in the opening. Next, chemical mechanical polishing (CMP) is performed, W and TiN are embedded in the openings, and the n-type source / drain regions 4 and n ⁺ Metal source / drain regions (W) 7 having barrier metals 6 are formed on both sides of the p-type epitaxial silicon layer 3 in which the type source / drain regions 5 are formed.
FIG.
Next, using an ordinary photolithography technique, a resist (not shown), a metal source / drain region (W) 7 having a barrier metal 6 and a p-type epitaxial silicon layer 3 are selectively used as mask layers to form an oxide film (SiO 2). ₂ 2) Perform anisotropic dry etching of 2 to about 5.5μm. (N formed in contact with at least the metal source / drain region ⁺ An opening for forming a gate electrode is formed so as to be deeper than the source / drain region 5 and the source / drain region 4. Then, the resist (not shown) is removed. Next, a gate oxide film 8 of about 12 nm (SiO ₂ / Ta ₂ O _Five ) Grow. Next, a barrier metal (TiN) 9 of about 20 nm and Al10 to be a gate electrode are grown by continuous sputtering. Next, by chemical mechanical polishing (CMP), the gate electrode film 8 (SiO ₂ / Ta ₂ O _Five ), A buried side surface gate electrode structure including a barrier metal (TiN) 9 and a gate electrode (Al) 10 is formed. FIG.
Next, a phosphosilicate glass (PSG) film 11 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the PSG film 11 is selectively anisotropically dry etched using a resist (not shown) as a mask layer to open a via. Next, the resist (not shown) is removed. Next, TiN 12 serving as a barrier metal is grown by sputtering. Next, a tungsten film 13 is grown by chemical vapor deposition. Then, the conductive plug (W) 13 is formed by embedding in the via by chemical mechanical polishing (CMP).
FIG.
Next, TiN 14 as a barrier metal is grown to about 50 nm by sputtering. Next, Al (containing several percent of Cu) 15 to be a wiring is grown to about 500 nm by sputtering. Next, TiN 16 serving as a barrier metal is grown to about 50 nm by sputtering. Next, using normal photolithography technology, anisotropic dry etching of barrier metal (TiN), Al (including several percent of Cu) and barrier metal (TiN) is performed using a resist (not shown) as a mask layer. An AlCu wiring 15 is formed. Next, the resist (not shown) is removed, and a lateral metal gate type MIS field effect transistor having a lateral pseudo SOI structure having a partial epitaxial silicon layer of the present invention is completed.
In the above description, the case where the p-type epitaxial silicon layer is formed on the p-type silicon substrate is described. However, the n-type epitaxial silicon layer may be formed on the n-type silicon substrate, or the silicon substrate may be formed. Without limitation, a compound semiconductor substrate may be used. Further, the metal source / drain region, the gate electrode, the barrier metal, the conductive plug, the wiring, and the like are not limited to the above embodiment, and any material may be used as long as it has the same characteristics.
[0014]
【Effect of the invention】
As described above, according to the present invention, the fine epitaxial semiconductor layer stacked on the exposed portion of the semiconductor substrate selectively opened in the insulating film stacked on the semiconductor substrate is formed in a conventional vertical direction. Instead of the SOI substrate, a lateral (lateral) fully depleted pseudo SOI substrate is formed, and minute low-concentration and high-concentration impurity source / drain regions are formed on the pseudo-SOI substrate, and most of the source / drain regions are made high. A gate electrode made of a metal layer is formed on one side surface of the pseudo SOI substrate with a gate insulating film interposed between the pair of metal layers (metal source drain region) in contact with the concentration source / drain region, and the opposite side surface of the pseudo SOI substrate. An insulating film is formed (or a gate electrode is formed on both opposing side surfaces through the gate insulating film), and the remaining metal source / drain regions and the remaining gate electrode are formed. MIS field effect transistor of the metal gate type lateral pseudo SOI structure insulating film is circumferentially provided on the surface and the bottom surface is formed.
Therefore, without forming an expensive SOI wafer or an SOI structure by SIMOX, a gate electrode is formed on one side with a gate oxide film and an insulating film is formed on the opposite side by a simple process on a semiconductor substrate. It is possible to form a lateral side operation MIS field effect transistor using a partially epitaxial semiconductor layer as a pseudo SOI substrate. In addition, a sufficient channel width can be secured with high integration by the thickness of the growing partial epitaxial semiconductor layer. In addition, since the source / drain region can be formed using the conductive film in which the insulating film is provided and the minute impurity region, the junction capacitance and resistance of the source / drain region can be reduced. Also, a thick film with a high dielectric constant Ta ₂ O _Five Can be used as a gate oxide film, so that a slight current leakage between the gate electrode and the epitaxial semiconductor layer can be improved and the gate capacitance can be reduced. In addition, since the gate electrode made of a low-melting-point low melting point metal can be formed, the resistance of the gate electrode wiring can be reduced. Further, since the gate structure is formed on the thin-film pseudo SOI substrate, the pseudo SOI substrate and the gate electrode can be used, and the depletion layer capacitance of the pseudo SOI substrate and the gate electrode can be removed. Since the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, the subthreshold characteristic can be improved, the threshold voltage can be reduced, and the power can be reduced. In addition, the insulating film in the element isolation region, the epitaxial semiconductor layer, the metal source / drain region, and the upper surface of the gate electrode portion can be formed on a continuous flat surface having no step, thereby forming an extremely reliable interlayer insulating film and wiring body. Is also possible. It is also possible to easily form a metal source / drain region and a connection to the gate electrode from the surface with a fine area. In addition, if a gate electrode is formed on both sides of the epitaxial semiconductor layer via a gate insulating film, a channel that is completely controlled by the gate electrode can be formed on both sides, so that more current can flow. High speed is possible.
That is, a lateral metal gate type MIS field effect transistor having a lateral pseudo-SOI structure using a partial epitaxial semiconductor layer that can form a semiconductor integrated circuit having high speed, low power, high reliability, high performance, and high integration can be obtained. .
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a first embodiment of a MIS field effect transistor according to the present invention.
FIG. 2 is a schematic side sectional view of a first embodiment of the MIS field effect transistor according to the present invention (cross-sectional view taken along the line pp).
FIG. 3 is a schematic side sectional view of the first embodiment of the MIS field effect transistor according to the present invention (cross-sectional view taken along the line q-q).
FIG. 4 is a schematic side sectional view of the first embodiment of the MIS field effect transistor according to the present invention (cross-sectional view taken along line r-r).
FIG. 5 is a schematic plan view of a second embodiment of the MIS field effect transistor of the present invention.
FIG. 6 is a schematic side sectional view (qq arrow sectional view) of a second embodiment of the MIS field effect transistor of the present invention.
FIG. 7 is a schematic plan view of a third embodiment of the MIS field effect transistor of the present invention.
FIG. 8 is a schematic side sectional view (qq arrow sectional view) of a third embodiment of the MIS field-effect transistor of the present invention.
FIG. 9 is a schematic plan view of a fourth embodiment of the MIS field effect transistor of the present invention.
FIG. 10 is a schematic side sectional view of a fourth embodiment of the MIS field effect transistor according to the present invention (cross-sectional view taken along the line pp).
FIG. 11 is a schematic side sectional view of a fifth embodiment of the MIS field-effect transistor of the present invention.
FIG. 12 is a schematic side sectional view of a sixth embodiment of the MIS field-effect transistor of the present invention.
FIG. 13 is a schematic plan view of a seventh embodiment of the MIS field effect transistor of the present invention.
FIG. 14 is a schematic side sectional view of a seventh embodiment of the MIS field effect transistor according to the present invention (cross-sectional view taken along the line pp).
FIG. 15 is a schematic side sectional view (qq arrow sectional view) of a seventh embodiment of the MIS field effect transistor of the present invention;
FIG. 16 is a process cross-sectional view of an embodiment of a manufacturing method of a MIS field effect transistor according to the present invention.
FIG. 17 is a process cross-sectional view of an embodiment of a manufacturing method of a MIS field effect transistor according to the present invention.
FIG. 18 is a process cross-sectional view of one embodiment of a manufacturing method for a MIS field effect transistor of the present invention.
FIG. 19 is a process cross-sectional view of an embodiment of a manufacturing method of a MIS field effect transistor according to the present invention.
FIG. 20 is a process cross-sectional view of an embodiment of a manufacturing method of a MIS field effect transistor according to the present invention.
FIG. 21 is a process cross-sectional view of one embodiment of a manufacturing method for a MIS field effect transistor of the present invention.
FIG. 22 is a schematic side sectional view of a conventional MIS field effect transistor.
[Explanation of symbols]
1 p-type silicon (Si) substrate
2 Insulating film / metal source / drain region in element isolation region and insulating film under gate electrode (SiO ₂ )
3 p-type epitaxial silicon layer
4 n-type source / drain region
5 n ⁺ Type source / drain region
6 Barrier metal (TiN)
7 Metal source drain region (W)
7a Metal drain region (W)
7b Metal source region (W)
8 Gate oxide film (SiO ₂ / Ta ₂ O _Five )
9 Barrier metal (TiN)
10 Gate electrode (Al)
11 Phosphorsilicate glass (PSG) film
12 Barrier metal (TiN)
13 Conductive plug (W)
14 Barrier metal (TiN)
15 AlCu wiring
16 Barrier metal (TiN)
17 n-type epitaxial silicon layer
18p ⁺ Type source / drain region
19 p-type impurity region
20 n-type impurity region

Claims (4)

A semiconductor substrate, a semiconductor layer selectively stacked on the semiconductor substrate, and a pair of opposing conductive films ( part of a source / drain region) provided in contact with part of two opposing side surfaces of the semiconductor layer, respectively ) And the conductive film ( a part of the source / drain region) , an impurity source / drain region provided in the semiconductor layer, and at least one remaining side surface of the semiconductor layer with a gate insulating film interposed therebetween. A gate electrode, the semiconductor layer, the conductive film ( a part of the source / drain region), and an insulating film provided around the remaining side and bottom surfaces of the gate electrode, and the semiconductor layer and the conductive film ( A side surface in contact with a part of the source / drain region and a side surface in contact with the insulating layer provided immediately below the semiconductor layer and the conductive film (a part of the source / drain region) are perpendicular to each other. And the top surface of the insulating layer and the gate electrode provided on the side surfaces of the semiconductor layer, the conductive film (a part of the source / drain region), the conductive film (a part of the source / drain region) are the same height MIS field effect transistor characterized by having . 2. The MIS field effect transistor according to claim 1, wherein the conductive film ( a part of the source / drain region) and the gate electrode have a barrier metal layer. The width of the semiconductor layer between the conductive films (a part of the source / drain region) defines a channel length, and the depth of the conductive film (a part of the source / drain region) defines the channel width. 3. The MIS field effect transistor according to claim 1 and claim 2.   A step of laminating an insulating film on the semiconductor substrate; a step of selectively removing the insulating film halfway; and further removing a central portion of the insulating film removed halfway to expose a surface of the semiconductor substrate. A step of forming an epitaxial semiconductor layer on the exposed semiconductor substrate that is higher than a height of the laminated insulating film, a step of implanting impurities into the exposed portion of the epitaxial semiconductor layer, and the laminated insulating layer Flattening the epitaxial semiconductor layer to the same height as the film, embedding a conductive film flatly on the insulating film removed halfway on both sides of the epitaxial semiconductor layer, and at least the epitaxial semiconductor layer Forming an opening selectively exposing a part of the side surface of the epitaxial semiconductor layer in the insulating film on the other side surface of the opening; and a bottom of the opening A method of manufacturing a MIS field effect transistor, comprising: forming a gate insulating film on a surface and a side surface; and embedding a metal film in the opening.

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