JP2001250950A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a high-speed C-MOS semiconductor device having a highly integrated SOI structure. SOLUTION: The SOI type C-MOS semiconductor device having a highly integrated high speed hetero-channel common metal source-drain structure comprises first, second and third metal source-drain regions (10a, 10b, 10c) partly contacting the opposite sides of a pair of p- and n-type SOI substrates (3, 4) which are overlaid through an insulation film 2 on a semiconductor substrate 1, formed into thin films and insulatively isolated like islands. A pair of n+ type and n-type source-drain regions (8, 6) thereof is provided on the p-type SOI substrate 3 at contacts with the metal-drain regions. A pair of p+ type and p-type source-drain regions (9, 7) is provided on the n-type SOI substrate 4. A gate oxide film 11 is provided on the upsides of both SOI substrates and the sides of the opposite metal source-drain regions. Gate electrodes 13 having a barrier metal 12 are buried through the gate oxide film 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an SOI structure, and more particularly to a short-channel C-MOS type semiconductor device having an SOI structure of high speed, low power, high reliability, high performance and high integration (especially C-MOS semiconductor device). C-MOS SRAM using a MOS inverter and a flip-flop). Conventionally, in a C-MOS semiconductor device including a pair of N-channel and P-channel MIS field-effect transistors, an N-channel MIS field-effect transistor and a P-channel MIS field-effect transistor are formed on respective substrates (actually, One is formed in the impurity well region of the same conductivity type as the semiconductor substrate formed in the semiconductor substrate, and the other is formed in the impurity well region of the opposite conductivity type to the semiconductor substrate formed in the semiconductor substrate. Since a relatively large space is required at the boundary of the MIS field-effect transistor, there has been a disadvantage that high integration has not been achieved despite the miniaturization of each element. Therefore, there is a demand for a means capable of forming a C-MOS semiconductor device capable of further miniaturization as well as element miniaturization, reducing the resistance of each element, and achieving higher speed.

[0002]

2. Description of the Related Art FIG. 15 is a schematic side sectional view of a conventional semiconductor device, and shows a C-MO formed on a p ^- type silicon (Si) substrate.
A part of a semiconductor integrated circuit including an S inverter is shown, 51 is a p ^- type silicon substrate, 52 is a p-type impurity well region, 53 is an n-type impurity well region, and 54 is a p-type and n-type impurity well. Trench and buried oxide film for region isolation,
55 is a trench for forming an element isolation region and a buried oxide film,
56 is an n-type source / drain region, 57 is a p-type source / drain region, 58 is an n ⁺ -type source / drain region and an n ⁺ -type impurity well contact region, 59 is a p ⁺ -type source / drain region and a p ⁺ -type impurity well contact region, 60 is a gate oxide film, 61 is a gate electrode (polySi / W), 62 is a base oxide film, 63 is a sidewall, 64 is an oxide film for impurity blocking, 65 is a phosphosilicate glass (PSG) film, 66 is a barrier metal ( Ti
/ TiN), 67 is a plug (W), 68 is a barrier metal (Ti /
TiN), 69 is AlCu wiring, 70 is barrier metal (Ti / TiN)
Is shown. In the figure, a p ^- type silicon substrate
A p-type impurity well region 52 and an n-type impurity well region 53 which are insulated and separated by an element isolation region forming trench and an impurity well region isolating trench (54, 55) in which an oxide film selectively embedded in 51 is embedded. Is formed in the p-type impurity well region 52 using the p-type impurity well region 52 as a substrate, an n-type source / drain region 56 self-aligned with the gate electrode 61, and an n ⁺ -type self-aligned formation with the side wall 63. N-channel LD including source / drain region 58 and p ⁺ -type impurity well contact region 59
A MIS field effect transistor having a D structure is formed.
The p-type source / drain region 57 self-aligned with the gate electrode 61, the p ⁺ source / drain region 59 self-aligned with the side wall 63, and the n-type impurity well region 53 as a substrate. And n ⁺
A MIS field-effect transistor having a P-channel LDD structure including a p-type impurity well contact region 58 is formed. Further, the p ⁺ -type impurity well contact region 59 and the n ⁺ -type source region 58 are each formed of a barrier metal (Ti / Ti
N) 66 and a plug (W) 67 are connected to an AlCu wiring 69 having upper and lower barrier metals (Ti / TiN) (68, 70), and a ground voltage is applied. On the other hand, the n ⁺ -type impurity well contact region 58 and the p ⁺ -type source region 59 are vertically connected with a barrier metal (Ti / TiN) (68, 70) via a barrier metal (Ti / TiN) 66 and a plug (W) 67, respectively. , And a power supply voltage is applied.
Although not shown in the figure, the gate electrodes 61 of the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are connected to the front or the back of the cut surface, and the input voltage is applied. The matching n ⁺ -type drain region 58 and p ⁺ -type drain region 59 have upper and lower barrier metals (Ti / TiN) (68, 70) via a barrier metal (Ti / TiN) 66 and a plug (W) 67, respectively. AlCu
C-MO connected to the wiring 69 and taking out the output voltage
An S inverter is configured. Therefore, since the source / drain region and the impurity well contact region which are insulated and separated by the trench for forming the element isolation region and the trench for separating the impurity well region in which the oxide film is buried can be formed, a considerably fine C-MOS inverter can be formed. However, the above configuration has the drawback that further high integration cannot be achieved other than miniaturization of each element, and further higher speed cannot be achieved other than an increase in switching speed due to miniaturization of the MIS field effect transistor.

[0003]

The problem to be solved by the present invention is, as shown in the prior art, a conventional N-channel MIS field-effect transistor and a P-channel M-channel transistor.
In a C-MOS semiconductor device (especially an inverter) comprising IS field-effect transistors, each element is miniaturized, and the switching speed of the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor is increased. That is, integration and high speed cannot be achieved.

[0004]

SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor substrate, an insulating film provided on the semiconductor substrate, and one conductive type and opposite conductive type S selectively provided on the insulating film.
An OI substrate, a gate insulating film provided on the one conductivity type and the opposite conductivity type SOI substrate, a gate electrode provided on the gate insulating film, and the one conductivity type and the opposite conductivity type SOI substrate. The SOI of the one conductivity type and the opposite conductivity type
A first metal source / drain region provided partially in contact with a side surface of the substrate; and a first metal source / drain region in contact with the first metal source / drain region on opposite side surfaces of the one conductivity type and the opposite conductivity type SOI substrate. The second provided in contact with a part
And a third metal source / drain region and an opposite conductivity type impurity region (source) provided at a contact portion of the opposing first and second metal source / drain regions on the one conductivity type SOI substrate. A drain region) and an impurity region of one conductivity type (source / drain region) provided on the opposite conductivity type SOI substrate at a contact portion between the opposed first and third metal source / drain regions.
The SOI C-MOS semiconductor device of the present invention having a common metal source / drain structure between different channels (strictly speaking, a common metal drain structure) comprising the following.

[0005]

[Operation] That is, in the semiconductor device of the present invention, p
^- Selectively on the oxide film provided on the silicon substrate
A p-type and an n-type SOI substrate are provided.
A part of the first metal is in contact with the sides of both SOI substrates between the plates.
A source drain region is provided, and a first metal source
Opposite sides of both SOI substrates in contact with the rain region
Second and third metal source drains partially contacting the side surface
An area is provided. In addition, the first and second
N-type SOI substrate at contact portion of metal source / drain region
P apart from each other⁺ Type source / drain region
And each p ⁺ P-type in contact with the source / drain region
A source / drain region is provided, while opposing first and
And p-type S at the contact portion of the third metal source / drain region
N apart from each other on the OI substrate⁺ Type source / drain region
Provided, each n⁺ Type source / drain region
And an n-type source / drain region is provided. Moreover
The top surface of the SOI substrate and the opposing metal source
Gate oxide (SiO_Two/ Ta_TwoO_Five )But
A barrier metal is provided on the opening inside the gate oxide film.
Gate electrode (Al) is buried flat through (TiN)
-Channel and p-channel formed in different structures
MIS field-effect transistor with LDD structure is formed
ing. In addition, each metal source drain region and both gates
Barrier metal (Ti / TiN) and plug (W) for electrodes
AlCu with barrier metal (Ti / TiN) above and below
The wiring is connected to the second metal source / drain region.
A power supply voltage is applied to the third metal source / drain region.
Is applied with the ground voltage, and the input voltage is imprinted on the gate electrode.
From the first metal source / drain region.
Common metal source between different channels extracting force voltage
Comprises SOI C-MOS inverter with drain structure
Have been. (What is the metal source drain region of the present invention?
Unlike normal metal source / drain regions, impurity regions
This is a region where only the metal film or the alloy film does not include the region. Therefore, conventionally, an element isolation region or impurity
Well trench isolation and buried oxide film
N separated and formed as separate regions⁺ Mold drain
Region and p⁺ Type drain region
Low resistance conductive film (metal film or alloy film)
Formable, all elements are self-contained on both SOI substrates
Both aligned SOI groups and fully depleted SOI groups
N-channel and P-channel MIS field effect on the plate respectively
As a result, transistors can be formed.
Extremely high integration because it can be configured without contact area
It is possible to form a simple C-MOS inverter. Also both S
The OI substrate has a channel region and a low-concentration source / drain region.
Area and very small high-concentration source / drain regions.
Form most source / drain regions with impurity regions
Without conductive film (metal film or alloy film)
Reduction of combined capacitance (almost zero) and reduction of source / drain regions
Ta that has low dielectric constant and high dielectric constant_TwoO_Five 
Because the film can be used as a gate oxide,
Thickness can be increased, and a minute gap between the gate electrode and the SOI substrate can be obtained.
It is possible to improve current leakage and reduce gate capacitance.
And sources that require high-temperature heat treatment to activate impurity regions
Self-align the drain region before forming the gate electrode
Formable from low-resistance low melting point metal (Al)
Gate electrode can be formed, so that the gate electrode wiring is low.
Resistance can be used, gate on thin SOI substrate
Because the structure is formed, the SOI substrate can be completely depleted
Depletion between the inversion layer under the gate oxide and the substrate
It is possible to eliminate the layer capacitance and add it to the gate electrode.
Voltage can be applied only between the gate electrode and the inversion layer
The sub-threshold characteristics can be improved,
High speed and high reliability C
A MOS inverter can be formed. That is, extremely
High speed, low power, high reliability, high performance and highly integrated semiconductor integration
Common metal source between different channels to enable circuit formation
Obtaining SOI type C-MOS semiconductor device having drain structure
be able to.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic plan view of the first embodiment of the semiconductor device of the present invention, and FIG. FIG. 4 is a schematic side sectional view of a semiconductor device according to a third embodiment of the present invention, and FIG.
Is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention, FIG. 6 is a schematic side sectional view of a fifth embodiment of the semiconductor device of the present invention, and FIG. 8 to 14 are process cross-sectional views of one embodiment of a method of manufacturing a semiconductor device according to the present invention. The same objects are denoted by the same reference numerals throughout the drawings. 1 and 2 are a schematic side sectional view and a schematic plan view of a first embodiment of a semiconductor device according to the present invention, and show a short channel N of an SOI structure formed using a bonded SOI wafer.
1 shows a part of a semiconductor integrated circuit including a C-MOS inverter including a channel and a P-channel MIS field-effect transistor, wherein 1 is a p ^- type silicon (Si) substrate of about 10 ¹⁵ cm ^-3 and 2 is A bonding oxide film (SiO ₂ ) having a thickness of about 0.5 μm, a p-type SOI substrate having a thickness of about 0.1 μm,
4 is an n-type SOI substrate having a thickness of about 0.1 μm; 5 is a trench for forming an isolation region and a buried oxide film (SiO ₂ );
Is 10 ¹⁷ cm ^-3 of about n-type source drain region, 7 10 ¹⁷ cm
P-type source and drain regions of about ^-3, 8 10 ²⁰ cm ^-3 of about n ⁺ -type source and drain regions, 9 10 ²⁰ cm ^-3 of about p ⁺ -type source and drain regions, 10a, 10b, 10c has a thickness A metal source / drain region (W) of about 0.3 μm, 11 is a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) of about 15 nm, 12 is a barrier metal (TiN) of about 20 nm, and 13 is a gate having a gate length of about 0.2 μm. Electrode (Al), 14 is a phosphosilicate glass (PSG) film of about 0.8 μm, 1
5 is a barrier metal (Ti / TiN) of about 50 nm, 16 is a plug (W), 17 is a barrier metal (Ti / TiN) of about 50 nm, 18
Indicates an AlCu wiring of about 0.8 μm, and 19 indicates a barrier metal (Ti / TiN) of about 50 nm. In FIG. 1, a p-type SOI substrate 3 and an n-type SOI substrate 4 are selectively provided on an oxide film 2 provided on a p ⁻ -type silicon substrate 1. A first metal source / drain region 10a is provided between the n-type SOI substrate 4 so as to be partially in contact with the side surfaces of the p-type SOI substrate 3 and the n-type SOI substrate 4, and the first metal source / drain region 10a is provided in the first metal source / drain region 10a. Touching p
A second metal source / drain region 10b and a third metal source / drain region 10c are provided partially in contact with the respective opposite side surfaces of the SOI substrate 3 and the n-type SOI substrate 4. Also, a p-type SOI at a contact portion between the opposing first and third metal source / drain regions (10a, 10c).
An n ⁺ -type source / drain region 8 is provided on the substrate 3 so as to be separated from each other, and an n-type source / drain region 6 is provided in contact with the respective n ⁺ -type source / drain regions 8, while the first and second opposing first and second regions are provided. Metal source drain region (10a, 10
b) The n-type SOI substrate 4 at the contact portion of FIG.
⁺ Type source / drain regions 9 are provided, and each p ⁺
A p-type source / drain region 7 is provided in contact with the type source / drain region 9. Further, a gate oxide film (SiO ₂ / Ta) is formed on the upper surface of the p-type SOI substrate 3 and the n-type SOI substrate 4 and on the side surfaces between the metal source / drain regions (10a, 10b, 10c).
₂ O ₅ ) 11 are provided, and a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 11
N-channel and P-channel LDD structures are formed in a structure in which a gate electrode (Al) 13 is buried flat in a hole inside the substrate via a barrier metal (TiN) 12.
An S field effect transistor is formed. The second metal source / drain region 10b has a barrier metal (Ti /
A power supply voltage (Vdd) is applied through an AlCu wiring 18 having barrier metals (Ti / TiN) (17, 19) above and below via a TiN) 15 and a plug (W) 16 to form a third metal source / drain region 10c. Through a barrier metal (Ti / TiN) 15 and a plug (W) 16 through a barrier metal (Ti / TiN)
) (17, 19), the ground voltage (V
ss) is applied, and a barrier metal (Ti / TiN) 15 is applied to the gate electrodes 13 of the connected N-channel MIS field-effect transistor and P-channel MIS field-effect transistor.
Via a plug (W) 16 and a barrier metal (Ti
/ TiN) (17, 19), is connected to the AlCu wiring 18 and an input voltage (Vin) is applied. The first metal source / drain region 10a has a barrier metal (Ti / TiN) 15 and a plug (W). ) 16 through the barrier metal (Ti /
An SOI type C-MOS inverter having a common metal source / drain structure between different channels, which is connected to an AlCu wiring 18 having TiN) (17, 19) and takes out an output voltage (Vout), is formed. The p-type SOI substrate 3 and n
No voltage is applied to the SOI substrate 4 of the type. Therefore, conventionally, the n ⁺ -type drain region and the p ⁺ -type drain region which are separated by a trench for forming an element isolation region or for separating an impurity well region and a buried oxide film and formed as separate regions are used as a common drain region. That it can be formed by a low-resistance metal film or alloy film, that all elements can be self-aligned on p-type and n-type SOI substrates, and that fully depleted p-type and n-type SOI
Since an N-channel MIS field-effect transistor and a P-channel MIS field-effect transistor can be formed on the substrate, respectively, the structure can be made without providing a contact region to the p-type and n-type SOI substrates.
An OS inverter can be formed. On the p-type and n-type SOI substrates, only a channel region, a low-concentration source / drain region and an extremely minute high-concentration source / drain region are formed. Since it can be formed of an alloy film, the junction capacitance can be reduced (almost zero) and the resistance of the source / drain region can be reduced. Since a Ta ₂ O ₅ film having a high dielectric constant can be used as a gate oxide film, the gate oxide film can be formed. The film can be made thicker, small current leakage between the gate electrode and the SOI substrate can be improved, and gate capacitance can be reduced. The source / drain region, which requires a high-temperature heat treatment to activate the impurity region, is gated. Since the gate electrode can be formed by self-alignment before the electrode is formed, a gate electrode made of a low-resistance low-melting-point metal (Al) can be formed. What is possible is that the SOI substrate can be completely depleted because the gate structure is formed on a thin SOI substrate, so that the depletion layer capacitance between the inversion layer below the gate oxide film and the substrate can be eliminated. It is possible, and the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer,
Since the sub-threshold characteristic can be improved, a C-MOS inverter having both extremely high speed and high reliability can be obtained because the threshold voltage can be reduced.

FIG. 3 is a schematic side sectional view of a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 1, an N-channel MIS and a P-channel MIS of a short channel having an SOI structure formed using a bonded SOI wafer. 1 shows a part of a semiconductor integrated circuit including a C-MOS inverter composed of a field effect transistor, and 1 to 6 and 8 to 19 show the same thing as FIG. In FIG.
In the S field effect transistor, a C-MOS inverter having the same structure as that of FIG. 1 is formed except that the p-type source / drain region 7 is not provided and the LDD structure is not formed. In this embodiment, the same effect as in the first embodiment can be obtained. In the P-channel MIS field-effect transistor, a structure in which a low-concentration source / drain region is not provided to avoid a hot carrier effect is provided. Since the diffusion in the horizontal direction can be suppressed, a higher speed due to further miniaturization can be expected.

FIG. 4 is a schematic side sectional view of a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 1, an N-channel MIS and a P-channel MIS of a short channel having an SOI structure formed using a bonded SOI wafer. 1 shows a part of a semiconductor integrated circuit including a C-MOS inverter composed of a field effect transistor, and 1 to 5 and 8 to 19 show the same thing as FIG. In the figure, N channel and P
In the channel MIS field-effect transistor, the C-MOS inverter having the same structure as that of FIG. 1 except that the n-type source / drain region 6 and the p-type source / drain region 7 are not provided and the LDD structure is not formed, respectively. Is formed. The present embodiment is suitable for a semiconductor integrated circuit that can operate at an extremely low power supply without having to consider the hot carrier effect. The same effect as that of the first embodiment can be obtained. Since it is formed in a structure without a drain region, diffusion in the horizontal direction can be suppressed, so that further miniaturization and higher speed due to lower resistance of the source / drain region can be expected.

FIG. 5 is a schematic side sectional view of a semiconductor device according to a fourth embodiment of the present invention. As shown in FIG. 1, N-channel and P-channel MISs of a short channel having an SOI structure formed using a bonded SOI wafer. 1 shows a part of a semiconductor integrated circuit including a C-MOS inverter composed of a field effect transistor, and 1 to 19 show the same parts as those in FIG. In the figure, the metal source regions (10b, 10b
c) Immediately below, a p-type SOI substrate 3 and an n-type SOI substrate 4 having an n ⁺ -type source region 8 and a p ⁺ -type source region 9 are provided. MO
An S inverter is formed. Also in this embodiment,
Almost the same effects as in the first embodiment can be obtained except that the resistance of the source region slightly increases.

FIG. 6 is a schematic side sectional view of a fifth embodiment of the semiconductor device according to the present invention. The short channel N-channel and P-channel MIS of the SOI structure formed using a bonded SOI wafer as in FIG. 1 to 19 show a part of a semiconductor integrated circuit including a C-MOS inverter composed of a field-effect transistor.
Reference numeral 20 denotes a buried sidewall (SiO ₂ ). In the figure, the opposite metal source / drain regions (10
a, 10b) and opposing metal source / drain regions (10a,
10c), buried sidewalls (SiO ₂ ) 20 are provided on the n-type SOI substrate 4 and the p-type SOI substrate 3 at equal intervals on the n-type SOI substrate 4 and between the buried sidewalls (SiO ₂ ) 20. Electrode (Al) 13 having a barrier metal (TiN) 12 through a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 11
Except that the C-MOS inverter is buried flat. In this embodiment, the same effects as those of the first embodiment can be obtained.
Although the number of manufacturing steps increases, the ability to form low-concentration source / drain regions that do not rely on lateral diffusion, the ability to increase the breakdown voltage at the corners of the gate oxide film, and the ability to reduce the capacitance between the gate electrode and the metal source / drain regions Thereby, higher speed and higher reliability can be expected.

FIG. 7 is a schematic side sectional view of a semiconductor device according to a sixth embodiment of the present invention. As shown in FIG. 1, an N-channel and a P-channel MIS of a short channel having an SOI structure formed using a bonded SOI wafer. 1 shows a part of a semiconductor integrated circuit including a C-MOS inverter composed of a field effect transistor, 1 to 11, 14 to 19 are the same as those in FIG. 1, 21 is a gate electrode (polySi / W), and 22 is A base oxide film 23 indicates a sidewall (SiO ₂ ). In the figure, a normal gate electrode 20 having a sidewall 22 is formed, and metal source / drain regions (10a, 10b,
A C-MOS inverter having the same structure as that of FIG. 1 is formed except that 10c) is buried in the same thickness as the p-type SOI substrate 3 and the n-type SOI substrate 4. In the present embodiment, although the resistance of the gate electrode increases, a manufacturing method in which a step of forming a metal source / drain region is added to the normal manufacturing process can be employed, and substantially the same effects as in the first embodiment can be obtained. be able to.

Next, a method of manufacturing a semiconductor device according to the present invention.
One embodiment will be described with reference to FIGS. 8 to 14 and FIG.
I will tell. However, here, in forming the semiconductor device of the present invention,
Only the manufacturing method related to semiconductor integrated circuits.
Various mounted elements (other transistors, resistors, capacitors
Etc.) are not described. Fig. 8 p^- The first silicon substrate 1 of the mold is formed by chemical vapor deposition.
Oxide film (SiO_Two2.) grow 2. Next
Come p^- Oxide film of about 20 nm on the second silicon substrate 3
Grow (not shown). Then ion implant hydrogen
Then, an H buried layer (not shown) is formed. Then p^- 
H buried layer was formed on the first silicon substrate 1 of the mold
P down^- The second silicon substrate 3 of
H-fill by annealing at about 000 ° C
Of the thin layer separated by foaming H^- The second part of the mold
Recon board 3^- On the first silicon substrate 1 of the mold
Match. Then, the irregular p^- The second silico of the mold
Mechanical polishing of the surface of the substrate 3Cchemical
MtechnicalPafter the CM
P), and a flat p with a thickness of about 0.1 μm.^- Type
Of the second silicon substrate 3 (p-type SOI substrate)
You. (Using SOI wafers manufactured by crystal manufacturers
You may. Fig. 9 Next, using ordinary photolithography technology,
The SOI substrate 3 is selected by using a mask (not shown) as a mask layer.
Selectively anisotropically dry-etch and position for alignment
To form Next, the resist (not shown) is removed.
You. Next, an oxide film (Si) of about 5 nm is formed on the p-type SOI substrate 3.
O_TwoA) grow 24. Then normal photolithography
Using a resist (not shown) as a mask layer
And selectively ion-implanting phosphorus to form a p-type SOI
A part of the substrate 3 is changed to an n-type SOI substrate 4. Then
The dist (not shown) is removed. Next, about 0.2 μm
Nitride film (Si_ThreeN_Four A) grow 25. Then the normal photo library
Using a lithography technique, a resist (not shown) is opened.
Holes and nitride film using resist (not shown) as mask layer
25, oxide film 24, p-type and n-type SOI substrates (3, 4)
Selective etching to form trenches 5 for forming element isolation regions
To form Next, the resist (not shown) is removed.
Next, a chemical vapor deposition oxide film (SiO_TwoGrow anisotropic
Line etching is performed to form trenches 5 for forming element isolation regions.
Embed. Fig. 10 Next, using ordinary photolithography technology,
Element (not shown) and element isolation region with embedded oxide film
Using the region forming trench 5 as a mask layer, a nitride film is selectively formed.
25 is subjected to anisotropic dry etching. Then resist (Figure
(Not shown). Then normal photolithography
Using technology to open holes only on the p-type SOI substrate 3
Using a resist (not shown) and the nitride film 25 as a mask layer,
Phosphorus ions are implanted into the p-type SOI substrate 3. Then cash register
The strike (not shown) is removed. Then normal photolithography
Utilizing only the n-type SOI substrate 4
Opening resist (not shown) and nitride film 24 as mask layer
Then, boron is ion-implanted into the n-type SOI substrate 4.
Next, the resist (not shown) is removed. Then 950
N around ° C_TwoLateral diffusion by annealing
The n-type source / drain region 6 and the p-type source
Formation region 7 is formed. Then normal photolithography
Using technology to open holes only on the p-type SOI substrate 3
Using a resist (not shown) and the nitride film 25 as a mask layer,
Arsenic is ion-implanted into the p-type SOI substrate 3. Then
The dist (not shown) is removed. Then the normal photo library
Using lithography technology, only on n-type SOI substrate 4
(Not shown) for opening holes and masking nitride film 25
As a layer, boron is ion-implanted into the n-type SOI substrate 4.
You. Next, the resist (not shown) is removed. Then 9
N of about 00 ° C_TwoBy adding annealing, some
N including lateral diffusion⁺ Type source drain region 8 and p⁺ 
Form source / drain regions 9 are formed. FIG. 11 Then n⁺ Type source drain region 8 and p⁺ Type sauced
Etching removal of extremely thin oxide film 24 on rain region 9
I do. Next, the element having the nitride film 24 and the oxide film embedded therein is
Using the trench 5 for forming the isolated region as a mask layer,
Lateral diffusion into lower p-type and n-type SOI substrates (3, 4)
N⁺ Type source drain region 8 and p ⁺ Type sauce drain
Excluding the in-region 9, n⁺ Type source drain region 8 and p
⁺ P-type and p-type regions where most of the source / drain regions 9 are formed.
And n-type SOI substrates (3, 4) are selectively etched away.
Then, a trench is formed in the source / drain region. Next
Grows tungsten film (W) by chemical vapor deposition
And then anisotropically dry-etch the tongue into the trench
Embedding a ten film (W), metal source drain region
(W) (10a, 10b, 10c) is formed. Fig. 12 Next, using ordinary photolithography technology,
Strike (not shown) and metal source / drain region
(W) An oxide film is buried using (10a, 10b, 10c) as a mask layer.
Oxidation of a part of the embedded trench 5 for forming an element isolation region
Film (the part of the gate electrode that is adjacent to the remaining nitride film 25)
Only the part that will be the contact part) is etched by about 0.2 μm
I do. Continuously, the remaining nitride film 25 and thin oxide film 24 are removed.
Etching to form trenches for gate electrodes
You. Next, the resist (not shown) is removed. FIG. 13 Next, the gate oxide film 11 (SiO_Two/ Ta_TwoO_Five )
Continue to grow. Next, a barrier metal (TiN) 12 of about 20 nm
And Al13 to be a gate electrode of about 0.2 μm
Grow by Next, chemical mechanical polishing (CMP)
More buried in the trench for the gate electrode, the gate oxide film
11 (SiO_Two/ Ta_TwoO_Five ), Barrier metal (TiN) 12 and game
Buried gate electrode structure composed of gate electrode (Al) 13
I do. In this case, the gate electrode (Al) 13 and barrier metal
(TiN) 12 and gate oxide film 11 (SiO_Two/ Ta_TwoO_Five ) Also excluded
Left. Figure 14 Next, by chemical vapor deposition, phosphoric acid silicate glass
(PSG) film 14 is grown. Then normal photolithography
Masks resist (not shown) using luffy technology
As a layer, the PSG film 14 is selected by anisotropic dry etching.
Alternatively, a contact hole is opened. Then to spatter
Then, Ti and TiN 15 serving as barrier metals are sequentially grown.
Next, W is applied to the entire surface by a blanket method of chemical vapor deposition.
Growing, anisotropic dry etching and buried plug
(W) 16 is formed. Figure 1 Next, Ti and TiN 17 that become barrier metal by sputtering
Grow sequentially. Next, by sputtering, Al
(Including several% of Cu) is grown to about 0.8 μm. Then
Using usual photolithography technology, resist (Fig.
(Not shown) as a mask layer, Al (including several percent of Cu) and
Anisotropic dry etching of barrier metal (Ti / TiN)
Forming an AlCu wiring 18 by using a C-MO having a highly integrated SOI structure.
Complete the S inverter. In the above manufacturing method
Is anisotropic dry etching in some processes.
Buried layer is formed.
It can be done by chemical mechanical polishing (CMP)
Absent.

[0013]

As described above, according to the semiconductor device of the present invention, a pair of p-type and n-type semiconductor layers which are bonded on a semiconductor substrate via an insulating film, are thinned, and are insulated and isolated in an island shape. Three metal source / drain regions are provided so as to be partially in contact with the respective side surfaces of the type SOI substrate, and a pair of n ⁺ type source / drain regions are provided on the p-type SOI substrate at a contact portion with each metal source / drain region. And an n-type source / drain region, and a pair of p-type
^{A +} -type source / drain region and a p-type source / drain region are provided, and a gate oxide film is provided on both SOI substrates and on side surfaces between the metal source / drain regions facing each other, and a barrier metal (TiN) is provided via the gate oxide film. A power supply voltage is applied to the second metal source / drain region, a ground voltage is applied to the third metal source / drain region, and an input voltage is applied to the gate electrode. An SOI type C-MOS inverter having a common metal source / drain structure between different channels, which takes out an output voltage from the region, is configured. Therefore, in the SOI structure, the resistance of the source / drain region is reduced and the junction capacitance is reduced by the formation of the metal source / drain region, the resistance of the gate electrode wiring is reduced by the formation of a low-resistance low melting point metal (Al) gate electrode, and the dielectric constant is increased. Electrode and SOI using Ta ₂ O ₅ gate oxide film
Improvement of minute current leakage between substrates and reduction of gate capacitance, elimination of depletion layer capacitance by using a fully depleted SOI substrate and reduction of threshold voltage by improvement of sub-threshold characteristics, MIS field effect of N-channel and P-channel Fine formation of a common source / drain region between transistors by a metal film or an alloy film and fine formation by self-alignment of each element can be performed. That is, it is possible to obtain an SOI type C-MOS semiconductor device having a common metal source / drain structure between different channels, which enables formation of a semiconductor integrated circuit with extremely high speed, low power, high reliability, high performance and high integration.

[Brief description of the drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic plan view of a first embodiment of the semiconductor device of the present invention.

FIG. 3 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a schematic side sectional view of a third embodiment of the semiconductor device according to the present invention;

FIG. 5 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention.

FIG. 6 is a schematic side sectional view of a fifth embodiment of the semiconductor device of the present invention.

FIG. 7 is a schematic side sectional view of a sixth embodiment of the semiconductor device according to the present invention;

FIG. 8 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a schematic side sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 p ^- type silicon (Si) substrate 2 bonding oxide film (SiO ₂ ) 3 p-type SOI substrate 4 n-type SOI substrate 5 trench for forming element isolation region and buried oxide film (SiO ₂ ) 6 n-type Source / drain region 7 p-type source / drain region 8 n ⁺ -type source / drain region 9 p ⁺ -type source / drain region 10a first metal source / drain region (W) 10b second metal source / drain region (W) 10c third metal Source / drain region (W) 11 Gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 12 Barrier metal (TiN) 13 Gate electrode (Al) 14 Phosphosilicate glass (PSG) film 15 Barrier metal (Ti / TiN) 16 Plug ( W) 17 Barrier metal (Ti / TiN) 18 AlCu wiring 19 Barrier metal (Ti / TiN) 20 Buried sidewall (SiO ₂ ) 21 Gate electrode (polySi / W) 22 Base oxide film 23 Side wall (SiO ₂ ) 24 Oxidation film( SiO ₂ ) 25 nitride film (Si ₃ N ₄ )

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/08 331 H01L 29/78 613A 21/336 616A F term (Reference) 4M104 AA09 BB18 BB30 CC01 CC05 DD08 DD19 DD37 DD43 DD66 FF04 FF17 FF18 GG09 GG10 GG14 5F048 AA01 AA07 AC04 BA16 BB04 BB05 BB09 BB11 BB12 BC01 BC06 BF02 BF07 BG01 BG05 BG14 DA19 DA25 5F110 AA01 AA04 AA09 BB04 CC02 DD05 DD13 EE01 GG03 EE01 GG01 HK34 HL01 HL04 HL11 HL23 HM02 HM15 HM17 HM19 NN04 NN25 NN35 NN62 NN65 QQ10 QQ11 QQ17 QQ19

Claims (3)

[Claims] A semiconductor substrate; an insulating film provided on the semiconductor substrate; a one conductivity type and an opposite conductivity type SOI substrate selectively provided on the insulating film; A gate insulating film provided on a conductive type SOI substrate; a gate electrode provided on the gate insulating film; and the one conductive type and the opposite conductive type between the one conductive type and the opposite conductive type SOI substrate. A first metal source / drain region provided partially in contact with a side surface of the SOI substrate;
A second and a third metal source / drain region provided partially in contact with opposite side surfaces of the one conductivity type and the opposite conductivity type SOI substrate in contact with the metal source / drain region; Opposite conductivity type impurity regions (source / drain regions) provided separately from each other on the one conductivity type SOI substrate at the contact portions of the first and second metal source / drain regions, and the first and third opposing regions. The opposite conductivity type SO at the contact portion of the metal source / drain region
A semiconductor device, comprising: an I-substrate; and a one-conductivity-type impurity region (source / drain region) provided separately from each other. 2. The semiconductor device according to claim 1, wherein said one conductivity type impurity region and said opposite conductivity type impurity region comprise high-concentration and low-concentration source / drain regions, respectively. A power supply voltage applied to the second metal source / drain region; a ground voltage applied to the third metal source / drain region; an input voltage applied to the gate electrode; 2. An output voltage obtained from a source / drain region.
And a semiconductor device according to claim 2.