JP2001250951A - Gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate array having a basic cell with a highly integrated highspeed SOI structure. SOLUTION: This gate array has a basic cell composed of C-MOS including the following structure. P-type and n-type SOI substrates (3, 4) are selectively provided on a semiconductor substrate 1 via an oxide film 2. Metal source/drain regions (10a, 10b, 10c) are provided on both sides of the SOI substrates so that parts thereof are brought into contact with side surfaces of the SOI substrates. High-concentration and low-concentration source/drain regions (6, 7, 8, 9) composed of impurities each having a conductive type opposite to that of each SOI substrate are provided on contact portions of the SOI substrates. Gate oxide films are provided on the upper surfaces of the SOI substrates and side surfaces of the metal source/drain regions brought into contact with the SOI substrates. N-type and p-type MIS field effect transistors with a structure wherein a gate electrode is buried in a hole inside the gate oxide film via a barrier metal are formed. Furthermore, source/drain regions of the adjacent n-type and p-type MIS field effect transistors are formed as common metal source/drain region 10a between different channels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an SOI structure, and more particularly to a short-channel complementary MIS having a high-speed, low-power, high-reliability, high-performance and highly integrated SOI structure.
The present invention relates to a gate array having a basic cell composed of a field effect transistor (hereinafter abbreviated as C-MOS). Conventionally,
In a C-MOS gate array having a basic cell including two pairs of N-channel and P-channel MIS field-effect transistors, the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are completely insulated and separated. Formed on each substrate (actually, one is formed in the impurity well region of the same conductivity type as the semiconductor substrate formed on the semiconductor substrate, and the other is formed in the impurity well region of the opposite conductivity type to the semiconductor substrate formed on the semiconductor substrate) Therefore, a relatively large space is required at the boundary between the N-channel and P-channel MIS field-effect transistors, and each element is miniaturized to form a basic cell in which a substrate contact region is formed on each substrate. For the most part, it was not possible to highly integrate the basic cells. or,
Since the resistance and capacitance of the gate electrode and the source / drain region constituting the N-channel and P-channel MIS field-effect transistors could not be reduced, the problem that the speed could not be increased in spite of the short channel was becoming remarkable. I have. Therefore, a C-MOS type having a basic cell which can be further miniaturized as well as an element, does not require a substrate contact region, can reduce the resistance and capacitance of each element, and can achieve higher speed. There is a need for a means that can form a gate array.

[0002]

14 to 16 show an embodiment of a conventional gate array. FIG. 14 is a schematic plan view of a basic cell.
5 is a schematic plan view of one wiring pattern (two-input NAND gate), and FIG. 16 is a schematic side sectional view (sectional view taken along the line PP in FIG. 15), which is formed on a p ^- type silicon (Si) substrate. 3 shows a part of a C-MOS gate array composed of short-channel N-channel and P-channel MIS field-effect transistors, 51 is a p ^- type silicon substrate, 52 is a trench for forming an isolation region and a buried oxide. Film, 53 is a p-type impurity well region, 54 is a p ⁺ -type impurity well contact region, 55 is an n-type source / drain region, 56 is an n ⁺ -type source / drain region, 57 is a gate oxide film (SiO ₂ ), 58 is a gate Electrode (polySi / W), 59 is a base oxide film, 60 is a sidewall, 61 is an oxide film for impurity blocking, 62 is a phosphosilicate glass (PSG) film, 63 is a barrier metal (Ti / TiN), and 64 is a plug ( W), 65 are barrier metals (Ti / TiN) ), 66 is AlCu
Reference numeral 67 denotes a barrier metal (Ti / TiN), 68 denotes a contact hole (including a formable region), 69 denotes an n ⁺ -type impurity well contact region, and 70 denotes a p ⁺ -type source / drain region. In FIG. 14, basic cell 1 of the gate array
(The dashed line indicates the area occupied by one basic cell, and no wiring is formed).
Channel MIS field-effect transistor
One P-channel MIS field-effect transistor is formed, a gate electrode 58 of the pair of N-channel and P-channel MIS field-effect transistors is connected by a gate electrode wiring, a contact hole 68 indicates a formable region, The regions (56, 70) are all n ⁺ type and p
⁺ -Type is formed by impurity, the N-channel MI
A p ⁺ -type impurity well contact region 54 is formed in the S field-effect transistor, and an n ⁺ -type impurity well contact region 69 is formed in the P-channel MIS field-effect transistor. In an actual gate array, the basic cells are formed in a matrix. In FIG. 15, FIG.
2 shows a wiring pattern diagram of a two-input NAND gate using one basic cell. The output unit connects the n ⁺ type source / drain region 56 and the p ⁺ type source / drain region 70.
It is taken out by the lCu wiring 66. FIG. 16 shows a cross-sectional view taken along the line PP of FIG. 15 (direction along the VSS line). In the figure, a p ^- type silicon well 51 is provided with a p-type impurity well region 53, and a p-type impurity well region 53 is formed in an element formation region insulated and separated by a trench 52 for forming an element separation region in which an oxide film is buried. An n-type source / drain region 55 self-aligned with the gate electrode 58, an n ⁺ -type source / drain region 56 self-aligned with the sidewall 60, and a p ⁺ -type impurity well contact region 54 L
An MIS field effect transistor having a DD structure is formed. Here, since a side sectional view taken along the VSS line is shown, a MIS field-effect transistor having a P-channel LDD structure is not shown. The p ⁺ -type impurity well contact region 54 is connected to an AlCu wiring 66 having upper and lower barrier metals (65, 67) via a barrier metal (Ti / TiN) 63 and a plug (W) 64 to form a p-type impurity well region. The ground voltage is applied to 53. Therefore, a relatively large space is required at the boundary between the N-channel and P-channel MIS field-effect transistors (two channels are used for connecting the gate electrodes, but two channels at both ends are sufficient). And the respective substrates (p
In order to constitute a basic cell in which a substrate contact region (p ⁺ -type impurity well contact region and n ⁺ -type impurity well contact region) is formed in the n-type impurity well region and the n-type impurity well region, each element is miniaturized. Has a disadvantage that the basic cells cannot be highly integrated. or,
Since the resistance and capacitance of the gate electrode and the source / drain region constituting the N-channel and P-channel MIS field-effect transistors could not be reduced, there was a drawback that high speed could not be achieved despite the short channel.

[0003]

The problem to be solved by the present invention is, as shown in the prior art, a C-type cell having a basic cell composed of N-channel and P-channel MIS field-effect transistors of conventional structure and configuration. In a MOS gate array, since the N-channel and P-channel MIS field-effect transistors must be completely separated, a relatively large space is required at the boundary between the N-channel and P-channel MIS field-effect transistors. And the basic cell having the respective substrate contact regions must be formed, so that further high integration other than miniaturization of each element could not be achieved. In addition, the N-channel and P-channel MIS The resistance and capacitance of the gate electrode and the source / drain region of the field effect transistor Because it could not reduction of, the split that short channel of is that the speed could not be achieved.

[0004]

The object of the present invention is to provide a semiconductor substrate, one-conductivity-type and opposite-conductivity-type SOI substrates selectively provided on a semiconductor substrate via an insulating film, and provided on the SOI substrate. A gate insulating film, a gate electrode provided on the gate insulating film, a metal source / drain region which is self-aligned with the SOI substrate and is provided partially in contact with a side surface of the SOI substrate; One-conductivity-type and opposite-conductivity-type MIS field effect composed of the SOI substrate and the impurity region (source / drain region) of the opposite conductivity type provided separately from each other on the SOI substrate at the contact portion with the source / drain region. The metal source / drain region of the adjacent one-conductivity-type and opposite-conductivity-type MIS field-effect transistor comprising a transistor, wherein the one-conductivity-type and the opposite-conductivity-type Array according to the present invention in which basic cells comprising the MIS field-effect transistors of the one conductivity type and the opposite conductivity type having a structure formed as a common metal source / drain region in contact with both of the impurity regions of the type are arranged in a matrix. A solution is possible.

[0005]

[Operation] That is, in the gate array of the present invention,
Two p-type SOI substrates and two n-type SOI substrates are selectively formed on oxide film 2 provided on p ^- type silicon substrate 1.
A substrate is provided, and a part of the SOI substrate is provided on both sides of the SOI substrate.
A metal source / drain region is provided in contact with the side surface of the substrate, and the p-type SOI substrate at the contact portion is separated from each other by n
⁺ -Type source and drain regions and in contact with the respective n ⁺ -type source and drain region is provided an n-type source drain region separated from each other, whereas the n-type SOI substrate of the contact portion spaced from each other p ⁺ -type source and drain regions And p-type source / drain regions which are in contact with and are separated from each other by p ⁺ -type source / drain regions. Also, p-type and n
A gate oxide film provided on the upper surface of the SOI substrate of the mold type and on the side surface of the metal source / drain region in contact with each SOI substrate;
MI of a pair of N-channel and P-channel LDD structures formed in a structure in which a gate electrode is buried flat in a hole inside a gate oxide film via a barrier metal.
An S field effect transistor is formed. Here, the metal source / drain region between the p-type SOI substrate and the n-type SOI substrate becomes a common metal source / drain region between different channels in contact with both the n ⁺ -type source drain region and the p ⁺ -type source / drain region. And also p-type and n
The SOI substrate of the type is completely depleted, and a gate array having a basic cell in which a voltage application region to the SOI substrate is not formed is formed. (The metal source / drain region of the present invention is different from a normal metal source / drain region and is a region of only a metal film or an alloy film which does not include an impurity region.) Therefore, conventionally, an element isolation region or an impurity well region is formed. Basically, it can be formed by a metal film or an alloy film in which an n ⁺ -type source drain region and a p ⁺ -type source / drain region separated by an isolation trench and a buried oxide film and formed as separate regions have a common source / drain region. All elements constituting the cell can be self-aligned on the p-type and n-type SOI substrates, and the fully depleted p-type and n-type SOI substrates have N
Since a channel MIS field-effect transistor and a P-channel MIS field-effect transistor can be formed, they can be configured without providing a contact region with a p-type or n-type SOI substrate, so that high integration of a basic cell can be achieved. or,
On the p-type and n-type SOI substrates, only a channel region, a low-concentration source / drain region and an extremely minute high-concentration source / drain region are formed. Alternatively, the gate capacitance can be reduced (almost zero) and the resistance of the source / drain region can be reduced because a Ta ₂ O ₅ film having a high dielectric constant can be used as a gate oxide film. The oxide film can be made thicker, and the gate electrode and SO
Improvement of minute current leakage between I-substrates and reduction of gate capacitance are also possible, and source-drain regions requiring high-temperature heat treatment for activation of impurity regions can be formed by self-alignment before forming gate electrodes. Since a gate electrode made of a low-resistance low-melting-point metal (Al) can be formed, the resistance of the gate electrode wiring can be reduced.
Since the gate structure is formed on the I-substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer below the gate oxide film and the substrate can be eliminated, and the gate electrode The applied voltage can be applied only between the gate electrode and the inversion layer, and the sub-threshold characteristic can be improved, so that the threshold voltage can be reduced. Thus, a basic cell having extremely high speed, low power, high performance and high reliability can be obtained. be able to. That is, it is possible to obtain a gate array capable of forming a large-scale semiconductor integrated circuit with extremely high speed, low power, high reliability, high performance, and high integration.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a schematic plan view of a basic cell of a first embodiment in a gate array of the present invention, FIG. 2 is a schematic plan view of one wiring pattern of the first embodiment in the gate array of the present invention, and FIG. FIG. 4 is a schematic side cross-sectional view of the first embodiment of the gate array (a cross-sectional view taken along the line P-P in FIG. 2), and FIG. 4 is a schematic plan view of a basic cell of the second embodiment in the gate array of the present invention. 5 is the second in the gate array of the present invention.
FIG. 6 is a schematic side sectional view of a second embodiment of the gate array of the present invention (cross-sectional view taken along the line P--P in FIG. 5), and FIGS. FIG. 6 is a process cross-sectional view of one embodiment of a method for manufacturing a gate array of the present invention. The same objects are denoted by the same reference numerals throughout the drawings. FIG.
3 to 3 show a first embodiment of the gate array of the present invention. FIG. 1 is a schematic plan view of a basic cell, FIG. 2 is a schematic plan view of one wiring pattern (two-input NAND gate), and FIG. FIG. 2 is a diagram (a cross-sectional view taken along the line PP in FIG. 2), showing a C-MOS gate array including short-channel N-channel and P-channel MIS field-effect transistors of an SOI structure formed using a bonded SOI wafer. 1 is a p ^- type silicon (Si) substrate, 2
Is a bonding oxide film (SiO ₂ ) having a thickness of about 0.5 μm, 3 is a p-type SOI substrate having a thickness of about 0.1 μm, 4 is an n-type SOI substrate having a thickness of about 0.1 μm, and 5 is an element isolation region. Trench and buried oxide film (SiO ₂ ), 6 is n of about 10 ¹⁷ cm ^-3
Type source drain region, is 10 ¹⁷ cm ^-3 of about p-type source drain regions 7, 8 10 ²⁰ cm ^-3 of about n ⁺ -type source and drain regions, the 10 ²⁰ cm ^-3 of about p ⁺ -type source and drain 9 Region, 10a is a common metal source / drain region (W) in contact with the n ⁺ -type and p ⁺ -type source / drain regions, 10b is a metal source / drain region (W) in contact with the p ⁺ -type source / drain region, and 10c is an n ⁺ -type source / drain Metal source drain region (W) in contact with the region, 11 is a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) of about 15 nm, 12 is a barrier metal (TiN) of about 20 nm, and 13 is a gate electrode having a gate length of about 0.2 μm (A
l), 14 is a phosphosilicate glass (PSG) film of about 0.8 μm, 15 is
Barrier metal (Ti / TiN) of about 50 nm, 16 is a plug (W), 17 is a barrier metal (Ti / TiN) of about 50 nm, 18
Is about 0.8μm AlCu wiring (including several% Cu), 19 is 50n
A barrier metal (Ti / TiN) 20 of about m indicates a contact hole (including a formable region). In FIG. 1, one basic cell of the gate array is shown (the dashed line indicates the area occupied by one basic cell, and no wiring is formed). Four MIS field-effect transistors are formed, the gate electrodes 13 are connected alternately, the contact holes 20 indicate a formable region, and metal source / drain regions (W) are formed on both sides of the gate electrode 13. The central metal source / drain region has a common metal source / drain region 10a in contact with the n ⁺ type and p ⁺ type source / drain regions. Further, a contact region to the SOI substrate is not formed. In this drawing, seven wiring channels can be formed. In an actual gate array, the basic cells are formed in a matrix. In FIG. 2, FIG.
2 shows a wiring pattern diagram of a two-input NAND gate using one basic cell. The output portion can be drawn out from only the common metal source / drain region 10a in contact with the n ⁺ type and p ⁺ type source / drain regions by one AlCu wiring 18,
It is formed with extremely high integration. In FIG. 3, FIG.
3 shows a cross-sectional view taken along the line PP of FIG. In this figure, p ^-
Two p-type SOI substrates 3 and two n-type SOI substrates 4 are selectively provided from the left side on an oxide film 2 provided on a silicon substrate 1 of a type, and a part is provided on both sides of each SOI substrate. Are provided in contact with the side surface of the SOI substrate, metal source / drain regions 10c, 10c, 10a, 10b, and 10b are provided in order from the left, and the p-type SOI substrate 3 of the contact portion is separated from each other by n
⁺ N-type source drain regions 6 spaced from each other in contact with a type source drain regions 8 and each of the n ⁺ -type source and drain region 8 is provided, whereas on the SOI substrate 4 n-type contact portions spaced from each other p ⁺ The p-type source / drain regions 9 are provided in contact with the p-type source / drain regions 9 and the respective p ⁺ -type source / drain regions 9 and separated from each other.
Further, a gate oxide film (SiO ₂ ) is formed on the upper surfaces of the p-type SOI substrate 3 and the n-type SOI substrate 4 and the side surfaces of the metal source / drain regions (10a, 10b, 10c) in contact with the respective SOI substrates (3, 4).
/ Ta ₂ O ₅ ) 11 is provided, and a gate electrode (Al) is formed in the opening inside the gate oxide film 11 via a barrier metal (TiN) 12.
Are formed in a structure in which the MIS field-effect transistor is formed into a structure in which the N-type and N-type LDD structures are formed so as to be buried flat. Here, the metal source / drain region 10a is composed of the n ⁺ type source / drain region 8 and p
A common metal source / drain region between different channels in contact with the ⁺ type source / drain region 9 and has a two-input NA
Becomes the output part of the ND gate, barrier metal (Ti / TiN)
It is led out by a single AlCu wiring 18 having barrier metals (Ti / TiN) 17 and 19 above and below via a plug 15 and a plug (W) 16. Note that the p-type SOI substrate 3 and the n-type SOI
I-substrate 4 is completely depleted, and no voltage is applied to the SOI substrate. Therefore, conventionally, the n ⁺ -type source / drain region and the p ⁺ -type source / drain region which are separated by the trench for forming the element isolation region or the impurity well region and the buried oxide film and formed as separate regions are shared by the common source / drain region. That it can be formed by a low-resistance metal film or alloy film as a region, that all elements constituting a basic cell can be formed in a self-aligned manner on p-type and n-type SOI substrates, and that fully depleted p-type and n-type SOI substrates To the N channel MI
Since an S field effect transistor and a P channel MIS field effect transistor can be formed, p-type and n-type SO
Since it can be configured without providing a contact region to the I substrate,
A gate array having extremely highly integrated basic cells can be formed. On the p-type and n-type SOI substrates, only a channel region, a low-concentration source / drain region and an extremely minute high-concentration source / drain region are formed. Since it can be formed of a metal film or an alloy film, the junction capacitance can be reduced (almost zero) and the resistance of the source / drain region can be reduced, and a Ta ₂ O ₅ film having a high dielectric constant can be used as a gate oxide film. A gate oxide film can be made thicker, a small current leak between the gate electrode and the SOI substrate can be improved, and a gate capacitance can be reduced. Since the region can be formed by self-alignment before the formation of the gate electrode, a gate electrode made of a low-resistance low-melting-point metal (Al) can be formed. Since the gate structure is formed on a thin SOI substrate, the SOI substrate can be completely depleted, and the depletion layer capacitance between the inversion layer below the gate oxide film and the substrate can be reduced. The voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, and the sub-threshold characteristics can be improved, so that the threshold voltage can be reduced. A gate array having basic cells having both properties can be obtained.

FIGS. 4 to 6 show a second embodiment of the gate array according to the present invention. FIG. 4 is a schematic plan view of a basic cell, and FIGS.
Is a schematic plan view of one wiring pattern (memory cell of a static ram), FIG. 6 is a schematic side sectional view (sectional view taken along the line PP in FIG. 5), and shows an SOI structure formed using a bonded SOI wafer. Composed of short-channel N-channel and P-channel MIS field-effect transistors
1 shows a part of a MOS gate array, and 1 to 20 denote the same elements as those in FIGS. In FIG. 4, one basic cell of the gate array having the same size as that of FIG. 1 is shown (the dashed line indicates the area occupied by one basic cell, and no wiring is formed). Four MIS field-effect transistors of PPN are formed, and adjacent N
The gate electrodes 13 of the channel and P channel MIS field-effect transistors are connected in a point-symmetrical manner, and two common metal source / drain regions 10a in contact with the n ⁺ -type and p ⁺ -type source / drain regions are formed. A basic cell. Also here, no contact region to the SOI substrate is formed. In FIG. 5, four elements (one N-channel and two P-channel MIS field effect transistors) for one basic cell of FIG. 4 and one N channel MIS field effect transistor of a vertically adjacent basic cell are used. FIG. 1 shows an example of a wiring pattern diagram of a memory cell of a static ram formed by using the method shown in FIG. 2
One common metal source / drain region 10a can be formed on the other gate electrode 13 by fine AlCu wiring 18. (Figure 1
Can be used, but it is advantageous in terms of wiring formation and effective use of the basic cells. FIG. 6 is a cross-sectional view taken along the line PP of FIG. In the figure, four of N-P-P-N are sequentially arranged from the left side.
The structure is the same as that of FIG. 3 except that two MIS field-effect transistors are formed, two common metal source / drain regions 10a exist between different channels, and the AlCu wiring 18 is different. In this embodiment, the same effects as in the first embodiment can be expected, and it is particularly suitable for a basic cell of a gate array having a built-in memory. In the present invention, a gate array using a basic cell to which a MIS field effect transistor having a buried gate structure which is extremely suitable for a short channel is described. However, a MIS field effect transistor having a gate electrode structure which forms a normal sidewall is used. A gate array using the applied basic cell may be formed, or a basic cell using three or more pairs of N-channel and P-channel MIS field-effect transistors may be formed. In addition, the gate electrodes of the N-channel and P-channel MIS field-effect transistors may form an unconnected basic cell. In short, the present invention can be realized if a C-MOS gate array using a basic cell forming a common metal source / drain region between different channels is formed.

Next, a method of manufacturing a gate array according to the present invention.
One embodiment of the method will be described with reference to FIGS.
explain. However, here, the shape of the gate array of the present invention is used.
Describe only the manufacturing method related to
And mounted on a general semiconductor integrated circuit.
Various elements (other transistors, resistors, capacitors, etc.)
The description of the manufacturing method relating to the formation of is omitted. Fig. 7 p^- The first silicon substrate 1 of the mold is formed by chemical vapor deposition.
Oxide film (SiO_Two2.) grow 2. Next
Come p^- Oxide film of about 20 nm on the second silicon substrate 3
Grow (not shown). Then ion implant hydrogen
Then, an H buried layer (not shown) is formed. Then p^- 
H buried layer was formed on the first silicon substrate 1 of the mold
P down^- The second silicon substrate 3 of
H-fill by annealing at about 000 ° C
Of the thin layer separated by foaming H^- The second part of the mold
Recon board 3^- On the first silicon substrate 1 of the mold
Match. Then, the irregular p^- The second silico of the mold
Mechanical polishing of the surface of the substrate 3Cchemical
MtechnicalPafter the CM
P), and a flat p with a thickness of about 0.1 μm.^- Type
Of the second silicon substrate 3 (p-type SOI substrate)
You. (Using SOI wafers manufactured by crystal manufacturers
You may. Fig. 8 Next, using ordinary photolithography technology,
The SOI substrate 3 is selected by using a mask (not shown) as a mask layer.
Selectively anisotropic dry etching, alignment pattern
To form Next, the resist (not shown) is removed.
Next, an oxide film (SiO 2) of about 5 nm is formed on the p-type SOI substrate 3._Two)
Grow 21 Next, normal photolithography technology
Using a resist (not shown) as a mask layer
Alternatively, phosphorus ion implantation is performed to form a p-type SOI substrate 3
Is changed to an n-type SOI substrate 4. Then resist
(Not shown). Next, a nitride film of about 0.2μm
(Si_ThreeN_Four To grow 22). Next, normal photolithography
Using a fee technology, a resist (not shown) is opened,
Using a resist (not shown) as a mask layer, nitride film 22, acid
Oxide film 21, p-type and n-type SOI substrates (3, 4) selectively
To form element isolation region forming trench 5
I do. Next, the resist (not shown) is removed. Then
Chemical vapor deposition oxide film (SiO_Two) Grow and anisotropic drier
And buried in the trenches 5 for forming element isolation regions.
No. Fig. 9 Next, using normal photolithography technology,
Element (not shown) and element isolation region with embedded oxide film
Using the region forming trench 5 as a mask layer, a nitride film is selectively formed.
22 is anisotropically dry-etched. Then resist (Figure
(Not shown). Then normal photolithography
Using technology to open holes only on the p-type SOI substrate 3
Using a resist (not shown) and the nitride film 22 as a mask layer,
Phosphorus ions are implanted into the p-type SOI substrate 3. Then cash register
The strike (not shown) is removed. Then normal photolithography
Utilizing only the n-type SOI substrate 4
Resist (not shown) to be opened and nitride film 22 as a mask layer
Then, boron is ion-implanted into the n-type SOI substrate 4.
Next, the resist (not shown) is removed. Then 950
N around ° C_TwoLateral diffusion by annealing
The n-type source / drain region 6 and the p-type source
Formation region 7 is formed. Then normal photolithography
Using technology to open holes only on the p-type SOI substrate 3
Using a resist (not shown) and the nitride film 22 as a mask layer,
Arsenic is ion-implanted into the p-type SOI substrate 3. Then
The dist (not shown) is removed. Then the normal photo library
Using lithography technology, only on n-type SOI substrate 4
(Not shown) for opening holes and masking nitride film 22
As a layer, boron is ion-implanted into the n-type SOI substrate 4.
You. Next, the resist (not shown) is removed. Then 9
N of about 00 ° C_TwoBy adding annealing, some
N including lateral diffusion⁺ Type source drain region 8 and p⁺ 
Form source / drain regions 9 are formed. Figure 10 Then n⁺ Type source drain region 8 and p⁺ Type sauced
Etching removal of extremely thin oxide film 21 on rain region 9
I do. Next, for the element in which the nitride film 22 and the oxide film are embedded,
Using the trench 5 for forming an isolated region as a mask layer,
Lateral diffusion into lower p-type and n-type SOI substrates (3, 4)
N⁺ Type source drain region 8 and p ⁺ Type sauce drain
Excluding the in-region 9, n⁺ Type source drain region 8 and p
⁺ P-type and p-type regions where most of the source / drain regions 9 are formed.
And n-type SOI substrates (3, 4) are selectively etched away.
Then, a trench is formed in the source / drain region. Next
Grows tungsten film (W) by chemical vapor deposition
And then anisotropically dry-etch the tongue into the trench
Embedding the ten film, metal source drain region (10a, 10
b, 10c). Fig. 11 Next, using ordinary photolithography technology,
(Not shown) and metal source / drain regions (10
a, 10b, 10c) as a mask layer and an oxide film is embedded
Part of the oxide film (remaining) in the trench 5 for forming an element isolation region.
Contact portion of the gate electrode at the portion adjacent to the nitrided film 22
Is etched only about 0.2 μm. Continuous
To etch the remaining nitride film 22 and thin oxide film 21
Then, a trench for a gate electrode is formed. Then
The dist (not shown) is removed. FIG. 12 Next, the gate oxide film 11 (SiO_Two/ Ta_TwoO_Five )
Continue to grow. Next, a barrier metal (TiN) 12 of about 20 nm
And Al13 to be a gate electrode of about 0.2 μm
Grow by Next, chemical mechanical polishing (CMP)
More buried in the trench for the gate electrode, the gate oxide film
11 (SiO_Two/ Ta_TwoO_Five ), Barrier metal (TiN) 12 and game
Buried gate electrode structure composed of gate electrode (Al) 13
I do. In this case, the gate electrode (Al) 13 and barrier metal
(TiN) 12 and gate oxide film 11 (SiO_Two/ Ta_TwoO_Five ) Also excluded
Left. Figure 13 Next, by chemical vapor deposition, phosphoric acid silicate glass
(PSG) film 14 is grown. Then normal photolithography
Masks resist (not shown) using luffy technology
As a layer, the PSG film 14 is selected by anisotropic dry etching.
Alternatively, a contact hole 20 is opened. Then sputter
To grow Ti and TiN 15 sequentially as barrier metal
You. Next, a blanket method of chemical vapor deposition
W is grown and anisotropic dry etching is performed to
(W) 16 is formed. Fig. 3 Next, Ti and TiN 17 that become barrier metal by sputtering
Grow sequentially. Next, by sputtering, Al
(Including several% of Cu) is grown to about 0.8 μm. Then
Ti and TiN 19, which are barrier metals, are sequentially formed by the putter.
Lengthen. Then use normal photolithography technology
Then, using a resist (not shown) as a mask layer,
Metal (Ti / TiN), Al (including several percent Cu) and barrier metal
Al (Cu / TiN) by anisotropic dry etching
A line 18 is formed. Normal gate arrays are multilayer wiring
Therefore, the mask process for forming a via hole,
The mask process is repeated to complete a desired gate array.
In the above manufacturing method, some of the steps are anisotropic.
Buried layer is formed by dry etching
However, all of these processes have been turned into chemical mechanical polishing (CMP).
You can do more.

[0009]

As described above, according to the gate array of the present invention, the N-channel and P-channel MI
A C-MOS having the source / drain region of the S field effect transistor as a common metal source / drain region can be formed, and N-channel and P-channel MIs in which all elements are self-aligned on p-type and n-type SOI substrates.
Since an S field-effect transistor can be formed and an N-channel or P-channel MIS field-effect transistor can be formed on a fully-depleted p-type or n-type SOI substrate, a contact region to the p-type and n-type SOI substrates is formed. The high integration of the basic cell due to the fact that it can be configured without the provision of the gate is achieved by reducing the resistance of the source / drain region and the junction capacitance by forming the metal source / drain region, and forming the gate by forming the low-resistance low melting point metal (Al) gate electrode. Low resistance of electrode wiring, improvement of minute current leak between gate electrode and SOI substrate by using gate oxide film of Ta ₂ O ₅ with high dielectric constant, reduction of gate capacitance, depletion by using fully depleted SOI substrate Higher speed, lower power, and higher reliability of basic cells by reducing the threshold voltage by removing layer capacitance and improving sub-threshold characteristics And high performance are possible. That is, it is possible to obtain a gate array capable of forming a large-scale semiconductor integrated circuit with extremely high speed, low power, high reliability, high performance, and high integration. When the basic cell of the present invention is used, about 75% of the basic cells can be configured as compared with the conventional basic cells.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a basic cell of a first embodiment in a gate array of the present invention.

FIG. 2 is a schematic plan view of one wiring pattern (2-input NAND) of the first embodiment in the gate array of the present invention;

FIG. 3 is a schematic side sectional view of a first embodiment of the gate array according to the present invention (a sectional view taken along line PP of FIG. 2);

FIG. 4 is a schematic plan view of a basic cell of a second embodiment in the gate array of the present invention.

FIG. 5 shows one wiring pattern (static ram memory cell) of the second embodiment in the gate array of the present invention.
Schematic plan view of

FIG. 6 is a schematic side sectional view of a gate array according to a second embodiment of the present invention (a sectional view taken along the line PP in FIG. 5).

FIG. 7 is a process sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 8 is a process sectional view of one embodiment of a method for manufacturing a gate array according to the present invention.

FIG. 9 is a process sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 10 is a process cross-sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 11 is a process sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 12 is a process sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 13 is a process sectional view of one embodiment of a method for manufacturing a gate array of the present invention.

FIG. 14 is a schematic plan view of a basic cell of a conventional gate array.

FIG. 15 shows one wiring pattern (2
Schematic plan view of input NAND)

FIG. 16 is a schematic side sectional view of a conventional gate array (FIG. 1)
5 is a sectional view taken along the line PP).

[Explanation of symbols]

Reference Signs List 1 p ^- type silicon (Si) substrate 2 bonding oxide film (SiO ₂ ) 3 p-type SOI substrate 4 n-type SOI substrate 5 trench for forming element isolation region and buried oxide film (SiO ₂ ) 6 n-type Source / drain region 7 P-type source / drain region 8 n ⁺ -type source / drain region 9 p ⁺ -type source / drain region 10a Common metal source / drain region (W) in contact with n-type and p-type impurity regions 10b Metal source in contact with p-type impurity region Drain region (W) 10c Metal source / drain region (W) in contact with n-type impurity region 11 Gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 12 Barrier metal (TiN) 13 Gate electrode (Al) 14 Phosphosilicate glass (PSG) ) Film 15 Barrier metal (Ti / TiN) 16 Plug (W) 17 Barrier metal (Ti / TiN) 18 AlCu wiring 19 Barrier metal (Ti / TiN) 20 Contact hole (including formable area) 21 Acid Oxide film (SiO ₂ ) 22 nitride film (Si ₃ N ₄ )

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 27/11 H01L 29/46 R 29/43 29/78 616S F term (reference) 4M104 AA01 AA09 BB02 BB14 BB18 BB30 DD08 DD19 DD26 DD37 DD43 DD66 DD75 FF13 FF22 GG09 GG10 GG14 HH16 5F048 AA00 AA01 AA04 AA07 AB02 AB03 AC04 BA16 BB04 BB09 BB11 BB13 BB19 BC06 BC11 BF02 BF07 BF16 BG05 BG14 GG15 GG14 5F019 A33 BS27 BS29 BS40 GA02 GA09 HA02 JA03 JA06 JA36 JA39 JA40 JA56 NA01 PR03 PR21 PR33 PR40 5F110 AA02 AA03 AA04 AA09 BB04 BB07 BB20 CC02 DD05 DD13 EE01 EE03 EE14 EE22 EE44 FF01 FF02 FF09 GG02 GG02 GG12 GG02 GG12 GG12 GG12 GG12 GG12 GG25 HL23 HM02 HM15 HM17 HM19 NN04 NN25 NN35 NN62 NN65 QQ10 QQ11 QQ17 QQ19

Claims (2)

[Claims] A semiconductor substrate and one conductivity type and opposite conductivity type SO selectively provided on a semiconductor substrate via an insulating film.
An I substrate, a gate insulating film provided on the SOI substrate, a gate electrode provided on the gate insulating film, self-aligned with the SOI substrate, and provided in partial contact with a side surface of the SOI substrate. And an impurity region (source / drain region) of the opposite conductivity type to each of the SOI substrates provided separately from each other on the SOI substrate at a contact portion with the metal source / drain region. A MIS field-effect transistor of a conductivity type and an opposite conductivity type, and wherein the metal source / drain regions of the adjacent MIS field-effect transistors of the one conductivity type and the opposite conductivity type are formed of the impurity regions of the one conductivity type and the opposite conductivity type. The one-conductivity-type and the opposite-conductivity-type MIS field effect having a structure formed as a common metal source / drain region in contact with both. Gate array, characterized in that arranged basic cells comprising transistors in a matrix. 2. The method according to claim 1, wherein the basic cell comprises at least two pairs of the MIS field effect transistors of the one conductivity type and the opposite conductivity type, and a common metal source / drain region between the MIS field effect transistors of the one conductivity type and the opposite conductivity type. 2. The gate array according to claim 1, wherein the gate array has at least one.