JPH03175670A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a Bi-CMOS IC in consideration of high integration of MOSFET without giving rise to deterioration of electric characteristics of a bipolar transistor by forming the gate oxide film of an LDD type MOSFET after providing a silicon dioxide layer having prescribed film thickness by thermal oxidation on a region in which a base is expected to be formed. CONSTITUTION:When an LDD type MOSFET and a semiconductor device including a bipolar transistor(BT) are formed on the same semiconductor substrate 1, a gate oxide film 12 in a MOSFET is formed after providing in advance a silicon dioxide layer 5 having prescribed film thickness on a region in which the base of BT is expected to be formed. For example, buried layers 2 and 3, an N-type epitaxial region 4, a silicon dioxide layer 5, well regions 6 and 7, an element isolation oxide film 10 are formed on a P-type substrate 1. Then, ion implantation for adjusting the threshold of an N-channel MOSFET is performed and subsequently, the silicon dioxide layer 5 in a mask opening part is removed. Further, ion implantation for adjesting the threshold of a P-channel MOSFET is performed and subsequently, the gate oxide film 12 is formed after removing the silicon dioxide layer 5 in the mask opening part.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an integrated circuit (complementary field effect transistor (CMOS) transistor) and bipolar transistor formed on the same semiconductor substrate. R1-CMOS IC).

[Prior art] High-speed operation, high drive capability and C
Bi-CMOS ICs, which combine the performance of both MOS transistors and are formed on the same semiconductor substrate, have been widely attempted in response to recent demands for lower power consumption and higher speeds.

Figures 3(a) to (i) show conventional B1-CMOS ICs.
1 shows step-by-step cross-sectional views of the manufacturing method.

First, as shown in FIG. 3<a), a P type semiconductor substrate 1 is provided with an N+ type buried region 2. A P+ type buried region 3 is formed, then an N type epitaxial region 4 is formed, the surface of which is thermally oxidized to form a first silicon dioxide layer 5 having a thickness of 600 to 800 nm, and selectively ionized. By injecting N
A P-type well region 6 for a channel MOSFET formation region and a bipolar transistor isolation region is formed, and further, by selective ion implantation, an N-type well region 7 for a P-channel MOSFET formation region is formed.

Next, as shown in FIG. 3(1), a silicon nitride layer 9 is deposited on the surface of the first silicon dioxide layer 5 using CVD technology. Furthermore, the silicon nitride layer 9 in the region where the element isolation oxide film is to be formed is selectively removed by anisotropic etching, and the element isolation oxide film 10 is formed by thermal oxidation.

Next, as shown in FIG. 3C, the silicon nitride layer 9 is removed using an etching technique, and ions are implanted for adjusting the threshold of the N-channel MOSFET using a mask. Ion implantation for adjusting the threshold of the P-channel MOSFET is performed using a mask such as the following.

Next, as shown in FIG. 3(), the first silicon dioxide layer 5 is removed by an etching technique, and a gate oxide film 12 with a thickness of 200 to 300 nm is formed by thermal oxidation. An opening is made in the region where the collector of the transistor is to be formed.Next, an N1 type polycrystalline silicon layer 13 containing, for example, phosphorus and a silicide layer 14, such as tungsten silicide or molybdenum silicide, are deposited by CVD technology.Furthermore, a mask is formed. By using known anisotropic etching, the area where the collector is to be formed and the MO
A silicon/silicide structure is left on the region where the gate electrode of the SFET is to be formed.

Here, there is also a method in which the gate electrode is formed only from a polycrystalline silicon layer. Next, by heat treatment, an N'' type collector region 8 is formed by mature diffusion from the N+ type polycrystalline silicon layer 13 on the region where the collector is to be formed.

Next, as shown in FIG. 3(e), a P-channel MOSF
ET low concentration P type diffusion region 15 and N channel MO8
Low concentration N type expansion rl of FET! Region 16 is formed using a mask. Subsequently, using CVD technology, 2000~3
A second silicon dioxide layer 18 having a thickness of 1,000 nm is deposited.

Next, as shown in FIG. 3(f), the second silicon dioxide layer 18 is etched back using a known anisotropic etching technique to form a sidewall 18a.

At this time, the formation of the high concentration source/drain region of the MOSFET (the high concentration P type diffusion region of the P channel MOSFET and the high concentration N type diffusion region of the N channel MOSFET) is performed on the region where the P type base of the bipolar transistor is planned to be formed. The gate oxide @12 above the planned area is also removed.

Next, as shown in FIG. 3 (g>), a film of 500 to 1000 layers was thermally oxidized on the region where the P-type base of the bipolar transistor was to be formed and the region where the high concentration source and drain of the MOSFET were to be formed. A thick third silicon dioxide layer 25 is formed.Subsequently, by ion implantation using a mask, the P-type base region 17. of the bipolar transistor is formed.
High concentration N type diffusion region 19 of N channel MOS FET
．． A heavily doped P-type diffusion region 20 of a P-channel MOSFET is formed.

Next, as shown in FIG. 3(h), 1
Fourth silicon dioxide layer 2 with a thickness of 000 to 2000 people
form 6. Subsequently, the emitter diffusion window of the bipolar transistor is opened using a mask, and a second N1 type polycrystalline silicon layer 22 containing, for example, phosphorus is deposited by CVD technology, and is then etched by known anisotropic etching using a mask. A second N+ type polycrystalline silicon layer 22 is left to cover the emitter diffusion window.

Finally, as shown in FIG. 3(i), the base contact region 21 and emitter region 23 of the bipolar I transistor are formed, and the lead electrode 28 is formed by a wiring forming process using an existing method.

[Problem to be solved by the invention]

According to the conventional B1-CMOS IC manufacturing method described above, when the second silicon dioxide layer 18 is etched back by anisotropic etching to form the sidewall 18a, the area other than the sidewall forming portion is etched back. The second silicon dioxide layer 18 must be completely removed from the surface 6. Let X be the time for etching away the second silicon dioxide layer 18 from the surface other than the sidewall forming area.
Usually 1.2x to 1.25x, taking into account variations in the thickness of the second silicon dioxide layer 18 and variations in etching.
In other words, an overetch of 20% to 25% is performed, but during overetching, a gate acid with a thickness of 200 to 300% is applied to the region where the P-type base of the bipolar transistor is to be formed and the region where the high concentration source/drain of the MOSFET is to be formed. Since only the 1-layer film 12 remains, the silicon surface of the region where the P-type base of the bipolar transistor is to be formed is directly exposed to anisotropic etching.

When the silicon surface of the P-type base formation area of bipolar 1 to transistor is overetched by about 10% or more,
This has the drawback that leakage current increases on the silicon surface between the emitter and base of the bipolar transistor, resulting in significant deterioration of electrical characteristics.

In addition, as higher integration progresses in the future, the gate oxide film will tend to become even thinner, but at this time the silicon surface in the region where the P-type base is planned to be formed will suffer even greater damage, so conventional manufacturing With this method, it is difficult to make the gate oxide film any thinner.

An object of the present invention is to provide a method for manufacturing a semiconductor device that allows manufacturing a Bi-CMOSIC that takes into account high integration of MOSFETs without causing deterioration of the electrical characteristics of bipolar transistors as described above. .

[Means to solve the problem]

The method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device including an LDD type MO9 field effect transistor and a bipolar transistor on the same semiconductor substrate, in which a predetermined thickness of thermal oxidation is applied to a region where the base of the bipolar transistor is to be formed. The method includes a step of forming a gate oxide film of an LDD type MO8 field effect l transistor after providing a silicon dioxide layer according to the method.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to (e) show Bi-
FIG. 3 is a cross-sectional view showing the main steps of the CMO5IC manufacturing method.

First, as shown in FIG. 1(a), an N+ type buried region 2, a P4 type buried region 3. N-type epitaxial region 4,600-80
The first silicon dioxide Jfffi5 with a film thickness of 0. P type now L area 6. N-type current region 7, element isolation oxide film 10
form.

Next, as shown in FIG. 1(b), photoresists 1 to 2 are
4 as a mask, ion implantation for adjusting the threshold of Nchanel MO8FE' is performed, and then the first silicon dioxide layer 5 in the mask openings is removed.

Next, as shown in FIG. 1(c), the photoresist 24
Ion implantation for adjusting the threshold of the P-channel MOSFET is performed using a mask as a mask, and then the first silicon dioxide〉' layer 5 in the mask opening is removed.

Next, as shown in FIG. 1(d), 200
A first silicon dioxide layer 5. is formed on the region where the collector of the bipolar transistor is to be formed. The gate I oxide film 12 is removed by etching, and a region where a collector is to be formed is opened.

Subsequently, an N+ type polycrystalline silicon layer 13 containing, for example, phosphorus is formed.
and a silicide layer 14, such as tungsten silicide or molybdenum silicide, are deposited by CVD technology. Furthermore, by using a mask and known anisotropic etching, the area where the collector is to be formed and the MOSFE are etched.
A silicon/silicide structure is left on the region where the gate electrode is to be formed. Here, there is also a method in which the gate electrode is formed only from a polycrystalline silicon layer.

Next, by heat treatment, an N+ type collector region 8 is formed by thermal diffusion from the N+ type polycrystalline silicon layer 13 on the region where the collector is to be formed.

Next, as shown in FIG. 1(e), by using the conventional manufacturing method, the low concentration P type diffusion region 15 of the P channel MOSFET and the low concentration N of the N channel MOSFET are formed.
A mold expansion region 16 is formed, and 2000 ~
A second 2#Ii silicon layer 18 having a thickness of 3000 nm is deposited.

Next, sidewalls are formed by anisotropic etching, and a gate oxide film 12 of 200 to 300 layers and a first silicon dioxide film of 600 to 800 layers are formed on the region where the P-type base of the bipolar transistor is to be formed. Since layer 5 remains, the silicon surface of the region where the P-type base of the bipolar transistor is to be formed is not directly exposed to anisotropic etching even during over-etching.

The subsequent steps up to the formation of the extraction electrodes are the same as the conventional manufacturing method.

In this example, an element isolation oxide layer 115110 is formed using the silicon nitride layer as a mask, and then the silicon nitride layer is removed by etching and sowing, and a photoresist 24.24a is used as a mask to form an element isolation oxide 115110 on the area where the P-type base of the bipolar transistor is to be formed. The first silicon dioxide layer 5 was protected from etching and remained, but the silicon nitride layer and the first silicon dioxide layer 5 were all etched away, a new thermally oxidized arsenic film was formed, and this thermally oxidized Bipolar membrane! - There is also a method of leaving it on the region where the P-type base of the transistor is planned to be formed.

FIGS. 2(a) to (c) show Bi-
It is a sectional view of the main steps of the manufacturing method of CMO5IC.

First, as shown in FIG. 2(a), using a conventional manufacturing method, an N++ buried region mt42, a P+ type buried region 3. N-type epitaxial region 1! i4,600
5. First dinocon dioxide layer with a thickness of ~800 mm. P-type well region6. An N-type well region 7 and an element isolation oxide film lO are formed. Subsequently, the first silicon dioxide layer 5 on the head 34 where the P-type base of the bipolar I transistor is to be formed is protected by a mask such as FoI resists 1 to 24b, and the first silicon dioxide layer 5 in the pond portion is protected. The silicon oxide layer 5 is removed by etching.

Next, as shown in Figure 2 1), thermal oxidation
Form a gate oxide M12 with a thickness of 300 nm. At this time, 200 to 300 layers of gate oxide 11112 and 600 to 800 layers of first silicon dioxide layer 5 are formed on the region where the P type base of the bipolar transistor is to be formed.

Next, as shown in FIG. 2(c), gate oxidation IBt1 is formed on the regions where the collectors of bipolar 1 to transistors are to be formed.
2 is removed by etching, and a region where a collector is to be formed is opened. Next, for example, N+ type packed crystal 1937 containing phosphorus
A layer 13 and a silicide layer 14, such as tungsten silicide or molybdenum silicide, are deposited by CVD techniques. Furthermore, by using a mask and known anisotropic etching, the collector formation area E and the MOS
A silicon/'silicide structure is left on the region where the gate electrode of the FET is to be formed. After that, P channel MOS
FET low concentration P type diffusion region 15 and N channel MO
8FET lightly doped N-type diffusion regions 16 are formed and a second silicon dioxide layer 18 having a thickness of 2000 to 3000 nm is deposited by CVD techniques.

The subsequent steps up to the formation of the extraction electrodes are the same as the conventional manufacturing method.

〔Effect of the invention〕

As explained above, the present invention provides an LD on the same semiconductor substrate.
In a method of manufacturing a semiconductor device including a D-type MOS field effect transistor and a bipolar transistor,
・By leaving the silicon dioxide layer formed by the thermal acid atomization on the areas where the bases of bipolar 1 to transistors are to be formed, gate oxide film is formed in these areas by performing gate oxidation. A silicon dioxide layer having the added thickness is formed.

Therefore, when forming the sidewall by anisotropic etching, it is possible to avoid directly exposing the silicon surfaces of the regions where the bases of the bipolar transistor 1 to the transistor are to be formed.

This makes it possible to prevent deterioration of electrical characteristics due to an increase in leakage current on the silicon surface between the emitter and base of the bipolar transistor.

Furthermore, the method of manufacturing a semiconductor device of the present invention can be sufficiently applied even when semi-midbody devices become more highly integrated and the gate oxide film becomes thinner.

[Brief explanation of drawings]

FIG. 1 (a) to (e) are steps 1 of the first embodiment of the present invention.
tllt Ili side view, Figures 2(a) to (c) are cross-sectional views of the second embodiment of the present invention, Figures 3(a) to (c).
i) is an old sectional view of step 11 of the prior art. 1... 1) is a semiconductor substrate, 2... N+ is a buried region, 3... P' type buried region, 4... N type epitaxial region, 5... First silicon dioxide layer, 6...P
type well region, 7...N type well region, 8...N4
collector region, 9... nitride, 1-arsenic silicon layer, 10...
・Element isolation oxide film, l 1, 24.24a, 24b...
・Fo I Regis 1~. 12...Glue l-oxide film, 1
3... N'' type polycrystalline silicon layer, 14... Silicide layer, 15... Low concentration " ] type diffusion region, 16... Low concentration N type diffusion region, 17... P type base region , 18・
...Second silicon dioxide layer, 18a...Side wall, 19...High concentration N type diffusion region, 20...High concentration P type diffusion region, 21...Base contact region, 2
2... Second N+ type polycrystalline silicon layer, 23... Emitter region, 25... Third silicon dioxide layer, 26
. . . fourth silicon dioxide layer, 27 . . . fifth silicon dioxide layer, 28 . . . bowed electrode.

Claims (1)

[Claims] In a method for manufacturing a semiconductor device including an LDD type MOS field effect transistor and a bipolar transistor on the same semiconductor substrate, a predetermined film thickness of 2 is deposited on a region where the base of the bipolar transistor is to be formed by thermal oxidation.
A method of manufacturing a semiconductor device, comprising forming a gate oxide film of the LDD type MOS field effect transistor after providing a silicon oxide layer.