JPH05145025A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent characteristics deterioration of a bipolar transistor. CONSTITUTION:At the time of forming a Bi-CMOS IC, CMOS channel dope ions are implanted via a first thin oxide film. After the first thin oxide film is eliminated and a new gate oxide film 111 is formed, an intrinsic base region 112 is formed by using ion implantation technique. A first polycrystalline silicon film 114 is precisely formed by using RIE technique. The film is used as a mask, and the gate oxide film 111 is etched by using wet solution, thus forming an emitter contact aperture. An emitter diffusion layer 117 is formed via an emitter electrode 119. Annealing in the process is performed by using RTA technique, and heat treatment time is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device (hereinafter referred to as Bi-CMOS IC) in which a bipolar transistor and a MOS transistor are mixed on one semiconductor substrate.
The present invention relates to a method for manufacturing a semiconductor device in which an OS transistor is formed at the same time.

[0002]

2. Description of the Related Art Conventionally, when forming a Bi-CMOS IC, the intrinsic base region of a bipolar transistor is C.
This has been carried out simultaneously with the ion implantation for forming the MOS channel. In this method, ion implantation for forming a channel in the CMOS portion is performed through the first thin oxide film, but the first thin oxide film cannot be directly applied to the gate oxide film.

This is because, in MOS transistors that have been miniaturized more and more in recent years, thinning of gate oxide film and high reliability are indispensable factors, and such gate oxide film is ion-implanted for channel formation. Because it is impossible to form before.

[0004]

Therefore, the ion implantation for forming a channel requires a first thin oxide film different from the gate oxide film, but once the ion implantation step is completed, the first thin oxide film is temporarily removed. The thin oxide film must be removed and the gate oxide film must be formed again.

Therefore, as in the conventional case, the ion implantation for forming the intrinsic base portion of the bipolar transistor is performed by CM.
When the ion implantation for forming the OS channel is performed at the same time,
When a new gate oxide film is formed after the first thin oxide film is removed, the intrinsic base region of the bipolar transistor is
It re-diffuses and spreads abnormally, which causes deterioration of performance of the bipolar transistor such as reduction of current gain rate.

Further, the emitter contact opening of the conventional bipolar transistor is formed in a region where an emitter diffusion layer is to be formed by RIE (reactive ion etching, reactive).
Ion Etching) technology,
This results in damage to the surface of the semiconductor substrate, which in turn causes a leak current between the base and the emitter diffusion layer.

Further, the emitter diffusion layer is formed by introducing impurities into a polycrystalline silicon film which can serve as an emitter electrode and diffusing the impurities from the polycrystalline silicon film. The heat treatment exposed at this time is the re-diffusion of the intrinsic base region as described above. To deteriorate the characteristics of the bipolar transistor.

An object of the present invention is to provide a method of manufacturing a semiconductor device which suppresses re-diffusion of the intrinsic base region of a bipolar transistor to prevent characteristic deterioration of the bipolar transistor.

[0009]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a bipolar transistor and a MOS transistor are mixed on one main surface of a semiconductor substrate of one conductivity type. When forming a MOS semiconductor device, a step of performing ion implantation for forming a channel of the MOS transistor through a first oxide film having a thickness substantially equal to that of the gate oxide film, and removing the first oxide film Then, a gate oxide film is formed, and the intrinsic base of the bipolar transistor is ion-implanted.

Further, a step of depositing a first polycrystalline silicon film on the gate oxide film, a step of simultaneously etching the first polycrystalline silicon film at the time of opening an emitter contact of the bipolar transistor, and an emitter contact. After the opening, the step of depositing a second polycrystalline silicon film and the step of implanting arsenic impurity ions on the second polycrystalline silicon film form an emitter electrode.

In forming the emitter electrode, RT
The emitter resistance is reduced by using A (Rapid Thermal Anneal) technology.

[0012]

Operation When forming the Bi-CMOS IC,
The CMOS channel dope ion implantation is performed through the first thin oxide film to prevent damage to the gate oxide film and re-diffusion of the intrinsic base region. Further, since the gate oxide film is also etched using the wet solution with the opening of the emitter contact using the first polycrystalline silicon film as a mask, damage to the emitter diffusion layer region is also suppressed.

[0013]

The present invention will be described below with reference to the drawings. 1 to 4 are vertical cross-sectional views for explaining one embodiment of the present invention.

First, as shown in FIG. 1, a P-type semiconductor substrate 1
01 selectively diffuses arsenic or antimony to N
A (plus) buried layer 102 is formed, and similarly, boron or the like is selectively diffused to form a P (plus) buried layer 103.
Next, the N-type epitaxial layer 104 is set to 0.7 to 1.5 μm.
After the growth, the N well 105 and the P well 106 are formed to form a CMOS transistor.

Then, a normal selective oxidation method (LOCOS) is performed.
Method, the field oxide film 107 is 0.5 to 0.8
Grow μm. Next, the first thin oxide film 108 is removed by 80
100 to 300 Å growth in an oxygen atmosphere of 0 to 900 ° C., an acceleration voltage of 15 to 40 KeV and a dose of 1 × 10 ¹² are applied to the channel regions of the NMOS transistor and the PMOS transistor through the first thin oxide film 108.
Ion implantation is performed under the conditions of up to 5 × 10 ¹³ cm ⁻² to form the N channel 109 and the P channel 110.

Next, as shown in FIG. 2, the first thin oxide film 108 is removed and the gate oxide film 111 is removed by 100 to 150.
Å Grow. After that, impurity ions and boron are implanted only through the gate oxide film 111 into the intrinsic base region 112 of the bipolar transistor by the photolithography technique. The implantation conditions at this time are ion seed boron and an acceleration voltage of 10 to 30 so that the junction depth does not become too deep.
KeV and a dose amount of 1 to 5 × 10 ¹³ cm ^-2 are desirable. Then, the N-type collector region 113 is formed.

According to the method described above, the channel region of the CMOS portion is ion-implanted through the first thin oxide film 108 to form a gate oxide film again. Since the intrinsic base and the collector are to be ion-implanted through the gate oxide film, it is not necessary to undergo extra heat treatment, and it is possible to avoid making the junction depth abnormally deep.

Next, the first polycrystalline silicon film 114 is formed to a thickness of 10
00 to 2000 Å is deposited, and an opening 115 is formed in the region where the emitter diffusion layer is formed. For the opening 115, it is necessary to successively etch two layers of the first polycrystalline silicon 114 and the gate oxide film 111. The former method uses RIE technology, and the latter method uses hydrofluoric acid or the like. Good.

This is because this method does not expose the emitter diffusion region opening to the plasma atmosphere during RIE, and therefore does not damage the interface of the substrate. Finally, the gate oxide film 111
Since it is etched with a solution such as hydrofluoric acid, it is naturally isotropic etching, and it is thought that it is wider than the patterning dimension by photoresist, but considering the gate oxide film thickness, the extent is at most about 200 Å on one side. It is a level that can be ignored.

Next, as shown in FIG. 3, a second polycrystalline silicon film 116, 500-1500Å is deposited. This second
The polycrystalline silicon film 116 becomes the emitter electrode of the bipolar transistor, and at the same time, it becomes the gate polysilicon electrode together with the first polycrystalline silicon film 114 in the CMOS transistor portion.

Next, with respect to the second polycrystalline silicon film 116 deposited on the entire surface, arsenic impurity ions are accelerated at a voltage of 50 to 100 KeV and a dose of 1 × 10 ^{15 to} 5 × 10.
Inject about ¹⁶ cm ^-2 .

Next, RTA (Rapid Therm)
al anneal) technology, temperature 900-100
Annealing is performed in a nitrogen atmosphere at 0 ° C. for a heating time of about 10 to 60 seconds. As a result, in the emitter diffusion layer forming region 115, the gate oxide film 111 immediately below the second polycrystalline silicon film 116 is thermally destroyed, and the emitter opening is provided with the second polycrystalline silicon film 116 interposed. The formed emitter diffusion layer 117 is obtained.

Finally, as shown in FIG. 4, after patterning the CMOS gate electrode 118 and the emitter electrode 119 by using the photolithography technique, the graft base region 120 is formed and the source and drain of each of the PMOS and NMOS are ion-implanted. Formed by LDD
If a structure is required, a process for that may be added.
Furthermore, the Bi-CMOS IC according to the present invention can be obtained through the steps generally required for manufacturing a semiconductor device such as an interlayer film, contact holes, and aluminum wiring.

[0024]

As described above, according to the present invention, C
The channel region ion implantation of the MOS is performed through the first thin oxide film, the first thin oxide film is removed, and then the intrinsic base region of the bipolar transistor is formed through the newly formed gate oxide film. Since the ion implantation is performed, heat treatment to the intrinsic base can be minimized after formation of the intrinsic base region, and therefore re-diffusion of the intrinsic base can be prevented.

Further, when the emitter diffusion region is to be opened, the polycrystalline silicon film is patterned accurately using the RIE technique, and the gate oxide film under the polycrystalline silicon film is exposed to hydrofluoric acid by using it as a mask. Since the etching is performed by using a wet liquid such as, the contact opening portion is not damaged by the etching.

Moreover, in the present invention, after the opening of the emitter contact, a second polycrystalline silicon film to be an emitter electrode is deposited, and impurity ion arsenic is introduced into the polycrystalline silicon film to form the emitter diffusion. ,At this time,
Since RTA technology is used, the heat treatment time can be shortened significantly,
Thereby, re-diffusion of impurities already introduced into the intrinsic base or the channel region of the CMOS portion can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a forming method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a forming method according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a forming method according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a forming method according to an embodiment of the present invention.

[Explanation of symbols]

 101 P-Type Semiconductor Substrate 102 N (Plus) Buried Layer 103 P (Plus) Buried Layer 104 N-Type Epitaxial Layer 105 N Well 106 P Well 107 Field Oxide Film 108 First Thin Oxide Film 109 N Channel 110 P Channel 111 Gate oxide film 112 Intrinsic base region 113 N-type collector region 114 First polycrystalline silicon film 115 Emitter contact opening 116 Second polycrystalline silicon film 117 Emitter diffusion layer 118 CMOS gate electrode 119 Emitter electrode 120 Graft base region

Claims (3)

[Claims] 1. When forming a bi-CMOS type semiconductor device in which a bipolar transistor and a MOS type transistor are mixed on one main surface of a semiconductor substrate of one conductivity type, a first oxide having a thickness substantially equal to that of a gate oxide film. A step of performing ion implantation for forming a channel of the MOS transistor through a film, and a step of forming a gate oxide film after removing the first oxide film and performing ion implantation of an intrinsic base of the bipolar transistor A method of manufacturing a semiconductor device, comprising: 2. A step of depositing a first polycrystalline silicon film on the gate oxide film, a step of simultaneously etching the first polycrystalline silicon film at the time of opening an emitter contact of the bipolar transistor, and an emitter contact. The step of depositing a second polycrystalline silicon film after opening, and forming an emitter electrode by implanting arsenic impurity ions on the second polycrystalline silicon film. Of manufacturing a semiconductor device of. 3. An RTA (Rapid Thermal Anneal) for forming the emitter electrode.
The method for manufacturing a semiconductor device according to claim 1, wherein the emitter resistance is reduced by using a technique.