JPS6113668A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attain the increase of withstanding voltage and the augmentation of currents by a fine occupying area by elevating only impurity concentration in a contact section with a wiring electrode and bringing impurity concentration in a drain region to one through which the drain region is fitted to the increase of withstanding voltage and currents hardly lower. CONSTITUTION:A field oxide film 2 is formed into a P conduction type Si substrate 1, and a gate electrode and a gate protective insulating film 5 are shaped onto the surface of the substrate 1 in an active region. An Si oxide film 8 is formed only onto the side wall sections of the electrode 4 and the film 5. A low impurity-concentration source region 6 and a low impurity-concentration drain region 7 are shaped into the substrate 1 so that surface impurity concentration of 10<17>-10<20>cm<-3> is obtained by implanting the ions of phosphorus into the substrate 1 while using the film 5 and the film 8 as masks. A source Si electrode 14 and a drain Si electrode 15 are formed, and the ions of arsenic are implanted under the state and thermally treated, thus shaping not less than 10<19>cm<-3> high impurity concentration layer and a region. Accordingly, a superfine type semiconductor device in which withstanding voltage between a source and a drain is increased and current driving capability hardly lowers can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to an ultra-fine MO8 field effect transistor having both high breakdown voltage characteristics and high current drive capability.

[Background of the invention]

Conventional ultra-fine MO with effective channel length of less than 1 μm
The 8-type field effect transistor (hereinafter simply abbreviated as MOS) has a high breakdown voltage structure as shown in Figures 1 and 2 in order to be able to operate with a 5V power supply. What it shows is LDD (Lightly Danaped Danrai)
n) Structure, the one shown in Figure 2 is DD (Double
Drain (double drain) structure is called e (
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cof lightly dooped drain-
sauce (L, D, D) insulated gate
field-effect transistor p
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) In Figures 1 and 2, 1 is a p-conductivity type silicon substrate, 2 is a thick field oxide film for isolation between elements, 3 is a gate insulating film, 4 is a gate electrode, and 5 is a gate protection insulator. It is a membrane. Reference numeral 6 indicates an n-conductivity type low impurity concentration source region (n- diffusion layer), and 7 indicates an n-conductivity type low impurity concentration drain region (n-
(diffusion layer), which is formed by introducing impurities using the gate electrode 4 as a mask. 8 is a gate sidewall insulating film, 9 is an n-conductivity type high impurity concentration source region (n+ diffusion layer), 10 is an n-conductivity type high impurity concentration drain region (n+ diffusion layer), and has an LDD structure (Fig. 1). In the case of the DD trench structure (FIG. 2), the gate sidewall insulating film 8 is used as a mask, and in the case of the DD trench structure (FIG. 2), the gate electrode 4 is used as a mask when introducing impurities. 11 is a surface protection insulating film, 12 is a source electrode, and 13 is a drain electrode.

In the ultra-fine MO8 with the conventional structure shown in FIGS. 1 and 2, the drain applied voltage drops within the n conductivity type low impurity concentration source and drain regions (n-diffusion layer) 6 and 7, so this By arbitrarily controlling or widening the width of the n-diffusion layer, it is possible to achieve a high breakdown voltage that does not cause avalanche precipitation even when a drain voltage of 5V is applied in ultrafine MO8 having an effective channel length of 1 μm or less. Especially the first
In the LDD structure shown in the figure, as mentioned above, the low impurity concentration source and drain regions (n-diffusion layers) 6, 7
and high impurity concentration source and drain regions (n+ diffusion layer)
Since the impurity doping boundaries of 9.10 are different, it is theoretically possible to increase the breakdown voltage to any extent by widening the width of the gate sidewall insulating film 8. However, since part of the low impurity concentration source and drain regions 6 and 7 in the LDD structure is not covered with the gate electrode 4 as shown in the figure, the low impurity concentration source and drain regions 6 and 7 are controlled by the gate voltage. Can not do it. In other words, the low impurity concentration source and drain regions 6 and 7 in the LDD structure act as a series resistance, and in order to increase the withstand voltage, the current driving ability decreases as the width of the low impurity concentration source and drain regions 6 and 7 increases. There are disadvantages to this. This drawback negates the main purpose of miniaturizing semiconductor devices, which is high-speed operation.

Another drawback of the LDD structure arises from the fact that the impurity doping boundaries of the low impurity concentration source and drain regions 6 and 7 and the high impurity concentration source and drain regions 9 and 10 are different.

That is, in the LDD structure, after the low impurity concentration source and drain regions 6 and 7 are formed using the gate electrode 4 as a mask, the gate sidewall insulating film 8 is formed, and the gate sidewall insulating film 8 is used as a mask. High impurity concentration source and drain regions 9 and 10 are formed. However, since the gate sidewall insulating film 8 is left behind by sputter etching, the controllability of its width is usually poor.
It varies depending on the variation in the width. This manifests itself in variations in source-drain breakdown voltage characteristics and current drive capability, which significantly reduces manufacturing yield.

- In the case of Figure 2, in the DD trench structure, as mentioned above, the impurity introduction boundaries of the low impurity concentration source and drain regions 6°7 and the high impurity concentration source and drain regions 9°10 coincide. The fluctuation width of the low impurity concentration source and drain regions 6.7 is also small, and the problem of yield reduction can be ignored. Furthermore, since the surface portions of the low impurity concentration source and drain regions 6.7 are covered with the gate electrode 4, there is no problem with a decrease in current driving ability. Therefore, in this DD groove structure, in order to achieve high breakdown voltage, the low impurity concentration source and drain regions 6°7 are formed sufficiently deep, and the high impurity concentration source and drain regions 9 and 10 are formed sufficiently deep. Must be formed shallowly. However, with the current manufacturing method, it is technically difficult to form the highly impurity-concentrated source and drain regions 9 and 10 with a sufficiently shallow junction depth of 0.1 μm or less. On the other hand, if the depth of the low impurity concentration source and drain regions 6 and 7 is made sufficiently deep,
In the case of an ultrafine structure with an effective channel length of 1 μm or less, a punch-through phenomenon occurs between the source and drain, and the withstand voltage decreases, making it impossible to achieve a high withstand voltage. Furthermore, another disadvantage of the DD groove structure is that the capacitance between the gate electrode 4 and the low impurity concentration source region 6 and the high impurity concentration source region 9, and between the low impurity concentration drain region 7 and the high impurity concentration drain region 10 becomes large, and the high speed It is to obstruct movement.

[Object of the Invention] An object of the present invention is to eliminate the drawbacks of the conventional techniques described above, and to provide a semiconductor device having a sufficiently high source-drain breakdown voltage and a small degree of decrease in current drive capability.

[Summary of the invention]

The present invention is an ultra-fine MO3 source with a high breakdown voltage structure.
This was done based on the results of factor analysis regarding the phenomenon of decrease in drain current (hereinafter simply referred to as current). As mentioned above, in the conventional MO8 having an ultra-fine high breakdown voltage structure with an effective channel length of 1 μm or less, the LDD structure shown in FIG. 1 is superior in terms of high breakdown voltage characteristics. However, the source-drain breakdown voltage (hereinafter m is referred to as breakdown voltage).

) In the LDDJ structure that secures 9V, the current of the ultra-fine MO8 with an effective channel length of 0.3 μm is 20% compared to the current value of a normal MO8 with the same effective channel length under the condition that the gate and drain voltage is 5V. % also decreases. This current drop is due to the low impurity concentration source and drain regions (n- diffusion layers) 6 and 7 inserted into the current path.

The present inventors conducted a detailed numerical analysis of the current drop characteristics of various n-diffusion layer configurations, and found that the surface impurity concentration of the n-diffusion layer, the width of the n-diffusion layer, and the gate electrode
It has become clear that the coverage ratio of the diffusion layer is closely related to the current reduction characteristics. In particular, the effective channel length is 0.3
In the LDD structure MO8, which guarantees a source-drain breakdown voltage of about 9V with an ultra-fine MO8 of μm, n- and n
The optimal conditions are + width between boundaries of the diffusion mask forming the diffusion layer (distance between the edge of the gate electrode and the edge of the gate sidewall insulating film) 0.3 μm, n- diffusion layer surface impurity concentration 5 × 1017■-3, etc. In the case of a low concentration n-diffusion layer as described above, it has become clear that the biggest factor in the current reduction is that the gate electrode does not even partially cover the n-diffusion layer. Furthermore, the current decreasing tendency described above becomes particularly noticeable when the impurity concentration region below 1017G-3 is not covered with a gate electrode, and even when the impurity concentration region above 1017an-'' is not covered with a gate electrode. It has also become clear from the results of numerical analysis of MO8 characteristics that it does not significantly affect the current drop.

In other words, from the viewpoint of current reduction, it is not necessary to configure the source/drain impurity concentration to be as high as 1020 -3 or higher as in the conventional structure, but instead
It has become clear that the above is sufficient. Based on the above analysis results, the n+ diffusion layer, which was always installed in the conventional high voltage structure MO8, is meaningless in terms of increasing the voltage resistance of the MOS and preventing current drop, and it should be installed in the active region in the semiconductor substrate. It turns out that there is no necessity. That is, the n+ diffusion layer is required only to ensure good ohmic contact with the wiring electrode, and there is no problem even if it is formed 1afW on the semiconductor substrate in order to fulfill the above role.

Based on the above numerical analysis results, the present invention provides a diffusion layer having a high impurity concentration of 101311 or higher, which is necessary only for good ohmic contact with wiring electrodes, in a semiconductor thin film provided on a semiconductor substrate. The impurity-concentrated drain region is suitable for high breakdown voltage and has extremely low current drop10
It is composed of a diffusion layer with a thickness of "Qll-" or more and less than 10"cm-".

In other words, the basic idea of the present invention is the conventional ultra-fine, high-voltage M
The low impurity concentration drain region of O8 has overcome the two roles of high breakdown voltage and good ohmic contact, and in the semiconductor substrate, the entire low impurity concentration drain region can be used for strong electric field relaxation and large current. The goal is to limit the use of security only to the purpose of securing security, and to pursue its effectiveness to the utmost.

The first advantage of not providing a high impurity concentration diffusion layer in the semiconductor substrate is that an MO8 structure suitable for high breakdown voltage and large current can be realized with a smaller occupied area than conventional structures. This makes it possible to achieve high integration. In addition, the second advantage is that the source/drain diffusion layer provided in the semiconductor substrate is not a high impurity concentration layer, so it is possible to control the gate potential to some extent even in the source/train diffusion layer region, which is a serious drawback in ultrafine MO8. Two-dimensional effects such as a reduction in punch-through voltage or threshold voltage value, or short channel effects, can be alleviated.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

Note that important parts are shown enlarged in the drawings, so care must be taken.

Embodiment 1 FIGS. 3(a) to 3(c) are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, specific resistance 1Ω
・After selectively forming a 0.6 μm thick field oxide film 2 on the p-conductivity type silicon electrode wiring (■) using a known device isolation technique, the active region surrounded by this field oxide film 2 is 10n on the semiconductor surface by a known method.
A normal gate oxide film of 3 m and a silicon thin film 4 of 0.3 μm are successively formed. POCQ z for silicon thin film 4
A high concentration of phosphorus is diffused by thermal diffusion using a diffusion source.
Thereafter, a silicon oxide film 5 slightly doped with phosphorus and having a thickness of 0.2 μm was deposited on the entire surface by a known method. Next, a silicon thin film 4 and a silicon oxide film 5 are formed.
The layered film was processed by a known photolithography method to form a gate electrode 4 and a gate protection insulating film 5. Note that the length of the gate electrode 4 was 0.5 μm. Next, a silicon oxide film with a thickness of 0.1 μm was deposited on the entire surface by a chemical vapor phase reaction using tetraethoxysilane (sl(oczHi)4). When this silicon oxide film is etched only in the direction perpendicular to the semiconductor substrate surface using the reactive ion etching method and the silicon oxide film deposited on the flat areas is removed, the gate electrode 4 is etched as shown in FIG. 3(a). A silicon oxide film is left only on the sidewall portions of the gate protection insulating film 5, and a gate sidewall insulating film 8 can be formed. In this state, the gate electrode 4. Phosphorus was ion-implanted into the silicon substrate 1 through the gate oxide film 3 using the gate protection insulating film 5 and the gate sidewall insulating film 8 as masks at an acceleration energy of 30 KeV. Regarding the implantation amount of this ion implantation, various implantation amount conditions were set so that a surface impurity concentration of 1017 to 10102 Ga'' was finally obtained, and a large number of transistors were manufactured.After the above ion implantation,
The implanted ions are subjected to activation heat treatment, and the low impurity concentration source region 6 and the low impurity concentration drain region 7 are formed in the semiconductor substrate 1.
formed within. The above heat treatment was carried out at 950°C,
The heat treatment time was set so that the junction depth was 0.2 μm regardless of the implantation amount (30 minutes in this example). Subsequently, as shown in FIG. 3(a), the gate oxide film 3 exposed on the low impurity concentration source and drain regions 6 and 7 is removed.
was completely removed.

Next, as shown in FIG. 3(b), a silicon thin film with a thickness of 0.35 μm is deposited by a known method, and processed according to a desired circuit configuration by photolithography to form a source silicon electrode 1.
4. A silicon electrode wiring including a drain silicon electrode 15 was formed. In this state, arsenic is accelerated with an energy of 70Ka.
Ion implantation was performed under the following conditions: V, implantation amount: 5 x 10"m-".

This condition is an implantation condition in which the maximum impurity concentration occurs near a depth of approximately 43 nm from the surface of the silicon thin film.

After the ion implantation, the implanted ions were activated by short-time heat treatment at 1100° C. for 30 seconds.

The source silicon electrode 14 and the train silicon electrode 1 made of polycrystalline or amorphous material formed in this way
The diffusion coefficient of impurities in the source silicon electrode 14 and the drain silicon electrode 15 is 10 to 20 times larger than the diffusion coefficient in single crystal silicon. Therefore, the impurities in the source silicon electrode 14 and the drain silicon electrode 15 are Thin film inner material II R1,0” rs-3 or more M
* If i, O'' an-a is distributed almost uniformly, but the impurity distribution in the low impurity concentration source and drain regions 6.7 in the silicon substrate 1 is hardly affected.

The uniformly distributed impurity concentration within the source silicon electrode 14 and drain silicon electrode 15 (
A high impurity concentration layer having substantially the same concentration as 1021an-a) is also formed in the low impurity concentration source and drain regions 6 and 7 in the semiconductor substrate 1. However, the junction depth of the above-mentioned high impurity concentration layer is about 3
It is extremely shallow at 0 nm.

After a short period of high-temperature heat treatment, a third
As shown in Figure (Q), the surface protection insulating film 11 is deposited and holes are formed at desired locations, and the AQ film is deposited and etched to form the desired electrode wiring including the source metal electrode 12 and drain metal electrode 13. It was formed according to the circuit system of.

The relationship between source-drain breakdown voltage and source-drain current was measured for various MOSs with low impurity concentration source and drain regions 6 and 7 having different surface impurity concentrations C and l manufactured through the above manufacturing process. The source-drain breakdown voltage BvDll is measured under the conditions of the gate voltage and the substrate voltage Ov, and for the source-drain currents 2, , and 6, the substrate voltage is set to O2 and the gate voltage is V. and the drain voltage v, , were measured under the conditions of 5. '' Both applied voltages are values based on the source voltage. The BV□ value of the MOS manufactured according to this example was about 9■. Further, the IDa value under the above conditions was about 5.9 mA. Gate length manufactured based on this example: 0.5 μ
The effective channel length in a MOS of m is approximately 0.3 μm.
However, the known LDD was designed and manufactured so that the effective channel length and Bvl values matched those of this example.
In structure MO8, ID under the conditions of V, =V, =5V
The a value was 5.1 mA. Furthermore, this LDD
Structure MO8 includes low impurity concentration source and drain regions 6,
Junction depth of 7 is 0.1 μm, surface impurity concentration is 5
X 1017an-”, the distance between the low impurity concentration source region 6 or the low impurity concentration drain region 7 and the high impurity concentration source region 9 or the high impurity concentration drain region 10, that is, between the end of the gate electrode 4 and the end of the gate sidewall insulating film 8 were manufactured so that the distance between them was 0.3 μm (see Figure 1).
. In order to evaluate each of the above values, the effective channel length is 0.
3 μm normal structure MO8+1 was manufactured, but its BV□
The value was only 4.8v.

Under the conditions of V0=VI and '=5V in the normal structure M OS. , ■ for 8 values. By extrapolating the normal current-voltage characteristics in the saturation region of =V, =3V or higher, and assuming that there is no breakdown state, the value was calculated to be 6.4 mA. Comparing the above-mentioned engineering values for each structure MO8 with respect to the normal structure, it is found that in the LDD structure MO8, which is a known high breakdown voltage structure, a current drop of about 20% is unavoidable, whereas the same In the MOS of this example having high breakdown voltage characteristics, the current drop was suppressed to about 8%. The drop in current in the ultra-fine MO8 leads to a decrease in operating speed, which halves the greatest advantage of miniaturization. However, based on this example, <5> In the MO8 structure, while maintaining the conditions for using a normal power supply, With miniaturization, even higher speed operation is possible.

It can be seen that the size of the high breakdown voltage and ultra-fine MO8 based on this example is smaller than that of the conventional LDD structure MO8 having the same high breakdown voltage characteristics, and is also superior in integration. That is, when comparing the two in terms of the distance between the ends of the gate sidewall insulating film 8, it is 0.7 μm based on this example,
In the LDD structure, it is 1.1 μm. Therefore, based on this embodiment, in an MOS with a gate length of 0.5 μm, it is possible to miniaturize the gate length by as much as 0.4 μm, which is approximately the same as the gate length.

Another effect based on this embodiment is that the so-called short channel effect, in which the threshold voltage value decreases as the channel length decreases, is alleviated compared to the normal structure MO8. i.e.%
Compared to the threshold voltage value of a MOS with an effective channel length of 2 μm, the effective channel length is 0.8 μm and 0.5 μm, respectively.
While the threshold voltage values of the normal structure MO8 of μm at V=5V are lowered by more than 0.3 and 0.87, respectively, the effective channel length according to this embodiment is reduced by 0.8p, respectively.
The threshold voltage values of the MOSs designed and manufactured to be 0.5 μm, 0.5 μm, and 0.3 μm are respectively 0.5 μm and 0.3 μm. IV, 0
．． 2 V and Q, the decrease remained at 48 V. The above tendency for the threshold voltage value to decrease is due to the short channel effect (0.3 μm when the effective channel length is 0.3 μm) in the known LDD structure.
Although it is slightly inferior to V), it remains within a range that does not pose a problem in practical use.

Embodiment 2 FIGS. 4(a) to 4(c) are cross-sectional views showing the manufacturing process of a second embodiment of the present invention.

In the above-described first embodiment shown in FIGS. 3(a) to (Q), after forming the field oxide film 2, the desired area is covered with a photoresist film with a thickness of 1 μm, and the active areas not covered with the photoresist film are Phosphorus ions are implanted into a desired region within the region, and an n-conductivity type well 16 having a junction depth of 2 μm and a surface impurity concentration of 3×10"Cal-" is formed by subsequent heat treatment. Thereafter, a gate oxide film 3. is formed according to the first embodiment. Gate electrode 4. A gate protection insulating film 5 and a gate sidewall insulating film 8 made of a silicon oxide film are formed. Next, after selectively covering the well region 16 with a photoresist film, a low impurity concentration source region 6 and a low impurity concentration drain region 7 of n conductivity type are formed by implanting phosphorus ions according to the conditions of the first embodiment. . Next, the active region other than the well region 16 is selectively covered with photoresist II, and boron ions are implanted under the condition of an acceleration energy of 25 K e V. A p-conductivity type wave diffusion layer was selectively formed in the region. Thereafter, the photoresist film used as a mask for ion implantation was removed, and the implanted ions were activated by heat treatment to form a low impurity concentration source region 17 and a low impurity concentration drain region 18 of n conductivity type. Regarding the implantation amount of this ion implantation, various implantation amount conditions were set so that a surface impurity concentration of 1017 to 10"cs-" was finally obtained, and a large number of transistors were manufactured. The above ion implantation was activated by heat treatment at 800°C to 900°C, but the heat treatment time was independent of each implantation amount and the junction depth was 0.
．． Each was set to 2 μm. Next, as shown in FIG. 4(a), the n-conductivity type low impurity concentration source/drain regions 6, 7 and further the n-conductivity type low impurity concentration source/drain regions 17 and 18 are exposed. Gate oxide film 3 was completely removed.

Next, as shown in FIG. 4(b), a silicon thin film with a thickness of 0.35 μm is deposited and processed according to the desired circuit configuration by photolithography, forming the n-conductivity type source low concentration diffusion layer 6 and A source electrode 21 connecting the p-conductivity type source low concentration diffusion layer 17. A silicon electrode wiring including a first drain electrode 20 connected to the n-conductivity type low impurity concentration drain region 7 and a second drain electrode 22 connected to the n-conductivity type low impurity concentration drain region 18 was formed. Thereafter, a photoresist film is applied and processed to selectively cover the well region 16, and arsenic ions are accelerated with an energy of 70 KeV.
Arsenic was implanted into a part of the source electrode 21 made of a silicon thin film and into the first drain electrode 20 by ion implantation with an implantation amount of 5.times.10 "an-". Next, the photoresist film used as a mask for arsenic ion implantation was removed, and a second photoresist film 23 was formed to selectively cover areas other than the well region 16. In this state, boron ions are accelerated with an energy of 30 KeV and an implantation amount of IX 1.
．． Ion implantation was performed under the condition of O''cM-''.

1- After the boron implantation, the photoresist film 23 was removed and the implanted ions were activated by short-time heat treatment at 1100''C for 30 seconds according to the first example. The distribution of the low-concentration impurity layer in the substrate 1 hardly changes, while the highly impurity-concentrated n-conductivity type first drain electrode 20, p-conductivity type second drain electrode 22, and source consisting of n-conductivity type and p-conductivity shadow regions. Electrode 2
1 is formed in a silicon thin film with an impurity concentration of 10"Qll-" or more, for example 10"an-", with a substantially uniform distribution.

Further, as shown in FIG. 4(c), the high impurity concentration regions formed in the low impurity concentration source and drain regions 6 and 7 in the silicon substrate 1 are 3
It was extremely shallow, on the order of nm. After the above-mentioned short-time heat treatment, the surface protection insulating film 11 is deposited and holes are formed at desired locations in accordance with the first embodiment, and the AQ film is formed and etched to form the first drain metal electrode 24. Source metal electrode 25
And electrode wiring including the second drain metal electrode 26 was formed according to a desired circuit configuration.

By completing the above manufacturing process, a complementary insulated gate field effect transistor (hereinafter abbreviated as CMO3) is produced.

was manufactured, but in this 0MO3, the characteristics of high breakdown voltage and extremely small current reduction rate were realized in the ultrafine CMO3 as in the case of the first embodiment.

In 0MO3 of this example, all the outstanding effects obtained in the first example were obtained, but additional effects unique to this example were also found. That is, CMO8 of this example
In this case, element destruction due to the latch-up phenomenon, which was a serious drawback in the conventional structure CMO8, is significantly alleviated. The latch-up phenomenon of 0MO3 is caused by the n-conductivity type low impurity concentration drain region 7. Silicon substrate 1. Well region 16 and p-type low impurity concentration source region 18
A parasitic thyristor having an npnp structure in between starts operating when triggered by the application of an overvoltage or an internal transient overvoltage during normal switch operation, and the thyristor operation cannot be suppressed until the power supply is stopped, destroying the transistor. It is known that this phenomenon occurs because the distance between each diffusion layer is reduced with the miniaturization of the CMO 3, and the product of the current gain factors of the parasitic pnp bipolar transistor and the parasitic npn bipolar transistor becomes larger than 1.

To evaluate the anti-latch-up characteristics of CMO3 of this example, the following were measured. That is, the n-conductivity type drain diffusion layer 7 is used as an emitter, the semiconductor substrate 1 is used as a base, and the well region 16 is used as an emitter.
The current gain factor β of a parasitic npn transistor with the collector being , and the current gain factor β2 of the parasitic pnp transistor having the p conductivity type low impurity concentration source region 17 as the emitter, the well region 16 as the base, and the silicon substrate 1 as the collector.
The product β, β, was measured. In this measurement, a voltage of 5μ was applied between the base and collector, and a voltage of 10-6 to 1O-2A was applied.
The product β,·β, was determined as a function of the emitter current in the range of . As a result, the ns@ type low impurity concentration drain region 7
and the surface impurity concentration of the p conductivity type low impurity concentration drain region 18 are both 5 x 10"s-", 1 x 10i
each β1 in each transistor with an effective channel length of 0.3 μm and 3 × 1017co-’
・The highest values of β and product were all between 10-2 and 10-4. The above value is the condition β for latch-up to occur.

・β≧1 was not satisfied, and based on this example, it was found that <CMO8 was excellent from the viewpoint of anti-latch-up characteristics. Note that CMO3 with the above drain surface impurity concentration set to 10"am-' or more was also manufactured at the same time, but the product β, ·β, increases as the drain surface impurity concentration increases, and the minimum value was 0.1 or more. Ta.

That is, it was found that in CMO3 having a drain surface impurity concentration of 10"C!l-" or more, the anti-latch-up characteristics were also inferior compared to the above results.

In addition, in the above-mentioned first embodiment, for the sake of explanation,
Although a so-called n-channel type MO8 has been described in which a conductive silicon substrate 1 is used and source and drain regions are formed with n-conductivity type impurities, the semiconductor device based on the present invention is limited to the n-channel type in the above case. The present invention can also be applied to a so-called p-channel type MO8, which is composed of an n-conductivity type semiconductor substrate and a source region and a drain region made of p-conductivity type impurities.

Further, the present invention is not limited to the above-mentioned single MO8, and the present invention is also applicable to semiconductor integrated circuit devices in which the gate insulating film is silicon nitride film, alumina film, titanium oxide film, tantalum oxide film, silicophosphoric glass acid, silicoborate glass. The present invention can also be applied to a so-called MIS-type structure composed of a film or a superimposed film of the above-mentioned insulating films including a silicon oxide film, and an integrated circuit thereof.

Furthermore, the present invention is not limited to insulated gate field effect transistors, but can also be applied to Schottky gate field effect transistors. Further, the substrate is not limited to silicon, and may be a compound semiconductor such as GaAs.

In the above embodiment, an example is described in which a short time high temperature heat treatment method is used as a heat treatment method for the high concentration ion implantation layer. It may be based on other methods such as irradiation method or electron beam irradiation method. Further, the source/drain silicon electrodes 14, 15 are not limited to polycrystalline or amorphous, but may be single crystal.

In this case, the high concentration source/drain diffusion layer does not need to reach the surface of the semiconductor substrate, but only needs to be present at the lowest silicon thin film surface portion.

〔Effect of the invention〕

According to the present invention, it is possible to obtain an ultra-fine MO8 that can operate with a normal power supply of 5V and can improve the current drop by 1.2% or more compared to the conventional structure. In this MOS,
Since the source or drain region with high impurity concentration is placed on the semiconductor substrate, the effective channel length is 0.3 μm.
The ultra-fine MO8 of m has the effect of being able to be reduced in size by about 0.4 μm compared to the high breakdown voltage MO3 having a known LDD structure. Furthermore, according to the present invention, there is also the effect of suppressing the tendency of threshold voltage reduction, so-called short channel effect, to be within a practically acceptable range of 0.5 V or less even in the case of an effective channel length of 0.3 μm. are doing.

Furthermore, according to the present invention, it is possible to completely prevent the latch-up phenomenon that has been a serious problem in ultra-fine complementary insulated gate field transistors with conventional structures, so that the ultra-fine trap type insulated gate field transistor can be completely prevented without impairing high-speed operation. It is possible to realize a transistor.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing a conventional LDD structure MOS, Figure 2
The figure is a cross-sectional view showing a MOS with a conventional DD tank structure.
Figures (a) to (c) are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and Figures 4 (a) to (o) are cross-sectional views showing a semiconductor device according to a second embodiment of the present invention. It is a sectional view showing the JL construction process. 1... Silicon substrate, 2... Field oxide film, 3
...Gate oxide film, 4...Gate electrode, 5...Gate protection insulating film, 6.17...Low impurity concentration source region, 7゜18...Low impurity concentration drain region, 8...
- Gate sidewall insulating film, 9... High impurity concentration source region, 10... High impurity concentration drain region, 11... Surface protection insulating film, 12... Source electrode - 113... Drain electrode, 14 ...Source silicon electrode, 15...
Drain silicon electrode, 16... Well region, 20.
...first drain electrode, 21...source electrode, 22
...Second DoreY

Claims (2)

[Claims] 1. A gate electrode, a gate sidewall insulating film formed adjacent to the end of the gate electrode, and a gate electrode having a conductivity type opposite to that of the semiconductor substrate, and introduced into the semiconductor substrate with the end of the gate sidewall insulating film as an impurity introduction boundary. ^1^7cm^-^3 or more 1
A low impurity concentration drain region with a surface concentration of less than 0^2^0cm^-^3, and a 10^1^9 layer adjacent to the gate sidewall insulating film and formed on the low impurity concentration drain region.
1. A semiconductor device comprising: a semiconductor thin film having a high impurity concentration of cm^-^3 or more. 2. 2. The semiconductor device according to claim 1, wherein the semiconductor thin film has p conductivity type.