JPS61156882A - Double-diffused igfet and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the breakdown at the time of switch-on by the difficulty of a parasitic transistor to turn on, by a method wherein the second conductivity type region of high temperature is provided immediately under a source region in the base region of the titled device. CONSTITUTION:A P-type base region 33 of high temperature is formed in an N-type drain region 32 of low concentration which has been formed on an N-type layer 31 of high concentration, and a P-type base region 34 of low concentration serving as the channel thereon. A P-type base region 35 of high concentration is formed in the P-type base region 34, and an N-type source region 36 thereon. Since the FET is largely reduced in base resistance and is provided with a P-N diode made of the base regions 34, 35 and the drain region 32, it becomes strong to breakdown without the action of the parasitic transistor.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a double diffused insulated gate field effect transistor (hereinafter abbreviated as D-MOSFET) in which the length of the channel is determined by impurity diffusion in the base and source. ) and its manufacturing method, and particularly relates to a D-MOSFET used as a switching element.

[Technical Background of the Invention] Conventionally, the source electrode portion of an N-channel D-MOSFET has a structure as shown in FIG. 3(a). In the figure, 11 is a highly doped N-type layer of the semiconductor substrate, and a drain region tJlt12 made of a lightly doped N-type layer formed by epitaxial growth is formed on this highly doped N-type layer 11. There is. In this drain region 12, there is a high concentration,
A P-type base region 13 is formed, and this base region 14!
A lightly doped P-type base region 14 that becomes a channel is formed on the base region 13 . Furthermore, N is present in the P-type base region 14.
A type source region 15 is formed. drain region 12
On the base region 14 between and the N-type source region 15,
A polycrystalline silicon film 17 serving as a gate electrode is formed via a gate isolation RIA 16. This polycrystalline silicon film 17 is covered with interlayer insulation M18, and this interlayer insulation!
! A source wiring electrode 20 is provided through a source contact opening 19 provided at 18 .

Figures 4(a) to (e) show D-MOSFETs with the above structure.
This shows a method of manufacturing. That is, first, the same figure (
As shown in a), an oxide film (SiO2) 21 is formed on the surface of a semiconductor substrate having a highly doped N-type layer 11 and a lightly doped N-type drain region 12. Next, this oxide film 2
After forming an opening 22 in the semiconductor substrate 1, a P-type impurity is diffused into the semiconductor substrate exposed within the opening 22 to form a highly-concentrated P-type base region 13.

Next, as shown in FIG. 2B, after removing the oxide film 21, the semiconductor substrate is oxidized again to form a gate insulating film (SiO2) 16 on this substrate. Polycrystalline silicon 1117 is deposited on film 16.

Next, as shown in the same figure (C), polycrystalline silicon g! 1
After forming an opening 23 in 7, P-type impurity ions are implanted into the semiconductor substrate through the gate insulating film 16 exposed in the opening 23. After that, by performing diffusion,
A P-type base region 14 extending outward from the opening 23 is formed. The impurity concentration and diffusion depth of this base region 14 are as shown in FIG.
It is smaller than those in the mold base region 13.

Next, as shown in FIG.
The resist 1124 is left in the opening 23 and then N-type impurities are ion-implanted into the semiconductor substrate exposed in the opening 23 using a graving technique. Subsequently, diffusion is performed to form an N-type source region 1 with a shallow diffusion depth directly under the opening 23, as shown in FIG.
form 5.

After that, as shown in FIG.
An interlayer insulating film (SiO2) is formed on 7 by, for example, the CVD method.
After forming, an opening 19 is formed by PEP, and a source wiring electrode 20 is roughly formed on the interlayer insulating film 18.

As a result, the D-MOSF with the structure shown in Fig. 3<8)
ET is obtained.

[Problems with Background Art] However, the D-MOSFET of the conventional structure has the following problems. That is, N type source region 1
5. P-type base region 13.14 and N-type drain region 1
It has a structure in which there is an NPNiF raw transistor Tn consisting of . Since the action of this strange transistor Tn is mainly performed in the base Ij region 14 which becomes a channel, the resistance of the base region 14 directly under the source region 15 is set to R.
a, then the D-MOSFET and this parasitic transistor Tn are equivalently shown in FIG. 3(b). That is, the emitter of this parasitic transistor corresponds to the N-type source region 15, the base corresponds to the P-type base region 14', and the collector corresponds to the N-type drain region 12, respectively.

By the way, this element is often used for motor drives and switching regulator type power supplies,
If the switch is turned off during such no-load operation, a large back electromotive force will be applied between the drain and source of the D-MOSFET. Also, the same figure (b
) Regarding the equivalent circuit of There was a drawback. D- due to parasitic transistor Tn
Preventing destruction of a MOSFET is extremely important for increasing the breakdown voltage of this element, and a method for preventing the effects of such anomalous transistors has been desired.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a high-voltage double diffused insulated gate field effect transistor that can prevent destruction during switch-off operation, and a method for manufacturing the same. It's about doing.

[Summary of the Invention] The present invention provides a drain region made of a first conductivity type semiconductor substrate, a second conductivity type drain region formed in the semiconductor substrate,
- a source region of a first conductivity type formed in the base region, and a gate electrode formed on the base region between the drain region and the source region via an insulating film. In the double-diffused insulated gate field effect transistor, a highly doped second conductivity type region is provided in the base region directly below the source region.

With such a structure, the base resistance can be significantly reduced, making it difficult for the parasitic transistor to turn on, thereby preventing destruction when the switch is turned on.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1(a), 31 is an N-type layer of silicon substrate; 1. A drain region 32 made of a lightly doped N-type layer formed by epitaxial growth is formed on this heavily doped N-type layer 31 .

In this drain region R32, there is a highly doped P-type base region 33.
' is formed, and a lightly doped P-type base region 34 serving as a channel is formed on this base region 33. In this P type base region 34, there is a highly concentrated P type base region 35.
is formed, and an N-type source region 1136 is further formed on this P-type base region 35.

On the base region 34 between the drain region [32 and the N-type source region 36, a gate 'i
! A polycrystalline silicon film 38 which becomes tLai is formed.

This polycrystalline silicon film 38 is covered with an interlayer insulating film 39, and through a source contact opening 40 provided in this interlayer insulating film 1I39, a film made of, for example, AI (aluminum)
A source wiring electrode 41 is provided.

That is, in the above D-MO3FET, a highly doped P-type base region 35 is formed directly below the source region 36.

With such a structure, as is clear from the equivalent circuit diagram shown in FIG.
A PN diode is formed. In other words, it can be seen that unlike the conventional transistors, the parasitic transistor does not operate, and there is no influence during switch-off operation, and therefore, it is resistant to destruction.

This effect can be considered as follows.

That is, in this D-MOSFET, when the base resistance R'a is large due to breakdown, a potential difference of 8G is generated across the resistance Re, and the source region 36 (corresponding to the emitter) and the base region 35 are forward biased. Therefore, electrons are injected from the source region 36, and as a result, the parasitic transistor is turned on. Roughly speaking, holes generated due to avalanche doubling within the base fI4 region flow into the source side, and the current increases rapidly, creating a hot spot, leading to destruction.

This potential difference VBE is the source! [It is related to the resistance Re in the base region immediately below 36, that is, the base concentration. In order to prevent the parasitic transistor from turning on, it is necessary to reduce this resistance Ra, that is, to make the base concentration directly below the source region 36 high. As shown in FIG. 3(a), the conventional D-MOSFET structure has a high concentration base region [13] due to the deep diffusion depth
Since the concentration of 4 determines the threshold voltage of the D-MOSFET, it was not possible to increase the concentration directly under the source region 15.

Therefore, in the present invention, a highly doped P-type base region 35 is provided directly below the source region 36 to reduce the base resistance Ra. It is most preferable that the region where the base region R35 is formed extends entirely directly below the source region 36, and only the side surface of the diffusion layer of the source region 36 is in contact with the base region 34.

Therefore, as a method for forming the base region 1g35, in the present invention, CVD is applied to the side surface of the opening of the polycrystalline silicon film 38, which serves as a double diffusion mask for the base region 34 and the source region 36.
(Chemical Vapor Repository
On) A self-alignment (self-alignment) method is employed in which a portion of the film is left.

Hereinafter, a method for manufacturing the above structure will be specifically explained.

First, as shown in FIG. 2(a), a! m degree N-type layer 31
Then, an oxide film (Si02) 51 is formed on the surface of the silicon substrate having the drain a region 32 made of a low concentration N-type layer. Subsequently, after an opening 52 is formed in this oxide film 51, a P-type impurity is diffused into the silicon substrate exposed in this opening 52 to form a heavily doped P-type base region 33.

Next, as shown in FIG. 5B, the oxide film 51 is removed and the silicon substrate is oxidized again to form a gate insulating film (SiO2) 37 on this substrate. A polycrystalline silicon film 38 is deposited thereon.

Next, as shown in FIG. 5C, an opening 53 is formed in the polycrystalline silicon film 38, and then P-type impurity ions are implanted into the silicon substrate through the gate insulating film 31 exposed in the opening 53. Then, by diffusing the ion-implanted impurity, a P-type base region 34 that spreads outside the opening 53 and becomes a channel is formed. The impurity concentration and diffusion depth of this base region 34 are smaller than those of the previously diffused high concentration P type base region 33, as shown in FIG. The process up to this point is the same as the conventional process.

Next, as shown in FIG. 4(d), the gate oxide film 37 in the opening 53 is removed, a two-layer CVD II 154 consisting of non-doped CVDII and phosphorus-doped CVD II is formed, and melt-door annealing is performed at a high temperature. "By making the CVD 1156 on the side of the opening 53 thicker than other areas,
Form smoothly. Next, reactive ion etching (R
When the CVD film 54 is removed by IE) to expose the silicon substrate and the polycrystalline silicon film 38 at the center of the opening 53 and the etching is stopped, the thickness of the CVD film 5 is 5 as shown in FIG. A width approximately equal to the thickness of the CVD 11-54 is left.

Next, a P-type impurity such as boron is ion-implanted at a high concentration and diffused into the P-type base region 3.
form 5. At this time, the P-type base region 35 is formed in a self-aligned manner at a distance approximately equal to the film width of the CVD1lI55 from the opening 53 of the polycrystalline silicon film 38, serving as a mask for implantation of the CVD film 5 to a thickness of 5.

Next, as shown in FIG. 5F, after removing the CVD film 5 to a thickness of 5, a resist film 56 is left in the center of the opening 53 by PEP, and an N-type impurity such as phosphorus is ion-implanted and diffused to form a source. Region 1a36 is formed. Next, as shown in FIG. 3(Q), after removing the resist film 56, the interlayer insulation 1! Form $39. Next, an opening 4 is formed in the interlayer insulation ll39 using PEP.
0 is formed, and the opening portion 40 and the interlayer insulating film 39 are roughly formed.
When a source wiring electrode 41 of A1, for example, is formed thereon, the structure shown in FIG. 1(a) is obtained.

In this way, in the present invention, the high concentration base region 35
As a method of forming base region @34 and drain region [3
A part of the CVD film 54 (the thickness of the CVD film 5 is 5) is placed on the side surface of the opening of the polycrystalline silicon film 38 which serves as a double diffusion mask in No. The width from the source region 36 is determined in a self-aligned manner, and therefore it is possible to reduce this width to 1μ or less (the limit for normal PEP is 2 to 3μ), and also to cover almost the entire surface immediately below the source region 36. It becomes possible to form the P-type base region 35 across the P-type base region 35. Therefore, the base-emitter voltage VBE of the parasitic transistor becomes smaller, making it more difficult to turn on.

In the above embodiments, the present invention was explained as an example in which the present invention was applied to a D-MOSFET with an N-channel structure, but the present invention is not limited to this, and
-Of course, it can also be applied to MOSFET.

[Effects of the Invention] As described above, according to the present invention, the base resistance can be significantly reduced compared to the conventional structure, so that the on-operation of an anomalous transistor can be prevented, and the double-diffused insulated gate field transistor is resistant to destruction. can be provided.

Furthermore, according to the manufacturing method of the present invention, since the position of the highly doped base region is determined in a self-aligned manner, it is possible to form the highly doped base region on almost the entire surface directly under the source region. is more difficult to turn on and can achieve even higher voltage resistance.

[Brief explanation of the drawing]

FIG. 1 shows the structure of a D-MOSFET according to an embodiment of the present invention. FIG. 1(a) is a cross-sectional view, FIG. 2(b) is an equivalent circuit diagram, and FIG. - Cross-sectional view showing the manufacturing process of MOSFET, Figure 3 shows the structure of a conventional D-MOSFET, Figure (a) is a cross-sectional view, Figure (b) is an equivalent circuit diagram, Figure 4 is a FIG. 4 is a cross-sectional view showing the manufacturing process of the D-MOSFET shown in FIG. 3; 31... High concentration N type layer, 32... Drain region, 3
3...High concentration P type base region, 34...Low concentration P type base region, 35...High 11 degree P type base region, 36
... Source region, 37... Gate insulating film, 38...
・Polycrystalline silicon film, 39... Interlayer insulating film, 41...
・Source wiring electrode. Applicant's agent Patent attorney Takehiko Suzue N1! IJ (a) (b) Figure 2

Claims (1)

[Claims] (1) a drain region made of a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed in this semiconductor substrate, a source region of a first conductivity type formed in this base region, In a double diffused insulated gate field effect transistor comprising a gate electrode formed on a base region between the drain region and the source region with a gate insulating film interposed therebetween, the source region in the base region; A double diffused insulated gate field effect transistor characterized by having a highly doped second conductivity type region directly below it. (2) a drain region made of a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed in this semiconductor substrate, a source region of a first conductivity type formed in this base region; A method for manufacturing a double diffused insulated gate field effect transistor comprising a gate electrode formed on a base region between the drain region and the source region with a gate insulating film interposed therebetween. forming a second conductivity type base region in the drain region made of the semiconductor substrate;
forming a highly concentrated second conductivity type region in the base region in a self-aligned manner leaving an insulating film on the side surface of the diffusion mask opening in the base region; and forming a first conductivity type region on the second conductivity type region. a step of forming a conductive type source region, a step of forming a gate electrode on a base region between the drain region and the source region via a gate insulating film, and a step of forming an interlayer over the entire surface of the semiconductor substrate including the gate electrode. After forming the insulating film,
A double diffusion type insulation comprising the steps of selectively removing a part of the interlayer insulating film on the base region and the source region, and forming source, gate, and drain electrodes. A method of manufacturing a gate field effect transistor.