JPS62229977A - Manufacture of conduction-modulation mosfet - Google Patents
Manufacture of conduction-modulation mosfetInfo
- Publication number
- JPS62229977A JPS62229977A JP7115986A JP7115986A JPS62229977A JP S62229977 A JPS62229977 A JP S62229977A JP 7115986 A JP7115986 A JP 7115986A JP 7115986 A JP7115986 A JP 7115986A JP S62229977 A JPS62229977 A JP S62229977A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base layer
- type
- mask
- type base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 2
- 230000004913 activation Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、導電変調型ＭＯＳＦＥＴの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a conductivity modulation type MOSFET.
（従来の技術）
従来の一般的な導電変調型ＭＯＳＦＥＴの構造を第３図
に示す。２１はｐ＋型トド９４２層２２はｎ＋型バッフ
ァ層、２３はｎ型高抵抗層である。高抵抗層２３表面に
ゲート絶縁膜２４を介してゲート電極２５が形成され、
このゲート２１！極２５に自己整合されてｐ型ベース層
２６およびｎ＋＋ソース１１２７が形成されている。ｐ
型ベース層２６表面のｎ＋＋ソース層２７とｎ型高抵抗
！１２３に挟まれた領域がチャネル領域となっている。(Prior Art) The structure of a conventional general conductivity modulation type MOSFET is shown in FIG. Reference numeral 21 indicates a p + -type layer 22 is an n + -type buffer layer, and reference numeral 23 indicates an n-type high resistance layer. A gate electrode 25 is formed on the surface of the high resistance layer 23 via a gate insulating film 24,
This gate 21! A p-type base layer 26 and an n++ source 1127 are formed self-aligned to the pole 25. p
N++ source layer 27 on the surface of type base layer 26 and n-type high resistance! The region sandwiched by 123 is a channel region.
ｐ型ベースＭ２６の中央部にはその低抵抗化のためにｐ
＋型層２８が深く拡散形成されている。There is a p-type base in the center of the p-type base M26 to reduce its resistance.
A + type layer 28 is formed by deep diffusion.
ゲート電極２５および拡散層が形成された基板上はＣｖ
Ｄ絶縁膜２９により覆われ、これにコンタクト孔が開け
られてｎ′″型ソース層２７およびｐ型ベース唐２６に
同時にコンタクトするソース電極３０が形成されている
。基板裏面のドレイン層２１にはドレイン電極３１が形
成されている。On the substrate on which the gate electrode 25 and the diffusion layer are formed, Cv
It is covered with a D insulating film 29, and a contact hole is formed in this to form a source electrode 30 that contacts the n'' type source layer 27 and the p type base layer 26 at the same time. A drain electrode 31 is formed.
この様な導電変調型ＭＯＳＦＥＴにおける大きい問題は
、ｎ＋型ソース層２７−ｐ型ベース唐２６−ｎ型高抵抗
１１！２３−ｐ＋型ドレイン！２１で構成される寄生サ
イリスタがラッチアップすることである。寄生サイリス
タを構成するｎエミッタおよびｐベースとなるｎ＋型ソ
ース層２７およびｐ型ベース唐２６はソース電極３０に
より短絡されているが、ドレイン層２１から流れて来る
正孔電流がｐ型ベース！Ｉ２６に入り込みソース電極２
７に扱ける時、ｐ型ベース層２６内で電圧降下が生じ、
この電圧降下でｎ＋型ソースＷＩ２７とｐ型ベース層２
６間が順バイアスされるとラッチアップを生じる。この
状態ではゲート電圧を零にしても素子をターンオフでき
なくなる。この様な寄生サイリスタのラッチアップを防
止するために、ｐ型ベース層２６中央部に深くｐ＋型層
２８を形成して、ｐ型ベース唐２６の抵抗を小さくして
いるのである。The big problem with such a conductivity modulation type MOSFET is the n+ type source layer 27-p type base layer 26-n type high resistance layer 11!23-p+ type drain! The problem is that the parasitic thyristor composed of 21 latches up. Although the n+ type source layer 27 and the p type base layer 26, which constitute the n emitter and p base constituting the parasitic thyristor, are short-circuited by the source electrode 30, the hole current flowing from the drain layer 21 flows into the p type base! Source electrode 2 enters I26
7, a voltage drop occurs within the p-type base layer 26,
With this voltage drop, the n+ type source WI27 and the p type base layer 2
6 is forward biased, latch-up occurs. In this state, the device cannot be turned off even if the gate voltage is reduced to zero. In order to prevent such latch-up of the parasitic thyristor, a p + -type layer 28 is formed deeply in the center of the p-type base layer 26 to reduce the resistance of the p-type base layer 26 .
ところで従来、ラッチアップ防止用のｐ＋型層２８は、
マスク合わせによりｐ型ベース唐２６の中央部に位置す
るように形成されているが、これを完全にｐ型ベース唐
２６の中央に形成することは難しかった。そしてｐ＋型
［１２８がｐ型ベース唐２６の中央からずれて形成され
ると、ｐ＋型層２８を形成したことの意味がなくなるだ
けでなく、新たな問題が生じる。By the way, conventionally, the p+ type layer 28 for latch-up prevention is
Although it is formed so as to be located in the center of the p-type base plate 26 by mask alignment, it was difficult to form it completely in the center of the p-type base plate 26. If the p+ type layer 128 is formed offset from the center of the p type base layer 26, not only the formation of the p+ type layer 28 becomes meaningless, but also a new problem arises.
第４図は、ｐ４″型ＷＩ２８がｐ型ベース１！２６の中
央部からずれて形成された様子を示している。FIG. 4 shows how the p4'' type WI 28 is formed offset from the center of the p type base 1!26.
この状態では、図の右側のｎ＋型ソース層２７下のｐ型
ベース唐２６の抵抗が低下せず、ｐ＋型層２８を入れた
効果が出ない。また図の左側のｎ＋型ソース層２７につ
いて見ると、ｐ４′４層型８がこのソース層２７を越え
て形成された場合、チャネル領域の不純物濃度が上昇す
る結果、ＭＯ８ＦＥ下のしきい値電圧が上がってしまう
。In this state, the resistance of the p-type base layer 26 under the n+-type source layer 27 on the right side of the figure does not decrease, and the effect of inserting the p+-type layer 28 is not produced. Also, looking at the n+ type source layer 27 on the left side of the figure, if the p4'4 layer type 8 is formed beyond this source layer 27, the impurity concentration in the channel region increases, resulting in a lower threshold voltage under MO8FE. will rise.
（発明が解決しようとする問題点）
以上のように従来の導電変調型ＭＯＳＦＥＴでは、ラッ
チアップ防止用のｐ＋型層をマスク合わせで形成してい
るために、位置あわせが難しく、僅かのマスク合わせず
れにより所望の素子特性が得られなくなり、歩留りが低
いものとなる欠点があった。(Problems to be Solved by the Invention) As described above, in the conventional conductivity modulation type MOSFET, the p+ type layer for latch-up prevention is formed by mask alignment, so alignment is difficult and slight mask alignment is required. Due to the misalignment, desired device characteristics cannot be obtained, resulting in a low yield.
本発明はこの様な従来の問題を解決して、優れた素子特
性を歩留りよく得ることを可能とした導電変調型ＭＯＳ
ＦＥＴの製造方法を提供することを目的とする。The present invention solves these conventional problems and provides a conductive modulation type MOS that makes it possible to obtain excellent device characteristics at a high yield.
The present invention aims to provide a method for manufacturing an FET.
「発明の構成」
（問題点を解決するための手段）
本発明は、Ｍ１導電型ドレイン層上に第２導電型の高抵
抗層を有する基板上にゲート絶縁膜を介して多結晶シリ
コン膜によりゲート電極を形成する際に、同じ多結晶シ
リコン膜によりゲート電極に隣接して第１のマスク材を
形成し、この第２のマスク材とゲート電極の間を第２の
マスク材で覆って、これら第１．第２のマスク材および
ゲート電極をマスクとして用いて不純物をドープして第
１導電型ベース層の低抵抗化のための第１導電型の高不
純物濃度層を形成する。この後第２のマスク相続いて第
１のマスク材を除去して、従来と同様にゲート電極をマ
スクとして用いて不純物をドープして第１導電型ベース
層および第２導電型ソース層を形成する。なお第１導電
型ベース層形成のための不純物ドーピングは、ゲート電
極と第１のマスク材を形成した後、第２のマスク材を形
成する前に行ってもよい。"Structure of the Invention" (Means for Solving Problems) The present invention provides a structure in which a polycrystalline silicon film is formed on a substrate having a high resistance layer of a second conductivity type on a drain layer of an M1 conductivity type via a gate insulating film. When forming the gate electrode, a first mask material is formed adjacent to the gate electrode using the same polycrystalline silicon film, and the space between the second mask material and the gate electrode is covered with a second mask material, These first. Using the second mask material and the gate electrode as a mask, impurities are doped to form a first conductivity type high impurity concentration layer for lowering the resistance of the first conductivity type base layer. Thereafter, the second mask is applied, the first mask material is removed, and impurities are doped using the gate electrode as a mask to form a first conductivity type base layer and a second conductivity type source layer. . Note that impurity doping for forming the first conductivity type base layer may be performed after forming the gate electrode and the first mask material and before forming the second mask material.
（作用）
本発明の方法を用いれば、ベース層の低抵抗化のための
高不純物濃度層は、ゲート電極と同時にパターン形成さ
れる第１のマスク材により端部が定義されて、ベース層
中央部にセルファラインされて形成される。従って、優
れた特性の導電変調型ＭＯＳＦＥＴを歩留りよく得るこ
とができる。(Function) When the method of the present invention is used, the ends of the high impurity concentration layer for reducing the resistance of the base layer are defined by the first mask material that is patterned at the same time as the gate electrode, and It is formed by self-lining in the area. Therefore, conductivity modulation type MOSFETs with excellent characteristics can be obtained with a high yield.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）〜（ｄ）は一実施例の製造工程断面図であ
る。（ａ）に示すように、ｐ＋＋ドレイン層１上にｎ“
型バラフッ層２を介してｎ型高抵抗１１３が形成された
基板に、ゲート絶縁ｌＩ４を介して多結晶シリコン膜に
よりゲート電極５１を形成する。このときゲート電極５
１と同じ多結晶シリコン膜により、ゲート１ｆｆ１５１
から所定距離離れた島状の第１のマスク材５２を形成す
る。図では、平面パターンは特定されていないが、ソー
ス領域をストライブ状のものとする場合は、この第１の
マスク材５２はゲート電ｔｉ５ｔ と並行して走るスト
ライブ状のパターンになり、またソース領域を島状のも
のとする場合は第１のマスク材５２はゲート電極５１で
囲まれた領域内に閉路をなして形成されることになる。FIGS. 1(a) to 1(d) are cross-sectional views of the manufacturing process of one embodiment. As shown in (a), n“ is formed on the p++ drain layer 1.
A gate electrode 51 is formed of a polycrystalline silicon film on a substrate on which an n-type high resistance 113 is formed with a gate insulating lI4 interposed therebetween. At this time, the gate electrode 5
The gate 1ff151 is made of the same polycrystalline silicon film as in 1.
An island-shaped first mask material 52 is formed at a predetermined distance from the substrate. Although the planar pattern is not specified in the figure, if the source region is made into a stripe-like pattern, this first mask material 52 will have a stripe-like pattern running parallel to the gate electrode ti5t, and When the source region is formed into an island shape, the first mask material 52 is formed in a closed circuit within the region surrounded by the gate electrode 51.
これらゲート電極５１および第１のマスク材５２は同じ
ＰＥＰ工程でパターン形成されるから、その相対位置関
係はＰＥＰのマスク合わせずれの影響がなく、一定に保
たれる。この後（ｂ）に示すように、ゲート電極５１と
第１のマスク材５２の間を覆う第２のマスク材を例えば
フォトレジストにより形成し、例えばボロンをイオン注
入してｐ＋＋層７を形成する。このときイオンはゲート
絶縁ＩＩ！４のみの部分は通過するが、第１．第２のマ
スク材５２，６およびゲート電極５１のある部分は通過
できない。Since the gate electrode 51 and the first mask material 52 are patterned in the same PEP process, their relative positional relationship is not affected by misalignment of the PEP mask and is kept constant. After this, as shown in (b), a second mask material covering between the gate electrode 51 and the first mask material 52 is formed using, for example, a photoresist, and a p++ layer 7 is formed by ion-implanting boron, for example. . At this time, the ions are gate insulation II! Only the part 4 passes through, but the part 1. Certain portions of the second mask materials 52 and 6 and the gate electrode 51 cannot pass through.
こうしてゲート電極５１のエツジから所定距離離れた領
域にイオン注入が行なわれる。この後筒２のマスク材６
を除去し、改めてゲート電極５１を覆うレジストを形成
して第１のマスク材５２をエツチング除去し、熱処理を
行ってｐ＋＋層７の不純物の活性化と拡散を行う。そし
て（Ｃ）に示すように、従来と同様の二重拡散法により
ｐ型ベース層８およびｎ＋＋ソース層９を形成する。即
ち先ず、ゲート電Ｎ ５ Ｌをマスクとして不純物をド
ープしてｐ型ベース層８を形成し、更にｐ型ベース層８
中央部にマスクを形成してこのマスクとゲートＮ極５１
をマスクとして不純物をドープしてｎ＋＋ソース層９を
形成する。この後（ｄ）に示すように、全面をＣｖＤ絶
縁膜１０で覆い、コンタクト孔を開けてＡ２膜を蒸着し
、ｎゝ型ソース層９とｐ型ベース層８に同時にコンタク
トするソース１極１１を形成する。ドレイン１１１側に
は、Ｖ−Ｎ ｔ−Ａｕの３層金属の蒸着によりドレイン
電極１２を形成する。In this way, ion implantation is performed in a region a predetermined distance away from the edge of gate electrode 51. This mask material 6 of the rear tube 2
is removed, a resist is again formed to cover the gate electrode 51, the first mask material 52 is etched away, and a heat treatment is performed to activate and diffuse impurities in the p++ layer 7. Then, as shown in (C), a p-type base layer 8 and an n++ source layer 9 are formed by the conventional double diffusion method. That is, first, the p-type base layer 8 is formed by doping impurities using the gate electrode N 5 L as a mask, and then the p-type base layer 8 is doped with impurities.
A mask is formed in the center and this mask and the gate N pole 51 are connected to each other.
An n++ source layer 9 is formed by doping impurities using as a mask. After that, as shown in (d), the entire surface is covered with a CvD insulating film 10, a contact hole is opened, an A2 film is deposited, and a source 1 pole 11 is formed, which contacts the n-type source layer 9 and the p-type base layer 8 at the same time. form. On the drain 111 side, a drain electrode 12 is formed by evaporating a three-layer metal layer of V-Nt-Au.
こうしてこの実施例によれば、ｐ型ベース層８の低抵抗
化のためのｐ＋＋層７を、自己整合的にｐ型ベースＷＩ
８の中央に形成することができる。In this way, according to this embodiment, the p++ layer 7 for lowering the resistance of the p-type base layer 8 is formed by the p-type base WI in a self-aligned manner.
It can be formed in the center of 8.
従って優れた素子特性を歩留りよく得ることができる。Therefore, excellent device characteristics can be obtained with a high yield.
実際にこのｐ＋＋層７を、チャネル領域に達しない程度
に幅広く拡散形成することによって、この導電変調型Ｍ
ＯＳＦＥＴの最大ターンオフ電流を従来のものに比べて
約４０％増大させることができた。By actually diffusing this p++ layer 7 widely to the extent that it does not reach the channel region, this conductivity modulation type M
The maximum turn-off current of the OSFET could be increased by about 40% compared to the conventional one.
第２図（ａ）〜（ｄ＞は他の実施例の製造工程断面図で
ある。先の実施例と対応する部分には同一符号を付して
詳細な説明は省略する。この実施例では、ｐ型ベース層
とｐ＋型層のイオン注入工程を逆にしている。即ち先ず
（ａ）に示すように、多結晶シリコン膜によりゲート電
極５１と第１のマスク材５２を形成する。１３はこのゲ
ート電極５１および第１のマスク材５２をパターン形成
するために用いたフォトレジストを示している。この実
ｙＩＩ例ではこの状態でボロンのイオン注入を行い、ｐ
型ベース開用のｐ型１１２１８１〜８３を形成する。こ
の後フォトレジスト１３を除去し、先の実施例と同様に
（ｂ）に示すようにゲート電極５１と第１のマスク材５
２の間を覆う第２のマスク材をフォトレジスト等により
形成し、ボロンを高１度にイオン注入してｐ＋型型子７
形成する。そして第２のマスク材６続いて第１のマスク
材５２を除去し、熱処理して不純物活性化と拡散を行う
ことにより、（Ｃ）に示すようにｐ型ベース層８とその
中央部に位置するｐ＋型ＦｊＪ７を形成する。そして（
ｄ）に示すように、ｐ型ベース層８内に自己整合的にｎ
＋＋ソースｌ１１９を形成し、ＣＶＤ絶縁ＩＩＩ＄１０
で濁ってこれにコンタクト孔を開けてソース電極１１を
形成し、裏面にはドレイン電極１２を形成して、導電変
調型ＭＯＳＦＥＴを完成する。FIGS. 2(a) to 2(d) are cross-sectional views of the manufacturing process of another embodiment. Parts corresponding to those in the previous embodiment are given the same reference numerals and detailed explanations are omitted. In this embodiment, , the ion implantation process for the p-type base layer and the p + type layer is reversed. That is, as shown in (a), first, the gate electrode 51 and the first mask material 52 are formed from a polycrystalline silicon film. 13 is The photoresist used to pattern the gate electrode 51 and the first mask material 52 is shown.In this practical example, boron ions are implanted in this state, and p
Form p-types 112181-83 for mold base opening. After that, the photoresist 13 is removed, and the gate electrode 51 and the first mask material 5 are removed as shown in FIG.
A second mask material covering between 2 and 2 is formed of photoresist or the like, and boron is ion-implanted at a high rate to form a p+ type element 7.
Form. Then, the second mask material 6 is removed and the first mask material 52 is heat-treated to activate and diffuse impurities, thereby forming the p-type base layer 8 and the central portion thereof, as shown in (C). A p+ type FjJ7 is formed. and(
As shown in d), n is formed in the p-type base layer 8 in a self-aligned manner.
++ Form source l119, CVD insulation III $10
A contact hole is formed in this to form a source electrode 11, and a drain electrode 12 is formed on the back surface to complete a conductivity modulation type MOSFET.
この実施例によっても、先の実施例と同様にｐ“型Ｗ４
７はｐ型ベース層８中夫に自己整合的に形成され、従っ
て先の実施例と同様の効果が得られる。In this embodiment as well, p" type W4 is used as in the previous embodiment.
7 is formed in a self-aligned manner with the p-type base layer 8, so that the same effect as in the previous embodiment can be obtained.
なお本発明は上記実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形して実施することがで
きる。Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.
［発明の効果］
以上述べたように本発明によれば、ベース層を低抵抗化
してラッチアップを防止するのための高不純物濃度層を
ベース層の中央部に自己整合的に形成することができ、
優れた特性の導電変調型ＭＯＳＦＥＴを歩留りよく製造
することができる。[Effects of the Invention] As described above, according to the present invention, a high impurity concentration layer for reducing the resistance of the base layer and preventing latch-up can be formed in a self-aligned manner in the center of the base layer. I can,
A conductivity modulation type MOSFET with excellent characteristics can be manufactured with high yield.
第１図（ａ）〜（ｄ）は本発明の一実施例の導電変調型
ＭＯＳＦＥＴの製造工程を示す断面図、第２図（ａ）〜
（ｄ）は他の実施例の製造工程を示す断面図、第３図は
一般的な導電変調型ＭＯ５ＦＥＴの構造を示す断面図、
第４図は従来法の問題を説明するための断面図である。
１・・・ｐ＋型ドレイン層、２・・・ｎ＋型バッファ層
、３・・・ｎ型高抵抗層、４・・・ゲート絶縁膜、５・
・・ゲートｆｆ電極（多結晶シリコン膜）、５２・・・
第１のマスク材（多結晶シリコンＩＩり、６・・・第２
のマスク材、７・・・ｐ“型層、８・・・ｐ型ベース層
、９・・・ｎ＋型ソー２Ｊｉ、１０・ＣＶＤ絶縁絶縁１
１・・・ソース電極、１２・・・ドレイン電極。
出願人代理人 弁理士 鈴江武彦
第１図
ｚ
第１図FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process of a conductivity modulation type MOSFET according to an embodiment of the present invention, and FIGS. 2(a) to 2(d) are
(d) is a sectional view showing the manufacturing process of another example, FIG. 3 is a sectional view showing the structure of a general conductivity modulation type MO5FET,
FIG. 4 is a sectional view for explaining the problems of the conventional method. DESCRIPTION OF SYMBOLS 1...p+ type drain layer, 2...n+ type buffer layer, 3...n type high resistance layer, 4...gate insulating film, 5...
...Gate ff electrode (polycrystalline silicon film), 52...
First mask material (polycrystalline silicon II, 6... second mask material)
mask material, 7...p" type layer, 8...p type base layer, 9...n+ type saw 2Ji, 10.CVD insulation 1
1... Source electrode, 12... Drain electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1z Figure 1
Claims (2)
電型の高抵抗層を有する基板の高抵抗層上にゲート絶縁
膜を介して多結晶シリコン膜を堆積する工程と、前記多
結晶シリコン膜を選択エッチングして、多結晶シリコン
・ゲート電極とこれに隣接して島状に残される多結晶シ
リコン膜からなる第１のマスク材を形成する工程と、前
記ゲート電極と第１のマスク材の間を覆う第２のマスク
材を形成する工程と、前記第１、第２のマスク材および
ゲート電極をマスクとして不純物をドープして前記高抵
抗層内に第１導電型の高不純物濃度層を形成する工程と
、前記第１および第２のマスク材を順次除去し、前記ゲ
ート電極をマスクとして不純物をドープして前記高抵抗
層内に第１導電型ベース層およびこのベース層内に位置
する第２導電型ソース層を形成する工程とを備えたこと
を特徴とする導電変調型ＭＯＳＦＥＴの製造方法。(1) A step of depositing a polycrystalline silicon film on a high resistance layer of a substrate having a high resistance layer of a second conductivity type on a drain layer of a first conductivity type with a high impurity concentration via a gate insulating film; selectively etching the crystalline silicon film to form a first mask material consisting of a polycrystalline silicon gate electrode and a polycrystalline silicon film left in an island shape adjacent to the polycrystalline silicon gate electrode; a step of forming a second mask material covering between the mask materials; and doping impurities using the first and second mask materials and the gate electrode as masks to form a high impurity of a first conductivity type in the high resistance layer. A step of forming a concentration layer, and sequentially removing the first and second mask materials, doping impurities using the gate electrode as a mask, and forming a first conductivity type base layer in the high resistance layer and forming a first conductivity type base layer in the base layer. A method for manufacturing a conductivity modulation type MOSFET, comprising the step of forming a second conductivity type source layer located at .
前記第２のマスク材形成前に行うようにした特許請求の
範囲第１項記載の導電変調型ＭＯＳＦＥＴの製造方法。(2) The method for manufacturing a conductivity modulation type MOSFET according to claim 1, wherein impurity doping for the second conductivity type base layer is performed before forming the second mask material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7115986A JPS62229977A (en) | 1986-03-31 | 1986-03-31 | Manufacture of conduction-modulation mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7115986A JPS62229977A (en) | 1986-03-31 | 1986-03-31 | Manufacture of conduction-modulation mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62229977A true JPS62229977A (en) | 1987-10-08 |
Family
ID=13452570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7115986A Pending JPS62229977A (en) | 1986-03-31 | 1986-03-31 | Manufacture of conduction-modulation mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62229977A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238172A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Manufacture of mos type semiconductor device |
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
| JPH02100365A (en) * | 1988-10-07 | 1990-04-12 | Fuji Electric Co Ltd | Manufacture of conductivity modulation type mosfet |
| US5262339A (en) * | 1989-06-12 | 1993-11-16 | Hitachi, Ltd. | Method of manufacturing a power semiconductor device using implants and solid diffusion source |
| EP1429391A1 (en) * | 2002-12-10 | 2004-06-16 | ABB Schweiz AG | Insulated gate semiconductor device and method of making the same |
-
1986
- 1986-03-31 JP JP7115986A patent/JPS62229977A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238172A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Manufacture of mos type semiconductor device |
| JPH02100365A (en) * | 1988-10-07 | 1990-04-12 | Fuji Electric Co Ltd | Manufacture of conductivity modulation type mosfet |
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
| US5262339A (en) * | 1989-06-12 | 1993-11-16 | Hitachi, Ltd. | Method of manufacturing a power semiconductor device using implants and solid diffusion source |
| EP1429391A1 (en) * | 2002-12-10 | 2004-06-16 | ABB Schweiz AG | Insulated gate semiconductor device and method of making the same |
| WO2004053998A1 (en) * | 2002-12-10 | 2004-06-24 | Abb Schweiz Ag | Insulated gate semiconductor device and method of making the same |
| US7224008B2 (en) | 2002-12-10 | 2007-05-29 | Abb Schweiz Ag | Self-aligned production method for an insulated gate semiconductor device cell and insulated gate semiconductor device cell |
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