JP3206726B2 - Method for manufacturing MOS type semiconductor device - Google Patents
Method for manufacturing MOS type semiconductor deviceInfo
- Publication number
- JP3206726B2 JP3206726B2 JP32626996A JP32626996A JP3206726B2 JP 3206726 B2 JP3206726 B2 JP 3206726B2 JP 32626996 A JP32626996 A JP 32626996A JP 32626996 A JP32626996 A JP 32626996A JP 3206726 B2 JP3206726 B2 JP 3206726B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- base region
- region
- electrode
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000000034 method Methods 0.000 title claims description 7
- 239000011229 interlayer Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000010410 layer Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000002344 surface layer Substances 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、トレンチ構造の
ＭＯＳＦＥＴ、ＩＧＢＴ（絶縁ゲート型バイポーラトラ
ンジスタ）およびインテリジェントパワーモジュール
（ＩＰＭ）などのＭＯＳ型半導体装置に関する。The present invention relates to a MOS type semiconductor device such as a MOSFET having a trench structure, an IGBT (insulated gate bipolar transistor) and an intelligent power module (IPM).
【０００２】[0002]
【従来の技術】図８は従来のトレンチ構造を有するＭＯ
Ｓ型半導体装置の製造工程で、同図（ａ）から同図
（ｅ）は製造順の工程図である。ｎ形半導体基板１の一
方の表面にボロン等を拡散しｐ形のベース領域２を形成
する（同図（ａ））。次に専用のフォト工程でパターン
ニングしたレジスト９のマスクをベース領域２上に形成
し、ヒ素（Ａｓ）やリン（Ｐ）等でソースイオン注入１
０を行う（同図（ｂ））。ソースイオン注入１０により
ｎ形領域３ｂをベース領域２の表面に形成した後レジス
ト９のマスクを除去する（同図（ｃ））。次にｎ形領域
３ｂより半導体基板１まで達するゲート溝１２を堀り、
このゲート溝１２にゲート絶縁膜４を被覆し、その後に
ポリシリコン等でゲート溝１２を詰めゲート電極５を形
成し、全面に層間絶縁膜６を被覆する（同図（ｄ））。
そして、層間絶縁膜６を貫通するゲート用およびソース
用のコンタクトホールを形成し、ベース領域２とソース
領域３の表面に共通して接触するソース電極７と図示さ
れてないがゲート電極と接触するゲート金属電極とを形
成する（同図（ｅ））。FIG. 8 shows an MO having a conventional trench structure.
In the manufacturing process of the S-type semiconductor device, FIG. Boron or the like is diffused on one surface of the n-type semiconductor substrate 1 to form a p-type base region 2 (FIG. 1A). Next, a mask of a resist 9 patterned by a dedicated photo process is formed on the base region 2 and source ion implantation 1 is performed with arsenic (As), phosphorus (P), or the like.
0 (FIG. 6B). After the n-type region 3b is formed on the surface of the base region 2 by source ion implantation 10, the mask of the resist 9 is removed (FIG. 3C). Next, a gate groove 12 extending from the n-type region 3b to the semiconductor substrate 1 is dug,
The gate trench 12 to cover the gate insulating film 4, followed by forming a gate electrode 5 stuffed gate trench 12 in <br/> polysilicon or the like, to cover the interlayer insulating film 6 on the entire surface (the (d) of FIG ).
Then, gate and source contact holes penetrating through the interlayer insulating film 6 are formed, and the source electrode 7 that is in common contact with the surfaces of the base region 2 and the source region 3 is in contact with the gate electrode (not shown). A gate metal electrode is formed (FIG. 3E).
【０００３】図９は従来の製造方法で製作されたストラ
イプ状のセル構造でトレンチ構造を有するＭＯＳ型半導
体装置の要部構成図で、同図（ａ）は平面図、同図
（ｂ）は同図（ａ）のＸ−Ｘ線で切断した断面図であ
る。同図（ａ）は電極や層間絶縁膜等が省略された半導
体表面から見た平面図である。図９では、ｎ形の半導体
基板１の表面層に選択的にストライプ状のｐ形のベース
領域２が形成され、ベース領域２の表面に選択的にｎ形
のソース領域３が形成され、エッチングで形成されたゲ
ート溝１２内の表面にゲート絶縁膜４が被覆され、さら
にポリシリコン等のゲート電極５が形成されている。コ
ンタクトホールが開けられた層間絶縁膜６を介してソー
ス電極７（主電極）および、図示されていないゲート金
属電極が表面上に形成される。この構成では、ゲート電
極５の側面と対向するベース領域２の側面領域にはチャ
ネル領域２０が形成されることとなる。FIGS. 9A and 9B are main part configuration diagrams of a MOS semiconductor device having a trench cell structure and a stripe-shaped cell structure manufactured by a conventional manufacturing method. FIG. 9A is a plan view, and FIG. It is sectional drawing cut | disconnected by XX of FIG. FIG. 1A is a plan view seen from the semiconductor surface from which electrodes, interlayer insulating films and the like are omitted. In FIG. 9, a stripe-shaped p-type base region 2 is selectively formed on a surface layer of an n-type semiconductor substrate 1, an n-type source region 3 is selectively formed on a surface of the base region 2, and etching is performed. The gate insulating film 4 is coated on the surface in the gate groove 12 formed by the above, and a gate electrode 5 of polysilicon or the like is formed. A source electrode 7 (main electrode) and a gate metal electrode (not shown) are formed on the surface via an interlayer insulating film 6 having a contact hole. In this configuration, the channel region 20 is formed in the side surface region of the base region 2 facing the side surface of the gate electrode 5.
【０００４】図１０は従来の製造方法で製作された四角
形のセル構造でトレンチ構造を有するＭＯＳ型半導体装
置の要部構成図で、同図（ａ）は平面図、同図（ｂ）は
同図（ａ）のＸ−Ｘ線で切断した断面図、同図（ｃ）は
同図（ａ）のＹ−Ｙ線で切断した断面図である。図８と
の違いはセル構造が四角形となっている点である。FIGS. 10A and 10B are main part configuration diagrams of a MOS type semiconductor device having a trench structure with a rectangular cell structure manufactured by a conventional manufacturing method. FIG. 10A is a plan view, and FIG. FIG. 2A is a cross-sectional view taken along line XX, and FIG. 2C is a cross-sectional view taken along line YY in FIG. The difference from FIG. 8 is that the cell structure is square.
【０００５】[0005]
【発明が解決しようとする課題】このように、従来のト
レンチ構造を有するＭＯＳ型半導体装置においては、ソ
ース領域形成のための専用のレジストマスクが必要とな
り、フォト工程が多く、製造コストは上昇する。また従
来の製造方法ではソース領域とソース電極のコンタクト
は半導体基板表面のみでとらねばならず、セルの微細化
の妨げとなっていた。また、ソース領域形成時のフォト
マスクとコンタクトホール形成時のフォトマスクとの位
置合わせにズレが生じると、素子特性にばらつきが発生
するという不具合を生じる。As described above, in a conventional MOS type semiconductor device having a trench structure, a dedicated resist mask for forming a source region is required, many photo steps are required, and the manufacturing cost is increased. . Further, in the conventional manufacturing method, the contact between the source region and the source electrode must be made only on the surface of the semiconductor substrate, which hinders miniaturization of the cell. In addition, when a misalignment occurs between the photomask at the time of forming the source region and the photomask at the time of forming the contact hole, a problem occurs that the element characteristics vary.
【０００６】この発明の目的は、前記の課題を解決し、
製造工程の削減による製造コストの低減と、ソース電極
のコンタクトを改善し、素子特性のバラツキ低減を図る
ことができるトレンチ構造を有するＭＯＳ型半導体装置
を提供することである。An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a MOS type semiconductor device having a trench structure capable of reducing the manufacturing cost by reducing the number of manufacturing steps, improving the contact of the source electrode, and reducing variation in element characteristics.
【０００７】[0007]
【課題を解決するための手段】前記の目的を達成するた
めに、第１導電形のドレイン層上の第２導電形のベース
領域の表面よりゲート溝を選択的に形成する工程と、該
ベース領域の表面より絶縁膜と導電膜とをこの順で形成
する工程と、該絶縁膜と導電膜とをベース領域の表面の
一部およびゲート溝に残して他を除去する工程と、ベー
ス領域の表面より第１導電形層を形成し、さらに層間絶
縁膜を被覆する工程と、該層間絶縁膜の窓開けと前記ベ
ース領域の表面上の絶縁膜と導電膜とを除去する工程
と、ゲート金属電極およびソース電極とを形成する工程
とを有するようにする。 In order to achieve the above object, a second conductivity type base on a first conductivity type drain layer is provided.
Selectively forming a gate groove from the surface of the region;
Insulating film and conductive film are formed in this order from the surface of the base region
And forming the insulating film and the conductive film on the surface of the base region.
Removing a part and the others while leaving them in the gate groove;
A first conductivity type layer is formed from the surface of the
Covering the edge film, opening a window in the interlayer insulating film, and
For removing the insulating film and the conductive film on the surface of the source region
And forming a gate metal electrode and a source electrode
To have.
【０００８】前記の製造方法により、第１導電形のソー
ス領域形成のための専用のフォト工程を削除できる。ま
た従来方法で問題であったソース電極と第１導電形のソ
ース領域および第２導電形のベース領域との接触での合
わせズレは生じない。さらに、ゲート金属電極（金属膜
で形成される）とゲート電極（ポリシリコンなどで形成
される）との接触をゲート溝に形成したゲート電極に開
けたゲートコンタクト溝で行うことで、ソースコンタク
ト溝とゲートコンタクト溝とは同時に形成できる。ま
た、ゲート溝部のゲート電極にソースコンタクト溝と同
時にゲートコンタクト溝を掘ることで、このゲートコン
タクト溝がゲート電極を突き抜け第１導電形のドレイン
領域に達することもなく、従って素子特性不良も発生し
ない。According to the above-described manufacturing method, a dedicated photo step for forming the source region of the first conductivity type can be omitted. Further, there is no misalignment caused by the contact between the source electrode and the source region of the first conductivity type and the base region of the second conductivity type, which is a problem in the conventional method. Further, the contact between the gate metal electrode (formed of a metal film) and the gate electrode (formed of polysilicon or the like) is performed by the gate contact groove formed in the gate electrode formed in the gate groove, so that the source contact groove is formed. And the gate contact groove can be formed simultaneously. In addition, since the gate contact groove is dug at the same time as the source contact groove in the gate electrode in the gate groove portion, the gate contact groove does not penetrate the gate electrode to reach the drain region of the first conductivity type, so that the element characteristic defect does not occur. .
【０００９】[0009]
【発明の実施の形態】図１はこの発明の第１参考例の製
造工程で、同図（ａ）ないし同図（ｅ）は製造順に工程
を示したものである。半導体基板１（ドレイン層とな
る）の一方の表面にボロン等を拡散しｐ形のベース領域
２を形成する（同図（ａ））。このベース領域２にヒ素
（Ａｓ）やリン（Ｐ）等でソースイオン注入１０を行い
（同図（ｂ））、ベース領域２の表面層にｎ形層３ａを
形成する（同図（ｃ））。このｎ形層３ａの表面から半
導体基板１に達するゲート溝１２を堀り、このゲート溝
１２内をゲート絶縁膜４で被覆し、その後にポリシリコ
ン等でゲート溝１２を詰めゲート電極５を形成し、全面
に層間絶縁膜６を被覆する（同図（ｄ））。次に層間絶
縁膜６を貫通するコンタクトホールを形成し、このコン
タクトホールが開けられた層間絶縁膜６をマスクとし
て、ベース領域２内に達する溝（ソースコンタクト溝１
６）とゲート電極５内に達する溝（ゲートコンタクト溝
１７）を堀り、ソース領域３の形成と、ソース領域３の
側面とベース領域２の側面とに共通して接触するソース
電極７（主電極）の形成と、ゲート電極と接触するゲー
ト金属電極８（金属膜で形成する）とを形成する（同図
（ｅ））。FIG. 1 shows a manufacturing process according to a first embodiment of the present invention. FIGS. 1A to 1E show the manufacturing steps in the order of manufacturing. Boron or the like is diffused on one surface of the semiconductor substrate 1 (which becomes a drain layer) to form a p-type base region 2 (FIG. 1A). Source ion implantation 10 is performed on the base region 2 with arsenic (As), phosphorus (P) or the like (FIG. 2B), and an n-type layer 3a is formed on the surface layer of the base region 2 (FIG. 2C). ). A gate groove 12 extending from the surface of the n-type layer 3a to the semiconductor substrate 1 is dug, the inside of the gate groove 12 is covered with a gate insulating film 4, and then the gate groove 12 is filled with polysilicon or the like to form a gate electrode 5. Then, the entire surface is covered with an interlayer insulating film 6 (FIG. 4D). Next, a contact hole penetrating through the interlayer insulating film 6 is formed, and using the interlayer insulating film 6 in which the contact hole is opened as a mask, a groove reaching the base region 2 (source contact groove 1).
6) and a groove (gate contact groove 17) reaching the inside of the gate electrode 5 is dug to form the source region 3 and to form the source electrode 7 (mainly in contact with the side surface of the source region 3 and the side surface of the base region 2 in common). An electrode) and a gate metal electrode 8 (formed of a metal film) that is in contact with the gate electrode are formed (FIG. 3E).
【００１０】図２は第１参考例の製造方法で形成したス
トライプ状のセルをしたトレンチ構造のＭＯＳ型半導体
装置の要部構成図で、同図（ａ）は平面図、同図（ｂ）
は断面図である。同図（ａ）はソース電極、ゲート金属
電極および層間絶縁膜等が省略された半導体表面から見
た平面図である。半導体基板１の表面層にストライプ状
のベース領域２、ベース領域２の表面層にソース領域３
が形成され、半導体基板１に達するゲート溝１２がスト
ライプ状に掘られ、ゲート溝１２の内壁にゲート絶縁膜
４が形成され、さらに、ゲート溝１２はポリシリコン等
で埋めてゲート電極５が形成され、層間絶縁膜６にコン
タクトホールが開けられ、ソース領域３とベース領域２
に共通に接触するソース電極７と、ゲート電極５と接続
するゲート金属電極８とが形成されている。ゲート金属
電極８は図示されていないゲートパッド部の金属膜と接
続する。このＭＯＳ型半導体装置ではゲート電圧を印加
するとゲート電極５の側面と対向するベース領域２の側
面領域にチャネル領域２０が形成される。FIGS. 2A and 2B are main part configuration diagrams of a trench type MOS semiconductor device having a striped cell formed by the manufacturing method of the first reference example . FIG. 2A is a plan view and FIG.
Is a sectional view. FIG. 2A is a plan view seen from the semiconductor surface from which a source electrode, a gate metal electrode, an interlayer insulating film and the like are omitted. A stripe-shaped base region 2 is formed on the surface layer of the semiconductor substrate 1, and a source region 3 is formed on the surface layer of the base region 2.
Is formed, a gate groove 12 reaching the semiconductor substrate 1 is dug in a stripe shape, a gate insulating film 4 is formed on the inner wall of the gate groove 12, and the gate electrode 12 is formed by filling the gate groove 12 with polysilicon or the like. Then, a contact hole is opened in the interlayer insulating film 6, and the source region 3 and the base region 2 are formed.
And a gate metal electrode 8 connected to the gate electrode 5. The gate metal electrode 8 is connected to a metal film of a gate pad portion (not shown). In this MOS semiconductor device, when a gate voltage is applied, a channel region 20 is formed in a side surface region of the base region 2 facing the side surface of the gate electrode 5.
【００１１】図３は第１参考例の製造方法で形成した四
角形のセルをしたトレンチ構造のＭＯＳ型半導体装置の
要部構成図で、同図（ａ）は平面図、同図（ｂ）は同図
（ａ）をＸ−Ｘ線で切断した断面図、同図（ｃ）は同図
（ａ）をＹ−Ｙ線で切断した断面図である。図２との違
いはセル構造が四角形をしている点である。同図
（ｂ）、（ｃ）のソース電極７をソース領域３およびベ
ース領域２と共通に接触させるためのソースコンタクト
溝１６と同図（ｂ）のゲート金属電極８とゲート電極５
とを接触させるためのゲートコンタクト溝１７はコンタ
クトホールが開けられた層間絶縁膜６をマスクとして同
時に形成される。ゲート金属電極８は図示されてないゲ
ートパッドの金属膜とソース電極７と層間絶縁されて接
続されるか、またはそれ自身ゲートパットになる場合も
ある。FIGS. 3A and 3B are main part configuration diagrams of a trench type MOS semiconductor device having a rectangular cell formed by the manufacturing method of the first reference example . FIG. 3A is a plan view, and FIG. FIG. 3A is a cross-sectional view taken along line XX, and FIG. 3C is a cross-sectional view taken along line YY in FIG. The difference from FIG. 2 is that the cell structure is square. 7B and 7C, the source contact groove 16 for making the source electrode 7 commonly contact the source region 3 and the base region 2, and the gate metal electrode 8 and the gate electrode 5 of FIG.
A gate contact groove 17 for making contact with the gate insulating film 6 is formed simultaneously using the interlayer insulating film 6 in which the contact hole is opened as a mask. The gate metal electrode 8 may be connected to the metal film of the gate pad (not shown) and the source electrode 7 with interlayer insulation, or may itself be a gate pad.
【００１２】図４はこの発明の第２参考例の製造工程
で、同図（ａ）ないし同図（ｅ）は順に追った工程を示
したものである。半導体基板１の一方の表面にボロン等
を拡散しベース領域２を形成し、このベース領域２を形
成する熱処理で酸化膜１１ａが形成される（同図
（ａ））。この酸化膜１１ａをソース領域以外の領域
（例えば、フィールドプレート領域など）を形成すると
きのフォト工程で、ソース領域形成用の酸化膜１１のマ
スクも同時に形成し、ヒ素などでソースイオン注入１０
を行い（同図（ｂ））、ソース領域３ｂをベース領域２
の表面層に形成する（同図（ｃ））。次に半導体基板に
達するゲート溝１２を堀り、このゲート溝１２内にゲー
ト絶縁膜４を被覆し、その後でポリシリコン等でゲート
溝１２を詰めゲート電極５を形成し、層間絶縁膜６を全
面に被覆する（同図（ｄ））。次に層間絶縁膜６を貫通
するコンタクトホールを形成する時に酸化膜１１も除去
し、ベース領域２とソース領域３に表面で共通して接触
するソース電極７の形成と、ゲート電極５と接触するゲ
ート金属電極８とを形成する。FIG. 4 shows a manufacturing process according to a second embodiment of the present invention, and FIGS. 4A to 4E show the steps in order. Boron or the like is diffused on one surface of the semiconductor substrate 1 to form a base region 2, and an oxide film 11 a is formed by a heat treatment for forming the base region 2 (FIG. 2A). In a photo process for forming the oxide film 11a in a region other than the source region (for example, a field plate region), a mask for the oxide film 11 for forming the source region is also formed at the same time.
(FIG. 2B), and the source region 3b is changed to the base region 2.
(FIG. 3C). Next, a gate groove 12 reaching the semiconductor substrate is dug, a gate insulating film 4 is covered in the gate groove 12, and then the gate groove 12 is filled with polysilicon or the like to form a gate electrode 5, and an interlayer insulating film 6 is formed. The entire surface is covered (FIG. 4D). Next, when a contact hole penetrating through interlayer insulating film 6 is formed, oxide film 11 is also removed, and source electrode 7 is formed in common with base region 2 and source region 3 on the surface, and contacts with gate electrode 5. A gate metal electrode 8 is formed.
【００１３】図５はこの発明の第１実施例の製造工程
で、同図（ａ）ないし同図（ｅ）は製造順に工程を示し
たものである。半導体基板１の一方の表面にボロン等を
拡散しベース領域２を形成する（同図（ａ））。同図
（ａ）はベース領域形成時の熱処理で形成される酸化膜
が除去された後の図を示す。ゲート溝１２をエッチング
（トレンチエッチングともいう）で形成する（同図
（ｂ））。ゲート絶縁膜４およびゲート電極５を形成す
る酸化膜１１およびポリシリコン膜１３はベース領域２
表面にも形成され、この酸化膜１１とポリシリコン膜１
３をソース領域以外の領域を形成するときのフォト工程
でソース領域形成用のマスクとして形成し、ヒ素などで
ソースイオン注入１０を行う（同図（ｃ））。ソース領
域形成後に層間絶縁膜６を全面に被覆する（同図
（ｄ））。層間絶縁膜６を貫通するコンタクトホールを
形成する時にポリシリコン膜１３と酸化膜１１も除去
し、ベース領域２とソース領域３の表面に共通して接触
するソース電極７の形成と、ゲート電極５と接触するゲ
ート金属電極８とを形成する（同図（ｅ））。FIGS. 5A to 5E show the manufacturing steps of the first embodiment of the present invention. FIGS. 5A to 5E show the steps in the manufacturing order. The base region 2 is formed by diffusing boron or the like on one surface of the semiconductor substrate 1 (FIG. 1A). FIG. 2A shows a state after an oxide film formed by a heat treatment for forming a base region is removed. The gate groove 12 is formed by etching (also referred to as trench etching) (FIG. 2B). Oxide film 11 and polysilicon film 13 forming gate insulating film 4 and gate electrode 5 are formed in base region 2.
The oxide film 11 and the polysilicon film 1 are also formed on the surface.
3 is formed as a mask for forming a source region in a photo process for forming a region other than the source region, and source ion implantation 10 is performed with arsenic or the like (FIG. 3C). After the formation of the source region, the entire surface is covered with the interlayer insulating film 6 (FIG. 4D). The polysilicon film 13 and the oxide film 11 are also removed when a contact hole penetrating the interlayer insulating film 6 is formed, so that the source electrode 7 is formed in common with the surfaces of the base region 2 and the source region 3 and the gate electrode 5 is formed. Is formed with the gate metal electrode 8 (FIG. 3E).
【００１４】また、第１参考例を適用して可変抵抗を形
成することもできる。図６は第１参考例を適用して製作
された可変抵抗の構成図で、同図（ａ）は平面図、同図
（ｂ）は同図（ａ）をＹ1 −Ｙ1 線で切断した断面図、
同図（ｃ）は同図（ａ）をＹ2 −Ｙ2 線で切断した断面
図である。同図（ａ）は電極や層間絶縁膜が省略された
半導体表面から見た平面図である。ベース領域２に選択
的にソース領域３を形成し、ゲート溝１２を形成し、ゲ
ート溝１２とベース領域２表面に酸化膜４、１１を形成
し、ゲート溝１２をポリシリコン等で埋めてゲート電極
５を形成する。層間絶縁膜６を全面に被覆し、層間絶縁
膜６を貫通し、ソースコンタクトホール１４とゲートコ
ンタクト溝１７を形成し、ゲート金属電極８と電極Ｂ
（ソース電極に相当する）と図示されていない電極Ａを
形成する。Further, a variable resistor can be formed by applying the first embodiment . 6A and 6B are configuration diagrams of a variable resistor manufactured by applying the first reference example . FIG. 6A is a plan view, and FIG. 6B is a view of FIG. 6A cut along line Y 1 -Y 1. Cross section,
FIG. 1C is a cross-sectional view of FIG. 1A taken along line Y 2 -Y 2 . FIG. 1A is a plan view seen from the semiconductor surface from which electrodes and interlayer insulating films are omitted. The source region 3 is selectively formed in the base region 2, the gate groove 12 is formed, the oxide films 4 and 11 are formed on the gate groove 12 and the surface of the base region 2, and the gate groove 12 is filled with polysilicon or the like. The electrode 5 is formed. A source contact hole 14 and a gate contact groove 17 are formed by covering the entire surface with the interlayer insulating film 6, penetrating the interlayer insulating film 6, and forming the gate metal electrode 8 and the electrode B
(Corresponding to a source electrode) and an electrode A (not shown) are formed.
【００１５】図７は図６（ａ）の断面図で、同図（ａ）
は図６（ａ）をＸ1 −Ｘ1 線で切断した断面図、同図
（ｂ）は図６（ａ）をＸ2 −Ｘ2 線で切断した断面図で
ある。ソース電極に相当する電極Ａと電極Ｂは離れて形
成されている。この図６、図７の構造により可変抵抗と
なるメカニズムをつぎに説明する。ゲート金属電極８が
無電圧のときは電極Ａと電極Ｂ間に電圧を印加すると電
極Ａと電極Ｂに接触するベース領域２を通り、キャリア
が流れる。このキャリアが流れる通路の抵抗はベース領
域２の拡散濃度、ベース領域２の深さ、ベース領域２の
幅とベース領域２の長さで決定する。ゲート電圧を印加
するとゲート電極５に対向するベース領域２の表面層に
チャネル領域２０が形成される。電極Ａと電極Ｂに電圧
を印加するとキャリアはこのチャネル領域２０を通して
流れる電流成分が追加されるため抵抗は低下する。この
チャネル領域２０の広さはゲート電圧に依存するため、
ゲート電圧を可変することで、抵抗を可変でき、可変抵
抗となる訳である。尚、この可変抵抗はＭＯＳＦＥＴや
ＩＧＢＴなどのＭＯＳ型素子と同一基板に製作するとき
には、ＭＯＳ型素子とは絶縁分離や接合分離で分離され
た領域に形成されることになる。FIG. 7 is a sectional view of FIG.
6A is a sectional view of FIG. 6A taken along the line X 1 -X 1 , and FIG. 6B is a sectional view of FIG. 6A taken along the line X 2 -X 2 . The electrode A and the electrode B corresponding to the source electrode are formed apart from each other. The mechanism that becomes a variable resistor by the structure of FIGS. 6 and 7 will be described below. When no voltage is applied to the gate metal electrode 8, when a voltage is applied between the electrodes A and B, carriers flow through the base region 2 that is in contact with the electrodes A and B. The resistance of the passage through which carriers flow is determined by the diffusion concentration of the base region 2, the depth of the base region 2, the width of the base region 2, and the length of the base region 2. When a gate voltage is applied, a channel region 20 is formed in the surface layer of the base region 2 facing the gate electrode 5. When a voltage is applied to the electrodes A and B, the resistance of the carriers decreases because a current component flowing through the channel region 20 is added to the carriers. Since the width of the channel region 20 depends on the gate voltage,
By varying the gate voltage, the resistance can be varied, resulting in a variable resistance. When this variable resistor is manufactured on the same substrate as a MOS element such as a MOSFET or IGBT, it is formed in a region separated from the MOS element by insulation or junction separation.
【００１６】[0016]
【発明の効果】この発明によれば、ＭＯＳ型半導体装置
を製造する際に必須となるソース領域形成のための専用
のフォト工程が不要となり、製造コストを低減できる。
また、ベース領域の表面層にソース領域と同一の導電形
の層を形成し、ベース領域に達する溝でこの層を分割し
てソース領域を形成し、且つ、この溝をソース電極とな
る金属膜で被覆することで、ソース電極をソース領域と
ベース領域とに共通に接触させることができ、従来の製
造方法で必要とされたフォト合わせが不要となり、且
つ、微細化や素子の特性ばらつきを低減できる。According to the present invention, a dedicated photo step for forming a source region, which is indispensable for manufacturing a MOS type semiconductor device, becomes unnecessary, and the manufacturing cost can be reduced.
Also, a layer of the same conductivity type as the source region is formed in the surface layer of the base region, the layer is divided by a groove reaching the base region to form a source region, and the groove is formed of a metal film serving as a source electrode. , The source electrode can be brought into common contact with the source region and the base region, eliminating the need for photo alignment required by conventional manufacturing methods, and miniaturizing and reducing variations in device characteristics. it can.
【図１】この発明の第１参考例の製造工程で、（ａ）な
いし（ｅ）は順に追った工程図FIGS. 1A to 1E show a manufacturing process according to a first embodiment of the present invention, in which FIGS.
【図２】図１の製造方法で形成したストライプ状のセル
をしたトレンチ構造のＭＯＳ型半導体装置の要部構成図
で、（ａ）は平面図、（ｂ）は断面図FIGS. 2A and 2B are main part configuration diagrams of a MOS type semiconductor device having a trench structure formed by stripe-shaped cells formed by the manufacturing method of FIG. 1, wherein FIG. 2A is a plan view and FIG.
【図３】図１の製造方法で形成した四角形のセルをした
トレンチ構造のＭＯＳ型半導体装置の要部構成図で、
（ａ）は平面図、（ｂ）は（ａ）をＸ−Ｘ線で切断した
断面図、（ｃ）は（ａ）をＹ−Ｙ線で切断した断面図3 is a main part configuration diagram of a trench type MOS semiconductor device having a rectangular cell formed by the manufacturing method of FIG. 1;
(A) is a plan view, (b) is a cross-sectional view of (a) taken along line XX, and (c) is a cross-sectional view of (a) taken along line YY.
【図４】この発明の第２参考例の製造工程で、（ａ）な
いし（ｅ）は製造順に示した工程図4 (a) to 4 (e) are process charts shown in a manufacturing order in a manufacturing process according to a second reference example of the present invention.
【図５】この発明の第１実施例の製造工程で、（ａ）な
いし（ｅ）は製造順に示した工程図5 (a) to (e) are process charts shown in a manufacturing order in the manufacturing process of the first embodiment of the present invention.
【図６】第１参考例を適用して製作された可変抵抗の構
成図で、（ａ）は平面図、同図（ｂ）は（ａ）をＹ1 −
Ｙ1 線で切断した断面図、（ｃ）は（ａ）をＹ2 −Ｙ2
線で切断した断面図[6] a configuration diagram of a variable resistor fabricated by applying the first reference example, (a) is a plan view, FIG. (B) is a (a) Y 1 -
Cut cross-sectional view in Y 1 line, the (c) is (a) Y 2 -Y 2
Cross section cut by line
【図７】図６の断面図で、（ａ）は図６（ａ）をＸ1 −
Ｘ1 線で切断した断面図、（ｂ）は図６（ａ）をＸ2 −
Ｘ2 線で切断した断面図[7] a sectional view of FIG. 6, (a) it is FIG. 6 (a) X 1 -
Section taken along a X 1 line diagram, the (b) FIG. 6 (a) X 2 -
Sectional view taken along a X 2-wire
【図８】従来のトレンチ構造を有するＭＯＳ型半導体装
置の製造工程で、（ａ）ないし（ｅ）は製造順に示した
工程図FIGS. 8A to 8E are views showing a manufacturing process of a conventional MOS type semiconductor device having a trench structure in the order of manufacturing. FIGS.
【図９】従来の製造方法で製作されたストライプ状のセ
ル構造でトレンチ構造を有するＭＯＳ型半導体装置の要
部構成図で、（ａ）は平面図、（ｂ）は（ａ）のＸ−Ｘ
線で切断した断面図9A and 9B are main part configuration diagrams of a MOS type semiconductor device having a trench cell structure and a stripe-shaped cell structure manufactured by a conventional manufacturing method, wherein FIG. 9A is a plan view and FIG. X
Cross section cut by line
【図１０】従来の製造方法で製作された四角形のセル構
造でトレンチ構造を有するＭＯＳ型半導体装置の要部断
面図で、（ａ）は平面図、（ｂ）は（ａ）のＸ−Ｘ線で
切断した断面図、（ｃ）は（ａ）のＹ−Ｙ線で切断した
断面図FIGS. 10A and 10B are main-portion cross-sectional views of a MOS-type semiconductor device having a trench structure and a rectangular cell structure manufactured by a conventional manufacturing method, wherein FIG. 10A is a plan view and FIG. 10B is XX of FIG. (C) is a cross-sectional view taken along line YY of (a).
１ ｎ形半導体基板（ドレイン層） ２ ｐ形のベース領域 ３ ｎ形のソース領域 ３ａ ｎ形層 ３ｂ ｎ形領域 ４ ゲート絶縁膜 ５ ゲート電極 ６ 層間絶縁膜 ７ ソース電極 ８ ゲート金属電極 １０ ソースイオン照射 １１ 酸化膜 １１ａ 酸化膜 １２ ゲート溝 １３ ポリシリコン １４ ソースコンタクトホール １６ ソースコンタクト溝 １７ ゲートコンタクト溝 ２０ チャネル領域 REFERENCE SIGNS LIST 1 n-type semiconductor substrate (drain layer) 2 p-type base region 3 n-type source region 3 a n-type layer 3 b n-type region 4 gate insulating film 5 gate electrode 6 interlayer insulating film 7 source electrode 8 gate metal electrode 10 source ion Irradiation 11 Oxide film 11a Oxide film 12 Gate groove 13 Polysilicon 14 Source contact hole 16 Source contact groove 17 Gate contact groove 20 Channel region
Claims (1)
ベース領域の表面よりゲート溝を選択的に形成する工程
と、該ベース領域の表面より絶縁膜と導電膜とをこの順
で形成する工程と、該絶縁膜と導電膜とをベース領域の
表面の一部およびゲート溝に残して他を除去する工程
と、ベース領域の表面より第１導電形層を形成し、さら
に層間絶縁膜を被覆する工程と、該層間絶縁膜の窓開け
と前記ベース領域の表面上の絶縁膜と導電膜とを除去す
る工程と、ゲート金属電極およびソース電極とを形成す
る工程とを有することを特徴とするＭＯＳ型半導体装置
の製造方法。A step of selectively forming a gate groove from a surface of a base region of a second conductivity type on a drain layer of a first conductivity type; and forming an insulating film and a conductive film from a surface of the base region in this order. Forming the first conductive type layer from the surface of the base region, removing the remaining part of the insulating film and the conductive film from the surface of the base region and the gate groove, and forming the first conductive type layer from the surface of the base region. Covering an insulating film, forming a window in the interlayer insulating film, removing the insulating film and the conductive film on the surface of the base region, and forming a gate metal electrode and a source electrode. A method for manufacturing a MOS semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32626996A JP3206726B2 (en) | 1995-12-07 | 1996-12-06 | Method for manufacturing MOS type semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7-318798 | 1995-12-07 | ||
| JP31879895 | 1995-12-07 | ||
| JP32626996A JP3206726B2 (en) | 1995-12-07 | 1996-12-06 | Method for manufacturing MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09219519A JPH09219519A (en) | 1997-08-19 |
| JP3206726B2 true JP3206726B2 (en) | 2001-09-10 |
Family
ID=26569513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32626996A Expired - Lifetime JP3206726B2 (en) | 1995-12-07 | 1996-12-06 | Method for manufacturing MOS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3206726B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
| JP2001284587A (en) * | 2000-03-28 | 2001-10-12 | Kaga Toshiba Electron Kk | Semiconductor device and method of manufacturing the same |
| US6815767B2 (en) * | 2001-02-01 | 2004-11-09 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate transistor |
| JP4909465B2 (en) * | 2001-03-28 | 2012-04-04 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP4608133B2 (en) * | 2001-06-08 | 2011-01-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device provided with vertical MOSFET and manufacturing method thereof |
| JP2005191487A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device and manufacturing method for the same |
| JP4824296B2 (en) * | 2004-11-04 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US20060163650A1 (en) * | 2005-01-27 | 2006-07-27 | Ling Ma | Power semiconductor device with endless gate trenches |
| JP2007059954A (en) * | 2006-12-05 | 2007-03-08 | Toshiba Corp | Semiconductor device |
| JP5138274B2 (en) * | 2007-05-25 | 2013-02-06 | 三菱電機株式会社 | Semiconductor device |
| JP2010147299A (en) * | 2008-12-19 | 2010-07-01 | Rohm Co Ltd | Semiconductor device and method of manufacturing the same |
| JP5775268B2 (en) | 2010-06-09 | 2015-09-09 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
-
1996
- 1996-12-06 JP JP32626996A patent/JP3206726B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09219519A (en) | 1997-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6872611B2 (en) | Method of manufacturing transistor | |
| JP4363736B2 (en) | Transistor and manufacturing method thereof | |
| US5366914A (en) | Vertical power MOSFET structure having reduced cell area | |
| KR100400079B1 (en) | Method for fabricating trench-gated power semiconductor device | |
| US5721148A (en) | Method for manufacturing MOS type semiconductor device | |
| US5798549A (en) | Conductive layer overlaid self-aligned MOS-gated semiconductor devices | |
| JP2002110978A (en) | Power semiconductor element | |
| KR20030062489A (en) | EDMOS device with the structure of lattice type drift region and method of manufacturing the same | |
| US6066534A (en) | Method of manufacturing a field effect transistor | |
| JP3206726B2 (en) | Method for manufacturing MOS type semiconductor device | |
| JPH08255913A (en) | Structure of high-voltage mosfet, and process for its manufacture | |
| KR0175442B1 (en) | Semiconductor device and manufacturing method | |
| KR100743339B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20000014215A (en) | Method for manufacturing the reliable lateral transistor | |
| JP2712359B2 (en) | Method for manufacturing semiconductor device | |
| JPH10335660A (en) | Semiconductor device and manufacture thereof | |
| JPS62229977A (en) | Manufacture of conduction-modulation mosfet | |
| KR100235620B1 (en) | Mosfet and method of manufacturing the same | |
| JP2004063918A (en) | Lateral mos transistor | |
| JP3303806B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH06163912A (en) | Vertical insulated gate transistor and fabrication thereof | |
| JP2000315792A (en) | Semiconductor device and its manufacture | |
| JPH11135783A (en) | Mos transistor and manufacture thereof | |
| KR100498406B1 (en) | Power mos device having trench gate and fabricating method therefor | |
| KR960013945B1 (en) | Soi transistor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080706 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080706 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080706 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080706 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090706 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090706 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100706 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100706 Year of fee payment: 9 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100706 Year of fee payment: 9 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110706 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110706 Year of fee payment: 10 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110706 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110706 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120706 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120706 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130706 Year of fee payment: 12 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |