JP3170610B2 - Manufacturing method of vertical field effect transistor - Google Patents

Manufacturing method of vertical field effect transistor

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Publication number
JP3170610B2
JP3170610B2 JP08515995A JP8515995A JP3170610B2 JP 3170610 B2 JP3170610 B2 JP 3170610B2 JP 08515995 A JP08515995 A JP 08515995A JP 8515995 A JP8515995 A JP 8515995A JP 3170610 B2 JP3170610 B2 JP 3170610B2
Authority
JP
Japan
Prior art keywords
oxide film
film
impurity
epitaxial layer
impurity diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08515995A
Other languages
Japanese (ja)
Other versions
JPH08288303A (en
Inventor
武始 桐原
正剛 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP08515995A priority Critical patent/JP3170610B2/en
Publication of JPH08288303A publication Critical patent/JPH08288303A/en
Application granted granted Critical
Publication of JP3170610B2 publication Critical patent/JP3170610B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、電力用デバイスとして
知られている縦型電界効果トランジスタの製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical field effect transistor known as a power device.

【0002】[0002]

【従来の技術】従来から、この種の縦型電界効果トラン
ジスタとしては図6及び図7でそれぞれ示すような構造
とされたものがあり、図6でもって第1従来例として示
す縦型電界効果トランジスタは、N型高濃度(N+)の
シリコン基板1上にN型低濃度(N-)のエピタキシャ
ル層2が形成され、かつ、このエピタキシャル層2上に
ゲート絶縁膜3を介したうえでゲート電極4が屈曲した
形状で形成されたものとなっている。
2. Description of the Related Art Conventionally, as a vertical field effect transistor of this type, there is a vertical field effect transistor having a structure as shown in FIGS. 6 and 7, respectively. In the transistor, an N-type low-concentration (N ) epitaxial layer 2 is formed on an N-type high-concentration (N + ) silicon substrate 1, and a gate insulating film 3 is formed on the epitaxial layer 2. The gate electrode 4 is formed in a bent shape.

【0003】そして、ここでのゲート絶縁膜3は中央部
3aの厚みが厚くて側部3bの厚みが薄くなった断面形
状を有しており、ゲート絶縁膜3の厚みが薄くなった側
部3bにおける端側部分直下のエピタキシャル層2内に
は、ソースとなるN+の第1不純物拡散領域5と、この
第1不純物拡散領域5を取り囲むP型高濃度(P+)の
第2不純物拡散領域6との各々が互いに離間して対向す
る位置ごとに形成されている。すなわち、このトランジ
スタは、ゲート絶縁膜3の中央部3aが厚膜化されてい
るためにゲート容量が低減することになる結果、高速動
作を実現し得るものである。
The gate insulating film 3 has a cross-sectional shape in which the thickness of the central portion 3a is large and the thickness of the side portion 3b is small. In the epitaxial layer 2 immediately below the end portion in FIG. 3b, an N + first impurity diffusion region 5 serving as a source and a P-type high concentration (P + ) second impurity diffusion surrounding the first impurity diffusion region 5 are formed. Each of the regions 6 is formed at a position facing each other at a distance from each other. In other words, this transistor can achieve high-speed operation as a result of the gate capacitance being reduced because the central portion 3a of the gate insulating film 3 is thickened.

【0004】一方、図7で示す第2従来例としての縦型
電界効果トランジスタは、N+のシリコン基板1上にN-
のエピタキシャル層2が形成されるとともに、このエピ
タキシャル層2上にゲート絶縁膜7を介したうえでフラ
ット形状のゲート電極8が形成されたものであり、ここ
でのゲート絶縁膜7は同一厚みを有している。そして、
このトランジスタにおけるエピタキシャル層2内にも、
+の第1不純物拡散領域5と、これを取り囲むP+の第
2不純物拡散領域6との各々が互いに離間した状態で形
成されており、ゲート絶縁膜7直下のエピタキシャル層
2内には第2不純物拡散領域6の各々に接するN+の不
純物拡散領域9が形成されている。
On the other hand, vertical field effect transistor of the second conventional example shown in FIG. 7, N on the silicon substrate 1 of the N + -
And a flat gate electrode 8 is formed on the epitaxial layer 2 with a gate insulating film 7 interposed therebetween. The gate insulating film 7 has the same thickness. Have. And
Also in the epitaxial layer 2 of this transistor,
The N + first impurity diffusion region 5 and the P + second impurity diffusion region 6 surrounding the first impurity diffusion region 5 are formed separately from each other, and the first impurity diffusion region 5 is formed in the epitaxial layer 2 immediately below the gate insulating film 7. N + impurity diffusion regions 9 in contact with each of the two impurity diffusion regions 6 are formed.

【0005】その結果、このトランジスタは、ゲート絶
縁膜7直下に所定深さでN+の不純物拡散領域9が設け
られていることにより、低オン抵抗化を実現し得るもの
となる。なお、図6及び図7中の符号10は層間絶縁
膜、11はソース電極であり、12はドレイン電極を示
している。
As a result, in this transistor, since the N + impurity diffusion region 9 is provided at a predetermined depth immediately below the gate insulating film 7, a low on-resistance can be realized. 6 and 7, reference numeral 10 denotes an interlayer insulating film, 11 denotes a source electrode, and 12 denotes a drain electrode.

【0006】[0006]

【発明が解決しようとする課題】ところで、縦型電界効
果トランジスタの高速動作化と低オン抵抗化とは相反す
る特性であり、図6で示したトランジスタでは、高速動
作化が実現可能となる反面、ゲート絶縁膜3直下にN-
のエピタキシャル層2が広く存在しているため、低オン
抵抗化を実現することが困難となってしまう。これに対
し、図7で示したトランジスタでは、ゲート絶縁膜7の
厚みが薄いため、ゲート容量の低容量化を実現すること
ができず、高速動作化を図ることが困難となる。
By the way, high-speed operation and low on-resistance of the vertical field effect transistor are contradictory to each other, and the transistor shown in FIG. 6 can realize high-speed operation. , N directly under the gate insulating film 3.
Since the epitaxial layer 2 exists widely, it is difficult to realize a low on-resistance. On the other hand, in the transistor shown in FIG. 7, since the thickness of the gate insulating film 7 is small, reduction in gate capacitance cannot be realized, and it is difficult to achieve high-speed operation.

【0007】そこで、これら両方の利点を兼ね備えたト
ランジスタを実現すべく、図8で第3従来例として示す
ような構造、つまり、中央部3aの厚みが厚くて側部3
bの厚みが薄くなった断面形状を有するゲート絶縁膜3
と、このゲート絶縁膜3直下のエピタキシャル層2内に
+の不純物拡散領域9が形成された構造を採用するこ
とも考えられているが、このような構造を実現するため
には、他の従来例よりもフォトリソグラフィ技術を多用
する必要があることになる結果、大幅な工程数増加を招
くという不都合が生じる。
Therefore, in order to realize a transistor having both of these advantages, a structure as shown in FIG. 8 as a third conventional example, that is, the central portion 3a is thick and the side portions 3
a gate insulating film 3 having a cross-sectional shape with a reduced thickness b
It is considered that a structure in which an N + impurity diffusion region 9 is formed in the epitaxial layer 2 directly below the gate insulating film 3 is considered. However, in order to realize such a structure, another structure is required. As a result, it is necessary to use the photolithography technique more frequently than in the conventional example.

【0008】 本発明は、このような不都合に鑑みて創
案されたものであって、工程数増加を招くことなく、高
速動作化及び低オン抵抗化を同時に実現することができ
る縦型電界効果トランジスタの製造方法の提供を目的と
している。
The present invention has been made in view of such inconvenience, and a vertical field-effect transistor capable of simultaneously realizing high-speed operation and low on-resistance without increasing the number of steps. The purpose is to provide a manufacturing method.

【0009】[0009]

【課題を解決するための手段】本発明に係る縦型電界効
果トランジスタの製造方法は、一導電型高濃度のシリコ
ン基板上に一導電型低濃度のエピタキシャル層を形成
し、かつ、該エピタキシャル層上に酸化膜を形成したう
えでのパターニングを行った後、パターニングされた酸
化膜をマスクとしてエピタキシャル層内の互いに離間し
た対向位置ごとに他導電型高濃度の不純物領域を形成す
る工程と、厚みの厚い酸化膜を形成し、かつ、他導電型
高濃度の不純物領域上及びこれら不純物領域間の中央部
上に厚膜部分をそれぞれ残す一方で厚膜部分同士間には
薄膜部分を形成する酸化膜のパターニングを行った後、
パターニングされた酸化膜をマスクとして酸化膜の薄膜
部分直下のエピタキシャル層内に一導電型の不純物を注
入する工程と、酸化膜上に導電膜を形成する工程と、酸
化膜の厚膜部分及び該厚膜部分と連続する薄膜部分の一
端側、並びに、これら上に形成された導電膜とを残すパ
ターニングを行った後、これら上に残ったレジスト層を
マスクとして他導電型の不純物をエピタキシャル層内に
注入する工程と、熱拡散処理を行って第2不純物拡散領
域と第3不純物拡散領域とを同時に形成する工程と、残
った酸化膜及び導電膜をマスクとしたうえで第2不純物
拡散領域内に一導電型高濃度の第1不純物拡散領域を形
成した後、第2不純物拡散領域上に残った酸化膜の厚膜
部分を除去する工程とを含むことを特徴としている。
A vertical electric field effect device according to the present invention.
The manufacturing method of the transistor is one conductivity type high concentration silicon.
Formation of low-concentration one-conductivity type epitaxial layer on substrate
And an oxide film is formed on the epitaxial layer.
After the patterning of the
Are separated from each other in the epitaxial layer using the oxide film as a mask.
High-concentration impurity regions of other conductivity type
Process, forming a thick oxide film, and using another conductive type
The central part on the high-concentration impurity regions and between these impurity regions
While leaving the thick film parts on the top, while between the thick film parts
After patterning the oxide film that forms the thin film part,
Thin oxide film using the patterned oxide film as a mask
Inject an impurity of one conductivity type into the epitaxial layer just below
And a step of forming a conductive film on the oxide film,
Of a thick portion of the thickened film and a thin portion continuous with the thick portion
A pattern for leaving the end side and the conductive film formed thereon.
After turning, the remaining resist layer on these
Impurity of other conductivity type as mask in epitaxial layer
Implanting and performing a thermal diffusion process to form a second impurity diffusion region.
Simultaneously forming a region and a third impurity diffusion region;
Using the oxide film and the conductive film as a mask,
Forming a first impurity diffusion region having a high concentration of one conductivity type in the diffusion region;
After the formation, a thick oxide film remaining on the second impurity diffusion region
Removing the portion.

【0010】[0010]

【0011】[0011]

【作用】上記した製造方法によれば、工程数増加を招く
ことなく、容易に縦型電界効果トランジスタを製造する
ことが可能になる。この製造方法で製造された縦型電界
効果トランジスタは、中央部の厚みが厚くて側部の厚み
が薄くなった断面形状を有するゲート絶縁膜がエピタキ
シャル層上に形成されており、かつ、ゲート絶縁膜の厚
みが薄くなった側部における中央側部分直下のエピタキ
シャル層内には、このエピタキシャル層と同一導電型で
高濃度の第3不純物拡散領域を形成しているので、ゲー
ト容量の低減による高速動作化を図ると同時に、低オン
抵抗化を図ることが可能となる。
According to the above manufacturing method, the number of steps is increased.
Easily manufacture vertical field effect transistors without
It becomes possible. Vertical electric field manufactured by this manufacturing method
The effect transistor has a thick central part and a thick side part.
Gate insulating film with a thinner cross section
Formed on the shallow layer and the thickness of the gate insulating film
Epitaxy just below the central part on the thinned side
The same conductivity type as this epitaxial layer
Since a high-concentration third impurity diffusion region is formed,
High-speed operation by reducing the
Resistance can be achieved.

【0012】[0012]

【実施例】以下、本発明に係る縦型電界効果トランジス
タの製造方法の実施例を図面に基いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a vertical field effect transistor according to the present invention will be described.
An embodiment of a method for manufacturing a semiconductor device will be described with reference to the drawings.

【0013】図1は本実施例に係る縦型電界効果トラン
ジスタの概略構造を示す断面図、図2は本実施例に係る
トランジスタの前段プロセスにおける製造手順を示す工
程断面図であり、図3は該トランジスタの後段プロセス
における製造手順を示す工程断面図である。なお、図1
ないし図3において、従来例を示す図6ないし図8と互
いに同一もしくは相当する部品、部分には同一符号を付
している。また、本実施例では縦型電界効果トランジス
タがNチャネル型であるとして説明するが、Pチャネル
型のトランジスタであっても同様となることは勿論であ
る。
FIG. 1 is a cross-sectional view showing a schematic structure of a vertical field-effect transistor according to the present embodiment, FIG. FIG. 14 is a process cross-sectional view showing a manufacturing procedure in a post-process of the transistor. FIG.
In FIG. 3 to FIG. 3, the same or corresponding parts and portions as those in FIGS. 6 to 8 showing the conventional example are denoted by the same reference numerals. In this embodiment, the vertical field-effect transistor is described as an N-channel transistor. However, the same applies to a P-channel transistor.

【0014】本実施例に係る縦型電界効果トランジスタ
は、図1で簡略化して示すように、N型高濃度(N+
のシリコン基板1上にN型低濃度(N-)のエピタキシ
ャル層2が形成されているとともに、このエピタキシャ
ル層2上にゲート絶縁膜3を介したうえでゲート電極4
が屈曲した形状で形成されたものである。そして、この
トランジスタが具備するゲート絶縁膜3は中央部3aの
厚みが厚くて側部3bの厚みが薄くなった断面形状を有
しており、ゲート絶縁膜3の側部3bにおける端側部分
直下のエピタキシャル層2内には、ソースとなるN+
第1不純物拡散領域5と、この第1不純物拡散領域5を
取り囲むP型高濃度(P+)の第2不純物拡散領域6と
の各々が互いに離間した対向位置ごとに形成されてい
る。
[0014] vertical field effect transistor according to this embodiment, as shown in simplified form in FIG. 1, N-type high concentration (N +)
An N-type low-concentration (N ) epitaxial layer 2 is formed on a silicon substrate 1, and a gate electrode 4 is formed on the epitaxial layer 2 via a gate insulating film 3.
Is formed in a bent shape. The gate insulating film 3 included in this transistor has a cross-sectional shape in which the thickness of the central portion 3a is thick and the thickness of the side portion 3b is thin, and is just below the end portion of the side portion 3b of the gate insulating film 3. In the epitaxial layer 2, each of an N + first impurity diffusion region 5 serving as a source and a P-type high concentration (P + ) second impurity diffusion region 6 surrounding the first impurity diffusion region 5 is formed. It is formed for each opposing position separated from each other.

【0015】また、この際、ゲート絶縁膜3の側部3b
における中央側部分直下のエピタキシャル層2内にはN
+となった第3不純物拡散領域15の各々が互いに離間
して形成されており、各第3不純物拡散領域15はP+
の第2不純物拡散領域6のそれぞれと接する状態となっ
ている。つまり、この実施例に係るトランジスタは、ゲ
ート絶縁膜3の厚みが厚い中央部3a直下にN-のエピ
タキシャル層2が存在し、かつ、ゲート絶縁膜3の厚み
が薄くなった側部3bの中央側部分直下にN+の第3不
純物拡散領域15が存在する構成とされており、これら
第3不純物拡散領域15の各々がN-のエピタキシャル
層2を介したうえで対向配置された構造を有しているこ
とになる。そして、このようなトランジスタ構造が、図
8で示した第3従来例であるところの縦型電界効果トラ
ンジスタの構造と似通っていることは明らかである。な
お、図1中の符号10は層間絶縁膜、11はソース電極
であり、12はドレイン電極である。
At this time, the side portions 3b of the gate insulating film 3 are formed.
In the epitaxial layer 2 immediately below the central portion in FIG.
+ And each of the third impurity diffusion region 15 are formed apart from each other becomes, the third impurity diffusion region 15 is P +
In contact with each of the second impurity diffusion regions 6. That is, in the transistor according to this embodiment, the N epitaxial layer 2 exists immediately below the central portion 3 a where the thickness of the gate insulating film 3 is large, and the center of the side portion 3 b where the thickness of the gate insulating film 3 is small. The structure is such that an N + third impurity diffusion region 15 exists immediately below the side portion, and each of the third impurity diffusion regions 15 is opposed to each other via the N epitaxial layer 2. You are doing. It is apparent that such a transistor structure is similar to the structure of the vertical field-effect transistor of the third conventional example shown in FIG. In FIG. 1, reference numeral 10 denotes an interlayer insulating film, 11 denotes a source electrode, and 12 denotes a drain electrode.

【0016】次に、本実施例に係る縦型電界効果トラン
ジスタの製造手順を、前段プロセスを示す図2と、前段
プロセスに引き続いて実行される後段プロセスを示す図
3とに基づいて説明する。
Next, a manufacturing procedure of the vertical field-effect transistor according to the present embodiment will be described with reference to FIG. 2 showing a pre-stage process and FIG. 3 showing a post-stage process executed following the pre-stage process.

【0017】まず、図2(a)で示すように、N+のシ
リコン基板1上にN-のエピタキシャル層2を形成し、
かつ、このエピタキシャル層2上に所定厚みの酸化膜1
6を形成する。そして、フォトリソグラフィ技術を利用
して酸化膜16のパターニングを行った後、パターニン
グされた酸化膜16をマスクとしたうえでのP型不純物
のイオン注入または拡散を行ってエピタキシャル層2内
におけるセル範囲の互いに離間した対向位置ごと、すな
わち、酸化膜16に形成された薄膜部分16a直下にP
+の不純物領域17を形成する。なお、この酸化膜16
の薄膜部分16aは、酸化膜16の開口窓形成を行った
うえで再度形成されたものである。次に、酸化膜16の
膜厚を厚くすることにより、厚みの厚い酸化膜16を形
成する。
First, as shown in FIG. 2A, an N epitaxial layer 2 is formed on an N + silicon substrate 1.
An oxide film 1 having a predetermined thickness is formed on the epitaxial layer 2.
6 is formed. Then, after patterning the oxide film 16 using the photolithography technique, ion implantation or diffusion of a P-type impurity is performed by using the patterned oxide film 16 as a mask to perform cell range in the epitaxial layer 2. At each of opposing positions separated from each other, that is, immediately below the thin film portion 16 a formed on the oxide film 16,
A + impurity region 17 is formed. The oxide film 16
The thin film portion 16a is formed again after the opening window of the oxide film 16 is formed. Next, thick oxide film 16 is formed by increasing the thickness of oxide film 16.

【0018】引き続き、図2(b)で示すように、厚み
の厚くなった酸化膜16のパターニングを行うことによ
り、P+の不純物領域17上及びこれら不純物領域17
間の中央部上に酸化膜16の厚膜部分16bをそれぞれ
残す一方で、厚膜部分16b同士間には薄膜部分16c
を形成する。その後、パターニングされた酸化膜16を
マスクとしたうえ、酸化膜16の薄膜部分16c直下の
エピタキシャル層2内にN型不純物をイオン注入する
(図中では、注入されたN型不純物を×印で示してい
る)。そして、図2(c)で示すように、パターニング
された酸化膜16上に所定厚みとされたポリシリコンな
どからなる導電膜19を全面的に形成する。さらに、図
3(a)で示すように、フォトリソグラフィ技術を用い
ることにより、酸化膜16の厚膜部分16b及び厚膜部
分16bと連続する薄膜部分16cの一端側、並びに、
これら上に形成された導電膜19とを残すパターニン
グ、つまり、ゲート絶縁膜3及びゲート電極4を形成す
るためのパターニングを行った後、これら上に残ったレ
ジスト層18をマスクとしたうえでP型不純物をエピタ
キシャル層2内にイオン注入する(図中では、注入され
たP型不純物を△印で示している)。その後、残ってい
たレジスト層18を除去したうえでの熱拡散処理を行う
と、図3(b)で示すように、エピタキシャル層2内に
注入されていたN型及びP型の不純物がそれぞれ拡散す
る結果、P+の第2不純物拡散領域6とN+の第3不純物
拡散領域15とが同時に形成される。引き続き、所定厚
みの酸化膜を形成したうえでのパターニングを行うこと
により、残った導電膜19(ゲート電極4)上に層間絶
縁膜10を形成する。
Subsequently, as shown in FIG. 2B, the oxide film 16 having a large thickness is patterned to form a pattern on the P + impurity regions 17 and these impurity regions 17.
The thick film portions 16b of the oxide film 16 are left on the central portion between them, while the thin film portions 16c are interposed between the thick film portions 16b.
To form Thereafter, using the patterned oxide film 16 as a mask, an N-type impurity is ion-implanted into the epitaxial layer 2 immediately below the thin film portion 16c of the oxide film 16 (in the figure, the implanted N-type impurity is indicated by a mark x). Shown). Then, as shown in FIG. 2C, a conductive film 19 made of polysilicon or the like having a predetermined thickness is entirely formed on the patterned oxide film 16. Further, as shown in FIG. 3A, by using the photolithography technique, the thick film portion 16b of the oxide film 16 and one end side of the thin film portion 16c continuous with the thick film portion 16b, and
After patterning to leave the conductive film 19 formed thereon, that is, patterning for forming the gate insulating film 3 and the gate electrode 4, the resist layer 18 remaining on these is used as a mask and A type impurity is ion-implanted into the epitaxial layer 2 (in the figure, the implanted P-type impurity is indicated by a triangle). After that, when the thermal diffusion process is performed after the remaining resist layer 18 is removed, as shown in FIG. 3B, the N-type and P-type impurities implanted in the epitaxial layer 2 are respectively diffused. As a result, the P + second impurity diffusion region 6 and the N + third impurity diffusion region 15 are simultaneously formed. Subsequently, an interlayer insulating film 10 is formed on the remaining conductive film 19 (gate electrode 4) by performing patterning after forming an oxide film having a predetermined thickness.

【0019】その後、図3(c)で示すように、層間絶
縁膜10で覆われた酸化膜16及び導電膜19をマスク
として第2不純物拡散領域6内にN型の不純物をイオン
注入したうえ、熱拡散処理によって第2不純物拡散領域
6内にN+の第1不純物拡散領域5を形成する。さら
に、エピタキシャル層2内の第2不純物拡散領域6上に
残っていた酸化膜16の厚膜部分16bを除去したうえ
でソース電極11及びドレイン電極12を形成すると、
図1で示した構造の縦型電界効果トランジスタが完成す
る。そして、以上説明した工程からなる本実施例に係る
製造方法においては、前述した従来例の場合と比べてフ
ォトリソグラフィ技術の適用頻度が増えることなく、図
1の構造を有する縦型電界効果トランジスタが構成され
たことになる。
Thereafter, as shown in FIG. 3C, an N-type impurity is ion-implanted into the second impurity diffusion region 6 using the oxide film 16 and the conductive film 19 covered with the interlayer insulating film 10 as a mask. Then, an N + first impurity diffusion region 5 is formed in the second impurity diffusion region 6 by a thermal diffusion process. Furthermore, after removing the thick film portion 16b of the oxide film 16 remaining on the second impurity diffusion region 6 in the epitaxial layer 2, the source electrode 11 and the drain electrode 12 are formed.
The vertical field effect transistor having the structure shown in FIG. 1 is completed. In the manufacturing method according to the present embodiment including the above-described steps, the vertical field-effect transistor having the structure shown in FIG. It is configured.

【0020】ところで、本発明の発明者らがシュミレー
ションによって検討してみた結果によれば、本実施例に
係る縦型電界効果トランジスタでは、ゲート絶縁膜3の
中央部3aが厚膜化されているのでゲート容量の低減に
伴う高速動作化を実現し得ると同時に、ゲート絶縁膜3
の側部3bにおける中央側部分直下にN+の第3不純物
拡散領域15が形成されているために低オン抵抗化をも
実現し得ることが確認されている。なお、このシュミレ
ーションにおいては、セル幅が37μmでセル厚みが1
μmであるとともに、ゲート絶縁膜3(ゲート電極4)
の総幅が17μmであり、ゲート絶縁膜3における中央
部3aの厚みが3500オングストローム、側部3bの
厚みが1000オングストロームであることを条件とし
ている。
According to the results of a study by the inventors of the present invention by simulation, according to the vertical field effect transistor according to the present embodiment, the central portion 3a of the gate insulating film 3 is made thicker. Therefore, high-speed operation can be realized with a reduction in gate capacitance, and at the same time, the gate insulating film 3
It is confirmed that since the N + third impurity diffusion region 15 is formed directly below the central portion of the side portion 3b, low on-resistance can be realized. In this simulation, the cell width was 37 μm and the cell thickness was 1
μm and the gate insulating film 3 (gate electrode 4)
Is 17 μm, the thickness of the central portion 3a of the gate insulating film 3 is 3500 angstroms, and the thickness of the side portions 3b is 1000 angstroms.

【0021】さらに、この際の検討結果によっては、ゲ
ート絶縁膜3の厚膜化幅とゲート容量との関係が図4の
説明図で示すようになり、また、厚膜化幅とオン抵抗と
の関係が図5の説明図で示すようになることも分かって
いる。そこで、これらの図で示された検討結果を利用す
るならば、ゲート絶縁膜3の中央部3aの幅のみに変更
する、つまりは、工程を変更せずにマスクを変更するだ
けの手立てにより、ゲート絶縁膜3の厚膜化によるゲー
ト容量の低減と、第3不純物拡散領域15によるオン抵
抗の低減との割合を制御し得ることになり、用途に応じ
た特性を有する縦型電界効果トランジスタの提供が可能
となる。なお、ここでは説明を省略するが、第3不純物
拡散領域15における不純物の濃度を調整することによ
り、縦型電界効果トランジスタの有する耐圧特性を向上
させることも可能である。
Further, depending on the result of the examination at this time, the relationship between the thickness of the gate insulating film 3 and the gate capacitance is as shown in the explanatory view of FIG. It is also known that the relationship is as shown in the explanatory diagram of FIG. Therefore, if the examination results shown in these figures are used, only the width of the central portion 3a of the gate insulating film 3 is changed, that is, by changing the mask without changing the process, It is possible to control the ratio between the reduction of the gate capacitance by increasing the thickness of the gate insulating film 3 and the reduction of the on-resistance due to the third impurity diffusion region 15. Provision is possible. Although the description is omitted here, the withstand voltage characteristic of the vertical field effect transistor can be improved by adjusting the impurity concentration in the third impurity diffusion region 15.

【0022】以上説明したように、本発明に係る縦型電
界効果トランジスタの製造方法によれば、工程数増加を
招くことなく、容易に縦型電界効果トランジスタを製造
することが可能となるという効果が得られる。該製造方
法で製造された縦型電界効果トランジスタは、中央部の
厚みが厚くて側部の厚みが薄くなった断面形状を有する
ゲート絶縁膜がエピタキシャル層上に形成され、かつ、
ゲート絶縁膜の厚みが薄くなった側部における中央側部
分直下のエピタキシャル層内には、このエピタキシャル
層と同一導電型で高濃度の第3不純物拡散領域を形成し
ている結果、ゲート容量の低減による高速動作化を図る
とともに、低オン抵抗化を図ることができる。
As described above, the vertical electric device according to the present invention
According to the field effect transistor manufacturing method,
Easily manufacture vertical field effect transistors without inviting
The effect that it becomes possible to do it is acquired. The manufacturing method
Vertical field-effect transistor manufactured by the
It has a cross-sectional shape with a thicker side and a thinner side
A gate insulating film is formed on the epitaxial layer, and
The central side of the side where the thickness of the gate insulating film is reduced
In the epitaxial layer just below
Forming a high concentration third impurity diffusion region of the same conductivity type as the layer;
As a result, high-speed operation is achieved by reducing the gate capacitance.
At the same time, low on-resistance can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本実施例に係る縦型電界効果トランジスタの概
略構造を示す断面図である。
FIG. 1 is a cross-sectional view illustrating a schematic structure of a vertical field effect transistor according to the present embodiment.

【図2】本実施例に係る縦型電界効果トランジスタの前
段プロセスにおける製造手順を示す工程断面図である。
FIG. 2 is a process cross-sectional view showing a manufacturing procedure in a pre-stage process of the vertical field effect transistor according to the present embodiment.

【図3】本実施例に係る縦型電界効果トランジスタの後
段プロセスにおける製造手順を示す工程断面図である。
FIG. 3 is a process cross-sectional view showing a manufacturing procedure in a post-process of the vertical field-effect transistor according to the present embodiment.

【図4】厚膜化幅とゲート容量との関係を示す説明図で
ある。
FIG. 4 is an explanatory diagram showing a relationship between a film thickness and a gate capacitance.

【図5】厚膜化幅とオン抵抗との関係を示す説明図であ
る。
FIG. 5 is an explanatory diagram showing a relationship between a film thickness and an on-resistance.

【図6】第1従来例に係る縦型電界効果トランジスタの
概略構造を示す断面図である。
FIG. 6 is a sectional view showing a schematic structure of a vertical field effect transistor according to a first conventional example.

【図7】第2従来例に係る縦型電界効果トランジスタの
概略構造を示す断面図である。
FIG. 7 is a sectional view showing a schematic structure of a vertical field-effect transistor according to a second conventional example.

【図8】第3従来例に係る縦型電界効果トランジスタの
概略構造を示す断面図である。
FIG. 8 is a sectional view showing a schematic structure of a vertical field effect transistor according to a third conventional example.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 エピタキシャル層 3 ゲート絶縁膜 3a 中央部 3b 側部 4 ゲート電極 5 第1不純物拡散領域 6 第2不純物拡散領域 15 第3不純物拡散領域 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Epitaxial layer 3 Gate insulating film 3a Central part 3b Side part 4 Gate electrode 5 1st impurity diffusion area 6 2nd impurity diffusion area 15 3rd impurity diffusion area

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/336 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/336 H01L 29/78

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一導電型高濃度のシリコン基板上に一導電
型低濃度のエピタキシャル層を形成し、かつ、該エピタ
キシャル層上に酸化膜を形成したうえでのパターニング
を行った後、パターニングされた酸化膜をマスクとして
エピタキシャル層内の互いに離間した対向位置ごとに他
導電型高濃度の不純物領域を形成する工程と、 厚みの厚い酸化膜を形成し、かつ、他導電型高濃度の不
純物領域上及びこれら不純物領域間の中央部上に厚膜部
分をそれぞれ残す一方で厚膜部分同士間には薄膜部分を
形成する酸化膜のパターニングを行った後、パターニン
グされた酸化膜をマスクとして酸化膜の薄膜部分直下の
エピタキシャル層内に一導電型の不純物を注入する工程
と、 酸化膜上に導電膜を形成する工程と、 酸化膜の厚膜部分及び該厚膜部分と連続する薄膜部分の
一端側、並びに、これら上に形成された導電膜とを残す
パターニングを行った後、これら上に残ったレジスト層
をマスクとして他導電型の不純物をエピタキシャル層内
に注入する工程と、 熱拡散処理を行って第2不純物拡散領域と第3不純物拡
散領域とを同時に形成する工程と、 残った酸化膜及び導電膜をマスクとしたうえで第2不純
物拡散領域内に一導電型高濃度の第1不純物拡散領域を
形成した後、第2不純物拡散領域上に残った酸化膜の厚
膜部分を除去する工程とを含むことを特徴とする縦型電
界効果トランジスタの製造方法。
An epitaxial layer having a low concentration of one conductivity type is formed on a silicon substrate having a high concentration of one conductivity type, and an oxide film is formed on the epitaxial layer. Forming a high-concentration impurity region of another conductivity type at each opposing position in the epitaxial layer using the oxide film as a mask, and forming a thick oxide film and a high-concentration impurity region of another conductivity type. After the oxide film is patterned to form a thin film portion between the thick film portions while leaving a thick film portion on the upper portion and on the central portion between these impurity regions, an oxide film is formed using the patterned oxide film as a mask. Implanting an impurity of one conductivity type into the epitaxial layer immediately below the thin film portion, forming a conductive film on the oxide film, and connecting the thick film portion of the oxide film and the thick film portion. After performing patterning to leave one end side of the thin film portion to be formed, and the conductive film formed thereon, implanting impurities of another conductivity type into the epitaxial layer using the resist layer remaining thereon as a mask; and Forming a second impurity diffusion region and a third impurity diffusion region at the same time by performing a thermal diffusion process; and using the remaining oxide film and conductive film as a mask, forming a first conductive type high impurity in the second impurity diffusion region. Forming a first impurity diffusion region having a high concentration and then removing a thick portion of an oxide film remaining on the second impurity diffusion region.
JP08515995A 1995-04-11 1995-04-11 Manufacturing method of vertical field effect transistor Expired - Fee Related JP3170610B2 (en)

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Application Number Priority Date Filing Date Title
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Publication Number Publication Date
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JP3170610B2 true JP3170610B2 (en) 2001-05-28

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CN101589471B (en) * 2007-01-04 2012-05-23 飞思卡尔半导体公司 Semiconductor device and method of forming a semiconductor device
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JP2011204711A (en) * 2010-03-24 2011-10-13 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2014107420A (en) * 2012-11-28 2014-06-09 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device and method for manufacturing the same
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Also Published As

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