WO2015033406A1 - Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle - Google Patents

Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle Download PDF

Info

Publication number
WO2015033406A1
WO2015033406A1 PCT/JP2013/073836 JP2013073836W WO2015033406A1 WO 2015033406 A1 WO2015033406 A1 WO 2015033406A1 JP 2013073836 W JP2013073836 W JP 2013073836W WO 2015033406 A1 WO2015033406 A1 WO 2015033406A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
semiconductor
region
type
film
Prior art date
Application number
PCT/JP2013/073836
Other languages
French (fr)
Japanese (ja)
Inventor
石垣　隆士
宏行 松島
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2013/073836 priority Critical patent/WO2015033406A1/en
Publication of WO2015033406A1 publication Critical patent/WO2015033406A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technology thereof, and relates to a semiconductor device including a vertical MISFET and a manufacturing technology thereof, and a power conversion device and a railway vehicle including such a semiconductor device.
  • An inverter is used as a power conversion device that converts electric power for driving a motor or the like between direct current and alternating current.
  • a pair of elements composed of IGBTs (Insulated Gate Bipolar Transistors) and PIN (P-intrinsic-n) diodes connected in antiparallel to each other are connected to the upper arm on the high voltage side and the low voltage side. For example, a pair of lower arms is provided.
  • IGBTs Insulated Gate Bipolar Transistors
  • PIN P-intrinsic-n diodes connected in antiparallel to each other are connected to the upper arm on the high voltage side and the low voltage side.
  • a pair of lower arms is provided.
  • Each of the IGBT and the PIN diode is a semiconductor device using silicon (Si).
  • the loss at the time of power conversion in the inverter provided with the IGBT and PIN diode using Si has been reduced to a value equal to the theoretical value determined from the physical property value of Si. Therefore, it is extremely difficult to further reduce the loss during power conversion in the inverter provided with the semiconductor device using Si.
  • the breakdown electric field of a so-called wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) is about an order of magnitude larger than that of silicon (Si).
  • the withstand voltage of a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) using SiC is in a wide voltage range from several hundred volts to several kV. Therefore, in the vertical MISFET using SiC, the on-resistance is expected to be significantly reduced as compared with the vertical MISFET using Si. Further, since the vertical MISFET is a unipolar element, the on / off state can be switched at a higher speed than an IGBT that is not a unipolar element.
  • Patent Document 1 describes a technique regarding a vertical MISFET using Si, and International Publication No. 2010/073991 relates to a vertical MISFET using SiC. The technology is described.
  • an n-type drain region, a p-type body region, and an n-type source region are provided between the drain electrode and the source electrode, and gate insulation is provided on the surface of the p-type body region.
  • a gate electrode is provided through the film.
  • the breakdown electric field of silicon carbide (SiC) is about one digit larger than the breakdown electric field of silicon (Si). Therefore, the vertical MISFET using SiC is designed so that the electric field in the n-type drain region is about one digit larger than that of the vertical MISFET using Si. Specifically, in the vertical MISFET using SiC, the impurity concentration in the n-type drain region is increased as compared with the vertical MISFET using Si. Further, in the vertical MISFET using SiC, the thickness of the n-type drain region is made smaller than that of the vertical MISFET using Si. At this time, the on-resistance of the vertical MISFET is reduced by reducing the thickness of the n-type drain region.
  • the n-type drain region opposite to the n-type source region across the p-type body region that is, the gate on the JFET (Junction-Field-Effect-Transistor) region
  • the strength of the electric field in the insulating film increases.
  • the reliability of the gate insulating film decreases due to, for example, non-uniform threshold voltages.
  • the feedback capacitance which is the capacitance between the gate electrode and the drain electrode, increases. If the feedback capacity is large, for example, the power converter may not be operated at high speed.
  • a vertical MISFET provided in an inverter that is used at a relatively high voltage such as for a railway vehicle the strength of the electric field in the gate insulating film on the JFET region is reduced, the feedback capacitance is reduced, Widening is not compatible. Therefore, for example, the loss of power conversion in the inverter increases due to the fact that the width of the JFET region cannot be increased so much, and the amount of heat generated by the inverter increases. Therefore, it is necessary to provide a large cooling device. Therefore, it is not possible to reduce the manufacturing cost of the power conversion device including the vertical MISFET or the railway vehicle including the power conversion device. Alternatively, a power converter provided with a vertical MISFET or a railway vehicle including the power converter cannot be easily reduced in size or weight.
  • An object of the present invention is to provide a semiconductor device that can reduce the strength of an electric field in an insulating film on a JFET region, improve the reliability of the insulating film, reduce the feedback capacitance, and reduce the on-resistance. It is to provide.
  • An object of the present invention is to provide a power converter that includes the semiconductor device as described above and can be easily reduced in cost, reduced in size, or reduced in weight, or includes such a power converter.
  • the object is to provide a railway vehicle that can be reduced in cost, size, or weight.
  • a semiconductor device includes a first conductivity type semiconductor substrate, a drain electrode formed on a lower surface of the semiconductor substrate, and a first conductivity type semiconductor layer formed on an upper surface of the semiconductor substrate. Have.
  • the semiconductor device is formed in an upper layer portion of the semiconductor layer and has a second conductivity type first semiconductor region different from the first conductivity type, and a first conductivity type formed in the upper layer portion of the first semiconductor region.
  • the semiconductor device includes a first film portion made of a first insulating film formed on the upper surface of the semiconductor layer opposite to the second semiconductor region across the first semiconductor region, and a second film on the second semiconductor region.
  • the semiconductor device includes a gate electrode formed on a top surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film, the second semiconductor region, and the third semiconductor.
  • a source electrode formed on the region.
  • the gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion.
  • the first conductivity type semiconductor layer is formed on the upper surface of the first conductivity type semiconductor substrate, and the upper layer portion of the semiconductor layer is different from the first conductivity type.
  • a second conductivity type first semiconductor region is formed, and a first conductivity type second semiconductor region and a second conductivity type third semiconductor region are formed in an upper layer portion of the first semiconductor region.
  • a first insulating film is formed over the semiconductor layer.
  • a first film portion made of the first insulating film is formed on the upper surface of the semiconductor layer opposite to the second semiconductor region with the first semiconductor region interposed therebetween.
  • a second film portion made of the first insulating film is formed on the semiconductor region.
  • a gate electrode is formed on the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film.
  • a source electrode is formed on the second semiconductor region and the third semiconductor region, and a drain electrode is formed on the lower surface of the semiconductor substrate. Then, when forming the gate electrode, the gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion.
  • the strength of the electric field in the insulating film on the JFET region is reduced to improve the reliability of the insulating film, the feedback capacitance is reduced, and the on-resistance is increased. Can be lowered.
  • the power converter device provided with the said semiconductor device, or a railway vehicle including such a power converter device can be reduced in cost, size, or weight easily.
  • FIG. 2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment;
  • FIG. 2 is a top view of the semiconductor device of First Embodiment.
  • FIG. 10 is a main-portion cross-sectional view of the semiconductor device in the first modification example of the first embodiment;
  • FIG. 10 is a top view of a semiconductor device according to a first modification example of the first embodiment.
  • FIG. 4 is a flowchart showing a part of the manufacturing process of the semiconductor device of First Embodiment; 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof;
  • FIG. FIG. 10 is a cross-sectional view of a principal part of a semiconductor device of Comparative Example 1.
  • FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 2;
  • FIG. 6 is a cross-sectional view of the outer periphery of the semiconductor device of the second embodiment.
  • FIG. 10 is a flowchart showing a part of the manufacturing process of the semiconductor device of the second embodiment.
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof.
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof.
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof.
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof.
  • FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment.
  • FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment.
  • FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment.
  • FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment.
  • FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment. It is a figure which shows the structure of the power converter device of Embodiment 3.
  • FIG. 10 is a diagram showing a configuration of a railway vehicle according to a fourth embodiment.
  • the constituent elements are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.
  • hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
  • the semiconductor device according to the first embodiment includes a vertical MISFET made of silicon carbide (SiC).
  • FIG. 1 is a cross-sectional view of a main part of the semiconductor device of the first embodiment.
  • FIG. 2 is a top view of the semiconductor device of the first embodiment.
  • FIG. 1 is a cross-sectional view taken along line AA in FIG.
  • the gate insulating film 18 see FIG. 1
  • the gate electrode 19 see FIG. 1
  • the source electrode 20 see FIG. 1
  • the interlayer insulating film 21 see FIG. 1). (See) is removed, that is, it is seen through.
  • the portion formed in the region AR1 (see FIG. 1) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
  • the semiconductor device 1 is a semiconductor device including a vertical MISFET, and includes an n + type SiC substrate 10, a drain electrode 11, an n ⁇ type epitaxial layer 12, p type body region 13, n + type source region 14 and p + type body contact region 15.
  • the semiconductor device 1 of the first embodiment includes a gate insulating film 18, a gate electrode 19, a source electrode 20, and an interlayer insulating film 21.
  • the n + -type SiC substrate 10 is an n-type semiconductor substrate made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. That is, the conductivity type of n + -type SiC substrate 10 as a semiconductor substrate is n-type.
  • the n type impurity concentration in the n + type SiC substrate 10 is relatively large, for example, about 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the thickness of the n + type SiC substrate 10 is, for example, about 50 to 500 ⁇ m.
  • the drain electrode 11 is an electrode formed on the lower surface of the n + type SiC substrate 10. Drain electrode 11 is electrically connected to n + type SiC substrate 10.
  • a conductive film in which titanium (Ti), nickel (Ni), gold (Au), or the like is stacked can be used as the drain electrode 11, for example, a conductive film in which titanium (Ti), nickel (Ni), gold (Au), or the like is stacked can be used. By using such a conductive film, the drain electrode 11 and the n + -type SiC substrate 10 can be electrically connected with low resistance.
  • being formed on the lower surface of a certain substrate or on the lower surface of a certain layer means forming below the lower surface of the substrate or lower than the lower surface of the layer. Is included.
  • the n ⁇ type epitaxial layer 12 is formed on the upper surface of the n + type SiC substrate 10, and is an n type semiconductor made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced. Is a layer. That is, the conductivity type of the n ⁇ type epitaxial layer 12 as the semiconductor layer is n type.
  • the n - type impurity concentration in the n ⁇ -type epitaxial layer 12 is smaller than the n-type impurity concentration in the n + -type SiC substrate 10, for example, about 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 3 . Further, n - the thickness of the type epitaxial layer 12 is, for example, about 5 ⁇ 50 [mu] m.
  • the n ⁇ type epitaxial layer 12 can be formed by, for example, an epitaxial growth method.
  • a p-type impurity such as aluminum (Al) or boron (B) by ion implantation implanted on the entire upper surface of the n + -type SiC substrate 10, reducing the impurity concentration of the n-type in the n + -type SiC substrate 10
  • the n ⁇ type epitaxial layer 12 can also be formed by the method (the same applies to the second embodiment described later).
  • being formed on the upper surface of a certain substrate or on the upper surface of a certain layer means being formed above the upper surface of the substrate or above the upper surface of the layer. It is included.
  • the p-type body region 13 is formed in the upper layer portion of the n ⁇ -type epitaxial layer 12, and is a p-type semiconductor made of silicon carbide (SiC) in which a p-type impurity such as aluminum (Al) or boron (B) is diffused. It is an area. That is, the conductivity type of the p-type body region 13 as a semiconductor region is p-type.
  • the p-type impurity concentration in the p-type body region 13 is, for example, about 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of the p-type body region 13 is, for example, about 1 to 2 ⁇ m.
  • the n + -type source region 14 is formed in the upper layer portion of the p-type body region 13, and is an n-type semiconductor made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. It is an area. That is, the conductivity type of the n + type source region 14 as the semiconductor region is n type.
  • the n-type impurity concentration in the n + -type source region 14 is higher than the n-type impurity concentration in the n ⁇ -type epitaxial layer 12, and can be, for example, about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the thickness of the n + -type source region 14 can be set to about 100 to 500 nm, for example.
  • the p + -type body contact region 15 is formed in the upper layer portion of the p-type body region 13 and is, for example, p-type made of silicon carbide (SiC) in which p-type impurities such as aluminum (Al) or boron (B) are diffused. It is a semiconductor region. That is, the conductivity type of the p + -type body contact region 15 as the semiconductor region is p-type.
  • the p-type impurity concentration in the p + -type body contact region 15 is higher than the p-type impurity concentration in the p-type body region 13, for example, about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the thickness of the p + type body contact region 15 is, for example, about 100 to 500 nm.
  • the upper layer portion of the n ⁇ -type epitaxial layer 12 sandwiched between two adjacent p-type body regions 13 is a JFET region 16. That is, the upper layer portion of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 across the p type body region 13 is the JFET region 16. Further, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the JFET region 16, that is, the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12. The upper layer portion is a channel region 17.
  • the gate insulating film 18 is an insulating film formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12.
  • the gate insulating film 18 is made of, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or the like, for example, thermal oxidation or CVD (Chemical Vapor Deposition). ) Method.
  • the thickness of the gate insulating film 18 is, for example, about several tens of nm.
  • the gate electrode 19 is an electrode formed on the gate insulating film 18. That is, the gate electrode 19 is an electrode formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 via the gate insulating film 18.
  • the gate electrode 19 is made of, for example, polysilicon, and is a conductive film formed by, for example, a CVD method.
  • the source electrode 20 is an electrode formed on the n + type source region 14 and the p + type body contact region 15.
  • a conductive film made of titanium (Ti) or aluminum (Al) can be used as the source electrode 20. By using such a conductive film, the source electrode 20 and the n + type source region 14 and the p + type body contact region 15 can be electrically connected with low resistance.
  • film portions 22 a and 22 b made of protective insulating film 22 are formed on the upper surface of n ⁇ type epitaxial layer 12 and on n + type source region 14. Yes.
  • the film portion 22 a is formed of a protective insulating film 22 formed on the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween.
  • the film part 22 b is formed of a protective insulating film 22 formed on the n + type source region 14.
  • the protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a.
  • the protective insulating film 22 is patterned, that is, processed to form the opening 22c, whereby the film portions 22a and 22b are formed.
  • the opening 22 c penetrates the protective insulating film 22 and reaches the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12. Therefore, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 22c.
  • the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22a.
  • the gate electrode 19 is formed on the gate insulating film 18 from above the portion 18 a formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12.
  • the insulating film 18 is continuously formed over the portion 18b formed on the upper surface of the film portion 22a.
  • the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22a via the gate insulating film 18. It is formed continuously.
  • the gate insulating film 18 is formed directly on the JFET region 16 instead of the film portion 22a, and the gate electrode 19 is formed on the gate insulating film 18 formed directly on the JFET region 16.
  • the strength of the electric field in the insulating film between the region 16 and the gate electrode 19 can be reduced and the reliability of the insulating film can be improved.
  • the thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be further reduced, and the reliability of the insulating film can be further improved.
  • the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22b. Is formed.
  • the gate electrode 19 is formed on the gate insulating film 18 from above the portion 18 a formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12.
  • the insulating film 18 is continuously formed over a portion 18c formed on the upper surface of the film portion 22b.
  • the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22b via the gate insulating film 18. It is formed continuously.
  • the end 19a of the gate electrode 19 on the film part 22b side is disposed on a portion 18c of the gate insulating film 18 formed on the upper surface of the film part 22b. That is, the gate electrode 19 is terminated on the film part 22b.
  • the semiconductor region such as the n + type source region 14 and the n ⁇ type epitaxial layer 12, and the n + type SiC substrate. It is possible to prevent or suppress damage to 10. In addition, it is possible to prevent or suppress an increase in electric field strength in the vicinity of the end portion 19a due to concentration of electric lines of force toward the end portion 19a of the gate electrode 19.
  • the opening 22c penetrates the protective insulating film 22, and not only the upper surface of the p-type body region 13, but also the upper surface of the n ⁇ -type epitaxial layer 12 and the n + -type source region.
  • the upper surface of 14 is reached. That is, consider the case where not only the upper surface of p-type body region 13 but also the upper surface of n ⁇ -type epitaxial layer 12 and the upper surface of n + -type source region 14 are exposed at the bottom of opening 22c.
  • the gate insulating film 18 is formed on the upper surface of the n ⁇ type epitaxial layer 12 sandwiched between the film portions 22a and 22b, and on the upper surface of the p-type body region 13 sandwiched between the film portions 22a and 22b. It is formed on the entire surface and on the upper surface of the n + -type source region 14 sandwiched between the film part 22a and the film part 22b.
  • the gate electrode 19 is formed on the upper surface of the n ⁇ type epitaxial layer 12 sandwiched between the film portions 22a and 22b and on the entire upper surface of the p-type body region 13 sandwiched between the film portions 22a and 22b.
  • the gate insulating film 18 is formed on the upper surface of the n + -type source region 14 sandwiched between the film part 22a and the film part 22b. That is, the gate electrode 19 does not contact the n ⁇ type epitaxial layer 12 sandwiched between the film part 22a and the film part 22b and the n + type source region 14 sandwiched between the film part 22a and the film part 22b. So that it is formed.
  • the gate insulating film 18 may not be formed on the upper surface of the film part 22a and the upper surface of the film part 22b, and the gate electrode 19 may be directly formed.
  • the gate electrode 19 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film part 22a. Yes.
  • the gate electrode 19 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film part 22b. .
  • the interlayer insulating film 21 is formed on the gate insulating film 18 including the surface of the gate electrode 19.
  • a material of the interlayer insulating film 21 for example, PSG (Phospho ⁇ ⁇ ⁇ Silicate Glass) or silicon oxide can be used.
  • the gate insulating film 18 is not formed on the upper surface of the film part 22a and on the upper surface of the film part 22b, the interlayer insulating film 21 covers the gate electrode 19 and the film parts 22a and 22b. Is formed.
  • a source contact hole 21 a as an opening is formed in the interlayer insulating film 21, the gate insulating film 18, and the protective insulating film 22.
  • Source contact hole 21 a penetrates interlayer insulating film 21, gate insulating film 18, and protective insulating film 22, and reaches the upper surface of n + -type source region 14 and the upper surface of p + -type body contact region 15. That is, the upper surface of the n + type source region 14 and the upper surface of the p + type body contact region 15 are exposed at the bottom surface of the source contact hole 21a.
  • the source electrode 20 is formed on the interlayer insulating film 21 including the bottom and side surfaces of the source contact hole 21a. With such a structure, the source electrode 20 includes the n + -type source region 14 and the p + -type body through the source contact hole 21 a formed in the interlayer insulating film 21, the gate insulating film 18 and the protective insulating film 22. The contact region 15 is electrically connected.
  • each of two directions that intersect each other, preferably orthogonally, in a plan view is defined as an X direction and a Y direction, respectively.
  • the term “when viewed from a direction perpendicular to the upper surface of the n + -type SiC substrate 10” is meant.
  • the X direction and the Y direction are two directions that intersect with each other and preferably are orthogonal to each other within the upper surface of the n + -type SiC substrate 10.
  • the semiconductor device 1 has a plurality of p-type body regions 13, a plurality of n + -type source regions 14, and a plurality of p + -type body contact regions 15.
  • the plurality of p-type body regions 13 are formed in the upper layer portion of the n ⁇ -type epitaxial layer 12 so as to be arranged in a matrix in the X direction and the Y direction in plan view.
  • the plurality of n + -type source regions 14 are respectively formed in the upper layer portions of the plurality of p-type body regions 13.
  • the plurality of p + type body contact regions 15 are respectively formed in the upper layer portions of the plurality of p type body regions 13.
  • the film portion 22a extends in the Y direction and extends in the X direction in a plan view, and extends in the X direction, and extends in the X direction. And a plurality of extending portions 22e arranged in the Y direction, and are formed in a lattice shape.
  • the plurality of n ⁇ -type epitaxial layers 12 arranged in a matrix are partitioned by a lattice-shaped film portion 22a.
  • each of the plurality of regions partitioned by the lattice-like film portion 22a is referred to as a cell.
  • FIG. 2 shows four n ⁇ type epitaxial layers 12 arranged in a matrix in the X and Y directions.
  • the film part 22 a has one extending part 22 d extending in the Y direction and one extending part extending in the X direction and intersecting the extending part 22 d in a plan view.
  • Part 22e and is formed in a cross shape.
  • the four n ⁇ -type epitaxial layers 12 arranged in a matrix are partitioned by a cross-shaped film portion 22a.
  • An area partitioned by the cross-shaped film portion 22a is referred to as a cell.
  • FIG. 3 is a diagram schematically showing a path through which electrons flow when the vertical MISFET is in the ON state in FIG.
  • a positive gate voltage VGS (VGS> 0 V) is applied to the gate electrode 19 with respect to the source electrode 20.
  • VGS positive gate voltage
  • an inversion layer is formed in the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12, that is, in the channel region 17.
  • path PS ⁇ b> 1 from the source electrode 20 to the n + -type source region 14, the inversion layer formed in the channel region 17, the n ⁇ -type epitaxial layer 12, and , Flows to the drain electrode 11 through the n + -type SiC substrate 10. That is, current flows from the drain electrode 11 to the source electrode 20 through the n + -type SiC substrate 10, the n ⁇ -type epitaxial layer 12, the inversion layer formed in the channel region 17, and the n + -type source region 14.
  • VGS negative or zero gate voltage
  • FIG. 4 is a cross-sectional view of main parts of a semiconductor device according to a first modification of the first embodiment.
  • FIG. 5 is a top view of the semiconductor device according to the first modification of the first embodiment. 4 is a cross-sectional view taken along line BB in FIG.
  • the gate insulating film 18 see FIG. 4
  • the gate electrode 19 see FIG. 4
  • the source electrode 20 see FIG. 4
  • the interlayer insulating film 21 FIG. 5
  • FIG. 5 for easy understanding, a region AR11 on the intersection 22f where the film part 22a is not formed is illustrated by a two-dot chain line.
  • a portion formed in the region AR1 (see FIG. 4) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
  • the semiconductor device 1 a of the first modification is a semiconductor device including a vertical MISFET, like the semiconductor device 1 of the first embodiment, and an n + type SiC substrate 10.
  • the semiconductor device 1a of the first modification example of the first embodiment includes the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21, like the semiconductor device 1 of the first embodiment.
  • FIG. 5 shows four n ⁇ -type epitaxial layers 12 arranged in a matrix in the X and Y directions, as in FIG.
  • the film part 22 a has one extension part 22 d extending in the Y direction and one extension extending in the X direction and intersecting the extension part 22 d in a plan view. Part 22e, and is formed in a cross shape.
  • the four n ⁇ -type epitaxial layers 12 arranged in a matrix are partitioned by a cross-shaped film portion 22a. As described above, a region defined by the cross-shaped film portion 22a is referred to as a cell.
  • the gate electrode 19 two n adjacent in the X direction - -type epitaxial layer 12 sandwiched by the extending portion 22d on, and two n adjacent in the Y direction - -type epitaxial layer 12
  • the gate insulating film 18 is formed on the extending portion 22e sandwiched between the gate insulating film 18 and the gate insulating film 18.
  • the gate electrode 19 is not formed in the area AR11 on the intersection 22f where the extension 22d and the extension 22e intersect.
  • the gate electrode 19 is not formed in the region AR11 on the intersection 22f as the corner of the cell.
  • the line BB in FIG. 5 is in a direction connecting the centers of cells located on opposite sides of the intersection 22f, for example, a direction inclined 45 degrees from both the X and Y directions orthogonal to each other. Extend.
  • the electric field strength in the JFET region 16 increases as the width of the JFET region 16 increases.
  • the width of the JFET region 16 in the direction along the line BB is larger than the width of the JFET region 16 in the X direction and the Y direction. Therefore, the strength of the electric field in the intersecting portion 22f is larger than the strength of the electric field in the extending portion 22d sandwiched between two n ⁇ type epitaxial layers 12 adjacent in the X direction. Further, the electric field strength in the intersecting portion 22f is larger than the electric field strength in the extending portion 22e sandwiched between two n ⁇ -type epitaxial layers 12 adjacent in the Y direction.
  • the electric field strength in the insulating film constituting the intersection 22f can be reduced, and the JFET at the corner of the cell The reliability of the insulating film on the region 16 can be improved. Further, the feedback capacitance that is the capacitance between the gate electrode 19 and the drain electrode 11 can be reduced.
  • FIG. 6 is a flowchart showing a part of the manufacturing process of the semiconductor device of the first embodiment.
  • 7 to 20 are fragmentary cross-sectional views of the semiconductor device of First Embodiment during the manufacturing steps thereof. In the following, the manufacturing process in the region AR1 on the upper surface side and the center side of the n + type SiC substrate 10 will be described.
  • an n + type SiC substrate 10 is prepared (step S11 in FIG. 6).
  • step S11 as shown in FIG. 7, for example, an n + type SiC substrate 10 made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced is prepared.
  • the n type impurity concentration in the n + type SiC substrate 10 is relatively high, and can be, for example, about 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the thickness of the n + -type SiC substrate 10 can be set to, for example, about 50 to 500 ⁇ m.
  • the n ⁇ type epitaxial layer 12 is formed (step S12 in FIG. 6).
  • an n ⁇ type epitaxial layer 12 is formed on the upper surface of the n + type SiC substrate 10 by an epitaxial growth method.
  • SiH 4 gas silicon
  • Cl chlorine
  • Cl carbon
  • C 3 H 8 gas carbon
  • reducing gas H 2 gas
  • n-type impurity such as nitrogen (N), phosphorus (P) or arsenic (As) is introduced into the n ⁇ -type epitaxial layer 12.
  • n - a n-type impurity concentration of the type epitaxial layer 12 for example, 1 ⁇ 10 15 can be a ⁇ 1 ⁇ 10 16 cm -3 approximately, n - the thickness of the type epitaxial layer 12, For example, the thickness can be about 5 to 50 ⁇ m.
  • step S13 in FIG. 6 a resist film R 1 is applied on the n ⁇ type epitaxial layer 12. Then, the resist film R1 is patterned by exposing and developing the applied resist film R1 using a photolithography technique, as shown in FIG. The patterning of the resist film R1 is performed so that the region where the p-type body region 13 is formed in the n ⁇ -type epitaxial layer 12 is exposed.
  • a p-type impurity such as aluminum (Al) or boron (B) is introduced into the n ⁇ -type epitaxial layer 12 by ion implantation using the patterned resist film R1 as a mask.
  • the p-type body region 13 is formed in the upper layer portion of the n ⁇ -type epitaxial layer 12.
  • the p-type impurity concentration in the p-type body region 13 can be set to about 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3 , for example.
  • the thickness of the p-type body region 13 can be set to about 1 to 2 ⁇ m, for example.
  • region 13 it can heat-process, for example at about 1700 degreeC after the process, and can implant
  • the n + type source region 14 is formed (step S14 in FIG. 6).
  • a resist film R2 is applied on the n ⁇ -type epitaxial layer 12. Then, the applied resist film R2 is subjected to exposure and development using a photolithography technique, thereby patterning the resist film R2 as shown in FIG. The patterning of the resist film R2 is performed so that the region where the n + -type source region 14 is formed in the p-type body region 13 is exposed.
  • an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced into the p-type body region 13 by ion implantation using the patterned resist film R2 as a mask.
  • an n + type source region 14 is formed in the upper layer portion of the p type body region 13.
  • the n-type impurity concentration in the n + -type source region 14 can be set to about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 , for example.
  • the thickness of the n + -type source region 14 can be set to about 100 to 500 nm, for example.
  • step S15 the p + type body contact region 15 is formed (step S15 in FIG. 6).
  • a resist film R3 is applied onto the n ⁇ type epitaxial layer 12. Then, the applied resist film R3 is exposed and developed using a photolithography technique to pattern the resist film R3 as shown in FIG. The patterning of the resist film R3 is performed so that a region where the p + type body contact region 15 is formed in the p type body region 13 or the n + type source region 14 is exposed.
  • a p-type impurity made of, for example, aluminum (Al) or boron (B) is introduced into the p-type body region 13 or the n + -type source region 14 by an ion implantation method using the patterned resist film R3 as a mask.
  • p + type body contact region 15 is formed in the upper layer portion of p type body region 13.
  • the p-type impurity concentration in the p + -type body contact region 15 can be set to, for example, about 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3 as described above. Further, the thickness of the p + -type body contact region 15 can be set to about 100 to 500 nm, for example.
  • FIG. 12 shows a state where the resist film R3 is removed.
  • the step of forming the n + -type source region 14 and the p + -type body contact region 15 is not limited to the above-described order, and any process can be used as long as a resist film that is appropriately patterned is used as a mask. You may carry out in order.
  • a heat treatment is performed at, for example, about 1700 ° C. Can be activated.
  • step S16 the protective insulating film 22 is formed (Step S16 in FIG. 6).
  • step S16 as shown in FIG. 13, on the upper surface of n ⁇ type epitaxial layer 12, on the upper surface of p type body region 13, on n + type source region 14 and on p + type body contact region 15. Then, the protective insulating film 22 is formed. That is, the protective insulating film 22 is formed on the n ⁇ type epitaxial layer 12.
  • the protective insulating film 22 is for reducing the strength of the electric field in the insulating film on the n ⁇ type epitaxial layer 12 on the opposite side of the n + type source region 14 across the p type body region 13.
  • the protective insulating film 22 is for reducing the capacitance generated by sandwiching the insulating film on the n ⁇ type epitaxial layer 12 on the opposite side of the n + type source region 14 with the p type body region 13 in between. .
  • the protective insulating film 22 various films made of, for example, silicon oxide (SiO 2 ) or silicon oxynitride (SiON) having a low density can be used.
  • various films made of carbon-containing silicon oxide (SiOC) as a low-k film having a dielectric constant lower than that of silicon oxide (SiO 2 ) are preferably used as the protective insulating film 22.
  • a laminated film in which the above various films are suitably laminated can be used as the protective insulating film 22.
  • Such a protective insulating film 22 can be formed by a CVD method at a relatively low temperature of, for example, 800 ° C. or lower. Further, the thickness of the protective insulating film 22 can be set to, for example, about several hundred nm.
  • step S17 the protective insulating film 22 is patterned (step S17 in FIG. 6).
  • step S17 the protective insulating film 22 is processed, that is, patterned by the photolithography technique and the dry etching technique to form the opening 22c, thereby forming the film parts 22a and 22b.
  • the opening 22 c penetrates the protective insulating film 22 and reaches the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12. Therefore, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 22c.
  • the film portion 22 a is formed of a protective insulating film 22 formed on the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween.
  • the film part 22 b is formed of a protective insulating film 22 formed on the n + type source region 14. That is, the protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a.
  • the opening 22 c penetrates the protective insulating film 22 and reaches at least the upper surface of the p-type body region 13. Therefore, the opening 22c may reach the upper surface of the n ⁇ -type epitaxial layer 12 on the opposite side of the n + -type source region 14 with the p-type body region 13 interposed therebetween, and reach the upper surface of the n + -type source region 14. Also good. That is, at the bottom of the opening 22c, the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 across the p type body region 13 may be exposed, and the upper surface of the n + type source region 14 may be exposed. May be exposed.
  • the cross-sectional shape of the opening 22c is a taper shape, and the width of the opening 22c decreases from the top to the bottom, that is, the bottom of the opening 22c.
  • the upper portion of the protective insulating film 22 is processed and removed by the dry etching technique, and then the lower portion of the protective insulating film 22 is processed and removed by the wet etching technique.
  • An opening 22c having a shape can be formed.
  • the strength of the electric field can be prevented from increasing in the vicinity of the gate electrode 19 (see FIG. 17 described later) formed at the end of the opening 22c on the film portion 22a side.
  • the gate insulating film 18 is formed (Step S18 in FIG. 6).
  • the gate insulating film 18 is formed on the upper surface of the p-type body region 13 exposed at the bottom of the opening 22c.
  • the density of the gate insulating film 18 is larger than the density of the protective insulating film 22.
  • the dielectric constant of the gate insulating film 18 is larger than the dielectric constant of the protective insulating film 22.
  • the gate insulating film 18 for example, an insulating film formed at a relatively high temperature can be used.
  • an insulating film formed by heat-treating a film deposited at a relatively low temperature at a high temperature can be used.
  • a gate insulating film 18 various films made of, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ) are preferably used. Can be used.
  • a laminated film in which the above various films are suitably laminated can be used. Further, such a gate insulating film 18 can be formed by, for example, a CVD method.
  • the thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved.
  • the thickness TH2 of the protective insulating film 22 constituting the film portion 22a is, for example, about several hundred nm
  • the thickness TH1 of the gate insulating film 18 can be, for example, about several tens of nm. .
  • the gate insulating film 18 is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12.
  • the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film part 22a.
  • the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22b. .
  • step S19 the gate electrode 19 is formed (step S19 in FIG. 6).
  • a conductive film 19b is formed on the gate insulating film 18, as shown in FIG.
  • the conductive film 19b is made of, for example, polysilicon in which n-type impurities such as phosphorus (P) or arsenic (As) are diffused at a high concentration, or polysilicon in which p-type impurities such as boron (B) are diffused at a high concentration.
  • the conductive film 19b can be formed by, for example, a CVD method.
  • the conductive film 19b is patterned to form the gate electrode 19.
  • the conductive film 19b is patterned, that is, processed by a photolithography technique and a dry etching technique. For example, patterning is performed by a dry etching technique using a resist film patterned by a photolithography technique as a mask, thereby forming a gate electrode 19 made of a conductive film 19b as shown in FIG.
  • the gate electrode 19 is formed on a portion 18a of the gate insulating film 18 formed on the upper surface of the p-type body region 13 sandwiched between the film part 22a and the film part 22b.
  • the gate electrode 19 is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 via the gate insulating film 18.
  • the gate electrode 19 is formed continuously from the portion 18a of the gate insulating film 18 to the portion 18b formed on the upper surface of the film portion 22a. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22a via the gate insulating film 18. It is formed continuously. As a result, the strength of the electric field in the insulating film between the n ⁇ type epitaxial layer 12 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved.
  • the gate electrode 19 is formed continuously from the portion 18a of the gate insulating film 18 to the portion 18c formed on the upper surface of the film portion 22b. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 to the upper surface of the film portion 22b via the gate insulating film 18. It is formed continuously.
  • the end portion 19a on the film portion 22b side of the gate electrode 19 is disposed on a portion 18c of the gate insulating film 18 formed on the surface of the film portion 22b. That is, the gate electrode 19 is formed so that the gate electrode 19 is terminated on the film part 22b.
  • the conductive film 19b is processed on the film portion 22b, that is, on the protective insulating film 22, so that the semiconductor regions such as the n + -type source region 14 and the p-type body region 13 are formed. And damage to the n + -type SiC substrate 10 can be prevented or suppressed. In addition, it is possible to prevent or suppress an increase in electric field strength in the vicinity of the end portion 19a due to concentration of electric lines of force toward the end portion 19a of the gate electrode 19.
  • the gate electrode 19 By forming the gate electrode 19 in this way, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 becomes the channel region 17. Further, the upper layer portion of the n ⁇ -type epitaxial layer 12 on the opposite side of the n + -type source region 14 with the p-type body region 13 interposed therebetween becomes the JFET region 16.
  • the gate insulating film 18 is formed by, for example, a thermal oxidation method, the gate insulating film 18 is not formed on the upper surface of the film portion 22a and the upper surface of the film portion 22b, and the gate electrode 19 is directly It is formed.
  • an interlayer insulating film 21 is formed (Step S20 in FIG. 6).
  • an interlayer insulating film 21 is formed on the gate insulating film 18 including the surface of the gate electrode 19 as shown in FIG.
  • a silicon oxide film can be used as the interlayer insulating film 21, and can be formed by, for example, a CVD method.
  • the source contact hole 21a is formed (step S21 in FIG. 6).
  • a source contact hole 21a as an opening is formed in the interlayer insulating film 21, the gate insulating film 18 and the protective insulating film 22 by using a photolithography technique and an etching technique. To do. That is, a source contact hole 21 a that penetrates the interlayer insulating film 21, the gate insulating film 18, and the protective insulating film 22 and reaches the n + type source region 14 and the p + type body contact region 15 is formed. The upper surface of the n + -type source region 14 and the upper surface of the p + -type body contact region 15 are exposed on the bottom surface of the source contact hole 21a.
  • the source electrode 20 is formed (step S22 in FIG. 6).
  • a conductive film made of, for example, aluminum (Al) is formed on the interlayer insulating film 21 and so as to cover the bottom surface and the inner wall of the source contact hole 21a, for example, by vapor deposition or
  • the source electrode 20 is formed by depositing by sputtering or the like.
  • the drain electrode 11 is formed (step S23 in FIG. 6).
  • a metal film made of, for example, any one of titanium (Ti), nickel (Ni), gold (Au), and silver (Ag), or any two of them is formed on the lower surface of the n + -type SiC substrate 10.
  • the drain electrode 11 is formed by depositing a laminated film in which metal films of seeds or more are laminated, for example, by vapor deposition or sputtering. Thereby, the semiconductor device 1 as shown in FIG. 1 can be manufactured.
  • a passivation film can be formed on the upper surface and the lower surface of the semiconductor device 1.
  • an opening can be formed in a portion to be a pad region for electrically connecting the drain electrode 11, the gate electrode 19, and the source electrode 20 to the outside.
  • FIG. 21 is a main-portion cross-sectional view of the semiconductor device of Comparative Example 1.
  • n + -type SiC substrate 10 of the semiconductor device 101 of Comparative Example 1 the drain electrode 11 and the n - each type epitaxial layer 12, the semiconductor device 1 of the n + -type SiC substrate 10, the drain electrode 11 and the n
  • each of the p-type body region 13, n + -type source region 14 and p + -type body contact region 15 of the semiconductor device 101, p-type body region 13 of the semiconductor device 1, n + -type source region 14 and p + corresponds to each of the mold body contact regions 15 (see FIG. 1).
  • each of the JFET region 16 and the channel region 17 of the semiconductor device 101 corresponds to each of the JFET region 16 and the channel region 17 of the semiconductor device 1 (see FIG. 1).
  • the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21 of the semiconductor device 101 are the same as the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21 of the semiconductor device 1. These correspond to each (see FIG. 1).
  • the film part 22a (see FIG. 1) and the film part 22b (see FIG. 1) formed in the semiconductor device 1 are not formed.
  • the breakdown electric field of silicon carbide (SiC) is about one digit larger than the breakdown electric field of silicon (Si). Therefore, the vertical MISFET using SiC is designed so that the electric field in the n ⁇ -type epitaxial layer 12 is increased by about one digit compared to the vertical MISFET using Si. Specifically, in the vertical MISFET using SiC, the impurity concentration in the n ⁇ type epitaxial layer 12 is increased as compared with the vertical MISFET using Si. In addition, in the vertical MISFET using SiC, the thickness of the n ⁇ type epitaxial layer 12 is made smaller than that in the vertical MISFET using Si. At this time, the on-resistance of the vertical MISFET is reduced by reducing the thickness of the n ⁇ type epitaxial layer 12.
  • the on-resistance of the vertical MISFET is reduced, reducing the thickness of the n ⁇ -type epitaxial layer 12 increases the strength of the electric field in the gate insulating film 18 on the JFET region 16. As a result, the reliability of the gate insulating film 18 decreases due to, for example, non-uniform threshold voltages.
  • the feedback capacitance Cgd that is the capacitance between the gate electrode 19 and the drain electrode 11 increases. When the feedback capacitance Cgd is large, the power converter cannot be operated at high speed, or the control process when driving the motor or the like by the power converter may be complicated.
  • an inverter that is used at a relatively high voltage such as for a railway vehicle is desirably provided with a vertical MISFET having a high withstand voltage of about several kV.
  • the impurity concentration in the n ⁇ -type epitaxial layer 12 is relatively small.
  • the width of the JFET region 16 is narrow, the ratio of the resistance of the JFET region 16 to the entire on-resistance of the vertical MISFET increases. It becomes difficult to reduce the on-resistance of the MISFET. For this reason, the width of the JFET region 16 is designed to be wide.
  • the strength of the electric field in the gate insulating film 18 on the JFET region 16 is reduced, and the feedback capacitance is reduced.
  • the widening of the JFET region 16 is not compatible. Therefore, for example, the width of the JFET region 16 cannot be increased so much that the loss at the time of power conversion in the inverter increases, and the amount of heat generated in the inverter increases. Therefore, in order to sufficiently cool the inverter corresponding to this large amount of heat generation, it is necessary to provide a large cooling device having a large cooling capacity.
  • a power converter provided with a vertical MISFET or a railway vehicle including the power converter cannot be easily reduced in size or weight.
  • the portion of the gate insulating film on the JFET region 16 is large and is sandwiched between the n + type source region 14 and the n ⁇ type epitaxial layer 12. Further, the thickness of the portion formed on the upper surface of p-type body region 13 is small.
  • the gate insulating film is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12. It is difficult to process the portion and leave a thin gate insulating film having a thickness of, for example, about several tens of nanometers. In particular, it is difficult to make the thickness of the portion thinned by processing uniform. Further, when forming the gate insulating film, the p-type body region 13 under the gate insulating film may be damaged.
  • the p-type body region 13 and the n ⁇ -type epitaxial layers 12 and n under the p-type body region 13 are interposed through the thin gate insulating film.
  • the + type SiC substrate 10 may be damaged.
  • film portions 22a and 22b are formed.
  • the gate electrode 19 is formed on the JFET region 16 via at least the film part 22a.
  • the gate insulating film 18 is formed directly on the JFET region 16 instead of the film portion 22a, and the gate electrode 19 is formed on the gate insulating film 18 formed directly on the JFET region 16.
  • the strength of the electric field in the insulating film between the region 16 and the gate electrode 19 can be reduced and the reliability of the insulating film can be improved. Further, the feedback capacitance Cgd can be reduced.
  • the electric field in the insulating film on the JFET region 16 is increased.
  • the strength of the electric field in the insulating film on the JFET region 16 can be reduced to improve the reliability of the insulating film, and the width of the JFET region 16 can be increased while reducing the feedback capacitance Cgd.
  • the gate electrode 19 is formed on the channel region 17 via only the gate insulating film 18 and not via the film part 22a. Accordingly, after the thick gate insulating film is formed, the gate insulating film is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12. There is no need to process the part to leave a thin gate insulating film having a thickness of about several tens of nanometers, for example. Therefore, when the gate insulating film 18 is formed, it is possible to prevent the p-type body region 13 under the gate insulating film 18 from being damaged.
  • the gate electrode 19 is processed after the gate insulating film 18 is formed, the p-type body region 13 and the n ⁇ -type epitaxial layer under the p-type body region 13 are interposed via the thin gate insulating film 18. It is possible to prevent the 12 and n + type SiC substrate 10 from being damaged.
  • the first embodiment can also be applied to the case where the conductivity types of the semiconductor substrate and each semiconductor region are interchanged between p-type and n-type. Even in such a case, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained (the same applies to the second embodiment described later).
  • n + type SiC substrate instead of the n + type SiC substrate, a semiconductor substrate made of various semiconductor materials such as silicon (Si) or gallium nitride (GaN) is used, and the n ⁇ type epitaxial layer is made of Si or the like.
  • the present invention is also applicable when a semiconductor layer made of various semiconductor materials such as GaN is used. Even in such a case, the effect similar to that of the semiconductor device of the first embodiment can be obtained to some extent, although the degree is less than that in the case of using silicon carbide (SiC) as the semiconductor material (second embodiment described later). The same applies to the above).
  • FIG. 22 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment.
  • a portion formed in the region AR1 (see FIG. 22) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
  • the semiconductor device 1b of the second embodiment is a semiconductor device including a vertical MISFET, like the semiconductor device 1 of the first embodiment, and includes an n + -type SiC substrate 10 and a drain electrode. 11, an n ⁇ type epitaxial layer 12, a p type body region 13, an n + type source region 14 and a p + type body contact region 15.
  • the semiconductor device 1b of the second embodiment includes the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21, like the semiconductor device 1 of the first embodiment.
  • the upper layer portion of the n ⁇ type epitaxial layer 12 on the opposite side of the n + type source region 14 across the p type body region 13 is a JFET region 16. Further, as in the first embodiment, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n ⁇ -type epitaxial layer 12 is a channel region 17.
  • Portions 22a and 22b are formed.
  • the film part 22 a is formed of a protective insulating film 22 formed above the upper part of the n ⁇ -type epitaxial layer 12, that is, above the JFET region 16, on the opposite side of the n + -type source region 14 across the p-type body region 13.
  • the film part 22 b is composed of a protective insulating film 22 formed above the n + -type source region 14.
  • the protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a.
  • the thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved.
  • the insulating film 23 is formed between the JFET region 16 and the film portion 22a made of the protective insulating film 22. That is, the insulating film 23 is formed on the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween. Therefore, the film portion 22 a is formed from the protective insulating film 22 formed on the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween via the insulating film 23. Become.
  • the insulating film 23 is made of silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or the like, for example, like the gate insulating film 18. It is formed by the method or the CVD method. Further, the thickness of the insulating film 23 is, for example, about several tens of nm.
  • Film portions 22a and 22b are formed by patterning the protective insulating film 22 to form the opening 22c.
  • the opening 22 c penetrates the protective insulating film 22 and reaches the insulating film 23. Further, when the protective insulating film 22 is patterned to form the opening 22c, the insulating film 23 is patterned to form the opening 23c. Opening 23 c communicates with opening 22 c and penetrates insulating film 23 to reach p type body region 13.
  • the insulating film 23 is a higher quality film than the protective insulating film 22.
  • the density of the insulating film 23 is larger than the density of the protective insulating film 22.
  • the dielectric constant of the insulating film 23 is larger than the dielectric constant of the protective insulating film 22. At this time, the density of levels in the insulating film 23 is smaller than the density of levels in the protective insulating film 22.
  • the JFET region 16 is a region where electrons as carriers move.
  • the portion in contact with the JFET region 16 is a portion where the intensity of the electric field in the insulating film is maximized. Therefore, by forming the insulating film 23 having a level lower than the density of the levels in the protective insulating film 22 at the interface portion between the JFET region 16 and the protective insulating film 22, It is possible to prevent or suppress the carriers that move in the JFET region 16 from being captured by the existing levels. Therefore, the reliability of the insulating film on the JFET region 16 can be further improved.
  • the insulating film 23 is also formed between the n + type source region 14 and the film part 22 b made of the protective insulating film 22. That is, the insulating film 23 is also formed on the n + type source region 14. Therefore, the film part 22 b is composed of the protective insulating film 22 formed on the n + type source region 14 via the insulating film 23.
  • the insulating film 23 under the film part 22b is an insulating film formed in the same layer as the insulating film 23 under the film part 22a. Thereby, like the insulating film on the JFET region 16, the reliability of the insulating film on the n + -type source region 14 can be improved.
  • FIG. 23 is a cross-sectional view of the outer periphery of the semiconductor device of the second embodiment.
  • the central portion of the semiconductor device 1 b according to the second embodiment is formed on the upper surface side of the n + -type SiC substrate 10 and in the central region AR ⁇ b > 1.
  • the outer peripheral portion of the semiconductor device 1b of the second embodiment is formed in the area AR2 on the upper surface side of the n + type SiC substrate 10 and on the outer peripheral side of the area AR1. Yes.
  • semiconductor device 1b of the second embodiment has electric field relaxation region 24.
  • the electric field relaxation region 24 is formed in the upper layer portion of the n ⁇ -type epitaxial layer 12 in the region AR2 on the upper surface side of the n + -type SiC substrate 10 and on the outer peripheral side of the region AR1, for example, aluminum (Al)
  • it is a p-type semiconductor region made of silicon carbide (SiC) in which a p-type impurity such as boron (B) is diffused. That is, the conductivity type of the electric field relaxation region 24 as a semiconductor region is p-type.
  • Drain electrode 11 is formed on the entire bottom surface of n + -type SiC substrate 10 in regions AR1 and AR2.
  • source electrode 20 is formed in region AR2 so as to recede from the outer peripheral portion of the upper surface of n + -type SiC substrate 10 toward the center. Therefore, when a high voltage is applied to the drain electrode 11, electric lines of force from the drain electrode 11 toward the source electrode 20 are concentrated on the outer peripheral end 20a on the lower surface of the source electrode 20, and the n ⁇ type epitaxial layer in the vicinity of the outer peripheral end 20a. 12, the electric field strength is higher than that in the n ⁇ type epitaxial layer 12 (see FIG. 22) in the region AR 1.
  • an electric field relaxation region 24 for relaxing the electric field is formed in the upper layer portion of n ⁇ type epitaxial layer 12 in place of p type body region 13.
  • the electric field relaxation region 24 is formed such that the outer peripheral edge 20a of the lower surface of the source electrode 20 is included in the electric field relaxation region 24 in plan view.
  • the p-type impurity concentration in the electric field relaxation region 24 is smaller than the p-type impurity concentration in the p-type body region 13.
  • the p-type impurity concentration in the electric field relaxation region 24 is, for example, about 1 ⁇ 10 16 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the electric field relaxation region 24 is, for example, about 1 to 2 ⁇ m.
  • the p-type impurity concentration in electric field relaxation region 24 decreases from the center side of the upper surface of n + -type SiC substrate 10 toward the outer peripheral side.
  • ap + type body contact region 15 is formed in the upper layer portion of electric field relaxation region 24.
  • An insulating film 23, a protective insulating film 22, a gate insulating film 18, and an interlayer insulating film 21 are formed on the upper surface of the n ⁇ type epitaxial layer 12, the upper surface of the electric field relaxation region 24, and the p + type body contact region 15. They are formed in order from bottom to top.
  • the film part 22g made of the protective insulating film 22 formed via the insulating film 23 is formed on the electric field relaxation region 24.
  • the insulating film 23 under the film part 22g is an insulating film formed in the same layer as the insulating film 23 under the film part 22a (see FIG. 22) in the region AR1, and the protective insulating film 22 constituting the film part 22g. Is an insulating film formed in the same layer as the protective insulating film 22 (see FIG. 22) constituting the film part 22a in the region AR1.
  • the gate insulating film 18 when the gate insulating film 18 is formed by a thermal oxidation method, the gate insulating film 18 may not be formed on the protective insulating film 22. At this time, the interlayer insulating film 21 is directly formed on the protective insulating film 22.
  • a source contact hole 21b as an opening is formed in the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22, and the insulating film 23.
  • Source contact hole 21 b passes through interlayer insulating film 21, gate insulating film 18, protective insulating film 22, and insulating film 23 and reaches the upper surface of p + -type body contact region 15. That is, the upper surface of the p + type body contact region 15 is exposed at the bottom surface of the source contact hole 21b.
  • the source electrode 20 is formed on the interlayer insulating film 21 including the bottom and side surfaces of the source contact hole 21b.
  • the source electrode 20 is electrically connected to the p + -type body contact region 15 via the source contact hole 21b formed in the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22, and the insulating film 23.
  • the p + type body contact region 15 is electrically connected to the electric field relaxation region 24. Therefore, the source electrode 20 is electrically connected to the electric field relaxation region 24 through the p + type body contact region 15.
  • the p + -type body contact region 15 may not be formed in the upper layer portion of the electric field relaxation region 24, and the source electrode 20 may be electrically connected directly to the electric field relaxation region 24.
  • an insulating film 23 of higher quality than the protective insulating film 22 is formed between the upper surface of the electric field relaxation region 24 and the protective insulating film 22 in the region AR2.
  • the protective insulating film 22 is not in contact with the electric field relaxation region 24, which is a region where current flows, it is possible to prevent or suppress carriers from being trapped in the levels existing in the protective insulating film 22. it can. Therefore, the performance of the semiconductor device 1b can be maintained even when the strength of the electric field applied to the electric field relaxation region 24 and the n ⁇ -type epitaxial layer 12 is larger than when the insulating film 23 is not formed.
  • the insulating film 23 by forming the insulating film 23, the area of the region where the electric field relaxation region 24 is formed can be reduced while maintaining the performance of the semiconductor device 1b, and the area of the semiconductor device 1b can be reduced. it can.
  • FIG. 24 is a flowchart showing a part of the manufacturing process of the semiconductor device of Second Embodiment.
  • 25 to 28 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device of the second embodiment.
  • the manufacturing process in the region AR1 on the upper surface side and the center side of the n + type SiC substrate 10 will be described.
  • steps S11 to S15 and steps S18 to S23 in the second embodiment are the same as steps S11 to S15 and steps S18 to S23 in the first embodiment. It is the same as each process (refer FIG. 6).
  • n ⁇ type epitaxial layer 12 p type body region 13, n + type source region 14 and p + type body contact region 15 are formed on the upper surface of n + type SiC substrate 10. (Step S11 to Step S15 in FIG. 24).
  • a two-layer insulating film including the insulating film 23 and the protective insulating film 22 is formed (step S26 in FIG. 24).
  • step S26 first, as shown in FIG. 25, on the upper surface of the n ⁇ type epitaxial layer 12, on the p type body region 13, on the n + type source region 14 and on the p + type body contact region 15. Then, the insulating film 23 is formed.
  • the density of the insulating film 23 is larger than the density of the protective insulating film 22 (see FIG. 26 described later). Further, the dielectric constant of the insulating film 23 is larger than the dielectric constant of the protective insulating film 22.
  • an insulating film formed at a relatively high temperature can be used.
  • an insulating film formed by heat-treating a film deposited at a relatively low temperature at a high temperature can be used.
  • an insulating film 23 preferably, for example, silicon oxide (SiO 2), silicon oxynitride (SiON), use various films made of aluminum oxide (Al 2 O 3) or hafnium oxide (HfO 2) be able to.
  • a laminated film in which the above various films are suitably laminated can be used.
  • an insulating film 23 can be formed by a thermal oxidation method or a CVD method at a temperature of, for example, 800 ° C. or higher.
  • the thickness of the insulating film 23 can be set to, for example, about several tens of nm.
  • a protective insulating film 22 is formed on the insulating film 23 as shown in FIG.
  • the process of forming this protective insulating film 22 can be the same as the process of step S16 in the first embodiment.
  • a two-layer insulating film composed of the insulating film 23 and the protective insulating film 22 is patterned (step S27 in FIG. 24).
  • the protective insulating film 22 is processed, that is, patterned by the photolithography technique and the dry etching technique to form the opening 22c, and the film part 22a and the film part 22b are formed.
  • the step of forming the opening 22c can be the same as the step S17 in the first embodiment. However, in the second embodiment, the opening 22 c penetrates the protective insulating film 22 and reaches the insulating film 23.
  • step S27 the opening 23c is formed by processing, that is, patterning, the insulating film 23 by a photolithography technique and a dry etching technique. Opening 23 c communicates with opening 22 c and penetrates insulating film 23 to reach the upper surface of p-type body region 13.
  • a film portion 22a is formed on the upper surface of the n ⁇ type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween via the insulating film 23, and the n + type source region
  • a film portion 22 b is formed on the insulating film 23 on the upper surface 14. Further, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 23c.
  • step S18 in FIG. 24 the gate insulating film 18 is formed (step S18 in FIG. 24).
  • step S18 as shown in FIG. 28, the gate insulating film 18 is formed on the upper surface of the p-type body region 13 exposed in the opening 23c.
  • the process of step S18 can be the same as the process of step S18 in the first embodiment except that the insulating film 23 is formed under the film portions 22a and 22b.
  • steps similar to the steps S19 and S20 in FIG. 6 are performed to form the gate electrode 19 and the interlayer insulating film 21 as shown in FIG. 22 (steps S19 and S20 in FIG. 24). .
  • a step similar to the step S21 in FIG. 6 is performed to form the source contact hole 21a as shown in FIG. 22 (step S21 in FIG. 24).
  • a source contact hole 21 a as an opening is formed in the insulating film 23. . That is, a source contact hole 21 a that penetrates the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22 and the insulating film 23 and reaches the n + type source region 14 and the p + type body contact region 15 is formed.
  • step S22 and step S23 in FIG. 24 are performed to form the source electrode 20 and the drain electrode 11, and as shown in FIG.
  • the semiconductor device 1b can be manufactured.
  • ⁇ Method for Manufacturing Semiconductor Device in Outer Periphery> 29 to 32 are cross-sectional views of the outer periphery during the manufacturing process of the semiconductor device of the second embodiment.
  • the manufacturing steps of the semiconductor device in the region AR2 on the upper surface side of the n + -type SiC substrate 10 and on the outer peripheral side of the region AR1 there are differences from the manufacturing steps of the semiconductor device in the region AR1 described above. ,explain.
  • step S13 of FIG. 24 an electric field relaxation region 24 is formed in the region AR2 in place of the p-type body region 13 (see FIG. 22) in the upper layer portion of the n ⁇ -type epitaxial layer 12, as shown in FIG. Thereafter, in step S15 of FIG. 24, ap + type body contact region 15 is formed in the upper portion of electric field relaxation region 24 in region AR2, as shown in FIG.
  • step S26 of FIG. 24 in the region AR2, as shown in FIG. 30, first, on the upper surface of the n ⁇ type epitaxial layer 12, on the upper surface of the electric field relaxation region 24, and on the p + type body contact region 15 Then, an insulating film 23 is formed. Then, in the region AR2, as shown in FIG. 31, the protective insulating film 22 is formed on the insulating film 23.
  • step S27 of FIG. 24 the two-layer insulating film including the insulating film 23 and the protective insulating film 22 is not patterned in the area AR2.
  • step S18 of FIG. 24 the gate insulating film 18 is formed on the protective insulating film 22 in the area AR2 as shown in FIG. Note that when the gate insulating film 18 is formed in the region AR1, for example, by a thermal oxidation method, the gate insulating film 18 is not formed on the protective insulating film 22 in the region AR2.
  • step S19 of FIG. 24 as shown in FIG. 23, the gate electrode 19 (see FIG. 22) is not formed in the area AR2.
  • step S20 of FIG. 24 the interlayer insulating film 21 is formed on the gate insulating film 18 in the region AR2 as shown in FIG.
  • step S21 of FIG. 24 the source contact hole 21b is formed in the area AR2 as shown in FIG. In this region AR2, a source contact hole 21b that penetrates through the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22 and the insulating film 23 and reaches the p + type body contact region 15 is formed.
  • step S22 of FIG. 24 in the region AR2, the source electrode 20 is formed on the interlayer insulating film 21 so as to cover the bottom surface and the inner wall of the source contact hole 21b.
  • film portions 22a and 22b are formed as in the semiconductor device 1 of the first embodiment.
  • the gate electrode 19 is formed on the JFET region 16 via at least the film part 22a.
  • an insulating film 23 of higher quality than the protective insulating film 22 constituting the film part 22a is formed between the JFET region 16 and the film part 22a.
  • Embodiment 3 Power conversion device
  • the power converter of Embodiment 3 is an inverter provided with the semiconductor device of Embodiment 1.
  • FIG. 33 is a diagram illustrating a configuration of the power conversion device according to the third embodiment.
  • the power conversion device 31 includes an inverter 32 as a three-phase inverter provided with the semiconductor device 1 of the first embodiment, a load 33 such as a motor, a DC power supply 34, and a capacity such as a capacitor. 35.
  • the load 33 is connected to the output side of the inverter 32, and the DC power supply 34 and the capacitor 35 are connected to the input side of the inverter 32.
  • the inverter 32 includes gate drive circuits 36u, 36v, 36w, 36x, 36y, and 36z, and switch elements 37u, 37v, 37w, 37x, 37y, and 37z.
  • the inverter 32 includes a drain node N1 and a source node N2 as a pair of DC input terminals.
  • Switch elements 37u and 37x are connected in series between drain node N1 and source node N2.
  • Switch elements 37v and 37y are connected in series between drain node N1 and source node N2.
  • Switch elements 37w and 37z are connected in series between drain node N1 and source node N2.
  • the switch elements 37u, 37v, and 37w are disposed on the upper arm side, that is, the high voltage side
  • the switch elements 37x, 37y, and 37z are disposed on the lower arm side, that is, the low voltage side.
  • the inverter 32 includes a U-phase output node N3, a V-phase output node N4, and a W-phase output node N5 as three-phase AC output terminals.
  • the output node N3 is connected to the switch element 37x side of the switch element 37u and the switch element 37u side of the switch element 37x.
  • the output node N4 is connected to the switch element 37y side of the switch element 37v and the switch element 37v side of the switch element 37y.
  • the output node N5 is connected to the switch element 37z side of the switch element 37w and the switch element 37w side of the switch element 37z. Therefore, switch elements 37u and 37x are U-phase switch elements, switch elements 37v and 37y are V-phase switch elements, and switch elements 37w and 37z are W-phase switch elements.
  • Each of switch elements 37u, 37v, 37w, 37x, 37y and 37z includes a MISFET 38 and a body diode 39.
  • the semiconductor device 1 (see FIG. 1) of the first embodiment can be used as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z.
  • the MISFET 38 includes the drain electrode 11, the n + type SiC substrate 10, the n ⁇ type epitaxial layer 12, the p type body region 13, the n + type source region 14, the p + type body contact region 15, the gate insulating film 18, This is a vertical MISFET formed by the gate electrode 19 and the source electrode 20 (see FIG. 1).
  • the body diode 39 is a diode formed by the drain electrode 11, the n + type SiC substrate 10, the n ⁇ type epitaxial layer 12, the p type body region 13, the p + type body contact region 15 and the source electrode 20 ( (See FIG. 1).
  • the gate drive circuit 36u is connected to the gate electrode of the MISFET 38 of the switch element 37u, and drives the switch element 37u.
  • the gate drive circuit 36x is connected to the gate electrode of the MISFET 38 of the switch element 37x, and drives the switch element 37x.
  • the gate drive circuit 36v is connected to the gate electrode of the MISFET 38 of the switch element 37v and drives the switch element 37v.
  • the gate drive circuit 36y is connected to the gate electrode of the MISFET 38 of the switch element 37y, and drives the switch element 37y.
  • the gate drive circuit 36w is connected to the gate electrode of the MISFET 38 of the switch element 37w, and drives the switch element 37w.
  • the gate drive circuit 36z is connected to the gate electrode of the MISFET 38 of the switch element 37z, and drives the switch element 37z.
  • each of the switch elements 37u, 37v and 37w provided on the upper arm side of the inverter 32 is connected to the drain node N1 arranged on the input side of the inverter 32 and on the upper arm side.
  • One end of each of the switching elements 37x, 37y and 37z on the lower arm side of the inverter 32 is connected to the source node N2 arranged on the input side of the inverter 32 and on the lower arm side.
  • a DC power supply 34 and a capacitor 35 are connected in parallel with each other between the drain node N1 and the source node N2. Therefore, the voltage VPP is applied between the drain node N1 and the source node N2 by the DC power supply 34.
  • Each of the gate drive circuits 36u, 36v, 36w, 36x, 36y, and 36z has switching elements 37u, 37v, 37w, 37x, so that the corresponding switch elements are switched on and off at preset timings.
  • Each of 37y and 37z is driven.
  • three-phase AC signals having different phases that is, U-phase, V-phase, and W-phase AC signals are generated from the voltage VPP that is a DC signal. That is, in each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z, the power is converted by switching between the on state and the off state.
  • the load 33 is driven by the three-phase AC signal.
  • the body diode 39 is built in the semiconductor device 1, and it is possible to flow a reflux current through the body diode 39 without using an antiparallel diode, that is, a reflux diode. is there. Therefore, in the power conversion device 31 of the third embodiment having the inverter 32 provided with the semiconductor device 1 of the first embodiment as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z, necessary components Thus, the power converter 31 can be easily downsized.
  • the power conversion device 31 according to the third embodiment includes the semiconductor device 1 according to the first embodiment as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z. According to the semiconductor device 1 of the first embodiment, the strength of the electric field in the insulating film on the JFET region 16 is reduced, the reliability of the insulating film is improved, the feedback capacitance is reduced, and the width of the JFET region 16 is reduced. Since the loss at the time of power conversion in the inverter can be reduced, a large cooling device may not be provided. Therefore, the power conversion device 31 can be easily reduced in cost, size, or weight by reducing the size of the cooling device.
  • the semiconductor device 1a of the first modification of the first embodiment or the semiconductor device 1b of the second embodiment is provided instead of the semiconductor device 1 of the first embodiment. Also good. In this case, since the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased, Further, it can be easily reduced in cost, size, or weight.
  • the railway vehicle according to the fourth embodiment is a railway vehicle including the power conversion device according to the third embodiment.
  • FIG. 34 is a diagram illustrating a configuration of the railway vehicle according to the fourth embodiment.
  • the railway vehicle 40 includes a pantograph 41 as a current collector, a transformer 42, a power converter 43, a load 44 that is an AC motor, and wheels 45.
  • the power conversion device 43 includes a converter 46, a capacitor 47 that is a capacitor, for example, and an inverter 48.
  • the converter 46 has switch elements 49 and 50.
  • the switch element 49 is disposed on the upper arm side, that is, the high voltage side
  • the switch element 50 is disposed on the lower arm side, that is, the low voltage side.
  • the switch elements 49 and 50 are shown for one phase among a plurality of phases.
  • the inverter 48 has switch elements 51 and 52.
  • the switch element 51 is arranged on the upper arm side, that is, the high voltage side
  • the switch element 52 is arranged on the lower arm side, that is, the low voltage side.
  • the switch elements 51 and 52 are shown for one of the three phases U phase, V phase and W phase.
  • One end of the primary side of the transformer 42 is connected to the overhead line 41 a via the pantograph 41.
  • the other end of the primary side of the transformer 42 is connected to the line 45 a via the wheel 45.
  • One end of the secondary side of the transformer 42 is connected to a terminal on the upper arm side opposite to the load 44 of the converter 46.
  • the other end of the secondary side of the transformer 42 is connected to a terminal on the lower arm side opposite to the load 44 of the converter 46.
  • the terminal on the load 44 side and the upper arm side of the converter 46 is connected to the terminal on the upper arm side opposite to the load 44 of the inverter 48. Further, the terminal on the load 44 side and the lower arm side of the converter 46 is connected to the terminal on the lower arm side opposite to the load 44 of the inverter 48. Further, a capacitor 47 is connected between a terminal on the side opposite to the load 44 of the inverter 48 on the upper arm side and a terminal on the side opposite to the load 44 of the inverter 48 and on the lower arm side. Although not shown in FIG. 34, each of the three terminals on the output side of the inverter 48 is connected to the load 44 as a U phase, a V phase, and a W phase.
  • the inverter 32 (refer FIG. 33) contained in the power converter device 31 of Embodiment 3 can be used as the inverter 48.
  • the AC power collected from the overhead line 41 a by the pantograph 41 is transformed into desired DC power by the converter 46 after the voltage is transformed by the transformer 42.
  • the DC power converted by the converter 46 is smoothed by the capacitor 47.
  • the DC power whose voltage is smoothed by the capacitor 47 is converted into AC power by the inverter 48.
  • the AC power converted by the inverter 48 is supplied to the load 44.
  • the load 44 supplied with AC power rotates the wheel 45, thereby accelerating the railway vehicle.
  • the inverter 48 of the railway vehicle 40 of the fourth embodiment the inverter 32 (see FIG. 33) included in the power conversion device 31 of the third embodiment can be used.
  • the switching element such as the switching element 37u provided in the inverter 32
  • a film part 22a (see FIG. 1) and a film part 22b (see FIG. 1) are formed.
  • the semiconductor device 1 of the first embodiment the strength of the electric field in the insulating film on the JFET region 16 is reduced, the reliability of the insulating film is improved, the feedback capacitance is reduced, and the width of the JFET region 16 is reduced. Since the loss at the time of power conversion in the inverter can be reduced, a large cooling device may not be provided. Therefore, the inverter 32 can be easily reduced in cost, size, or weight by reducing the size of the cooling device. Therefore, the railway vehicle 40 including the inverter 32 as the inverter 48 can be easily reduced in cost, size, or weight.
  • the semiconductor device 1a of the first modification of the first embodiment is used instead of the semiconductor device 1 of the first embodiment.
  • the semiconductor device 1b of the second embodiment may be provided.
  • the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased.
  • the cost, size and weight can be reduced. Therefore, the railway vehicle 40 including the inverter 48 can be more easily reduced in cost, size, or weight.
  • the semiconductor device 1 of the first embodiment may be provided as the switch elements 49 and 50.
  • converter 46 may be provided with semiconductor device 1a of the first modification example of the first embodiment or semiconductor device 1b of the second embodiment instead of semiconductor device 1 of the first embodiment.
  • the switch elements 49 and 50 the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased. Therefore, the converter 46 can be further easily reduced in cost, size, or weight. Therefore, the railway vehicle 40 including the converter 46 can be more easily reduced in cost, size, or weight.
  • the power conversion device of the third embodiment can be applied to various electric devices other than railroad vehicles such as an electric vehicle or a solar power generation device.
  • the power conversion device according to the third embodiment can be easily reduced in cost, size, or weight. Therefore, an electric vehicle including the power conversion device can be reduced. Cost reduction, size reduction or weight reduction can be achieved.
  • it is possible to increase the degree of freedom of design in the electric vehicle for example, the interior of the electric vehicle including the power conversion device can be widened.
  • the present invention is effective when applied to a semiconductor device, a manufacturing method thereof, a power conversion device, and a railway vehicle.

Abstract

A semiconductor device (1) has: a p-type body region (13) formed as an upper layer portion of an n--type epitaxial layer (12); and an n+-type source region (14) and a p+-type body contact region (15), which are formed as upper layer portions of the p-type body region (13). The semiconductor device (1) also has: a film section (22a) formed on an upper surface of the n--type epitaxial layer (12); and a film section (22b) formed on the n+-type source region (14). Furthermore, the semiconductor device (1) has, on an upper surface of the p-type body region (13), a gate electrode (19) that is formed with a gate insulating film (18) therebetween. The gate electrode (19) is continuously formed from above the upper surface of the p-type body region (13) to above the upper surface of the film section (22a).

Description

半導体装置およびその製造方法、電力変換装置ならびに鉄道車両Semiconductor device and manufacturing method thereof, power conversion device, and railcar
　本発明は半導体装置およびその製造技術に関し、縦型ＭＩＳＦＥＴを備えた半導体装置およびその製造技術、ならびに、そのような半導体装置を備えた電力変換装置および鉄道車両に関する。 The present invention relates to a semiconductor device and a manufacturing technology thereof, and relates to a semiconductor device including a vertical MISFET and a manufacturing technology thereof, and a power conversion device and a railway vehicle including such a semiconductor device.
　モータ等を駆動するための電力を、直流と交流との間で変換する電力変換装置として、インバータが用いられている。従来のインバータでは、互いに逆並列に接続されたＩＧＢＴ（Insulated Gate Bipolar Transistor）と、ＰＩＮ（P-intrinsic-n）ダイオードとからなる素子対が、高電圧側の上アーム、および、低電圧側の下アームのそれぞれに、例えば１対ずつ設けられている。ＩＧＢＴおよびＰＩＮダイオードの各々は、シリコン（Ｓｉ）を用いた半導体装置である。 An inverter is used as a power conversion device that converts electric power for driving a motor or the like between direct current and alternating current. In a conventional inverter, a pair of elements composed of IGBTs (Insulated Gate Bipolar Transistors) and PIN (P-intrinsic-n) diodes connected in antiparallel to each other are connected to the upper arm on the high voltage side and the low voltage side. For example, a pair of lower arms is provided. Each of the IGBT and the PIN diode is a semiconductor device using silicon (Si).
　Ｓｉを用いたＩＧＢＴおよびＰＩＮダイオードが備えられたインバータにおける電力変換の際の損失は、Ｓｉの物性値から決定される理論値に等しい値まで低減されている。そのため、Ｓｉを用いた半導体装置が備えられたインバータにおける電力変換の際の損失をさらに低減することは、極めて困難である。 The loss at the time of power conversion in the inverter provided with the IGBT and PIN diode using Si has been reduced to a value equal to the theoretical value determined from the physical property value of Si. Therefore, it is extremely difficult to further reduce the loss during power conversion in the inverter provided with the semiconductor device using Si.
　一方、炭化ケイ素（ＳｉＣ）または窒化ガリウム（ＧａＮ）などのいわゆるワイドバンドギャップ半導体の絶縁破壊電界は、シリコン（Ｓｉ）の絶縁破壊電界に比べて１桁程度大きい。特に、ＳｉＣを用いた縦型ＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）の耐電圧は、数百Ｖから数ｋＶの幅広い電圧の範囲にある。そのため、ＳｉＣを用いた縦型ＭＩＳＦＥＴでは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、オン抵抗が大幅に低減されることが予想される。また、縦型ＭＩＳＦＥＴはユニポーラ素子であるため、ユニポーラ素子ではないＩＧＢＴに比べて、オンオフ状態を高速に切り替えることができる。 On the other hand, the breakdown electric field of a so-called wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) is about an order of magnitude larger than that of silicon (Si). In particular, the withstand voltage of a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) using SiC is in a wide voltage range from several hundred volts to several kV. Therefore, in the vertical MISFET using SiC, the on-resistance is expected to be significantly reduced as compared with the vertical MISFET using Si. Further, since the vertical MISFET is a unipolar element, the on / off state can be switched at a higher speed than an IGBT that is not a unipolar element.
　特開平８－２８８３０３号公報（特許文献１）には、Ｓｉを用いた縦型ＭＩＳＦＥＴについての技術が記載されており、国際公開第２０１０／０７３９９１号公報には、ＳｉＣを用いた縦型ＭＩＳＦＥＴについての技術が記載されている。このような縦型パワーＭＩＳＦＥＴでは、ドレイン電極とソース電極との間に、ｎ型のドレイン領域、ｐ型のボディ領域およびｎ型のソース領域が設けられ、ｐ型のボディ領域の表面にゲート絶縁膜を介してゲート電極が設けられている。 Japanese Patent Application Laid-Open No. 8-288303 (Patent Document 1) describes a technique regarding a vertical MISFET using Si, and International Publication No. 2010/073991 relates to a vertical MISFET using SiC. The technology is described. In such a vertical power MISFET, an n-type drain region, a p-type body region, and an n-type source region are provided between the drain electrode and the source electrode, and gate insulation is provided on the surface of the p-type body region. A gate electrode is provided through the film.
特開平８－２８８３０３号公報JP-A-8-288303 国際公開第２０１０／０７３９９１号公報International Publication No. 2010/073991
　前述したように、炭化ケイ素（ＳｉＣ）の絶縁破壊電界は、シリコン（Ｓｉ）の絶縁破壊電界よりも１桁程度大きい。そのため、ＳｉＣを用いた縦型ＭＩＳＦＥＴは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ型のドレイン領域中の電界が１桁程度大きくなるように設計される。具体的には、ＳｉＣを用いた縦型ＭＩＳＦＥＴでは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ型のドレイン領域中の不純物濃度を大きくする。また、ＳｉＣを用いた縦型ＭＩＳＦＥＴでは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ型のドレイン領域の厚さを小さくする。このとき、ｎ型のドレイン領域の厚さを小さくすることで、縦型ＭＩＳＦＥＴのオン抵抗は、低減される。 As described above, the breakdown electric field of silicon carbide (SiC) is about one digit larger than the breakdown electric field of silicon (Si). Therefore, the vertical MISFET using SiC is designed so that the electric field in the n-type drain region is about one digit larger than that of the vertical MISFET using Si. Specifically, in the vertical MISFET using SiC, the impurity concentration in the n-type drain region is increased as compared with the vertical MISFET using Si. Further, in the vertical MISFET using SiC, the thickness of the n-type drain region is made smaller than that of the vertical MISFET using Si. At this time, the on-resistance of the vertical MISFET is reduced by reducing the thickness of the n-type drain region.
　ところが、縦型ＭＩＳＦＥＴのオン抵抗が低減される一方で、ｐ型のボディ領域を挟んでｎ型のソース領域と反対側のｎ型のドレイン領域、すなわちＪＦＥＴ（Junction Field Effect Transistor）領域上のゲート絶縁膜中の電界の強度が増大する。その結果、例えば閾値電圧が不均一になることなどにより、ゲート絶縁膜の信頼性が低下する。また、ゲート電極とドレイン電極との間の容量である帰還容量が、増大する。この帰還容量が大きい場合には、例えば電力変換装置を高速に動作させることができないおそれがある。 However, while the on-resistance of the vertical MISFET is reduced, the n-type drain region opposite to the n-type source region across the p-type body region, that is, the gate on the JFET (Junction-Field-Effect-Transistor) region The strength of the electric field in the insulating film increases. As a result, the reliability of the gate insulating film decreases due to, for example, non-uniform threshold voltages. In addition, the feedback capacitance, which is the capacitance between the gate electrode and the drain electrode, increases. If the feedback capacity is large, for example, the power converter may not be operated at high speed.
　例えば、鉄道車両用など比較的高い電圧で用いられるインバータに備えられた縦型ＭＩＳＦＥＴでは、ＪＦＥＴ領域上のゲート絶縁膜中の電界の強度を小さくし、帰還容量を小さくすることと、ＪＦＥＴ領域の幅を広くすることとは、両立しない。したがって、例えばＪＦＥＴ領域の幅をあまり広くすることができないことなどにより、インバータにおける電力変換の際の損失が大きくなり、インバータの発熱量が大きくなる。そのため、大型の冷却装置が設けられる必要が生ずる。よって、縦型ＭＩＳＦＥＴを備えた電力変換装置、または、この電力変換装置を含む鉄道車両についての製造コストを低減することができない。あるいは、縦型ＭＩＳＦＥＴを備えた電力変換装置、または、この電力変換装置を含む鉄道車両を、容易に小型化または軽量化することができない。 For example, in a vertical MISFET provided in an inverter that is used at a relatively high voltage such as for a railway vehicle, the strength of the electric field in the gate insulating film on the JFET region is reduced, the feedback capacitance is reduced, Widening is not compatible. Therefore, for example, the loss of power conversion in the inverter increases due to the fact that the width of the JFET region cannot be increased so much, and the amount of heat generated by the inverter increases. Therefore, it is necessary to provide a large cooling device. Therefore, it is not possible to reduce the manufacturing cost of the power conversion device including the vertical MISFET or the railway vehicle including the power conversion device. Alternatively, a power converter provided with a vertical MISFET or a railway vehicle including the power converter cannot be easily reduced in size or weight.
　本発明の目的は、ＪＦＥＴ領域上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量を小さくし、かつ、オン抵抗を低くすることができる半導体装置を提供することにある。そして、本発明の目的は、上記のような半導体装置を備え、容易に低コスト化、小型化もしくは軽量化することができる電力変換装置、または、このような電力変換装置を含み、容易に低コスト化、小型化もしくは軽量化することができる鉄道車両を提供することにある。 An object of the present invention is to provide a semiconductor device that can reduce the strength of an electric field in an insulating film on a JFET region, improve the reliability of the insulating film, reduce the feedback capacitance, and reduce the on-resistance. It is to provide. An object of the present invention is to provide a power converter that includes the semiconductor device as described above and can be easily reduced in cost, reduced in size, or reduced in weight, or includes such a power converter. The object is to provide a railway vehicle that can be reduced in cost, size, or weight.
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　代表的な実施の形態による半導体装置は、第１導電型の半導体基板と、半導体基板の下面に形成されたドレイン電極と、半導体基板の上面に形成された、第１導電型の半導体層とを有する。また、当該半導体装置は、半導体層の上層部に形成され、第１導電型と異なる第２導電型の第１半導体領域と、第１半導体領域の上層部に形成された、第１導電型の第２半導体領域と、第１半導体領域の上層部に形成された、第２導電型の第３半導体領域とを有する。さらに、当該半導体装置は、第１半導体領域を挟んで第２半導体領域と反対側の半導体層の上面上に形成された第１絶縁膜からなる第１膜部と、第２半導体領域上に第１絶縁膜と同層に形成された第２絶縁膜からなる第２膜部とを有する。また、当該半導体装置は、第２半導体領域と半導体層とに挟まれた第１半導体領域の上面上に、ゲート絶縁膜を介して形成されたゲート電極と、第２半導体領域上および第３半導体領域上に形成されたソース電極とを有する。ゲート電極は、第２半導体領域と半導体層とに挟まれた第１半導体領域の上面上から、第１膜部の上面上にかけて、連続的に形成されている。 A semiconductor device according to a representative embodiment includes a first conductivity type semiconductor substrate, a drain electrode formed on a lower surface of the semiconductor substrate, and a first conductivity type semiconductor layer formed on an upper surface of the semiconductor substrate. Have. In addition, the semiconductor device is formed in an upper layer portion of the semiconductor layer and has a second conductivity type first semiconductor region different from the first conductivity type, and a first conductivity type formed in the upper layer portion of the first semiconductor region. A second semiconductor region; and a third semiconductor region of a second conductivity type formed in an upper layer portion of the first semiconductor region. Further, the semiconductor device includes a first film portion made of a first insulating film formed on the upper surface of the semiconductor layer opposite to the second semiconductor region across the first semiconductor region, and a second film on the second semiconductor region. And a second film portion made of a second insulating film formed in the same layer as the first insulating film. In addition, the semiconductor device includes a gate electrode formed on a top surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film, the second semiconductor region, and the third semiconductor. A source electrode formed on the region. The gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion.
　また、代表的な実施の形態による半導体装置の製造方法では、第１導電型の半導体基板の上面に第１導電型の半導体層を形成し、半導体層の上層部に、第１導電型と異なる第２導電型の第１半導体領域を形成し、第１半導体領域の上層部に、第１導電型の第２半導体領域、および、第２導電型の第３半導体領域を形成する。次いで、半導体層上に、第１絶縁膜を形成する。次いで、第１絶縁膜をパターニングすることで、第１半導体領域を挟んで第２半導体領域と反対側の半導体層の上面上に、第１絶縁膜からなる第１膜部を形成し、第２半導体領域上に、第１絶縁膜からなる第２膜部を形成する。次いで、第２半導体領域と半導体層とに挟まれた第１半導体領域の上面上に、ゲート絶縁膜を介してゲート電極を形成する。次いで、第２半導体領域上および第３半導体領域上にソース電極を形成し、半導体基板の下面にドレイン電極を形成する。そして、ゲート電極を形成する際に、第２半導体領域と半導体層とに挟まれた第１半導体領域の上面上から、第１膜部の上面上にかけて、連続的にゲート電極を形成する。 Further, in the method of manufacturing a semiconductor device according to the representative embodiment, the first conductivity type semiconductor layer is formed on the upper surface of the first conductivity type semiconductor substrate, and the upper layer portion of the semiconductor layer is different from the first conductivity type. A second conductivity type first semiconductor region is formed, and a first conductivity type second semiconductor region and a second conductivity type third semiconductor region are formed in an upper layer portion of the first semiconductor region. Next, a first insulating film is formed over the semiconductor layer. Next, by patterning the first insulating film, a first film portion made of the first insulating film is formed on the upper surface of the semiconductor layer opposite to the second semiconductor region with the first semiconductor region interposed therebetween. A second film portion made of the first insulating film is formed on the semiconductor region. Next, a gate electrode is formed on the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film. Next, a source electrode is formed on the second semiconductor region and the third semiconductor region, and a drain electrode is formed on the lower surface of the semiconductor substrate. Then, when forming the gate electrode, the gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　代表的な実施の形態によれば、半導体装置において、ＪＦＥＴ領域上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量を小さくし、かつ、オン抵抗を低くすることができる。そして、当該半導体装置を備えた電力変換装置、または、このような電力変換装置を含む鉄道車両を、容易に低コスト化、小型化または軽量化することができる。 According to a typical embodiment, in a semiconductor device, the strength of the electric field in the insulating film on the JFET region is reduced to improve the reliability of the insulating film, the feedback capacitance is reduced, and the on-resistance is increased. Can be lowered. And the power converter device provided with the said semiconductor device, or a railway vehicle including such a power converter device can be reduced in cost, size, or weight easily.
実施の形態１の半導体装置の要部断面図である。2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. 実施の形態１の半導体装置の上面図である。2 is a top view of the semiconductor device of First Embodiment. FIG. 図１において、縦型ＭＩＳＦＥＴがオン状態のときに電子が流れる経路を模式的に示した図である。In FIG. 1, it is the figure which showed typically the path | route through which an electron flows, when a vertical MISFET is an ON state. 実施の形態１の第１変形例の半導体装置の要部断面図である。FIG. 10 is a main-portion cross-sectional view of the semiconductor device in the first modification example of the first embodiment; 実施の形態１の第１変形例の半導体装置の上面図である。FIG. 10 is a top view of a semiconductor device according to a first modification example of the first embodiment. 実施の形態１の半導体装置の製造工程の一部を示すフロー図である。FIG. 4 is a flowchart showing a part of the manufacturing process of the semiconductor device of First Embodiment; 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 実施の形態１の半導体装置の製造工程中の要部断面図である。7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 比較例１の半導体装置の要部断面図である。FIG. 10 is a cross-sectional view of a principal part of a semiconductor device of Comparative Example 1. 実施の形態２の半導体装置の要部断面図である。FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 2; 実施の形態２の半導体装置の外周部における断面図である。FIG. 6 is a cross-sectional view of the outer periphery of the semiconductor device of the second embodiment. 実施の形態２の半導体装置の製造工程の一部を示すフロー図である。FIG. 10 is a flowchart showing a part of the manufacturing process of the semiconductor device of the second embodiment. 実施の形態２の半導体装置の製造工程中の要部断面図である。FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. 実施の形態２の半導体装置の製造工程中の要部断面図である。FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. 実施の形態２の半導体装置の製造工程中の要部断面図である。FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. 実施の形態２の半導体装置の製造工程中の要部断面図である。FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. 実施の形態２の半導体装置の製造工程中の外周部における断面図である。FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment. 実施の形態２の半導体装置の製造工程中の外周部における断面図である。FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment. 実施の形態２の半導体装置の製造工程中の外周部における断面図である。FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment. 実施の形態２の半導体装置の製造工程中の外周部における断面図である。FIG. 10 is a cross-sectional view of the outer periphery during the manufacturing process of the semiconductor device of Second Embodiment. 実施の形態３の電力変換装置の構成を示す図である。It is a figure which shows the structure of the power converter device of Embodiment 3. FIG. 実施の形態４の鉄道車両の構成を示す図である。FIG. 10 is a diagram showing a configuration of a railway vehicle according to a fourth embodiment.
　以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。 In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.
　また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。 Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.
　さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことはいうまでもない。 Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.
　同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
　また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図であっても図面を見易くするためにハッチングを付す場合もある。 In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
　（実施の形態１）
　＜半導体装置＞
　本発明の実施の形態１の半導体装置について説明する。実施の形態１の半導体装置は、炭化ケイ素（ＳｉＣ）からなる縦型ＭＩＳＦＥＴを備えたものである。 (Embodiment 1)
<Semiconductor device>
A semiconductor device according to the first embodiment of the present invention will be described. The semiconductor device according to the first embodiment includes a vertical MISFET made of silicon carbide (SiC).
　図１は、実施の形態１の半導体装置の要部断面図である。図２は、実施の形態１の半導体装置の上面図である。図１は、図２のＡ－Ａ線に沿った断面図である。なお、図２においては、理解を簡単にするために、ゲート絶縁膜１８（図１参照）、ゲート電極１９（図１参照）、ソース電極２０（図１参照）および層間絶縁膜２１（図１参照）を除去、すなわち透視した状態を図示している。また、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１（図1参照）に形成された部分、すなわち半導体装置の中心部について、説明する。 FIG. 1 is a cross-sectional view of a main part of the semiconductor device of the first embodiment. FIG. 2 is a top view of the semiconductor device of the first embodiment. FIG. 1 is a cross-sectional view taken along line AA in FIG. In FIG. 2, for easy understanding, the gate insulating film 18 (see FIG. 1), the gate electrode 19 (see FIG. 1), the source electrode 20 (see FIG. 1), and the interlayer insulating film 21 (see FIG. 1). (See) is removed, that is, it is seen through. In the following, the portion formed in the region AR1 (see FIG. 1) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
　図１および図２に示すように、本実施の形態１の半導体装置１は、縦型ＭＩＳＦＥＴを備えた半導体装置であり、ｎ＋型ＳｉＣ基板１０、ドレイン電極１１、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を有する。また、本実施の形態１の半導体装置１は、ゲート絶縁膜１８、ゲート電極１９、ソース電極２０および層間絶縁膜２１を有する。 As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment is a semiconductor device including a vertical MISFET, and includes an n + type SiC substrate 10, a drain electrode 11, an n − type epitaxial layer 12, p type body region 13, n + type source region 14 and p + type body contact region 15. In addition, the semiconductor device 1 of the first embodiment includes a gate insulating film 18, a gate electrode 19, a source electrode 20, and an interlayer insulating film 21.
　ｎ＋型ＳｉＣ基板１０は、例えば窒素（Ｎ）またはリン（Ｐ）などのｎ型不純物を導入した炭化ケイ素（ＳｉＣ）からなるｎ型の半導体基板である。すなわち半導体基板としてのｎ＋型ＳｉＣ基板１０の導電型は、ｎ型である。ｎ＋型ＳｉＣ基板１０におけるｎ型の不純物濃度は、比較的大きく、例えば１×１０１８～１×１０２１ｃｍ－３程度である。また、ｎ＋型ＳｉＣ基板１０の厚さは、例えば５０～５００μｍ程度である。 The n + -type SiC substrate 10 is an n-type semiconductor substrate made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. That is, the conductivity type of n + -type SiC substrate 10 as a semiconductor substrate is n-type. The n type impurity concentration in the n + type SiC substrate 10 is relatively large, for example, about 1 × 10 18 to 1 × 10 21 cm −3 . The thickness of the n + type SiC substrate 10 is, for example, about 50 to 500 μm.
　ドレイン電極１１は、ｎ＋型ＳｉＣ基板１０の下面に形成された電極である。ドレイン電極１１は、ｎ＋型ＳｉＣ基板１０と電気的に接続されている。ドレイン電極１１として、例えばチタン（Ｔｉ）、ニッケル（Ｎｉ）または金（Ａｕ）などを積層した導電膜を用いることができる。このような導電膜を用いることで、ドレイン電極１１とｎ＋型ＳｉＣ基板１０とを、低抵抗で電気的に接続することができる。 The drain electrode 11 is an electrode formed on the lower surface of the n + type SiC substrate 10. Drain electrode 11 is electrically connected to n + type SiC substrate 10. As the drain electrode 11, for example, a conductive film in which titanium (Ti), nickel (Ni), gold (Au), or the like is stacked can be used. By using such a conductive film, the drain electrode 11 and the n + -type SiC substrate 10 can be electrically connected with low resistance.
　なお、本願明細書では、ある基板の下面に、または、ある層の下面に形成されているということは、その基板の下面よりも下側に、または、その層の下面よりも下側に形成されていることを含むものとする。 In the specification of the present application, being formed on the lower surface of a certain substrate or on the lower surface of a certain layer means forming below the lower surface of the substrate or lower than the lower surface of the layer. Is included.
　ｎ－型エピタキシャル層１２は、ｎ＋型ＳｉＣ基板１０の上面に形成されており、例えば窒素（Ｎ）またはリン（Ｐ）などのｎ型不純物を導入した炭化ケイ素（ＳｉＣ）からなるｎ型半導体層である。すなわち半導体層としてのｎ－型エピタキシャル層１２の導電型は、ｎ型である。ｎ－型エピタキシャル層１２におけるｎ型の不純物濃度は、ｎ＋型ＳｉＣ基板１０におけるｎ型の不純物濃度よりも小さく、例えば１×１０１５～１×１０１６ｃｍ－３程度である。また、ｎ－型エピタキシャル層１２の厚さは、例えば５～５０μｍ程度である。 The n − type epitaxial layer 12 is formed on the upper surface of the n + type SiC substrate 10, and is an n type semiconductor made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced. Is a layer. That is, the conductivity type of the n − type epitaxial layer 12 as the semiconductor layer is n type. The n - type impurity concentration in the n − -type epitaxial layer 12 is smaller than the n-type impurity concentration in the n + -type SiC substrate 10, for example, about 1 × 10 15 to 1 × 10 16 cm −3 . Further, n - the thickness of the type epitaxial layer 12 is, for example, about 5 ~ 50 [mu] m.
　ｎ－型エピタキシャル層１２を、例えばエピタキシャル成長法により形成することができる。あるいは、例えばイオン注入法によりアルミニウム（Ａｌ）またはホウ素（Ｂ）などのｐ型不純物をｎ＋型ＳｉＣ基板１０の上面全面に注入し、ｎ＋型ＳｉＣ基板１０におけるｎ型の不純物濃度を減少させる方法により、ｎ－型エピタキシャル層１２を形成することもできる（後述する実施の形態２においても同様）。 The n − type epitaxial layer 12 can be formed by, for example, an epitaxial growth method. Alternatively, for example, a p-type impurity such as aluminum (Al) or boron (B) by ion implantation implanted on the entire upper surface of the n + -type SiC substrate 10, reducing the impurity concentration of the n-type in the n + -type SiC substrate 10 The n − type epitaxial layer 12 can also be formed by the method (the same applies to the second embodiment described later).
　なお、本願明細書では、ある基板の上面に、または、ある層の上面に形成されているということは、その基板の上面よりも上側に、または、その層の上面よりも上側に形成されていることを含むものとする。 Note that in this specification, being formed on the upper surface of a certain substrate or on the upper surface of a certain layer means being formed above the upper surface of the substrate or above the upper surface of the layer. It is included.
　ｐ型ボディ領域１３は、ｎ－型エピタキシャル層１２の上層部に形成されており、例えばアルミニウム（Ａｌ）またはホウ素（Ｂ）などのｐ型不純物が拡散した炭化ケイ素（ＳｉＣ）からなるｐ型半導体領域である。すなわち半導体領域としてのｐ型ボディ領域１３の導電型は、ｐ型である。ｐ型ボディ領域１３におけるｐ型の不純物濃度は、例えば１×１０１７～１×１０１８ｃｍ－３程度である。また、ｐ型ボディ領域１３の厚さは、例えば１～２μｍ程度である。 The p-type body region 13 is formed in the upper layer portion of the n − -type epitaxial layer 12, and is a p-type semiconductor made of silicon carbide (SiC) in which a p-type impurity such as aluminum (Al) or boron (B) is diffused. It is an area. That is, the conductivity type of the p-type body region 13 as a semiconductor region is p-type. The p-type impurity concentration in the p-type body region 13 is, for example, about 1 × 10 17 to 1 × 10 18 cm −3 . The thickness of the p-type body region 13 is, for example, about 1 to 2 μm.
　ｎ＋型ソース領域１４は、ｐ型ボディ領域１３の上層部に形成されており、例えば窒素（Ｎ）またはリン（Ｐ）などのｎ型不純物を導入した炭化ケイ素（ＳｉＣ）からなるｎ型半導体領域である。すなわち半導体領域としてのｎ＋型ソース領域１４の導電型は、ｎ型である。ｎ＋型ソース領域１４におけるｎ型の不純物濃度は、ｎ－型エピタキシャル層１２におけるｎ型の不純物濃度よりも大きく、例えば１×１０１９～１×１０２０ｃｍ－３程度とすることができる。また、ｎ＋型ソース領域１４の厚さを、例えば１００～５００ｎｍ程度とすることができる。 The n + -type source region 14 is formed in the upper layer portion of the p-type body region 13, and is an n-type semiconductor made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. It is an area. That is, the conductivity type of the n + type source region 14 as the semiconductor region is n type. The n-type impurity concentration in the n + -type source region 14 is higher than the n-type impurity concentration in the n − -type epitaxial layer 12, and can be, for example, about 1 × 10 19 to 1 × 10 20 cm −3 . In addition, the thickness of the n + -type source region 14 can be set to about 100 to 500 nm, for example.
　ｐ＋型ボディコンタクト領域１５は、ｐ型ボディ領域１３の上層部に形成されており、例えばアルミニウム（Ａｌ）またはホウ素（Ｂ）などのｐ型不純物が拡散した炭化ケイ素（ＳｉＣ）からなるｐ型半導体領域である。すなわち半導体領域としてのｐ＋型ボディコンタクト領域１５の導電型は、ｐ型である。ｐ＋型ボディコンタクト領域１５におけるｐ型の不純物濃度は、ｐ型ボディ領域１３におけるｐ型の不純物濃度よりも大きく、例えば１×１０１９～１×１０２０ｃｍ－３程度である。また、ｐ＋型ボディコンタクト領域１５の厚さは、例えば１００～５００ｎｍ程度である。 The p + -type body contact region 15 is formed in the upper layer portion of the p-type body region 13 and is, for example, p-type made of silicon carbide (SiC) in which p-type impurities such as aluminum (Al) or boron (B) are diffused. It is a semiconductor region. That is, the conductivity type of the p + -type body contact region 15 as the semiconductor region is p-type. The p-type impurity concentration in the p + -type body contact region 15 is higher than the p-type impurity concentration in the p-type body region 13, for example, about 1 × 10 19 to 1 × 10 20 cm −3 . The thickness of the p + type body contact region 15 is, for example, about 100 to 500 nm.
　隣り合う２つのｐ型ボディ領域１３に挟まれたｎ－型エピタキシャル層１２の上層部は、ＪＦＥＴ領域１６である。すなわちｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上層部は、ＪＦＥＴ領域１６である。また、ｎ＋型ソース領域１４とＪＦＥＴ領域１６とに挟まれたｐ型ボディ領域１３の上層部、すなわちｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上層部は、チャネル領域１７である。 The upper layer portion of the n − -type epitaxial layer 12 sandwiched between two adjacent p-type body regions 13 is a JFET region 16. That is, the upper layer portion of the n − type epitaxial layer 12 opposite to the n + type source region 14 across the p type body region 13 is the JFET region 16. Further, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the JFET region 16, that is, the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. The upper layer portion is a channel region 17.
　ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に、形成された絶縁膜である。ゲート絶縁膜１８は、例えば酸化シリコン（ＳｉＯ２）、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）または酸化ハフニウム（ＨｆＯ２）などからなり、例えば熱酸化法またはＣＶＤ（Chemical Vapor Deposition）法などにより形成されている。また、ゲート絶縁膜１８の厚さは、例えば数十ｎｍ程度である。 The gate insulating film 18 is an insulating film formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. The gate insulating film 18 is made of, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or the like, for example, thermal oxidation or CVD (Chemical Vapor Deposition). ) Method. The thickness of the gate insulating film 18 is, for example, about several tens of nm.
　ゲート電極１９は、ゲート絶縁膜１８上に形成された電極である。すなわち、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に、ゲート絶縁膜１８を介して形成された電極である。ゲート電極１９は、例えばポリシリコンなどからなり、例えばＣＶＤ法などにより形成された導電膜である。 The gate electrode 19 is an electrode formed on the gate insulating film 18. That is, the gate electrode 19 is an electrode formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 via the gate insulating film 18. The gate electrode 19 is made of, for example, polysilicon, and is a conductive film formed by, for example, a CVD method.
　ソース電極２０は、ｎ＋型ソース領域１４上、および、ｐ＋型ボディコンタクト領域１５上に形成された電極である。ソース電極２０として、例えばチタン（Ｔｉ）またはアルミニウム（Ａｌ）などからなる導電膜を用いることができる。このような導電膜を用いることで、ソース電極２０と、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５とを、低抵抗で電気的に接続することができる。 The source electrode 20 is an electrode formed on the n + type source region 14 and the p + type body contact region 15. As the source electrode 20, for example, a conductive film made of titanium (Ti) or aluminum (Al) can be used. By using such a conductive film, the source electrode 20 and the n + type source region 14 and the p + type body contact region 15 can be electrically connected with low resistance.
　図１に示すように、本実施の形態１では、ｎ－型エピタキシャル層１２の上面上、および、ｎ＋型ソース領域１４上に、保護絶縁膜２２からなる膜部２２ａおよび２２ｂが形成されている。膜部２２ａは、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面上に形成された保護絶縁膜２２からなる。膜部２２ｂは、ｎ＋型ソース領域１４上に形成された保護絶縁膜２２からなる。膜部２２ｂを構成する保護絶縁膜２２は、膜部２２ａを構成する保護絶縁膜２２と同層に形成された絶縁膜である。保護絶縁膜２２をパターニング、すなわち加工し、開口部２２ｃを形成することで、膜部２２ａおよび２２ｂが形成されている。開口部２２ｃは、保護絶縁膜２２を貫通して、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面に達する。したがって、開口部２２ｃの底部には、ｐ型ボディ領域１３の上面が露出している。 As shown in FIG. 1, in the first embodiment, film portions 22 a and 22 b made of protective insulating film 22 are formed on the upper surface of n − type epitaxial layer 12 and on n + type source region 14. Yes. The film portion 22 a is formed of a protective insulating film 22 formed on the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween. The film part 22 b is formed of a protective insulating film 22 formed on the n + type source region 14. The protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a. The protective insulating film 22 is patterned, that is, processed to form the opening 22c, whereby the film portions 22a and 22b are formed. The opening 22 c penetrates the protective insulating film 22 and reaches the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. Therefore, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 22c.
　好適には、ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ａの上面上にかけて、連続的に形成されている。そして、ゲート電極１９は、ゲート絶縁膜１８のうち、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に形成された部分１８ａ上から、ゲート絶縁膜１８のうち、膜部２２ａの上面上に形成された部分１８ｂ上にかけて、連続的に形成されている。すなわち、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ａの上面上にかけて、ゲート絶縁膜１８を介して連続的に形成されている。 Preferably, the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22a. Has been. The gate electrode 19 is formed on the gate insulating film 18 from above the portion 18 a formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. The insulating film 18 is continuously formed over the portion 18b formed on the upper surface of the film portion 22a. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22a via the gate insulating film 18. It is formed continuously.
　これにより、ＪＦＥＴ領域１６上に膜部２２ａに代えてゲート絶縁膜１８が直接形成され、ＪＦＥＴ領域１６上に直接形成されたゲート絶縁膜１８上にゲート電極１９が形成された場合に比べ、ＪＦＥＴ領域１６とゲート電極１９との間の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させることができる。 As a result, the gate insulating film 18 is formed directly on the JFET region 16 instead of the film portion 22a, and the gate electrode 19 is formed on the gate insulating film 18 formed directly on the JFET region 16. The strength of the electric field in the insulating film between the region 16 and the gate electrode 19 can be reduced and the reliability of the insulating film can be improved.
　ゲート絶縁膜１８の厚さＴＨ１は、膜部２２ａの厚さＴＨ２よりも小さく、かつ、膜部２２ｂの厚さＴＨ３よりも小さい。これにより、ＪＦＥＴ領域１６とゲート電極１９との間の絶縁膜中の電界の強度をさらに小さくして当該絶縁膜の信頼性をさらに向上させることができる。 The thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be further reduced, and the reliability of the insulating film can be further improved.
　さらに好適には、ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ｂの上面上にかけて、連続的に形成されている。そして、ゲート電極１９は、ゲート絶縁膜１８のうち、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に形成された部分１８ａ上から、ゲート絶縁膜１８のうち、膜部２２ｂの上面上に形成された部分１８ｃ上にかけて、連続的に形成されている。すなわち、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ｂの上面上にかけて、ゲート絶縁膜１８を介して連続的に形成されている。そして、ゲート電極１９の膜部２２ｂ側の端部１９ａは、ゲート絶縁膜１８のうち、膜部２２ｂの上面上に形成された部分１８ｃ上に配置されている。すなわち、ゲート電極１９は、膜部２２ｂ上で終端されている。 More preferably, the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22b. Is formed. The gate electrode 19 is formed on the gate insulating film 18 from above the portion 18 a formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. The insulating film 18 is continuously formed over a portion 18c formed on the upper surface of the film portion 22b. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22b via the gate insulating film 18. It is formed continuously. The end 19a of the gate electrode 19 on the film part 22b side is disposed on a portion 18c of the gate insulating film 18 formed on the upper surface of the film part 22b. That is, the gate electrode 19 is terminated on the film part 22b.
　これにより、後述する図１７を用いて説明するように、導電膜１９ｂを加工する際に、例えばｎ＋型ソース領域１４、ｎ－型エピタキシャル層１２などの半導体領域、および、ｎ＋型ＳｉＣ基板１０に損傷が加えられることを、防止または抑制することができる。また、ゲート電極１９の端部１９ａに向かう電気力線が集中し、端部１９ａの近傍で電界の強度が大きくなることを、防止または抑制することができる。 Thus, as will be described with reference to FIG. 17 described later, when the conductive film 19b is processed, for example, the semiconductor region such as the n + type source region 14 and the n − type epitaxial layer 12, and the n + type SiC substrate. It is possible to prevent or suppress damage to 10. In addition, it is possible to prevent or suppress an increase in electric field strength in the vicinity of the end portion 19a due to concentration of electric lines of force toward the end portion 19a of the gate electrode 19.
　なお、図１に示すように、開口部２２ｃが、保護絶縁膜２２を貫通して、ｐ型ボディ領域１３の上面のみならず、ｎ－型エピタキシャル層１２の上面、および、ｎ＋型ソース領域１４の上面に達する場合を考える。すなわち開口部２２ｃの底部に、ｐ型ボディ領域１３の上面のみならず、ｎ－型エピタキシャル層１２の上面、および、ｎ＋型ソース領域１４の上面が露出する場合を考える。この場合、ゲート絶縁膜１８は、膜部２２ａと膜部２２ｂとに挟まれたｎ－型エピタキシャル層１２の上面上、膜部２２ａと膜部２２ｂとに挟まれたｐ型ボディ領域１３の上面全面上、および、膜部２２ａと膜部２２ｂとに挟まれたｎ＋型ソース領域１４の上面上に、形成されている。そして、ゲート電極１９は、膜部２２ａと膜部２２ｂとに挟まれたｎ－型エピタキシャル層１２の上面上、膜部２２ａと膜部２２ｂとに挟まれたｐ型ボディ領域１３の上面全面上、および、膜部２２ａと膜部２２ｂとに挟まれたｎ＋型ソース領域１４の上面上に、ゲート絶縁膜１８を介して形成されている。つまり、ゲート電極１９は、膜部２２ａと膜部２２ｂとに挟まれたｎ－型エピタキシャル層１２、および、膜部２２ａと膜部２２ｂとに挟まれたｎ＋型ソース領域１４には接触しないように、形成されている。 As shown in FIG. 1, the opening 22c penetrates the protective insulating film 22, and not only the upper surface of the p-type body region 13, but also the upper surface of the n − -type epitaxial layer 12 and the n + -type source region. Consider the case where the upper surface of 14 is reached. That is, consider the case where not only the upper surface of p-type body region 13 but also the upper surface of n − -type epitaxial layer 12 and the upper surface of n + -type source region 14 are exposed at the bottom of opening 22c. In this case, the gate insulating film 18 is formed on the upper surface of the n − type epitaxial layer 12 sandwiched between the film portions 22a and 22b, and on the upper surface of the p-type body region 13 sandwiched between the film portions 22a and 22b. It is formed on the entire surface and on the upper surface of the n + -type source region 14 sandwiched between the film part 22a and the film part 22b. The gate electrode 19 is formed on the upper surface of the n − type epitaxial layer 12 sandwiched between the film portions 22a and 22b and on the entire upper surface of the p-type body region 13 sandwiched between the film portions 22a and 22b. In addition, the gate insulating film 18 is formed on the upper surface of the n + -type source region 14 sandwiched between the film part 22a and the film part 22b. That is, the gate electrode 19 does not contact the n − type epitaxial layer 12 sandwiched between the film part 22a and the film part 22b and the n + type source region 14 sandwiched between the film part 22a and the film part 22b. So that it is formed.
　あるいは、膜部２２ａの上面上、および、膜部２２ｂの上面上に、ゲート絶縁膜１８が形成されず、ゲート電極１９が、直接形成されていてもよい。このとき、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ａの上面上にかけて、連続的に形成されている。また、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ｂの上面上にかけて、連続的に形成されている。 Alternatively, the gate insulating film 18 may not be formed on the upper surface of the film part 22a and the upper surface of the film part 22b, and the gate electrode 19 may be directly formed. At this time, the gate electrode 19 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film part 22a. Yes. The gate electrode 19 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film part 22b. .
　層間絶縁膜２１は、ゲート電極１９の表面を含めてゲート絶縁膜１８上に形成されている。層間絶縁膜２１の材料として、例えばＰＳＧ（Phospho Silicate Glass）または酸化シリコンなどを用いることができる。なお、膜部２２ａの上面上、および、膜部２２ｂの上面上にゲート絶縁膜１８が形成されていないときは、層間絶縁膜２１は、ゲート電極１９、ならびに、膜部２２ａおよび２２ｂを覆うように、形成されている。 The interlayer insulating film 21 is formed on the gate insulating film 18 including the surface of the gate electrode 19. As a material of the interlayer insulating film 21, for example, PSG (Phospho ま た は Silicate Glass) or silicon oxide can be used. When the gate insulating film 18 is not formed on the upper surface of the film part 22a and on the upper surface of the film part 22b, the interlayer insulating film 21 covers the gate electrode 19 and the film parts 22a and 22b. Is formed.
　層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２には、開口部としてのソースコンタクト孔２１ａが形成されている。ソースコンタクト孔２１ａは、層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２を貫通して、ｎ＋型ソース領域１４の上面、および、ｐ＋型ボディコンタクト領域１５の上面に達する。すなわちソースコンタクト孔２１ａの底面には、ｎ＋型ソース領域１４の上面、および、ｐ＋型ボディコンタクト領域１５の上面が露出している。 A source contact hole 21 a as an opening is formed in the interlayer insulating film 21, the gate insulating film 18, and the protective insulating film 22. Source contact hole 21 a penetrates interlayer insulating film 21, gate insulating film 18, and protective insulating film 22, and reaches the upper surface of n + -type source region 14 and the upper surface of p + -type body contact region 15. That is, the upper surface of the n + type source region 14 and the upper surface of the p + type body contact region 15 are exposed at the bottom surface of the source contact hole 21a.
　ソース電極２０は、ソースコンタクト孔２１ａの底面および側面を含めて層間絶縁膜２１上に形成されている。このような構造により、ソース電極２０は、層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２に形成されたソースコンタクト孔２１ａを介して、ｎ＋型ソース領域１４、および、ｐ＋型ボディコンタクト領域１５と、電気的に接続されている。 The source electrode 20 is formed on the interlayer insulating film 21 including the bottom and side surfaces of the source contact hole 21a. With such a structure, the source electrode 20 includes the n + -type source region 14 and the p + -type body through the source contact hole 21 a formed in the interlayer insulating film 21, the gate insulating film 18 and the protective insulating film 22. The contact region 15 is electrically connected.
　図２に示すように、平面視において、互いに交差、好適には直交する２つの方向の各々を、Ｘ方向およびＹ方向のそれぞれとする。なお、平面視において、とは、ｎ＋型ＳｉＣ基板１０の上面に垂直な方向から視た場合を意味する。言い換えれば、Ｘ方向およびＹ方向は、ｎ＋型ＳｉＣ基板１０の上面内で互いに交差、好適には直交する２つの方向である。 As shown in FIG. 2, each of two directions that intersect each other, preferably orthogonally, in a plan view is defined as an X direction and a Y direction, respectively. In the plan view, the term “when viewed from a direction perpendicular to the upper surface of the n + -type SiC substrate 10” is meant. In other words, the X direction and the Y direction are two directions that intersect with each other and preferably are orthogonal to each other within the upper surface of the n + -type SiC substrate 10.
　本実施の形態１の半導体装置１は、複数のｐ型ボディ領域１３と、複数のｎ＋型ソース領域１４と、複数のｐ＋型ボディコンタクト領域１５とを有する。複数のｐ型ボディ領域１３は、ｎ－型エピタキシャル層１２の上層部に、平面視において、Ｘ方向およびＹ方向にマトリクス状に配列するように、形成されている。複数のｎ＋型ソース領域１４は、複数のｐ型ボディ領域１３の各々の上層部に、それぞれ形成されている。複数のｐ＋型ボディコンタクト領域１５は、複数のｐ型ボディ領域１３の各々の上層部に、それぞれ形成されている。 The semiconductor device 1 according to the first embodiment has a plurality of p-type body regions 13, a plurality of n + -type source regions 14, and a plurality of p + -type body contact regions 15. The plurality of p-type body regions 13 are formed in the upper layer portion of the n − -type epitaxial layer 12 so as to be arranged in a matrix in the X direction and the Y direction in plan view. The plurality of n + -type source regions 14 are respectively formed in the upper layer portions of the plurality of p-type body regions 13. The plurality of p + type body contact regions 15 are respectively formed in the upper layer portions of the plurality of p type body regions 13.
　このとき、膜部２２ａは、平面視において、Ｙ方向にそれぞれ延在し、かつ、Ｘ方向に配列された複数の延在部２２ｄと、Ｘ方向にそれぞれ延在し、複数の延在部２２ｄとそれぞれ交差し、かつ、Ｙ方向に配列された複数の延在部２２ｅとを含み、格子状に形成されている。そして、マトリクス状に配列された複数のｎ－型エピタキシャル層１２は、格子状の膜部２２ａにより区画されている。ここで、格子状の膜部２２ａにより区画された複数の領域の各々を、セルと称する。 At this time, the film portion 22a extends in the Y direction and extends in the X direction in a plan view, and extends in the X direction, and extends in the X direction. And a plurality of extending portions 22e arranged in the Y direction, and are formed in a lattice shape. The plurality of n − -type epitaxial layers 12 arranged in a matrix are partitioned by a lattice-shaped film portion 22a. Here, each of the plurality of regions partitioned by the lattice-like film portion 22a is referred to as a cell.
　なお、図２には、Ｘ方向およびＹ方向にマトリクス状に配列された４つのｎ－型エピタキシャル層１２を示している。図２に示す範囲では、膜部２２ａは、平面視において、Ｙ方向に延在する１つの延在部２２ｄと、Ｘ方向に延在し、かつ、延在部２２ｄと交差する１つの延在部２２ｅとを含み、十字状に形成されている。そして、図２に示す範囲では、マトリクス状に配列された４つのｎ－型エピタキシャル層１２は、十字状の膜部２２ａにより区画されている。また、十字状の膜部２２ａにより区画された領域を、セルと称することになる。 FIG. 2 shows four n − type epitaxial layers 12 arranged in a matrix in the X and Y directions. In the range shown in FIG. 2, the film part 22 a has one extending part 22 d extending in the Y direction and one extending part extending in the X direction and intersecting the extending part 22 d in a plan view. Part 22e, and is formed in a cross shape. In the range shown in FIG. 2, the four n − -type epitaxial layers 12 arranged in a matrix are partitioned by a cross-shaped film portion 22a. An area partitioned by the cross-shaped film portion 22a is referred to as a cell.
　＜半導体装置の動作＞
　続いて、本実施の形態１の半導体装置１に含まれる縦型ＭＩＳＦＥＴの動作について説明する。図３は、図１において、縦型ＭＩＳＦＥＴがオン状態のときに電子が流れる経路を模式的に示した図である。 <Operation of semiconductor device>
Subsequently, the operation of the vertical MISFET included in the semiconductor device 1 of the first embodiment will be described. FIG. 3 is a diagram schematically showing a path through which electrons flow when the vertical MISFET is in the ON state in FIG.
　本実施の形態１の半導体装置１に含まれる縦型ＭＩＳＦＥＴをオン状態にするオン動作においては、ゲート電極１９に、ソース電極２０に対して正のゲート電圧ＶＧＳ（ＶＧＳ＞０Ｖ）を印加する。このとき、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上層部、すなわちチャネル領域１７には、反転層が形成される。 In the on operation for turning on the vertical MISFET included in the semiconductor device 1 of the first embodiment, a positive gate voltage VGS (VGS> 0 V) is applied to the gate electrode 19 with respect to the source electrode 20. At this time, an inversion layer is formed in the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12, that is, in the channel region 17.
　したがって、電子は、図３に一部の経路を経路ＰＳ１として示すように、ソース電極２０から、ｎ＋型ソース領域１４、チャネル領域１７に形成された反転層、ｎ－型エピタキシャル層１２、および、ｎ＋型ＳｉＣ基板１０を通して、ドレイン電極１１に流れる。すなわち電流は、ドレイン電極１１から、ｎ＋型ＳｉＣ基板１０、ｎ－型エピタキシャル層１２、チャネル領域１７に形成された反転層、および、ｎ＋型ソース領域１４を通して、ソース電極２０に流れる。 Therefore, as shown in FIG. 3, a part of the path is shown as path PS < b> 1 , from the source electrode 20 to the n + -type source region 14, the inversion layer formed in the channel region 17, the n − -type epitaxial layer 12, and , Flows to the drain electrode 11 through the n + -type SiC substrate 10. That is, current flows from the drain electrode 11 to the source electrode 20 through the n + -type SiC substrate 10, the n − -type epitaxial layer 12, the inversion layer formed in the channel region 17, and the n + -type source region 14.
　一方、縦型ＭＩＳＦＥＴをオフ状態にするオフ動作においては、ゲート電極１９に、ソース電極２０に対して負または零のゲート電圧ＶＧＳ（ＶＧＳ≦０Ｖ）を印加する。このとき、チャネル領域１７に形成されていた反転層を消滅させることで、電流が遮断される。 On the other hand, in the off operation for turning off the vertical MISFET, a negative or zero gate voltage VGS (VGS ≦ 0 V) is applied to the gate electrode 19 with respect to the source electrode 20. At this time, the current is interrupted by eliminating the inversion layer formed in the channel region 17.
　＜半導体装置の第１変形例＞
　次に、実施の形態１の第１変形例の半導体装置について説明する。 <First Modification of Semiconductor Device>
Next, the semiconductor device of the 1st modification of Embodiment 1 is demonstrated.
　図４は、実施の形態１の第１変形例の半導体装置の要部断面図である。図５は、実施の形態１の第１変形例の半導体装置の上面図である。図４は、図５のＢ－Ｂ線に沿った断面図である。なお、図５においては、理解を簡単にするために、ゲート絶縁膜１８（図４参照）、ゲート電極１９（図４参照）、ソース電極２０（図４参照）および層間絶縁膜２１（図４参照）を除去、すなわち透視した状態を図示している。また、図５においては、理解を簡単にするために、交差部２２ｆ上であって、膜部２２ａが形成されない領域ＡＲ１１を二点鎖線により図示している。なお、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１（図４参照）に形成された部分、すなわち半導体装置の中心部について、説明する。 FIG. 4 is a cross-sectional view of main parts of a semiconductor device according to a first modification of the first embodiment. FIG. 5 is a top view of the semiconductor device according to the first modification of the first embodiment. 4 is a cross-sectional view taken along line BB in FIG. In FIG. 5, for easy understanding, the gate insulating film 18 (see FIG. 4), the gate electrode 19 (see FIG. 4), the source electrode 20 (see FIG. 4), and the interlayer insulating film 21 (FIG. 4). (See) is removed, that is, it is seen through. In FIG. 5, for easy understanding, a region AR11 on the intersection 22f where the film part 22a is not formed is illustrated by a two-dot chain line. Hereinafter, a portion formed in the region AR1 (see FIG. 4) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
　図４および図５に示すように、本第１変形例の半導体装置１ａは、実施の形態１の半導体装置１と同様に、縦型ＭＩＳＦＥＴを備えた半導体装置であり、ｎ＋型ＳｉＣ基板１０、ドレイン電極１１、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を有する。また、本実施の形態１の第１変形例の半導体装置１ａは、実施の形態１の半導体装置１と同様に、ゲート絶縁膜１８、ゲート電極１９、ソース電極２０および層間絶縁膜２１を有する。 As shown in FIGS. 4 and 5, the semiconductor device 1 a of the first modification is a semiconductor device including a vertical MISFET, like the semiconductor device 1 of the first embodiment, and an n + type SiC substrate 10. A drain electrode 11, an n − type epitaxial layer 12, a p type body region 13, an n + type source region 14 and a p + type body contact region 15. Further, the semiconductor device 1a of the first modification example of the first embodiment includes the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21, like the semiconductor device 1 of the first embodiment.
　図５には、図２と同様に、Ｘ方向およびＹ方向にマトリクス状に配列された４つのｎ－型エピタキシャル層１２を示している。図５に示す範囲では、膜部２２ａは、平面視において、Ｙ方向に延在する１つの延在部２２ｄと、Ｘ方向に延在し、かつ、延在部２２ｄと交差する１つの延在部２２ｅとを含み、十字状に形成されている。そして、図５に示す範囲では、マトリクス状に配列された４つのｎ－型エピタキシャル層１２は、十字状の膜部２２ａにより区画されている。前述したように、十字状の膜部２２ａにより区画された領域を、セルと称する。 FIG. 5 shows four n − -type epitaxial layers 12 arranged in a matrix in the X and Y directions, as in FIG. In the range shown in FIG. 5, the film part 22 a has one extension part 22 d extending in the Y direction and one extension extending in the X direction and intersecting the extension part 22 d in a plan view. Part 22e, and is formed in a cross shape. In the range shown in FIG. 5, the four n − -type epitaxial layers 12 arranged in a matrix are partitioned by a cross-shaped film portion 22a. As described above, a region defined by the cross-shaped film portion 22a is referred to as a cell.
　本第１変形例では、ゲート電極１９は、Ｘ方向で隣り合う２つのｎ－型エピタキシャル層１２に挟まれた延在部２２ｄ上、および、Ｙ方向で隣り合う２つのｎ－型エピタキシャル層１２に挟まれた延在部２２ｅ上には、ゲート絶縁膜１８を介して形成されている。 In the first modification, the gate electrode 19, two n adjacent in the X direction - -type epitaxial layer 12 sandwiched by the extending portion 22d on, and two n adjacent in the Y direction - -type epitaxial layer 12 The gate insulating film 18 is formed on the extending portion 22e sandwiched between the gate insulating film 18 and the gate insulating film 18.
　一方、本第１変形例では、ゲート電極１９は、延在部２２ｄと延在部２２ｅとが交差する交差部２２ｆ上の領域ＡＲ１１には、形成されていない。言い換えれば、交差部２２ｆが前述したセルの角部であると定義した場合、ゲート電極１９は、セルの角部としての交差部２２ｆ上の領域ＡＲ１１には、形成されていない。なお、図５におけるＢ－Ｂ線は、交差部２２ｆを挟んで互いに反対側に位置するセルの中心を結ぶ方向、例えば互いに直交するＸ方向およびＹ方向のいずれからも４５度傾斜した方向に、延在する。 On the other hand, in the first modification, the gate electrode 19 is not formed in the area AR11 on the intersection 22f where the extension 22d and the extension 22e intersect. In other words, when it is defined that the intersection 22f is the aforementioned corner of the cell, the gate electrode 19 is not formed in the region AR11 on the intersection 22f as the corner of the cell. Note that the line BB in FIG. 5 is in a direction connecting the centers of cells located on opposite sides of the intersection 22f, for example, a direction inclined 45 degrees from both the X and Y directions orthogonal to each other. Extend.
　後述する図２１を用いて説明するように、ＪＦＥＴ領域１６の幅が広くなるほど、ＪＦＥＴ領域１６中の電界の強度が大きくなる。また、セルの角部としての交差部２２ｆにおいては、例えばＢ－Ｂ線に沿った方向のＪＦＥＴ領域１６の幅は、Ｘ方向およびＹ方向のＪＦＥＴ領域１６の幅よりも大きい。したがって、交差部２２ｆ中の電界の強度は、Ｘ方向で隣り合う２つのｎ－型エピタキシャル層１２に挟まれた延在部２２ｄ中の電界の強度よりも大きくなる。また、交差部２２ｆ中の電界の強度は、Ｙ方向で隣り合う２つのｎ－型エピタキシャル層１２に挟まれた延在部２２ｅ中の電界の強度よりも大きくなる。 As described later with reference to FIG. 21, the electric field strength in the JFET region 16 increases as the width of the JFET region 16 increases. At the intersection 22f as the corner of the cell, for example, the width of the JFET region 16 in the direction along the line BB is larger than the width of the JFET region 16 in the X direction and the Y direction. Therefore, the strength of the electric field in the intersecting portion 22f is larger than the strength of the electric field in the extending portion 22d sandwiched between two n − type epitaxial layers 12 adjacent in the X direction. Further, the electric field strength in the intersecting portion 22f is larger than the electric field strength in the extending portion 22e sandwiched between two n − -type epitaxial layers 12 adjacent in the Y direction.
　本第１変形例では、交差部２２ｆ上の領域ＡＲ１１にゲート電極１９を形成しないことで、交差部２２ｆを構成する絶縁膜中の電界の強度を小さくすることができ、セルの角部におけるＪＦＥＴ領域１６上の絶縁膜の信頼性を向上させることができる。また、ゲート電極１９とドレイン電極１１との間の容量である帰還容量を、小さくすることができる。 In the first modification, by not forming the gate electrode 19 in the region AR11 on the intersection 22f, the electric field strength in the insulating film constituting the intersection 22f can be reduced, and the JFET at the corner of the cell The reliability of the insulating film on the region 16 can be improved. Further, the feedback capacitance that is the capacitance between the gate electrode 19 and the drain electrode 11 can be reduced.
　＜半導体装置の製造工程＞
　次に、本実施の形態１の半導体装置の製造工程の例を、図面を参照して説明する。図６は、実施の形態１の半導体装置の製造工程の一部を示すフロー図である。図７～図２０は、実施の形態１の半導体装置の製造工程中の要部断面図である。なお、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１における製造工程について、説明する。 <Manufacturing process of semiconductor device>
Next, an example of a manufacturing process of the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 6 is a flowchart showing a part of the manufacturing process of the semiconductor device of the first embodiment. 7 to 20 are fragmentary cross-sectional views of the semiconductor device of First Embodiment during the manufacturing steps thereof. In the following, the manufacturing process in the region AR1 on the upper surface side and the center side of the n + type SiC substrate 10 will be described.
　まず、ｎ＋型ＳｉＣ基板１０を用意する（図６のステップＳ１１）。このステップＳ１１では、図７に示すように、例えば窒素（Ｎ）またはリン（Ｐ）などのｎ型不純物を導入した炭化ケイ素（ＳｉＣ）からなるｎ＋型ＳｉＣ基板１０を用意する。前述したように、ｎ＋型ＳｉＣ基板１０におけるｎ型の不純物濃度は、比較的大きく、例えば１×１０１８～１×１０２１ｃｍ－３程度とすることができる。また、ｎ＋型ＳｉＣ基板１０の厚さを、例えば５０～５００μｍ程度とすることができる。 First, an n + type SiC substrate 10 is prepared (step S11 in FIG. 6). In step S11, as shown in FIG. 7, for example, an n + type SiC substrate 10 made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced is prepared. As described above, the n type impurity concentration in the n + type SiC substrate 10 is relatively high, and can be, for example, about 1 × 10 18 to 1 × 10 21 cm −3 . In addition, the thickness of the n + -type SiC substrate 10 can be set to, for example, about 50 to 500 μm.
　次いで、ｎ－型エピタキシャル層１２を形成する（図６のステップＳ１２）。このステップＳ１２では、図８に示すように、ｎ＋型ＳｉＣ基板１０の上面に、エピタキシャル成長法によりｎ－型エピタキシャル層１２を形成する。例えばシリコン（Ｓｉ）原子含有ガス（ＳｉＨ４ガス）、塩素（Ｃｌ）原子含有ガス（ＨＣｌガス）、炭素（Ｃ）原子含有ガス（Ｃ３Ｈ８ガス）および還元ガス（Ｈ２ガス）等を用い、基板温度を例えば１５００～１８００℃程度にすることで、ＳｉＣからなるｎ－型エピタキシャル層１２を形成する。 Next, the n − type epitaxial layer 12 is formed (step S12 in FIG. 6). In this step S12, as shown in FIG. 8, an n − type epitaxial layer 12 is formed on the upper surface of the n + type SiC substrate 10 by an epitaxial growth method. For example, silicon (Si) atom-containing gas (SiH 4 gas), chlorine (Cl) atom-containing gas (HCl gas), carbon (C) atom-containing gas (C 3 H 8 gas), reducing gas (H 2 gas), etc. By using the substrate temperature of, for example, about 1500 to 1800 ° C., the n − type epitaxial layer 12 made of SiC is formed.
　ｎ－型エピタキシャル層１２には、例えば窒素（Ｎ）、リン（Ｐ）または砒素（Ａｓ）などのｎ型不純物が導入される。前述したように、ｎ－型エピタキシャル層１２におけるｎ型の不純物濃度を、例えば１×１０１５～１×１０１６ｃｍ－３程度とすることができ、ｎ－型エピタキシャル層１２の厚さを、例えば５～５０μｍ程度とすることができる。 An n-type impurity such as nitrogen (N), phosphorus (P) or arsenic (As) is introduced into the n − -type epitaxial layer 12. As described above, n - a n-type impurity concentration of the type epitaxial layer 12, for example, 1 × 10 15 can be a ~ 1 × 10 16 cm -3 approximately, n - the thickness of the type epitaxial layer 12, For example, the thickness can be about 5 to 50 μm.
　次いで、ｐ型ボディ領域１３を形成する（図６のステップＳ１３）。このステップＳ１３では、ｎ－型エピタキシャル層１２上にレジスト膜Ｒ１を塗布する。そして、塗布されたレジスト膜Ｒ１に対してフォトリソグラフィ技術を用いて露光および現像処理を施すことにより、図９に示すように、レジスト膜Ｒ１をパターニングする。レジスト膜Ｒ１のパターニングは、ｎ－型エピタキシャル層１２のうち、ｐ型ボディ領域１３が形成される領域が露出するように行われる。 Next, the p-type body region 13 is formed (step S13 in FIG. 6). In this step S 13, a resist film R 1 is applied on the n − type epitaxial layer 12. Then, the resist film R1 is patterned by exposing and developing the applied resist film R1 using a photolithography technique, as shown in FIG. The patterning of the resist film R1 is performed so that the region where the p-type body region 13 is formed in the n − -type epitaxial layer 12 is exposed.
　そして、パターニングされたレジスト膜Ｒ１をマスクにしたイオン注入法により、ｎ－型エピタキシャル層１２に例えばアルミニウム（Ａｌ）またはホウ素（Ｂ）などのｐ型不純物を導入する。これにより、ｎ－型エピタキシャル層１２の上層部に、ｐ型ボディ領域１３が形成される。ｐ型ボディ領域１３におけるｐ型の不純物濃度については、前述したように、例えば１×１０１７～１×１０１８ｃｍ－３程度とすることができる。また、ｐ型ボディ領域１３の厚さを、例えば１～２μｍ程度とすることができる。 Then, a p-type impurity such as aluminum (Al) or boron (B) is introduced into the n − -type epitaxial layer 12 by ion implantation using the patterned resist film R1 as a mask. As a result, the p-type body region 13 is formed in the upper layer portion of the n − -type epitaxial layer 12. As described above, the p-type impurity concentration in the p-type body region 13 can be set to about 1 × 10 17 to 1 × 10 18 cm −3 , for example. Further, the thickness of the p-type body region 13 can be set to about 1 to 2 μm, for example.
　なお、ｐ型ボディ領域１３を形成する工程については、その工程の後、例えば１７００℃程度で熱処理を行い、注入した不純物を活性化させることができる。 In addition, about the process of forming the p-type body area | region 13, it can heat-process, for example at about 1700 degreeC after the process, and can implant | stimulate the implanted impurity.
　次いで、ｎ＋型ソース領域１４を形成する（図６のステップＳ１４）。このステップＳ１４では、パターニングされたレジスト膜Ｒ１を除去した後、ｎ－型エピタキシャル層１２上にレジスト膜Ｒ２を塗布する。そして、塗布されたレジスト膜Ｒ２に対してフォトリソグラフィ技術を用いて露光および現像処理を施すことにより、図１０に示すように、レジスト膜Ｒ２をパターニングする。レジスト膜Ｒ２のパターニングは、ｐ型ボディ領域１３のうち、ｎ＋型ソース領域１４が形成される領域が露出するように行われる。 Next, the n + type source region 14 is formed (step S14 in FIG. 6). In this step S14, after removing the patterned resist film R1, a resist film R2 is applied on the n − -type epitaxial layer 12. Then, the applied resist film R2 is subjected to exposure and development using a photolithography technique, thereby patterning the resist film R2 as shown in FIG. The patterning of the resist film R2 is performed so that the region where the n + -type source region 14 is formed in the p-type body region 13 is exposed.
　そして、パターニングされたレジスト膜Ｒ２をマスクにしたイオン注入法により、ｐ型ボディ領域１３に例えば窒素（Ｎ）またはリン（Ｐ）などのｎ型不純物を導入する。これにより、図１０に示すように、ｐ型ボディ領域１３の上層部に、ｎ＋型ソース領域１４が形成される。ｎ＋型ソース領域１４におけるｎ型の不純物濃度については、前述したように、例えば１×１０１９～１×１０２０ｃｍ－３程度とすることができる。また、ｎ＋型ソース領域１４の厚さを、例えば１００～５００ｎｍ程度とすることができる。 Then, an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced into the p-type body region 13 by ion implantation using the patterned resist film R2 as a mask. Thereby, as shown in FIG. 10, an n + type source region 14 is formed in the upper layer portion of the p type body region 13. As described above, the n-type impurity concentration in the n + -type source region 14 can be set to about 1 × 10 19 to 1 × 10 20 cm −3 , for example. In addition, the thickness of the n + -type source region 14 can be set to about 100 to 500 nm, for example.
　次いで、ｐ＋型ボディコンタクト領域１５を形成する（図６のステップＳ１５）。このステップＳ１５では、パターニングされたレジスト膜Ｒ２を除去した後、ｎ－型エピタキシャル層１２上にレジスト膜Ｒ３を塗布する。そして、塗布されたレジスト膜Ｒ３に対してフォトリソグラフィ技術を用いて露光および現像処理を施すことにより、図１１に示すように、レジスト膜Ｒ３をパターニングする。レジスト膜Ｒ３のパターニングは、ｐ型ボディ領域１３またはｎ＋型ソース領域１４のうち、ｐ＋型ボディコンタクト領域１５が形成される領域が露出するように行われる。 Next, the p + type body contact region 15 is formed (step S15 in FIG. 6). In this step S15, after removing the patterned resist film R2, a resist film R3 is applied onto the n − type epitaxial layer 12. Then, the applied resist film R3 is exposed and developed using a photolithography technique to pattern the resist film R3 as shown in FIG. The patterning of the resist film R3 is performed so that a region where the p + type body contact region 15 is formed in the p type body region 13 or the n + type source region 14 is exposed.
　そして、パターニングされたレジスト膜Ｒ３をマスクにしたイオン注入法により、ｐ型ボディ領域１３またはｎ＋型ソース領域１４に、例えばアルミニウム（Ａｌ）またはホウ素（Ｂ）からなるｐ型不純物を導入する。これにより、図１１に示すように、ｐ型ボディ領域１３の上層部に、ｐ＋型ボディコンタクト領域１５が形成される。ｐ＋型ボディコンタクト領域１５におけるｐ型の不純物濃度については、前述したように、例えば１×１０１９～１×１０２０ｃｍ－３程度とすることができる。また、ｐ＋型ボディコンタクト領域１５の厚さを、例えば１００～５００ｎｍ程度とすることができる。 Then, a p-type impurity made of, for example, aluminum (Al) or boron (B) is introduced into the p-type body region 13 or the n + -type source region 14 by an ion implantation method using the patterned resist film R3 as a mask. Thereby, as shown in FIG. 11, p + type body contact region 15 is formed in the upper layer portion of p type body region 13. The p-type impurity concentration in the p + -type body contact region 15 can be set to, for example, about 1 × 10 19 to 1 × 10 20 cm −3 as described above. Further, the thickness of the p + -type body contact region 15 can be set to about 100 to 500 nm, for example.
　その後、パターニングされたレジスト膜Ｒ３を除去する。このレジスト膜Ｒ３を除去した状態を、図１２に示す。 Thereafter, the patterned resist film R3 is removed. FIG. 12 shows a state where the resist film R3 is removed.
　なお、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を形成する工程については、上記した順番で行う場合に限られず、適切にパターニングされたレジスト膜をマスクに用いるものであれば、いずれの順番で行ってもよい。また、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を形成する工程については、各工程の後、または、全ての工程が終わった後、例えば１７００℃程度で熱処理を行い、注入した不純物を活性化させることができる。 Note that the step of forming the n + -type source region 14 and the p + -type body contact region 15 is not limited to the above-described order, and any process can be used as long as a resist film that is appropriately patterned is used as a mask. You may carry out in order. In addition, with respect to the process of forming the n + -type source region 14 and the p + -type body contact region 15, after each process or after all the processes are completed, a heat treatment is performed at, for example, about 1700 ° C. Can be activated.
　次いで、保護絶縁膜２２を形成する（図６のステップＳ１６）。このステップＳ１６では、図１３に示すように、ｎ－型エピタキシャル層１２の上面上、ｐ型ボディ領域１３の上面上、ｎ＋型ソース領域１４上、および、ｐ＋型ボディコンタクト領域１５上に、保護絶縁膜２２を形成する。すなわちｎ－型エピタキシャル層１２上に、保護絶縁膜２２を形成する。 Next, the protective insulating film 22 is formed (Step S16 in FIG. 6). In step S16, as shown in FIG. 13, on the upper surface of n − type epitaxial layer 12, on the upper surface of p type body region 13, on n + type source region 14 and on p + type body contact region 15. Then, the protective insulating film 22 is formed. That is, the protective insulating film 22 is formed on the n − type epitaxial layer 12.
　保護絶縁膜２２は、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２上の絶縁膜中における電界の強度を小さくするためのものである。また、保護絶縁膜２２は、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２上の絶縁膜を挟んで発生する容量を低減するためのものである。 The protective insulating film 22 is for reducing the strength of the electric field in the insulating film on the n − type epitaxial layer 12 on the opposite side of the n + type source region 14 across the p type body region 13. The protective insulating film 22 is for reducing the capacitance generated by sandwiching the insulating film on the n − type epitaxial layer 12 on the opposite side of the n + type source region 14 with the p type body region 13 in between. .
　そのため、保護絶縁膜２２として、好適には、例えば密度が小さい酸化シリコン（ＳｉＯ２）または酸窒化シリコン（ＳｉＯＮ）からなる各種の膜を用いることができる。または、保護絶縁膜２２として、好適には、例えば酸化シリコン（ＳｉＯ２）の誘電率よりも低い誘電率を有するｌｏｗ－ｋ膜としての炭素含有酸化シリコン（ＳｉＯＣ）からなる各種の膜を用いることができる。あるいは、保護絶縁膜２２として、好適には、上記の各種の膜が積層された積層膜を用いることができる。このような保護絶縁膜２２を、例えば８００℃以下の比較的低い温度で、ＣＶＤ法により形成することができる。また、保護絶縁膜２２の厚さを、例えば数百ｎｍ程度とすることができる。 Therefore, as the protective insulating film 22, various films made of, for example, silicon oxide (SiO 2 ) or silicon oxynitride (SiON) having a low density can be used. Alternatively, for example, various films made of carbon-containing silicon oxide (SiOC) as a low-k film having a dielectric constant lower than that of silicon oxide (SiO 2 ) are preferably used as the protective insulating film 22. Can do. Alternatively, as the protective insulating film 22, a laminated film in which the above various films are suitably laminated can be used. Such a protective insulating film 22 can be formed by a CVD method at a relatively low temperature of, for example, 800 ° C. or lower. Further, the thickness of the protective insulating film 22 can be set to, for example, about several hundred nm.
　次いで、保護絶縁膜２２をパターニングする（図６のステップＳ１７）。このステップＳ１７では、図１４に示すように、フォトリソグラフィ技術およびドライエッチング技術により、保護絶縁膜２２を加工、すなわちパターニングし、開口部２２ｃを形成することで、膜部２２ａおよび２２ｂを形成する。開口部２２ｃは、保護絶縁膜２２を貫通して、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面に達する。したがって、開口部２２ｃの底部には、ｐ型ボディ領域１３の上面が露出する。膜部２２ａは、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面上に形成された保護絶縁膜２２からなる。膜部２２ｂは、ｎ＋型ソース領域１４上に形成された保護絶縁膜２２からなる。すなわち膜部２２ｂを構成する保護絶縁膜２２は、膜部２２ａを構成する保護絶縁膜２２と同層に形成された絶縁膜である。 Next, the protective insulating film 22 is patterned (step S17 in FIG. 6). In step S17, as shown in FIG. 14, the protective insulating film 22 is processed, that is, patterned by the photolithography technique and the dry etching technique to form the opening 22c, thereby forming the film parts 22a and 22b. The opening 22 c penetrates the protective insulating film 22 and reaches the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. Therefore, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 22c. The film portion 22 a is formed of a protective insulating film 22 formed on the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween. The film part 22 b is formed of a protective insulating film 22 formed on the n + type source region 14. That is, the protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a.
　開口部２２ｃは、保護絶縁膜２２を貫通して、少なくともｐ型ボディ領域１３の上面に達する。したがって、開口部２２ｃは、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面に達してもよく、ｎ＋型ソース領域１４の上面に達してもよい。すなわち開口部２２ｃの底部には、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面が露出してもよく、ｎ＋型ソース領域１４の上面が露出してもよい。 The opening 22 c penetrates the protective insulating film 22 and reaches at least the upper surface of the p-type body region 13. Therefore, the opening 22c may reach the upper surface of the n − -type epitaxial layer 12 on the opposite side of the n + -type source region 14 with the p-type body region 13 interposed therebetween, and reach the upper surface of the n + -type source region 14. Also good. That is, at the bottom of the opening 22c, the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 across the p type body region 13 may be exposed, and the upper surface of the n + type source region 14 may be exposed. May be exposed.
　好適には、開口部２２ｃの断面形状は、テーパ形状であり、開口部２２ｃの幅は、開口部２２ｃの上部から下部、すなわち底部に向かって減少している。開口部２２ｃを形成する領域において、保護絶縁膜２２の上部をドライエッチング技術により加工して除去した後、保護絶縁膜２２の下部をウェットエッチング技術により加工して除去することで、このようなテーパ形状を有する開口部２２ｃを形成することができる。これにより、保護絶縁膜２２を加工する際に、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上層部、すなわちチャネル領域１７（後述する図１７参照）となる部分、に損傷を与えないようにすることができる。また、開口部２２ｃの底部の膜部２２ａ側の端部に形成されるゲート電極１９（後述する図１７参照）の近傍で電界の強度が大きくならないようにすることができる。 Preferably, the cross-sectional shape of the opening 22c is a taper shape, and the width of the opening 22c decreases from the top to the bottom, that is, the bottom of the opening 22c. In the region where the opening 22c is to be formed, the upper portion of the protective insulating film 22 is processed and removed by the dry etching technique, and then the lower portion of the protective insulating film 22 is processed and removed by the wet etching technique. An opening 22c having a shape can be formed. Thus, when processing the protective insulating film 22, n + -type source region 14 and n - upper part -type epitaxial layer 12 and sandwiched by p-type body region 13, i.e. see Fig. 17 to the channel region 17 (described later ) Can be prevented from being damaged. In addition, the strength of the electric field can be prevented from increasing in the vicinity of the gate electrode 19 (see FIG. 17 described later) formed at the end of the opening 22c on the film portion 22a side.
　次いで、ゲート絶縁膜１８を形成する（図６のステップＳ１８）。このステップＳ１８では、図１５に示すように、開口部２２ｃの底部に露出したｐ型ボディ領域１３の上面上に、ゲート絶縁膜１８を形成する。ゲート絶縁膜１８の密度は、保護絶縁膜２２の密度よりも大きい。また、ゲート絶縁膜１８の誘電率は、保護絶縁膜２２の誘電率よりも大きい。好適には、ゲート絶縁膜１８として、例えば比較的高温で形成された絶縁膜を用いることができる。または、好適には、ゲート絶縁膜１８として、比較的低温で堆積された膜を高温で熱処理することにより形成された絶縁膜を用いることができる。 Next, the gate insulating film 18 is formed (Step S18 in FIG. 6). In this step S18, as shown in FIG. 15, the gate insulating film 18 is formed on the upper surface of the p-type body region 13 exposed at the bottom of the opening 22c. The density of the gate insulating film 18 is larger than the density of the protective insulating film 22. Further, the dielectric constant of the gate insulating film 18 is larger than the dielectric constant of the protective insulating film 22. Preferably, as the gate insulating film 18, for example, an insulating film formed at a relatively high temperature can be used. Alternatively, as the gate insulating film 18, an insulating film formed by heat-treating a film deposited at a relatively low temperature at a high temperature can be used.
　このようなゲート絶縁膜１８として、好適には、例えば酸化シリコン（ＳｉＯ２）、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）または酸化ハフニウム（ＨｆＯ２）などからなる各種の膜を用いることができる。あるいは、ゲート絶縁膜１８として、好適には、上記の各種の膜が積層された積層膜を用いることができる。また、このようなゲート絶縁膜１８を、例えばＣＶＤ法により形成することができる。 As such a gate insulating film 18, various films made of, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ) are preferably used. Can be used. Alternatively, as the gate insulating film 18, a laminated film in which the above various films are suitably laminated can be used. Further, such a gate insulating film 18 can be formed by, for example, a CVD method.
　ゲート絶縁膜１８の厚さＴＨ１は、膜部２２ａの厚さＴＨ２よりも小さく、かつ、膜部２２ｂの厚さＴＨ３よりも小さい。これにより、ＪＦＥＴ領域１６とゲート電極１９との間の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させることができる。前述したように、膜部２２ａを構成する保護絶縁膜２２の厚さＴＨ２を、例えば数百ｎｍ程度とした場合、ゲート絶縁膜１８の厚さＴＨ１を、例えば数十ｎｍ程度とすることができる。 The thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved. As described above, when the thickness TH2 of the protective insulating film 22 constituting the film portion 22a is, for example, about several hundred nm, the thickness TH1 of the gate insulating film 18 can be, for example, about several tens of nm. .
　図１５に示す例では、ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に、形成される。また、ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ａの上面上にかけて、連続的に形成される。さらに、ゲート絶縁膜１８は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ｂの上面上にかけて、連続的に形成される。 In the example shown in FIG. 15, the gate insulating film 18 is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. The gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film part 22a. . Furthermore, the gate insulating film 18 is continuously formed from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22b. .
　次いで、ゲート電極１９を形成する（図６のステップＳ１９）。このステップＳ１９では、まず、図１６に示すように、ゲート絶縁膜１８上に導電膜１９ｂを形成する。導電膜１９ｂは、例えばリン（Ｐ）もしくは砒素（Ａｓ）などのｎ型不純物が大きな濃度で拡散したポリシリコン、または、ホウ素（Ｂ）などのｐ型不純物が大きな濃度で拡散したポリシリコンなどからなる。導電膜１９ｂを、例えばＣＶＤ法などにより形成することができる。 Next, the gate electrode 19 is formed (step S19 in FIG. 6). In step S19, first, a conductive film 19b is formed on the gate insulating film 18, as shown in FIG. The conductive film 19b is made of, for example, polysilicon in which n-type impurities such as phosphorus (P) or arsenic (As) are diffused at a high concentration, or polysilicon in which p-type impurities such as boron (B) are diffused at a high concentration. Become. The conductive film 19b can be formed by, for example, a CVD method.
　そして、図１７に示すように、導電膜１９ｂをパターニングしてゲート電極１９を形成する。このゲート電極１９を形成する工程では、フォトリソグラフィ技術およびドライエッチング技術により、導電膜１９ｂをパターニング、すなわち加工する。例えばフォトリソグラフィ技術によりパターニングされたレジスト膜をマスクにしたドライエッチング技術によりパターニングすることで、図１７に示すように、導電膜１９ｂからなるゲート電極１９を形成する。 Then, as shown in FIG. 17, the conductive film 19b is patterned to form the gate electrode 19. In the step of forming the gate electrode 19, the conductive film 19b is patterned, that is, processed by a photolithography technique and a dry etching technique. For example, patterning is performed by a dry etching technique using a resist film patterned by a photolithography technique as a mask, thereby forming a gate electrode 19 made of a conductive film 19b as shown in FIG.
　図１７に示すように、ゲート電極１９は、ゲート絶縁膜１８のうち、膜部２２ａと膜部２２ｂとに挟まれたｐ型ボディ領域１３の上面上に形成された部分１８ａ上に、形成される。言い換えれば、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に、ゲート絶縁膜１８を介して形成される。 As shown in FIG. 17, the gate electrode 19 is formed on a portion 18a of the gate insulating film 18 formed on the upper surface of the p-type body region 13 sandwiched between the film part 22a and the film part 22b. The In other words, the gate electrode 19 is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 via the gate insulating film 18.
　好適には、ゲート電極１９は、ゲート絶縁膜１８のうち、部分１８ａ上から、膜部２２ａの上面上に形成された部分１８ｂ上にかけて、連続的に形成される。すなわち、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ａの上面上にかけて、ゲート絶縁膜１８を介して連続的に形成される。これにより、ｎ－型エピタキシャル層１２とゲート電極１９との間の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させることができる。 Preferably, the gate electrode 19 is formed continuously from the portion 18a of the gate insulating film 18 to the portion 18b formed on the upper surface of the film portion 22a. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22a via the gate insulating film 18. It is formed continuously. As a result, the strength of the electric field in the insulating film between the n − type epitaxial layer 12 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved.
　さらに好適には、ゲート電極１９は、ゲート絶縁膜１８のうち、部分１８ａ上から、膜部２２ｂの上面上に形成された部分１８ｃ上にかけて、連続的に形成される。すなわち、ゲート電極１９は、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上から、膜部２２ｂの上面上にかけて、ゲート絶縁膜１８を介して連続的に形成される。そして、ゲート電極１９の膜部２２ｂ側の端部１９ａは、ゲート絶縁膜１８のうち、膜部２２ｂの表面に形成された部分１８ｃ上に配置される。すなわち、ゲート電極１９は、ゲート電極１９が、膜部２２ｂ上で終端されるように、形成される。 More preferably, the gate electrode 19 is formed continuously from the portion 18a of the gate insulating film 18 to the portion 18c formed on the upper surface of the film portion 22b. That is, the gate electrode 19 extends from the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 to the upper surface of the film portion 22b via the gate insulating film 18. It is formed continuously. The end portion 19a on the film portion 22b side of the gate electrode 19 is disposed on a portion 18c of the gate insulating film 18 formed on the surface of the film portion 22b. That is, the gate electrode 19 is formed so that the gate electrode 19 is terminated on the film part 22b.
　これにより、導電膜１９ｂを加工する際に、導電膜１９ｂが膜部２２ｂ上、すなわち保護絶縁膜２２上で加工されるので、例えばｎ＋型ソース領域１４、ｐ型ボディ領域１３などの半導体領域、および、ｎ＋型ＳｉＣ基板１０に損傷が与えられることを、防止または抑制することができる。また、ゲート電極１９の端部１９ａに向かう電気力線が集中し、端部１９ａの近傍で電界の強度が大きくなることを、防止または抑制することができる。 Thus, when the conductive film 19b is processed, the conductive film 19b is processed on the film portion 22b, that is, on the protective insulating film 22, so that the semiconductor regions such as the n + -type source region 14 and the p-type body region 13 are formed. And damage to the n + -type SiC substrate 10 can be prevented or suppressed. In addition, it is possible to prevent or suppress an increase in electric field strength in the vicinity of the end portion 19a due to concentration of electric lines of force toward the end portion 19a of the gate electrode 19.
　このようにしてゲート電極１９を形成することで、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上層部が、チャネル領域１７となる。また、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上層部が、ＪＦＥＴ領域１６となる。 By forming the gate electrode 19 in this way, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 becomes the channel region 17. Further, the upper layer portion of the n − -type epitaxial layer 12 on the opposite side of the n + -type source region 14 with the p-type body region 13 interposed therebetween becomes the JFET region 16.
　なお、ゲート絶縁膜１８を、例えば熱酸化法により形成するときは、膜部２２ａの上面上、および、膜部２２ｂの上面上に、ゲート絶縁膜１８が形成されず、ゲート電極１９が、直接形成される。 When the gate insulating film 18 is formed by, for example, a thermal oxidation method, the gate insulating film 18 is not formed on the upper surface of the film portion 22a and the upper surface of the film portion 22b, and the gate electrode 19 is directly It is formed.
　次いで、層間絶縁膜２１を形成する（図６のステップＳ２０）。このステップＳ２１では、図１８に示すように、ゲート電極１９の表面を含めてゲート絶縁膜１８上に、層間絶縁膜２１を形成する。層間絶縁膜２１として、例えば酸化シリコン膜を用いることができ、例えばＣＶＤ法により形成することができる。 Next, an interlayer insulating film 21 is formed (Step S20 in FIG. 6). In step S21, an interlayer insulating film 21 is formed on the gate insulating film 18 including the surface of the gate electrode 19 as shown in FIG. For example, a silicon oxide film can be used as the interlayer insulating film 21, and can be formed by, for example, a CVD method.
　次いで、ソースコンタクト孔２１ａを形成する（図６のステップＳ２１）。このステップＳ２１では、図１９に示すように、フォトリソグラフィ技術およびエッチング技術を使用することにより、層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２に、開口部としてのソースコンタクト孔２１ａを形成する。すなわち層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２を貫通し、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５に達するソースコンタクト孔２１ａを形成する。ソースコンタクト孔２１ａの底面には、ｎ＋型ソース領域１４の上面、および、ｐ＋型ボディコンタクト領域１５の上面が露出する。 Next, the source contact hole 21a is formed (step S21 in FIG. 6). In this step S21, as shown in FIG. 19, a source contact hole 21a as an opening is formed in the interlayer insulating film 21, the gate insulating film 18 and the protective insulating film 22 by using a photolithography technique and an etching technique. To do. That is, a source contact hole 21 a that penetrates the interlayer insulating film 21, the gate insulating film 18, and the protective insulating film 22 and reaches the n + type source region 14 and the p + type body contact region 15 is formed. The upper surface of the n + -type source region 14 and the upper surface of the p + -type body contact region 15 are exposed on the bottom surface of the source contact hole 21a.
　次いで、ソース電極２０を形成する（図６のステップＳ２２）。このステップＳ２２では、図２０に示すように、層間絶縁膜２１上に、ならびに、ソースコンタクト孔２１ａの底面および内壁を覆うように、例えばアルミニウム（Ａｌ）などからなる導電膜を、例えば蒸着法またはスパッタ法などにより堆積することで、ソース電極２０を形成する。 Next, the source electrode 20 is formed (step S22 in FIG. 6). In this step S22, as shown in FIG. 20, a conductive film made of, for example, aluminum (Al) is formed on the interlayer insulating film 21 and so as to cover the bottom surface and the inner wall of the source contact hole 21a, for example, by vapor deposition or The source electrode 20 is formed by depositing by sputtering or the like.
　次いで、ドレイン電極１１を形成する（図６のステップＳ２３）。このステップＳ２３では、ｎ＋型ＳｉＣ基板１０の下面に、例えばチタン（Ｔｉ）、ニッケル（Ｎｉ）、金（Ａｕ）および銀（Ａｇ）のいずれかからなる金属膜、または、これらのいずれか２種以上の金属膜が積層された積層膜を、例えば蒸着法またはスパッタ法などにより堆積することで、ドレイン電極１１を形成する。これにより、図１に示したような、半導体装置１を製造することができる。 Next, the drain electrode 11 is formed (step S23 in FIG. 6). In this step S23, a metal film made of, for example, any one of titanium (Ti), nickel (Ni), gold (Au), and silver (Ag), or any two of them is formed on the lower surface of the n + -type SiC substrate 10. The drain electrode 11 is formed by depositing a laminated film in which metal films of seeds or more are laminated, for example, by vapor deposition or sputtering. Thereby, the semiconductor device 1 as shown in FIG. 1 can be manufactured.
　なお、図１では図示を省略するが、ドレイン電極１１を形成した後、半導体装置１の上面および下面にパッシベーション膜を形成することができる。次いで、形成されたパッシベーション膜のうち、ドレイン電極１１、ゲート電極１９およびソース電極２０の各電極を外部と電気的に接続するためのパッド領域となる部分に開口部を形成することができる。 Although not shown in FIG. 1, after forming the drain electrode 11, a passivation film can be formed on the upper surface and the lower surface of the semiconductor device 1. Next, in the formed passivation film, an opening can be formed in a portion to be a pad region for electrically connecting the drain electrode 11, the gate electrode 19, and the source electrode 20 to the outside.
　＜ＪＦＥＴ領域上の絶縁膜中の電界の強度について＞
　次に、ＪＦＥＴ領域上の絶縁膜中の電界の強度について、比較例１の半導体装置と比較しながら説明する。図２１は、比較例１の半導体装置の要部断面図である。 <Intensity of electric field in insulating film on JFET region>
Next, the intensity of the electric field in the insulating film on the JFET region will be described in comparison with the semiconductor device of Comparative Example 1. FIG. 21 is a main-portion cross-sectional view of the semiconductor device of Comparative Example 1.
　図２１において、比較例１の半導体装置１０１のｎ＋型ＳｉＣ基板１０、ドレイン電極１１およびｎ－型エピタキシャル層１２の各々は、上記半導体装置１のｎ＋型ＳｉＣ基板１０、ドレイン電極１１およびｎ－型エピタキシャル層１２のそれぞれに相当するものである（図１参照）。また、半導体装置１０１のｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５の各々は、上記半導体装置１のｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５のそれぞれに相当するものである（図１参照）。 In Figure 21, n + -type SiC substrate 10 of the semiconductor device 101 of Comparative Example 1, the drain electrode 11 and the n - each type epitaxial layer 12, the semiconductor device 1 of the n + -type SiC substrate 10, the drain electrode 11 and the n This corresponds to each of the − type epitaxial layers 12 (see FIG. 1). Each of the p-type body region 13, n + -type source region 14 and p + -type body contact region 15 of the semiconductor device 101, p-type body region 13 of the semiconductor device 1, n + -type source region 14 and p + This corresponds to each of the mold body contact regions 15 (see FIG. 1).
　また、半導体装置１０１のＪＦＥＴ領域１６およびチャネル領域１７の各々は、上記半導体装置１のＪＦＥＴ領域１６およびチャネル領域１７のそれぞれに相当するものである（図１参照）。また、半導体装置１０１のゲート絶縁膜１８、ゲート電極１９、ソース電極２０および層間絶縁膜２１の各々は、上記半導体装置１のゲート絶縁膜１８、ゲート電極１９、ソース電極２０および層間絶縁膜２１のそれぞれに相当するものである（図１参照）。 Further, each of the JFET region 16 and the channel region 17 of the semiconductor device 101 corresponds to each of the JFET region 16 and the channel region 17 of the semiconductor device 1 (see FIG. 1). The gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21 of the semiconductor device 101 are the same as the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21 of the semiconductor device 1. These correspond to each (see FIG. 1).
　しかし、比較例１の半導体装置１０１には、上記半導体装置１に形成されていた膜部２２ａ（図１参照）および膜部２２ｂ（図１参照）が形成されていない。 However, in the semiconductor device 101 of Comparative Example 1, the film part 22a (see FIG. 1) and the film part 22b (see FIG. 1) formed in the semiconductor device 1 are not formed.
　前述したように、炭化ケイ素（ＳｉＣ）の絶縁破壊電界は、シリコン（Ｓｉ）の絶縁破壊電界よりも１桁程度大きい。そのため、ＳｉＣを用いた縦型ＭＩＳＦＥＴは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ－型エピタキシャル層１２中の電界が１桁程度大きくなるように、設計される。具体的には、ＳｉＣを用いた縦型ＭＩＳＦＥＴでは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ－型エピタキシャル層１２における不純物濃度を大きくする。また、ＳｉＣを用いた縦型ＭＩＳＦＥＴでは、Ｓｉを用いた縦型ＭＩＳＦＥＴに比べて、ｎ－型エピタキシャル層１２の厚さを小さくする。このとき、ｎ－型エピタキシャル層１２の厚さを小さくすることで、縦型ＭＩＳＦＥＴのオン抵抗は、低減される。 As described above, the breakdown electric field of silicon carbide (SiC) is about one digit larger than the breakdown electric field of silicon (Si). Therefore, the vertical MISFET using SiC is designed so that the electric field in the n − -type epitaxial layer 12 is increased by about one digit compared to the vertical MISFET using Si. Specifically, in the vertical MISFET using SiC, the impurity concentration in the n − type epitaxial layer 12 is increased as compared with the vertical MISFET using Si. In addition, in the vertical MISFET using SiC, the thickness of the n − type epitaxial layer 12 is made smaller than that in the vertical MISFET using Si. At this time, the on-resistance of the vertical MISFET is reduced by reducing the thickness of the n − type epitaxial layer 12.
　ところが、縦型ＭＩＳＦＥＴのオン抵抗が低減される一方で、ｎ－型エピタキシャル層１２の厚さを小さくすることで、ＪＦＥＴ領域１６上のゲート絶縁膜１８中の電界の強度が増大する。その結果、例えば閾値電圧が不均一になることなどにより、ゲート絶縁膜１８の信頼性が低下する。また、ゲート電極１９とドレイン電極１１との間の容量である帰還容量Ｃｇｄが、増大する。この帰還容量Ｃｇｄが大きい場合には、電力変換装置を高速に動作させることができないか、または、電力変換装置によりモータ等を駆動する際の制御工程が複雑になるおそれがある。 However, while the on-resistance of the vertical MISFET is reduced, reducing the thickness of the n − -type epitaxial layer 12 increases the strength of the electric field in the gate insulating film 18 on the JFET region 16. As a result, the reliability of the gate insulating film 18 decreases due to, for example, non-uniform threshold voltages. In addition, the feedback capacitance Cgd that is the capacitance between the gate electrode 19 and the drain electrode 11 increases. When the feedback capacitance Cgd is large, the power converter cannot be operated at high speed, or the control process when driving the motor or the like by the power converter may be complicated.
　上記した、ゲート絶縁膜中の電界の強度が増大するという課題、および、帰還容量が増大するという課題は、ＪＦＥＴ領域１６の幅が広いほど、顕著である。これは、ＪＦＥＴ領域１６の幅が広くなるほど、ｐ型ボディ領域１３の下のｎ－型エピタキシャル層１２中の電界の強度よりもＪＦＥＴ領域１６中の電界の強度が大きくなるからである。また、ＪＦＥＴ領域１６の幅が広くなるほど、ドレイン電極１１のうちゲート電極１９と対向する部分の面積が大きくなるからである。 The above-described problem that the electric field strength in the gate insulating film increases and the problem that the feedback capacitance increases increase as the width of the JFET region 16 increases. This is because the electric field strength in the JFET region 16 becomes larger as the width of the JFET region 16 becomes wider than the electric field strength in the n − -type epitaxial layer 12 below the p-type body region 13. This is also because the area of the drain electrode 11 facing the gate electrode 19 increases as the width of the JFET region 16 increases.
　例えば、鉄道車両用など比較的高い電圧で用いられるインバータには、数ｋＶ程度の高い耐電圧を有する縦型ＭＩＳＦＥＴが備えられることが望まれる。また、耐電圧を高くするために、ｎ－型エピタキシャル層１２における不純物濃度は、比較的小さくなる。このようにｎ－型エピタキシャル層１２における不純物濃度が小さい場合には、ＪＦＥＴ領域１６の幅が狭いとき、縦型ＭＩＳＦＥＴのオン抵抗の全体に対する、ＪＦＥＴ領域１６の抵抗の割合が大きくなり、縦型ＭＩＳＦＥＴのオン抵抗を小さくすることが困難となる。そのため、ＪＦＥＴ領域１６の幅は、広くなるように、設計される。 For example, an inverter that is used at a relatively high voltage such as for a railway vehicle is desirably provided with a vertical MISFET having a high withstand voltage of about several kV. In order to increase the withstand voltage, the impurity concentration in the n − -type epitaxial layer 12 is relatively small. As described above, when the impurity concentration in the n − -type epitaxial layer 12 is small, when the width of the JFET region 16 is narrow, the ratio of the resistance of the JFET region 16 to the entire on-resistance of the vertical MISFET increases. It becomes difficult to reduce the on-resistance of the MISFET. For this reason, the width of the JFET region 16 is designed to be wide.
　このように、鉄道車両用など比較的高い電圧で用いられるインバータに備えられた縦型ＭＩＳＦＥＴでは、ＪＦＥＴ領域１６上のゲート絶縁膜１８中の電界の強度を小さくし、帰還容量を小さくすることと、ＪＦＥＴ領域１６の幅を広くすることとは、両立しない。したがって、例えばＪＦＥＴ領域１６の幅をあまり広くすることができないことなどにより、インバータにおける電力変換の際の損失が大きくなり、インバータの発熱量が大きくなる。そのため、この大きな発熱量に対応して、インバータを十分冷却するために、大きな冷却能力を有する、大型の冷却装置が設けられる必要が生ずる。よって、縦型ＭＩＳＦＥＴを備えた電力変換装置、または、この電力変換装置を備えた鉄道車両の製造コストを低減することができない。あるいは、縦型ＭＩＳＦＥＴを備えた電力変換装置、または、この電力変換装置を含む鉄道車両を、容易に小型化または軽量化することができない。 As described above, in the vertical MISFET provided in an inverter used for a railway vehicle or the like at a relatively high voltage, the strength of the electric field in the gate insulating film 18 on the JFET region 16 is reduced, and the feedback capacitance is reduced. The widening of the JFET region 16 is not compatible. Therefore, for example, the width of the JFET region 16 cannot be increased so much that the loss at the time of power conversion in the inverter increases, and the amount of heat generated in the inverter increases. Therefore, in order to sufficiently cool the inverter corresponding to this large amount of heat generation, it is necessary to provide a large cooling device having a large cooling capacity. Therefore, it is not possible to reduce the manufacturing cost of the power conversion device provided with the vertical MISFET or the railway vehicle provided with this power conversion device. Alternatively, a power converter provided with a vertical MISFET or a railway vehicle including the power converter cannot be easily reduced in size or weight.
　上記特許文献１および２に記載された技術を用いる場合、ゲート絶縁膜のうち、ＪＦＥＴ領域１６上の部分の厚さが大きく、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に形成された部分の厚さが小さい。 When the techniques described in Patent Documents 1 and 2 are used, the portion of the gate insulating film on the JFET region 16 is large and is sandwiched between the n + type source region 14 and the n − type epitaxial layer 12. Further, the thickness of the portion formed on the upper surface of p-type body region 13 is small.
　しかし、厚いゲート絶縁膜を形成した後、形成されたゲート絶縁膜のうち、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に形成された部分を加工して、例えば数十ｎｍ程度の厚さを有する薄いゲート絶縁膜を残すことは、困難である。特に、加工により薄くされる部分の厚さを均一にすることは、困難である。また、ゲート絶縁膜を形成する際に、ゲート絶縁膜の下のｐ型ボディ領域１３に損傷が与えられるおそれがある。また、ゲート絶縁膜を形成した後、ゲート電極を加工する際に、薄いゲート絶縁膜を介して、ｐ型ボディ領域１３、ならびに、ｐ型ボディ領域１３の下のｎ－型エピタキシャル層１２およびｎ＋型ＳｉＣ基板１０に損傷が与えられるおそれがある。 However, after the thick gate insulating film is formed, the gate insulating film is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. It is difficult to process the portion and leave a thin gate insulating film having a thickness of, for example, about several tens of nanometers. In particular, it is difficult to make the thickness of the portion thinned by processing uniform. Further, when forming the gate insulating film, the p-type body region 13 under the gate insulating film may be damaged. When the gate electrode is processed after forming the gate insulating film, the p-type body region 13 and the n − -type epitaxial layers 12 and n under the p-type body region 13 are interposed through the thin gate insulating film. The + type SiC substrate 10 may be damaged.
　＜本実施の形態の主要な特徴と効果＞
　一方、本実施の形態１の半導体装置１には、膜部２２ａおよび２２ｂが形成されている。ゲート電極１９は、ＪＦＥＴ領域１６上に、少なくとも膜部２２ａを介して形成されている。これにより、ＪＦＥＴ領域１６上に膜部２２ａに代えてゲート絶縁膜１８が直接形成され、ＪＦＥＴ領域１６上に直接形成されたゲート絶縁膜１８上にゲート電極１９が形成された場合に比べ、ＪＦＥＴ領域１６とゲート電極１９との間の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させることができる。また、帰還容量Ｃｇｄを小さくすることができる。 <Main features and effects of the present embodiment>
On the other hand, in the semiconductor device 1 of the first embodiment, film portions 22a and 22b are formed. The gate electrode 19 is formed on the JFET region 16 via at least the film part 22a. As a result, the gate insulating film 18 is formed directly on the JFET region 16 instead of the film portion 22a, and the gate electrode 19 is formed on the gate insulating film 18 formed directly on the JFET region 16. The strength of the electric field in the insulating film between the region 16 and the gate electrode 19 can be reduced and the reliability of the insulating film can be improved. Further, the feedback capacitance Cgd can be reduced.
　また、耐電圧を高くするために、ｎ－型エピタキシャル層１２における不純物濃度を小さくし、ＪＦＥＴ領域１６の幅が広くなるように設計された場合でも、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量Ｃｇｄを容易に小さくすることができる。つまり、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量Ｃｇｄを小さくしつつ、ＪＦＥＴ領域１６の幅を広くすることができる。よって、インバータにおける電力変換の際の損失を小さくすることができるので、インバータを十分冷却するために、大きな冷却能力を有する、大型の冷却装置が設けられなくてもよい。そのため、冷却装置を小型化することなどにより、電力変換装置、または、この電力変換装置を含む鉄道車両を、容易に低コスト化、小型化または軽量化することができる。 Even when the impurity concentration in the n − -type epitaxial layer 12 is decreased and the width of the JFET region 16 is increased in order to increase the withstand voltage, the electric field in the insulating film on the JFET region 16 is increased. By reducing the strength, the reliability of the insulating film can be improved, and the feedback capacitance Cgd can be easily reduced. That is, the strength of the electric field in the insulating film on the JFET region 16 can be reduced to improve the reliability of the insulating film, and the width of the JFET region 16 can be increased while reducing the feedback capacitance Cgd. Therefore, since the loss at the time of the power conversion in an inverter can be made small, in order to fully cool an inverter, it is not necessary to provide a large-sized cooling device having a large cooling capacity. Therefore, it is possible to easily reduce the cost, size, or weight of the power conversion device or the railway vehicle including the power conversion device by downsizing the cooling device.
　一方、ゲート電極１９は、チャネル領域１７上に、膜部２２ａを介さず、ゲート絶縁膜１８のみを介して形成されている。したがって、厚いゲート絶縁膜を形成した後、形成されたゲート絶縁膜のうち、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上面上に形成された部分を加工して、例えば数十ｎｍ程度の厚さを有する薄いゲート絶縁膜を残す工程を行う必要がない。そのため、ゲート絶縁膜１８を形成する際に、ゲート絶縁膜１８の下のｐ型ボディ領域１３に損傷が与えられることを防止することができる。また、ゲート絶縁膜１８を形成した後、ゲート電極１９を加工する際に、薄いゲート絶縁膜１８を介して、ｐ型ボディ領域１３、ならびに、ｐ型ボディ領域１３の下のｎ－型エピタキシャル層１２およびｎ＋型ＳｉＣ基板１０に損傷が与えられることを防止することができる。 On the other hand, the gate electrode 19 is formed on the channel region 17 via only the gate insulating film 18 and not via the film part 22a. Accordingly, after the thick gate insulating film is formed, the gate insulating film is formed on the upper surface of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12. There is no need to process the part to leave a thin gate insulating film having a thickness of about several tens of nanometers, for example. Therefore, when the gate insulating film 18 is formed, it is possible to prevent the p-type body region 13 under the gate insulating film 18 from being damaged. In addition, when the gate electrode 19 is processed after the gate insulating film 18 is formed, the p-type body region 13 and the n − -type epitaxial layer under the p-type body region 13 are interposed via the thin gate insulating film 18. It is possible to prevent the 12 and n + type SiC substrate 10 from being damaged.
　なお、本実施の形態１については、半導体基板および各半導体領域の導電型をｐ型とｎ型との間で互いに入れ替えた場合にも適用可能である。このような場合でも、本実施の形態１の半導体装置１と同様の効果が得られる（後述する実施の形態２においても同様）。 The first embodiment can also be applied to the case where the conductivity types of the semiconductor substrate and each semiconductor region are interchanged between p-type and n-type. Even in such a case, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained (the same applies to the second embodiment described later).
　また、本実施の形態１については、ｎ＋型ＳｉＣ基板に代え、例えばシリコン（Ｓｉ）または窒化ガリウム（ＧａＮ）など各種の半導体材料からなる半導体基板を用い、ｎ－型エピタキシャル層として例えばＳｉまたはＧａＮなど各種の半導体材料からなる半導体層を用いた場合にも適用可能である。このような場合でも、半導体材料として炭化ケイ素（ＳｉＣ）を用いる場合に比べれば程度は少なくなるものの、本実施の形態１の半導体装置と同様の効果が、ある程度得られる（後述する実施の形態２においても同様）。 In the first embodiment, instead of the n + type SiC substrate, a semiconductor substrate made of various semiconductor materials such as silicon (Si) or gallium nitride (GaN) is used, and the n − type epitaxial layer is made of Si or the like. The present invention is also applicable when a semiconductor layer made of various semiconductor materials such as GaN is used. Even in such a case, the effect similar to that of the semiconductor device of the first embodiment can be obtained to some extent, although the degree is less than that in the case of using silicon carbide (SiC) as the semiconductor material (second embodiment described later). The same applies to the above).
　（実施の形態２）
　＜半導体装置＞
　次に、本発明の実施の形態２の半導体装置について説明する。実施の形態１では、ＪＦＥＴ領域上には、保護絶縁膜が形成されていた。それに対して、実施の形態２では、ＪＦＥＴ領域上に、保護絶縁膜とは別の絶縁膜を介して、保護絶縁膜が形成されている。 (Embodiment 2)
<Semiconductor device>
Next, a semiconductor device according to the second embodiment of the present invention will be described. In the first embodiment, a protective insulating film is formed on the JFET region. In contrast, in the second embodiment, a protective insulating film is formed on the JFET region via an insulating film different from the protective insulating film.
　図２２は、実施の形態２の半導体装置の要部断面図である。なお、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１（図２２参照）に形成された部分、すなわち半導体装置の中心部について、説明する。 FIG. 22 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment. Hereinafter, a portion formed in the region AR1 (see FIG. 22) on the upper surface side and the center side of the n + -type SiC substrate 10, that is, the central portion of the semiconductor device will be described.
　図２２に示すように、本実施の形態２の半導体装置１ｂは、実施の形態１の半導体装置１と同様に、縦型ＭＩＳＦＥＴを備えた半導体装置であり、ｎ＋型ＳｉＣ基板１０、ドレイン電極１１、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を有する。また、本実施の形態２の半導体装置１ｂは、実施の形態１の半導体装置１と同様に、ゲート絶縁膜１８、ゲート電極１９、ソース電極２０および層間絶縁膜２１を有する。また、実施の形態１と同様に、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上層部は、ＪＦＥＴ領域１６である。さらに、実施の形態１と同様に、ｎ＋型ソース領域１４とｎ－型エピタキシャル層１２とに挟まれたｐ型ボディ領域１３の上層部は、チャネル領域１７である。 As shown in FIG. 22, the semiconductor device 1b of the second embodiment is a semiconductor device including a vertical MISFET, like the semiconductor device 1 of the first embodiment, and includes an n + -type SiC substrate 10 and a drain electrode. 11, an n − type epitaxial layer 12, a p type body region 13, an n + type source region 14 and a p + type body contact region 15. In addition, the semiconductor device 1b of the second embodiment includes the gate insulating film 18, the gate electrode 19, the source electrode 20, and the interlayer insulating film 21, like the semiconductor device 1 of the first embodiment. Similarly to the first embodiment, the upper layer portion of the n − type epitaxial layer 12 on the opposite side of the n + type source region 14 across the p type body region 13 is a JFET region 16. Further, as in the first embodiment, the upper layer portion of the p-type body region 13 sandwiched between the n + -type source region 14 and the n − -type epitaxial layer 12 is a channel region 17.
　図２２に示すように、本実施の形態２では、実施の形態１と同様に、ｎ－型エピタキシャル層１２の上方、および、ｎ＋型ソース領域１４の上方に、保護絶縁膜２２からなる膜部２２ａおよび２２ｂが形成されている。膜部２２ａは、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上層部、すなわちＪＦＥＴ領域１６の上方に形成された保護絶縁膜２２からなる。膜部２２ｂは、ｎ＋型ソース領域１４の上方に形成された保護絶縁膜２２からなる。膜部２２ｂを構成する保護絶縁膜２２は、膜部２２ａを構成する保護絶縁膜２２と同層に形成された絶縁膜である。 As shown in FIG. 22, in the second embodiment, as in the first embodiment, a film made of the protective insulating film 22 above the n − type epitaxial layer 12 and above the n + type source region 14. Portions 22a and 22b are formed. The film part 22 a is formed of a protective insulating film 22 formed above the upper part of the n − -type epitaxial layer 12, that is, above the JFET region 16, on the opposite side of the n + -type source region 14 across the p-type body region 13. The film part 22 b is composed of a protective insulating film 22 formed above the n + -type source region 14. The protective insulating film 22 constituting the film part 22b is an insulating film formed in the same layer as the protective insulating film 22 constituting the film part 22a.
　ゲート絶縁膜１８の厚さＴＨ１は、膜部２２ａの厚さＴＨ２よりも小さく、かつ、膜部２２ｂの厚さＴＨ３よりも小さい。これにより、ＪＦＥＴ領域１６とゲート電極１９との間の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させることができる。 The thickness TH1 of the gate insulating film 18 is smaller than the thickness TH2 of the film part 22a and smaller than the thickness TH3 of the film part 22b. Thereby, the strength of the electric field in the insulating film between the JFET region 16 and the gate electrode 19 can be reduced, and the reliability of the insulating film can be improved.
　ただし、本実施の形態２では、実施の形態１と異なり、ＪＦＥＴ領域１６と、保護絶縁膜２２からなる膜部２２ａとの間に、絶縁膜２３が形成されている。すなわち絶縁膜２３は、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面上に、形成されている。したがって、膜部２２ａは、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面上に、絶縁膜２３を介して形成された保護絶縁膜２２からなる。 However, in the second embodiment, unlike the first embodiment, the insulating film 23 is formed between the JFET region 16 and the film portion 22a made of the protective insulating film 22. That is, the insulating film 23 is formed on the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween. Therefore, the film portion 22 a is formed from the protective insulating film 22 formed on the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween via the insulating film 23. Become.
　絶縁膜２３は、例えばゲート絶縁膜１８と同様に、酸化シリコン（ＳｉＯ２）、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）または酸化ハフニウム（ＨｆＯ２）などからなり、例えば熱酸化法またはＣＶＤ法などにより形成されている。また、絶縁膜２３の厚さは、例えば数十ｎｍ程度である。 The insulating film 23 is made of silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or the like, for example, like the gate insulating film 18. It is formed by the method or the CVD method. Further, the thickness of the insulating film 23 is, for example, about several tens of nm.
　保護絶縁膜２２をパターニングして開口部２２ｃを形成することで、膜部２２ａおよび２２ｂが形成されている。開口部２２ｃは、保護絶縁膜２２を貫通して絶縁膜２３に達する。また、保護絶縁膜２２をパターニングして開口部２２ｃを形成する際に、絶縁膜２３をパターニングして開口部２３ｃを形成する。開口部２３ｃは、開口部２２ｃと連通し、絶縁膜２３を貫通してｐ型ボディ領域１３に達する。 Film portions 22a and 22b are formed by patterning the protective insulating film 22 to form the opening 22c. The opening 22 c penetrates the protective insulating film 22 and reaches the insulating film 23. Further, when the protective insulating film 22 is patterned to form the opening 22c, the insulating film 23 is patterned to form the opening 23c. Opening 23 c communicates with opening 22 c and penetrates insulating film 23 to reach p type body region 13.
　絶縁膜２３は、保護絶縁膜２２よりも高品質の膜である。好適には、絶縁膜２３の密度は、保護絶縁膜２２の密度よりも大きい。また、好適には、絶縁膜２３の誘電率は、保護絶縁膜２２の誘電率よりも大きい。このとき、絶縁膜２３中の準位の密度は、保護絶縁膜２２中の準位の密度よりも小さい。 The insulating film 23 is a higher quality film than the protective insulating film 22. Preferably, the density of the insulating film 23 is larger than the density of the protective insulating film 22. Preferably, the dielectric constant of the insulating film 23 is larger than the dielectric constant of the protective insulating film 22. At this time, the density of levels in the insulating film 23 is smaller than the density of levels in the protective insulating film 22.
　ＪＦＥＴ領域１６は、キャリアとしての電子が移動する領域である。また、ＪＦＥＴ領域１６上に形成される絶縁膜のうち、ＪＦＥＴ領域１６と接触する部分は、当該絶縁膜中の電界の強度が最大になる部分である。したがって、ＪＦＥＴ領域１６と保護絶縁膜２２との界面部分に、保護絶縁膜２２中の準位の密度よりも小さい密度の準位を有する絶縁膜２３を形成することで、保護絶縁膜２２中に存在する準位に、ＪＦＥＴ領域１６中を移動するキャリアが捕獲されることを、防止または抑制することができる。よって、ＪＦＥＴ領域１６上の絶縁膜の信頼性をさらに向上させることができる。 The JFET region 16 is a region where electrons as carriers move. In addition, in the insulating film formed on the JFET region 16, the portion in contact with the JFET region 16 is a portion where the intensity of the electric field in the insulating film is maximized. Therefore, by forming the insulating film 23 having a level lower than the density of the levels in the protective insulating film 22 at the interface portion between the JFET region 16 and the protective insulating film 22, It is possible to prevent or suppress the carriers that move in the JFET region 16 from being captured by the existing levels. Therefore, the reliability of the insulating film on the JFET region 16 can be further improved.
　なお、図２２に示す例では、ｎ＋型ソース領域１４と、保護絶縁膜２２からなる膜部２２ｂとの間にも、絶縁膜２３が形成されている。すなわち絶縁膜２３は、ｎ＋型ソース領域１４上にも、形成されている。したがって、膜部２２ｂは、ｎ＋型ソース領域１４上に、絶縁膜２３を介して形成された保護絶縁膜２２からなる。膜部２２ｂの下の絶縁膜２３は、膜部２２ａの下の絶縁膜２３と同層に形成された絶縁膜である。これにより、ＪＦＥＴ領域１６上の絶縁膜と同様に、ｎ＋型ソース領域１４上の絶縁膜の信頼性を向上させることができる。 In the example shown in FIG. 22, the insulating film 23 is also formed between the n + type source region 14 and the film part 22 b made of the protective insulating film 22. That is, the insulating film 23 is also formed on the n + type source region 14. Therefore, the film part 22 b is composed of the protective insulating film 22 formed on the n + type source region 14 via the insulating film 23. The insulating film 23 under the film part 22b is an insulating film formed in the same layer as the insulating film 23 under the film part 22a. Thereby, like the insulating film on the JFET region 16, the reliability of the insulating film on the n + -type source region 14 can be improved.
　＜半導体装置の動作＞
　実施の形態２の半導体装置１ｂの動作については、実施の形態１の半導体装置１の動作と同様であるため、その説明を省略する。 <Operation of semiconductor device>
Since the operation of the semiconductor device 1b of the second embodiment is the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted.
　＜半導体装置の外周部＞
　次に、実施の形態２の半導体装置の外周部について説明する。図２３は、実施の形態２の半導体装置の外周部における断面図である。 <Outer peripheral portion of semiconductor device>
Next, the outer peripheral part of the semiconductor device of Embodiment 2 is demonstrated. FIG. 23 is a cross-sectional view of the outer periphery of the semiconductor device of the second embodiment.
　図２２を用いて前述したように、本実施の形態２の半導体装置１ｂの中心部は、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１に、形成されている。一方、図２３に示すように、本実施の形態２の半導体装置１ｂの外周部は、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、領域ＡＲ１よりも外周側の領域ＡＲ２に、形成されている。 As described above with reference to FIG. 22, the central portion of the semiconductor device 1 b according to the second embodiment is formed on the upper surface side of the n + -type SiC substrate 10 and in the central region AR < b > 1. On the other hand, as shown in FIG. 23, the outer peripheral portion of the semiconductor device 1b of the second embodiment is formed in the area AR2 on the upper surface side of the n + type SiC substrate 10 and on the outer peripheral side of the area AR1. Yes.
　図２３に示すように、領域ＡＲ２で、実施の形態２の半導体装置１ｂは、電界緩和領域２４を有する。電界緩和領域２４は、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、領域ＡＲ１よりも外周側の領域ＡＲ２において、ｎ－型エピタキシャル層１２の上層部に形成されており、例えばアルミニウム（Ａｌ）またはホウ素（Ｂ）などのｐ型不純物が拡散した炭化ケイ素（ＳｉＣ）からなるｐ型半導体領域である。すなわち半導体領域としての電界緩和領域２４の導電型は、ｐ型である。 As shown in FIG. 23, in region AR2, semiconductor device 1b of the second embodiment has electric field relaxation region 24. The electric field relaxation region 24 is formed in the upper layer portion of the n − -type epitaxial layer 12 in the region AR2 on the upper surface side of the n + -type SiC substrate 10 and on the outer peripheral side of the region AR1, for example, aluminum (Al) Alternatively, it is a p-type semiconductor region made of silicon carbide (SiC) in which a p-type impurity such as boron (B) is diffused. That is, the conductivity type of the electric field relaxation region 24 as a semiconductor region is p-type.
　ドレイン電極１１は、領域ＡＲ１およびＡＲ２で、ｎ＋型ＳｉＣ基板１０の下面全面に形成されている。一方、ソース電極２０は、領域ＡＲ２で、ｎ＋型ＳｉＣ基板１０の上面の外周部よりも中心部側に後退して形成されている。そのため、ドレイン電極１１に高電圧が印加された場合、ドレイン電極１１からソース電極２０に向かう電気力線がソース電極２０の下面の外周端２０ａに集中し、外周端２０ａ近傍のｎ－型エピタキシャル層１２中で、領域ＡＲ１でのｎ－型エピタキシャル層１２（図２２参照）中に比べ、電界の強度が大きくなる。そこで、領域ＡＲ２で、ｎ－型エピタキシャル層１２の上層部に、ｐ型ボディ領域１３に代え、電界を緩和、すなわち電界の強度を小さくするための電界緩和領域２４が形成されている。好適には、電界緩和領域２４は、ソース電極２０の下面の外周端２０ａが、平面視において、電界緩和領域２４に内包されるように、形成される。 Drain electrode 11 is formed on the entire bottom surface of n + -type SiC substrate 10 in regions AR1 and AR2. On the other hand, source electrode 20 is formed in region AR2 so as to recede from the outer peripheral portion of the upper surface of n + -type SiC substrate 10 toward the center. Therefore, when a high voltage is applied to the drain electrode 11, electric lines of force from the drain electrode 11 toward the source electrode 20 are concentrated on the outer peripheral end 20a on the lower surface of the source electrode 20, and the n − type epitaxial layer in the vicinity of the outer peripheral end 20a. 12, the electric field strength is higher than that in the n − type epitaxial layer 12 (see FIG. 22) in the region AR 1. Therefore, in region AR2, an electric field relaxation region 24 for relaxing the electric field, that is, reducing the strength of the electric field, is formed in the upper layer portion of n − type epitaxial layer 12 in place of p type body region 13. Preferably, the electric field relaxation region 24 is formed such that the outer peripheral edge 20a of the lower surface of the source electrode 20 is included in the electric field relaxation region 24 in plan view.
　電界緩和領域２４におけるp型の不純物濃度は、ｐ型ボディ領域１３におけるｐ型の不純物濃度よりも小さい。電界緩和領域２４におけるp型の不純物濃度は、例えば１×１０１６～１×１０１７ｃｍ－３程度である。また、電界緩和領域２４の厚さは、例えば１～２μｍ程度である。好適には、電界緩和領域２４におけるp型の不純物濃度は、ｎ＋型ＳｉＣ基板１０の上面の中心部側から外周部側に向かって減少している。 The p-type impurity concentration in the electric field relaxation region 24 is smaller than the p-type impurity concentration in the p-type body region 13. The p-type impurity concentration in the electric field relaxation region 24 is, for example, about 1 × 10 16 to 1 × 10 17 cm −3 . Further, the thickness of the electric field relaxation region 24 is, for example, about 1 to 2 μm. Preferably, the p-type impurity concentration in electric field relaxation region 24 decreases from the center side of the upper surface of n + -type SiC substrate 10 toward the outer peripheral side.
　領域ＡＲ２で、電界緩和領域２４の上層部に、ｐ＋型ボディコンタクト領域１５が形成されている。ｎ－型エピタキシャル層１２の上面上、電界緩和領域２４の上面上、および、ｐ＋型ボディコンタクト領域１５上には、絶縁膜２３、保護絶縁膜２２、ゲート絶縁膜１８および層間絶縁膜２１が、下から上に向かって順に形成されている。 In region AR2, ap + type body contact region 15 is formed in the upper layer portion of electric field relaxation region 24. An insulating film 23, a protective insulating film 22, a gate insulating film 18, and an interlayer insulating film 21 are formed on the upper surface of the n − type epitaxial layer 12, the upper surface of the electric field relaxation region 24, and the p + type body contact region 15. They are formed in order from bottom to top.
　言い換えれば、領域ＡＲ２では、電界緩和領域２４上に、絶縁膜２３を介して形成された保護絶縁膜２２からなる膜部２２ｇが形成されている。膜部２２ｇの下の絶縁膜２３は、領域ＡＲ１で膜部２２ａの下の絶縁膜２３（図２２参照）と同層に形成された絶縁膜であり、膜部２２ｇを構成する保護絶縁膜２２は、領域ＡＲ１で膜部２２ａを構成する保護絶縁膜２２（図２２参照）と同層に形成された絶縁膜である。 In other words, in the region AR2, the film part 22g made of the protective insulating film 22 formed via the insulating film 23 is formed on the electric field relaxation region 24. The insulating film 23 under the film part 22g is an insulating film formed in the same layer as the insulating film 23 under the film part 22a (see FIG. 22) in the region AR1, and the protective insulating film 22 constituting the film part 22g. Is an insulating film formed in the same layer as the protective insulating film 22 (see FIG. 22) constituting the film part 22a in the region AR1.
　なお、例えば熱酸化法によりゲート絶縁膜１８を形成する場合、保護絶縁膜２２上にゲート絶縁膜１８が形成されないこともある。このとき、保護絶縁膜２２上に、層間絶縁膜２１が直接形成される。 For example, when the gate insulating film 18 is formed by a thermal oxidation method, the gate insulating film 18 may not be formed on the protective insulating film 22. At this time, the interlayer insulating film 21 is directly formed on the protective insulating film 22.
　領域ＡＲ２で、層間絶縁膜２１、ゲート絶縁膜１８、保護絶縁膜２２および絶縁膜２３には、開口部としてのソースコンタクト孔２１ｂが形成されている。ソースコンタクト孔２１ｂは、層間絶縁膜２１、ゲート絶縁膜１８、保護絶縁膜２２および絶縁膜２３を貫通して、ｐ＋型ボディコンタクト領域１５の上面に達する。すなわちソースコンタクト孔２１ｂの底面には、ｐ＋型ボディコンタクト領域１５の上面が露出している。 In the region AR2, a source contact hole 21b as an opening is formed in the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22, and the insulating film 23. Source contact hole 21 b passes through interlayer insulating film 21, gate insulating film 18, protective insulating film 22, and insulating film 23 and reaches the upper surface of p + -type body contact region 15. That is, the upper surface of the p + type body contact region 15 is exposed at the bottom surface of the source contact hole 21b.
　領域ＡＲ２で、ソース電極２０は、ソースコンタクト孔２１ｂの底面および側面を含めて層間絶縁膜２１上に形成されている。このような構造により、ソース電極２０は、層間絶縁膜２１、ゲート絶縁膜１８、保護絶縁膜２２および絶縁膜２３に形成されたソースコンタクト孔２１ｂを介して、ｐ＋型ボディコンタクト領域１５と電気的に接続されている。そして、ｐ＋型ボディコンタクト領域１５は、電界緩和領域２４と電気的に接続されている。そのため、ソース電極２０は、ｐ＋型ボディコンタクト領域１５を介して電界緩和領域２４と電気的に接続されている。なお、電界緩和領域２４の上層部にｐ＋型ボディコンタクト領域１５が形成されていなくてもよく、ソース電極２０が、電界緩和領域２４と電気的に直接接続されていてもよい。 In the region AR2, the source electrode 20 is formed on the interlayer insulating film 21 including the bottom and side surfaces of the source contact hole 21b. With such a structure, the source electrode 20 is electrically connected to the p + -type body contact region 15 via the source contact hole 21b formed in the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22, and the insulating film 23. Connected. The p + type body contact region 15 is electrically connected to the electric field relaxation region 24. Therefore, the source electrode 20 is electrically connected to the electric field relaxation region 24 through the p + type body contact region 15. Note that the p + -type body contact region 15 may not be formed in the upper layer portion of the electric field relaxation region 24, and the source electrode 20 may be electrically connected directly to the electric field relaxation region 24.
　本実施の形態２では、領域ＡＲ２で、電界緩和領域２４の上面と保護絶縁膜２２との間に、保護絶縁膜２２よりも高品質な絶縁膜２３が形成されている。このとき、保護絶縁膜２２が、電流が流れる領域である電界緩和領域２４に接触していないので、保護絶縁膜２２中に存在する準位にキャリアが捕獲されることを防止または抑制することができる。したがって、絶縁膜２３が形成されない場合に比べ、電界緩和領域２４およびｎ－型エピタキシャル層１２に印加される電界の強度がより大きい場合でも、半導体装置１ｂの性能を維持することができる。言い換えれば、絶縁膜２３を形成することで、半導体装置１ｂの性能を維持しつつ、電界緩和領域２４が形成される領域の面積を小さくすることができ、半導体装置１ｂの面積を小さくすることができる。 In the second embodiment, an insulating film 23 of higher quality than the protective insulating film 22 is formed between the upper surface of the electric field relaxation region 24 and the protective insulating film 22 in the region AR2. At this time, since the protective insulating film 22 is not in contact with the electric field relaxation region 24, which is a region where current flows, it is possible to prevent or suppress carriers from being trapped in the levels existing in the protective insulating film 22. it can. Therefore, the performance of the semiconductor device 1b can be maintained even when the strength of the electric field applied to the electric field relaxation region 24 and the n − -type epitaxial layer 12 is larger than when the insulating film 23 is not formed. In other words, by forming the insulating film 23, the area of the region where the electric field relaxation region 24 is formed can be reduced while maintaining the performance of the semiconductor device 1b, and the area of the semiconductor device 1b can be reduced. it can.
　＜半導体装置の製造工程＞
　次に、本実施の形態２の半導体装置の製造工程の例を、図面を参照して説明する。図２４は、実施の形態２の半導体装置の製造工程の一部を示すフロー図である。図２５～図２８は、実施の形態２の半導体装置の製造工程中の要部断面図である。なお、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、中心側の領域ＡＲ１における製造工程について、説明する。 <Manufacturing process of semiconductor device>
Next, an example of a manufacturing process of the semiconductor device according to the second embodiment will be described with reference to the drawings. FIG. 24 is a flowchart showing a part of the manufacturing process of the semiconductor device of Second Embodiment. 25 to 28 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device of the second embodiment. In the following, the manufacturing process in the region AR1 on the upper surface side and the center side of the n + type SiC substrate 10 will be described.
　図２４に示すように、本実施の形態２におけるステップＳ１１～ステップＳ１５、および、ステップＳ１８～ステップＳ２３の各工程は、実施の形態１におけるステップＳ１１～ステップＳ１５、および、ステップＳ１８～ステップＳ２３の各工程（図６参照）と同様である。 As shown in FIG. 24, steps S11 to S15 and steps S18 to S23 in the second embodiment are the same as steps S11 to S15 and steps S18 to S23 in the first embodiment. It is the same as each process (refer FIG. 6).
　本実施の形態２では、まず、図６のステップＳ１１～ステップＳ１５の各工程と同様の工程を行う。そして、図１２に示したように、ｎ＋型ＳｉＣ基板１０の上面に、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５を形成する（図２４のステップＳ１１～ステップＳ１５）。 In the second embodiment, first, processes similar to those in steps S11 to S15 in FIG. 6 are performed. Then, as shown in FIG. 12, n − type epitaxial layer 12, p type body region 13, n + type source region 14 and p + type body contact region 15 are formed on the upper surface of n + type SiC substrate 10. (Step S11 to Step S15 in FIG. 24).
　次いで、絶縁膜２３および保護絶縁膜２２からなる２層の絶縁膜を形成する（図２４のステップＳ２６）。 Next, a two-layer insulating film including the insulating film 23 and the protective insulating film 22 is formed (step S26 in FIG. 24).
　このステップＳ２６では、まず、図２５に示すように、ｎ－型エピタキシャル層１２の上面上、ｐ型ボディ領域１３上、ｎ＋型ソース領域１４上、および、ｐ＋型ボディコンタクト領域１５上に、絶縁膜２３を形成する。絶縁膜２３の密度は、保護絶縁膜２２（後述する図２６参照）の密度よりも大きい。また、絶縁膜２３の誘電率は、保護絶縁膜２２の誘電率よりも大きい。 In this step S26, first, as shown in FIG. 25, on the upper surface of the n − type epitaxial layer 12, on the p type body region 13, on the n + type source region 14 and on the p + type body contact region 15. Then, the insulating film 23 is formed. The density of the insulating film 23 is larger than the density of the protective insulating film 22 (see FIG. 26 described later). Further, the dielectric constant of the insulating film 23 is larger than the dielectric constant of the protective insulating film 22.
　好適には、絶縁膜２３として、例えば比較的高温で形成された絶縁膜を用いることができる。または、好適には、絶縁膜２３として、比較的低温で堆積された膜を高温で熱処理することにより形成された絶縁膜を用いることができる。このような絶縁膜２３として、好適には、例えば酸化シリコン（ＳｉＯ２）、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）または酸化ハフニウム（ＨｆＯ２）などからなる各種の膜を用いることができる。あるいは、絶縁膜２３として、好適には、上記の各種の膜が積層された積層膜を用いることができる。また、このような絶縁膜２３を、例えば８００℃以上の温度で、熱酸化法またはＣＶＤ法により形成することができる。そして、絶縁膜２３の厚さを、例えば数十ｎｍ程度とすることができる。 Preferably, as the insulating film 23, for example, an insulating film formed at a relatively high temperature can be used. Alternatively, as the insulating film 23, an insulating film formed by heat-treating a film deposited at a relatively low temperature at a high temperature can be used. As such an insulating film 23, preferably, for example, silicon oxide (SiO 2), silicon oxynitride (SiON), use various films made of aluminum oxide (Al 2 O 3) or hafnium oxide (HfO 2) be able to. Alternatively, as the insulating film 23, a laminated film in which the above various films are suitably laminated can be used. Further, such an insulating film 23 can be formed by a thermal oxidation method or a CVD method at a temperature of, for example, 800 ° C. or higher. The thickness of the insulating film 23 can be set to, for example, about several tens of nm.
　このようにして絶縁膜２３を形成した後、図２６に示すように、絶縁膜２３上に、保護絶縁膜２２を形成する。この保護絶縁膜２２を形成する工程は、実施の形態１におけるステップＳ１６の工程と同様にすることができる。 After forming the insulating film 23 in this manner, a protective insulating film 22 is formed on the insulating film 23 as shown in FIG. The process of forming this protective insulating film 22 can be the same as the process of step S16 in the first embodiment.
　次いで、絶縁膜２３および保護絶縁膜２２からなる２層の絶縁膜をパターニングする（図２４のステップＳ２７）。このステップＳ２７では、図２７に示すように、フォトリソグラフィ技術およびドライエッチング技術により、保護絶縁膜２２を加工、すなわちパターニングすることで、開口部２２ｃを形成し、膜部２２ａおよび膜部２２ｂを形成する。この開口部２２ｃを形成する工程は、実施の形態１におけるステップＳ１７の工程と同様にすることができる。ただし、本実施の形態２では、開口部２２ｃは、保護絶縁膜２２を貫通して絶縁膜２３に達する。 Next, a two-layer insulating film composed of the insulating film 23 and the protective insulating film 22 is patterned (step S27 in FIG. 24). In this step S27, as shown in FIG. 27, the protective insulating film 22 is processed, that is, patterned by the photolithography technique and the dry etching technique to form the opening 22c, and the film part 22a and the film part 22b are formed. To do. The step of forming the opening 22c can be the same as the step S17 in the first embodiment. However, in the second embodiment, the opening 22 c penetrates the protective insulating film 22 and reaches the insulating film 23.
　また、ステップＳ２７では、図２７に示すように、フォトリソグラフィ技術およびドライエッチング技術により、絶縁膜２３を加工、すなわちパターニングすることで、開口部２３ｃを形成する。開口部２３ｃは、開口部２２ｃと連通し、絶縁膜２３を貫通してｐ型ボディ領域１３の上面に達する。これにより、ｐ型ボディ領域１３を挟んでｎ＋型ソース領域１４と反対側のｎ－型エピタキシャル層１２の上面上に、絶縁膜２３を介して膜部２２ａが形成され、ｎ＋型ソース領域１４上に、絶縁膜２３を介して膜部２２ｂが形成される。また、開口部２３ｃの底部には、ｐ型ボディ領域１３の上面が露出する。 In step S27, as shown in FIG. 27, the opening 23c is formed by processing, that is, patterning, the insulating film 23 by a photolithography technique and a dry etching technique. Opening 23 c communicates with opening 22 c and penetrates insulating film 23 to reach the upper surface of p-type body region 13. As a result, a film portion 22a is formed on the upper surface of the n − type epitaxial layer 12 opposite to the n + type source region 14 with the p type body region 13 interposed therebetween via the insulating film 23, and the n + type source region A film portion 22 b is formed on the insulating film 23 on the upper surface 14. Further, the upper surface of the p-type body region 13 is exposed at the bottom of the opening 23c.
　次いで、ゲート絶縁膜１８を形成する（図２４のステップＳ１８）。このステップＳ１８では、図２８に示すように、開口部２３ｃに露出したｐ型ボディ領域１３の上面上に、ゲート絶縁膜１８を形成する。このステップＳ１８の工程は、膜部２２ａおよび２２ｂの下に絶縁膜２３が形成されている点を除き、実施の形態１におけるステップＳ１８の工程と同様にすることができる。 Next, the gate insulating film 18 is formed (step S18 in FIG. 24). In this step S18, as shown in FIG. 28, the gate insulating film 18 is formed on the upper surface of the p-type body region 13 exposed in the opening 23c. The process of step S18 can be the same as the process of step S18 in the first embodiment except that the insulating film 23 is formed under the film portions 22a and 22b.
　次いで、図６のステップＳ１９およびステップＳ２０の各工程と同様の工程を行って、図２２に示したように、ゲート電極１９および層間絶縁膜２１を形成する（図２４のステップＳ１９およびステップＳ２０）。 Next, steps similar to the steps S19 and S20 in FIG. 6 are performed to form the gate electrode 19 and the interlayer insulating film 21 as shown in FIG. 22 (steps S19 and S20 in FIG. 24). .
　次いで、図６のステップＳ２１の工程と同様の工程を行って、図２２に示したように、ソースコンタクト孔２１ａを形成する（図２４のステップＳ２１）。ただし、本実施の形態２では、実施の形態１と異なり、層間絶縁膜２１、ゲート絶縁膜１８および保護絶縁膜２２に加え、さらに絶縁膜２３に、開口部としてのソースコンタクト孔２１ａを形成する。すなわち層間絶縁膜２１、ゲート絶縁膜１８、保護絶縁膜２２および絶縁膜２３を貫通し、ｎ＋型ソース領域１４およびｐ＋型ボディコンタクト領域１５に達するソースコンタクト孔２１ａを形成する。 Next, a step similar to the step S21 in FIG. 6 is performed to form the source contact hole 21a as shown in FIG. 22 (step S21 in FIG. 24). However, in the second embodiment, unlike the first embodiment, in addition to the interlayer insulating film 21, the gate insulating film 18 and the protective insulating film 22, a source contact hole 21 a as an opening is formed in the insulating film 23. . That is, a source contact hole 21 a that penetrates the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22 and the insulating film 23 and reaches the n + type source region 14 and the p + type body contact region 15 is formed.
　その後、図６のステップＳ２２およびステップＳ２３の各工程と同様の工程（図２４のステップＳ２２およびステップＳ２３）を行って、ソース電極２０およびドレイン電極１１を形成することで、図２２に示したような、半導体装置１ｂを製造することができる。 Thereafter, the same processes (step S22 and step S23 in FIG. 24) as the respective processes in step S22 and step S23 in FIG. 6 are performed to form the source electrode 20 and the drain electrode 11, and as shown in FIG. In addition, the semiconductor device 1b can be manufactured.
　＜外周部における半導体装置の製造方法＞
　図２９～図３２は、実施の形態２の半導体装置の製造工程中の外周部における断面図である。なお、以下では、ｎ＋型ＳｉＣ基板１０の上面側で、かつ、領域ＡＲ１よりも外周側の領域ＡＲ２における半導体装置の製造工程のうち、前述した領域ＡＲ１における半導体装置の製造工程と異なる点について、説明する。 <Method for Manufacturing Semiconductor Device in Outer Periphery>
29 to 32 are cross-sectional views of the outer periphery during the manufacturing process of the semiconductor device of the second embodiment. In the following, among the manufacturing steps of the semiconductor device in the region AR2 on the upper surface side of the n + -type SiC substrate 10 and on the outer peripheral side of the region AR1, there are differences from the manufacturing steps of the semiconductor device in the region AR1 described above. ,explain.
　図２４のステップＳ１３では、領域ＡＲ２において、図２９に示すように、ｎ－型エピタキシャル層１２の上層部に、ｐ型ボディ領域１３（図２２参照）に代え、電界緩和領域２４を形成する。その後、図２４のステップＳ１５では、領域ＡＲ２において、図２９に示すように、電界緩和領域２４の上層部に、ｐ＋型ボディコンタクト領域１５を形成する。 In step S13 of FIG. 24, an electric field relaxation region 24 is formed in the region AR2 in place of the p-type body region 13 (see FIG. 22) in the upper layer portion of the n − -type epitaxial layer 12, as shown in FIG. Thereafter, in step S15 of FIG. 24, ap + type body contact region 15 is formed in the upper portion of electric field relaxation region 24 in region AR2, as shown in FIG.
　次いで、図２４のステップＳ２６では、領域ＡＲ２において、まず、図３０に示すように、ｎ－型エピタキシャル層１２の上面上、電界緩和領域２４の上面上、および、ｐ＋型ボディコンタクト領域１５上に、絶縁膜２３を形成する。そして、領域ＡＲ２において、図３１に示すように、絶縁膜２３上に、保護絶縁膜２２を形成する。 Next, in step S26 of FIG. 24, in the region AR2, as shown in FIG. 30, first, on the upper surface of the n − type epitaxial layer 12, on the upper surface of the electric field relaxation region 24, and on the p + type body contact region 15 Then, an insulating film 23 is formed. Then, in the region AR2, as shown in FIG. 31, the protective insulating film 22 is formed on the insulating film 23.
　次いで、図２４のステップＳ２７では、領域ＡＲ２において、絶縁膜２３および保護絶縁膜２２からなる２層の絶縁膜は、パターニングされない。次いで、図２４のステップＳ１８では、領域ＡＲ２において、図３２に示すように、保護絶縁膜２２上に、ゲート絶縁膜１８を形成する。なお、領域ＡＲ１において、例えば熱酸化法によりゲート絶縁膜１８を形成する場合、領域ＡＲ２において、保護絶縁膜２２上には、ゲート絶縁膜１８が形成されない。 Next, in step S27 of FIG. 24, the two-layer insulating film including the insulating film 23 and the protective insulating film 22 is not patterned in the area AR2. Next, in step S18 of FIG. 24, the gate insulating film 18 is formed on the protective insulating film 22 in the area AR2 as shown in FIG. Note that when the gate insulating film 18 is formed in the region AR1, for example, by a thermal oxidation method, the gate insulating film 18 is not formed on the protective insulating film 22 in the region AR2.
　次いで、図２４のステップＳ１９では、領域ＡＲ２において、図２３に示したように、ゲート電極１９（図２２参照）を形成しない。次いで、図２４のステップＳ２０では、領域ＡＲ２において、図２３に示したように、ゲート絶縁膜１８上に、層間絶縁膜２１を形成する。 Next, in step S19 of FIG. 24, as shown in FIG. 23, the gate electrode 19 (see FIG. 22) is not formed in the area AR2. Next, in step S20 of FIG. 24, the interlayer insulating film 21 is formed on the gate insulating film 18 in the region AR2 as shown in FIG.
　次いで、図２４のステップＳ２１では、領域ＡＲ２において、図２３に示したように、ソースコンタクト孔２１ｂを形成する。この領域ＡＲ２においては、層間絶縁膜２１、ゲート絶縁膜１８、保護絶縁膜２２および絶縁膜２３を貫通し、ｐ＋型ボディコンタクト領域１５に達するソースコンタクト孔２１ｂを形成する。次いで、図２４のステップＳ２２では、領域ＡＲ２において、層間絶縁膜２１上に、ならびに、ソースコンタクト孔２１ｂの底面および内壁を覆うように、ソース電極２０を形成する。 Next, in step S21 of FIG. 24, the source contact hole 21b is formed in the area AR2 as shown in FIG. In this region AR2, a source contact hole 21b that penetrates through the interlayer insulating film 21, the gate insulating film 18, the protective insulating film 22 and the insulating film 23 and reaches the p + type body contact region 15 is formed. Next, in step S22 of FIG. 24, in the region AR2, the source electrode 20 is formed on the interlayer insulating film 21 so as to cover the bottom surface and the inner wall of the source contact hole 21b.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態２の半導体装置１ｂには、実施の形態１の半導体装置１と同様に、膜部２２ａおよび２２ｂが形成されている。ゲート電極１９は、ＪＦＥＴ領域１６上に、少なくとも膜部２２ａを介して形成されている。これにより、実施の形態１の半導体装置１と同様に、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量を小さくしつつ、ＪＦＥＴ領域１６の幅を広くすることができ、インバータにおける電力変換の際の損失を小さくすることができる。したがって、大型の冷却装置が設けられなくてもよく、電力変換装置、または、この電力変換装置を備えた鉄道車両を、容易に低コスト化、小型化または軽量化することができる。 <Main features and effects of the present embodiment>
In the semiconductor device 1b of the second embodiment, film portions 22a and 22b are formed as in the semiconductor device 1 of the first embodiment. The gate electrode 19 is formed on the JFET region 16 via at least the film part 22a. Thus, as in the semiconductor device 1 of the first embodiment, the strength of the electric field in the insulating film on the JFET region 16 is reduced to improve the reliability of the insulating film, and the feedback capacitance is reduced, while reducing the feedback capacitance. The width of 16 can be widened, and the loss during power conversion in the inverter can be reduced. Therefore, it is not necessary to provide a large-sized cooling device, and the power conversion device or the railway vehicle including the power conversion device can be easily reduced in cost, size, or weight.
　一方、本実施の形態２の半導体装置１ｂでは、ＪＦＥＴ領域１６と膜部２２ａとの間に、膜部２２ａを構成する保護絶縁膜２２よりも高品質の絶縁膜２３が形成されている。これにより、保護絶縁膜２２中に存在する準位にキャリアが捕獲されることを防止または抑制することができ、ＪＦＥＴ領域１６上の絶縁膜の信頼性をさらに向上させることができる。 On the other hand, in the semiconductor device 1b of the second embodiment, an insulating film 23 of higher quality than the protective insulating film 22 constituting the film part 22a is formed between the JFET region 16 and the film part 22a. As a result, carriers can be prevented or suppressed from being trapped at the level present in the protective insulating film 22, and the reliability of the insulating film on the JFET region 16 can be further improved.
　（実施の形態３）
　＜電力変換装置＞
　次に、本発明の実施の形態３の電力変換装置について説明する。実施の形態３の電力変換装置は、実施の形態１の半導体装置を備えたインバータである。 (Embodiment 3)
<Power conversion device>
Next, a power conversion device according to Embodiment 3 of the present invention will be described. The power converter of Embodiment 3 is an inverter provided with the semiconductor device of Embodiment 1.
　図３３は、実施の形態３の電力変換装置の構成を示す図である。 FIG. 33 is a diagram illustrating a configuration of the power conversion device according to the third embodiment.
　図３３に示すように、電力変換装置３１は、実施の形態１の半導体装置１が備えられた三相インバータとしてのインバータ３２と、モータ等の負荷３３と、直流電源３４と、コンデンサ等の容量３５とを有する。負荷３３は、インバータ３２の出力側に接続されており、直流電源３４および容量３５は、インバータ３２の入力側に接続されている。 As shown in FIG. 33, the power conversion device 31 includes an inverter 32 as a three-phase inverter provided with the semiconductor device 1 of the first embodiment, a load 33 such as a motor, a DC power supply 34, and a capacity such as a capacitor. 35. The load 33 is connected to the output side of the inverter 32, and the DC power supply 34 and the capacitor 35 are connected to the input side of the inverter 32.
　インバータ３２は、ゲート駆動回路３６ｕ、３６ｖ、３６ｗ、３６ｘ、３６ｙおよび３６ｚと、スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚとを備えている。 The inverter 32 includes gate drive circuits 36u, 36v, 36w, 36x, 36y, and 36z, and switch elements 37u, 37v, 37w, 37x, 37y, and 37z.
　インバータ３２は、一対の直流の入力端子としてのドレインノードＮ１とソースノードＮ２とを備えている。スイッチ素子３７ｕおよび３７ｘは、ドレインノードＮ１とソースノードＮ２との間に、直列に接続されている。スイッチ素子３７ｖおよび３７ｙは、ドレインノードＮ１とソースノードＮ２との間に、直列に接続されている。スイッチ素子３７ｗおよび３７ｚは、ドレインノードＮ１とソースノードＮ２との間に、直列に接続されている。スイッチ素子３７ｕ、３７ｖおよび３７ｗは、上アーム側、すなわち高電圧側に配置されており、スイッチ素子３７ｘ、３７ｙおよび３７ｚは、下アーム側、すなわち低電圧側に配置されている。 The inverter 32 includes a drain node N1 and a source node N2 as a pair of DC input terminals. Switch elements 37u and 37x are connected in series between drain node N1 and source node N2. Switch elements 37v and 37y are connected in series between drain node N1 and source node N2. Switch elements 37w and 37z are connected in series between drain node N1 and source node N2. The switch elements 37u, 37v, and 37w are disposed on the upper arm side, that is, the high voltage side, and the switch elements 37x, 37y, and 37z are disposed on the lower arm side, that is, the low voltage side.
　インバータ３２は、三相交流の出力端子として、Ｕ相の出力ノードＮ３と、Ｖ相の出力ノードＮ４と、Ｗ相の出力ノードＮ５とを備えている。出力ノードＮ３は、スイッチ素子３７ｕのスイッチ素子３７ｘ側、および、スイッチ素子３７ｘのスイッチ素子３７ｕ側に接続されている。出力ノードＮ４は、スイッチ素子３７ｖのスイッチ素子３７ｙ側、および、スイッチ素子３７ｙのスイッチ素子３７ｖ側に接続されている。出力ノードＮ５は、スイッチ素子３７ｗのスイッチ素子３７ｚ側、および、スイッチ素子３７ｚのスイッチ素子３７ｗ側に接続されている。したがって、スイッチ素子３７ｕおよび３７ｘは、Ｕ相用のスイッチ素子であり、スイッチ素子３７ｖおよび３７ｙは、Ｖ相用のスイッチ素子であり、スイッチ素子３７ｗおよび３７ｚは、Ｗ相用のスイッチ素子である。 The inverter 32 includes a U-phase output node N3, a V-phase output node N4, and a W-phase output node N5 as three-phase AC output terminals. The output node N3 is connected to the switch element 37x side of the switch element 37u and the switch element 37u side of the switch element 37x. The output node N4 is connected to the switch element 37y side of the switch element 37v and the switch element 37v side of the switch element 37y. The output node N5 is connected to the switch element 37z side of the switch element 37w and the switch element 37w side of the switch element 37z. Therefore, switch elements 37u and 37x are U-phase switch elements, switch elements 37v and 37y are V-phase switch elements, and switch elements 37w and 37z are W-phase switch elements.
　スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚの各々は、ＭＩＳＦＥＴ３８とボディダイオード３９とを含む。そして、本実施の形態３では、スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚの各々として、実施の形態１の半導体装置１（図１参照）を用いることができる。このとき、ＭＩＳＦＥＴ３８は、ドレイン電極１１、ｎ＋型ＳｉＣ基板１０、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｎ＋型ソース領域１４、ｐ＋型ボディコンタクト領域１５、ゲート絶縁膜１８、ゲート電極１９およびソース電極２０により形成される縦型ＭＩＳＦＥＴである（図１参照）。また、ボディダイオード３９は、ドレイン電極１１、ｎ＋型ＳｉＣ基板１０、ｎ－型エピタキシャル層１２、ｐ型ボディ領域１３、ｐ＋型ボディコンタクト領域１５およびソース電極２０により形成されるダイオードである（図１参照）。 Each of switch elements 37u, 37v, 37w, 37x, 37y and 37z includes a MISFET 38 and a body diode 39. In the third embodiment, the semiconductor device 1 (see FIG. 1) of the first embodiment can be used as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z. At this time, the MISFET 38 includes the drain electrode 11, the n + type SiC substrate 10, the n − type epitaxial layer 12, the p type body region 13, the n + type source region 14, the p + type body contact region 15, the gate insulating film 18, This is a vertical MISFET formed by the gate electrode 19 and the source electrode 20 (see FIG. 1). The body diode 39 is a diode formed by the drain electrode 11, the n + type SiC substrate 10, the n − type epitaxial layer 12, the p type body region 13, the p + type body contact region 15 and the source electrode 20 ( (See FIG. 1).
　ゲート駆動回路３６ｕは、スイッチ素子３７ｕのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｕを駆動する。ゲート駆動回路３６ｘは、スイッチ素子３７ｘのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｘを駆動する。ゲート駆動回路３６ｖは、スイッチ素子３７ｖのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｖを駆動する。ゲート駆動回路３６ｙは、スイッチ素子３７ｙのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｙを駆動する。ゲート駆動回路３６ｗは、スイッチ素子３７ｗのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｗを駆動する。ゲート駆動回路３６ｚは、スイッチ素子３７ｚのＭＩＳＦＥＴ３８のゲート電極に接続されており、スイッチ素子３７ｚを駆動する。 The gate drive circuit 36u is connected to the gate electrode of the MISFET 38 of the switch element 37u, and drives the switch element 37u. The gate drive circuit 36x is connected to the gate electrode of the MISFET 38 of the switch element 37x, and drives the switch element 37x. The gate drive circuit 36v is connected to the gate electrode of the MISFET 38 of the switch element 37v and drives the switch element 37v. The gate drive circuit 36y is connected to the gate electrode of the MISFET 38 of the switch element 37y, and drives the switch element 37y. The gate drive circuit 36w is connected to the gate electrode of the MISFET 38 of the switch element 37w, and drives the switch element 37w. The gate drive circuit 36z is connected to the gate electrode of the MISFET 38 of the switch element 37z, and drives the switch element 37z.
　インバータ３２の入力側で、かつ、上アーム側に配置されたドレインノードＮ１には、インバータ３２の上アーム側に設けられたスイッチ素子３７ｕ、３７ｖおよび３７ｗのそれぞれの一端が、接続されている。インバータ３２の入力側で、かつ、下アーム側に配置されたソースノードＮ２には、インバータ３２の下アーム側のスイッチ素子３７ｘ、３７ｙおよび３７ｚのそれぞれの一端が、接続されている。 One end of each of the switch elements 37u, 37v and 37w provided on the upper arm side of the inverter 32 is connected to the drain node N1 arranged on the input side of the inverter 32 and on the upper arm side. One end of each of the switching elements 37x, 37y and 37z on the lower arm side of the inverter 32 is connected to the source node N2 arranged on the input side of the inverter 32 and on the lower arm side.
　ドレインノードＮ１とソースノードＮ２との間には、直流電源３４と容量３５とが、互いに並列に接続されている。したがって、ドレインノードＮ１とソースノードＮ２との間には、直流電源３４により、電圧ＶＰＰが印加されている。 A DC power supply 34 and a capacitor 35 are connected in parallel with each other between the drain node N1 and the source node N2. Therefore, the voltage VPP is applied between the drain node N1 and the source node N2 by the DC power supply 34.
　ゲート駆動回路３６ｕ、３６ｖ、３６ｗ、３６ｘ、３６ｙおよび３６ｚの各々は、対応するスイッチ素子のオン状態とオフ状態とが予め設定されたタイミングで切り替わるように、スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚのそれぞれを駆動する。これにより、直流信号である電圧ＶＰＰから、位相がそれぞれ異なる三相、すなわちＵ相、Ｖ相およびＷ相の交流信号を生成する。すなわち、スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚの各々において、オン状態とオフ状態とが切り替えられることで、電力が変換される。負荷３３は、この三相の交流信号によって駆動される。 Each of the gate drive circuits 36u, 36v, 36w, 36x, 36y, and 36z has switching elements 37u, 37v, 37w, 37x, so that the corresponding switch elements are switched on and off at preset timings. Each of 37y and 37z is driven. Thus, three-phase AC signals having different phases, that is, U-phase, V-phase, and W-phase AC signals are generated from the voltage VPP that is a DC signal. That is, in each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z, the power is converted by switching between the on state and the off state. The load 33 is driven by the three-phase AC signal.
　前述したように、半導体装置１の内部には、ボディダイオード３９が内蔵されており、逆並列のダイオード、すなわち還流ダイオードを用いなくても、ボディダイオード３９を介して還流電流を流すことが可能である。したがって、実施の形態１の半導体装置１をスイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚの各々として備えたインバータ３２を有する、本実施の形態３の電力変換装置３１においては、必要な部品の数を削減することができ、電力変換装置３１を容易に小型化することができる。 As described above, the body diode 39 is built in the semiconductor device 1, and it is possible to flow a reflux current through the body diode 39 without using an antiparallel diode, that is, a reflux diode. is there. Therefore, in the power conversion device 31 of the third embodiment having the inverter 32 provided with the semiconductor device 1 of the first embodiment as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z, necessary components Thus, the power converter 31 can be easily downsized.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態３の電力変換装置３１には、スイッチ素子３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙおよび３７ｚの各々として、実施の形態１の半導体装置１が備えられている。実施の形態１の半導体装置１によれば、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量を小さくしつつ、ＪＦＥＴ領域１６の幅を広くすることができ、インバータにおける電力変換の際の損失を小さくすることができるので、大型の冷却装置が設けられなくてもよい。したがって、冷却装置を小型化することなどにより、電力変換装置３１を、容易に低コスト化、小型化または軽量化することができる。 <Main features and effects of the present embodiment>
The power conversion device 31 according to the third embodiment includes the semiconductor device 1 according to the first embodiment as each of the switch elements 37u, 37v, 37w, 37x, 37y, and 37z. According to the semiconductor device 1 of the first embodiment, the strength of the electric field in the insulating film on the JFET region 16 is reduced, the reliability of the insulating film is improved, the feedback capacitance is reduced, and the width of the JFET region 16 is reduced. Since the loss at the time of power conversion in the inverter can be reduced, a large cooling device may not be provided. Therefore, the power conversion device 31 can be easily reduced in cost, size, or weight by reducing the size of the cooling device.
　なお、スイッチ素子３７ｕなどのスイッチ素子として、実施の形態１の半導体装置１に代え、実施の形態１の第１変形例の半導体装置１ａ、または、実施の形態２の半導体装置１ｂが備えられてもよい。この場合、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させる効果、および、帰還容量を小さくする効果がさらに増加するので、電力変換装置３１を、さらに容易に低コスト化、小型化または軽量化することができる。 In addition, as a switching element such as the switching element 37u, the semiconductor device 1a of the first modification of the first embodiment or the semiconductor device 1b of the second embodiment is provided instead of the semiconductor device 1 of the first embodiment. Also good. In this case, since the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased, Further, it can be easily reduced in cost, size, or weight.
　（実施の形態４）
　＜鉄道車両＞
　次に、本発明の実施の形態４の鉄道車両について説明する。実施の形態４の鉄道車両は、実施の形態３の電力変換装置を含む鉄道車両である。 (Embodiment 4)
<Railway vehicle>
Next, a railway vehicle according to the fourth embodiment of the present invention will be described. The railway vehicle according to the fourth embodiment is a railway vehicle including the power conversion device according to the third embodiment.
　図３４は、実施の形態４の鉄道車両の構成を示す図である。 FIG. 34 is a diagram illustrating a configuration of the railway vehicle according to the fourth embodiment.
　図３４に示すように、鉄道車両４０は、集電装置としてのパンタグラフ４１と、変圧器４２と、電力変換装置４３と、交流電動機である負荷４４と、車輪４５とを含む。電力変換装置４３は、コンバータ４６と、例えばコンデンサである容量４７と、インバータ４８とを有する。 As shown in FIG. 34, the railway vehicle 40 includes a pantograph 41 as a current collector, a transformer 42, a power converter 43, a load 44 that is an AC motor, and wheels 45. The power conversion device 43 includes a converter 46, a capacitor 47 that is a capacitor, for example, and an inverter 48.
　コンバータ４６は、スイッチ素子４９および５０を有する。スイッチ素子４９は、上アーム側、すなわち高電圧側に配置されており、スイッチ素子５０は、下アーム側、すなわち低電圧側に配置されている。なお、図３４では、スイッチ素子４９および５０については、複数相のうち一相について示している。 The converter 46 has switch elements 49 and 50. The switch element 49 is disposed on the upper arm side, that is, the high voltage side, and the switch element 50 is disposed on the lower arm side, that is, the low voltage side. In FIG. 34, the switch elements 49 and 50 are shown for one phase among a plurality of phases.
　インバータ４８は、スイッチ素子５１および５２を有する。スイッチ素子５１は、上アーム側、すなわち高電圧側に配置されており、スイッチ素子５２は、下アーム側、すなわち低電圧側に配置されている。なお、図３４では、スイッチ素子５１および５２については、Ｕ相、Ｖ相およびＷ相の三相のうち一相について示している。 The inverter 48 has switch elements 51 and 52. The switch element 51 is arranged on the upper arm side, that is, the high voltage side, and the switch element 52 is arranged on the lower arm side, that is, the low voltage side. In FIG. 34, the switch elements 51 and 52 are shown for one of the three phases U phase, V phase and W phase.
　変圧器４２の一次側の一端は、パンタグラフ４１を介して架線４１ａに接続されている。変圧器４２の一次側の他端は、車輪４５を介して線路４５ａに接続されている。変圧器４２の二次側の一端は、コンバータ４６の負荷４４と反対側であって上アーム側の端子に接続されている。変圧器４２の二次側の他端は、コンバータ４６の負荷４４と反対側であって下アーム側の端子に接続されている。 One end of the primary side of the transformer 42 is connected to the overhead line 41 a via the pantograph 41. The other end of the primary side of the transformer 42 is connected to the line 45 a via the wheel 45. One end of the secondary side of the transformer 42 is connected to a terminal on the upper arm side opposite to the load 44 of the converter 46. The other end of the secondary side of the transformer 42 is connected to a terminal on the lower arm side opposite to the load 44 of the converter 46.
　コンバータ４６の負荷４４側であって上アーム側の端子は、インバータ４８の負荷４４と反対側であって上アーム側の端子に接続されている。また、コンバータ４６の負荷４４側であって下アーム側の端子は、インバータ４８の負荷４４と反対側であって下アーム側の端子に接続されている。さらに、インバータ４８の負荷４４と反対側であって上アーム側の端子と、インバータ４８の負荷４４と反対側であって下アーム側の端子との間に、容量４７が接続されている。また、図３４では図示を省略するが、インバータ４８の出力側の３つの端子の各々は、Ｕ相、Ｖ相およびＷ相のそれぞれとして、負荷４４に接続されている。 The terminal on the load 44 side and the upper arm side of the converter 46 is connected to the terminal on the upper arm side opposite to the load 44 of the inverter 48. Further, the terminal on the load 44 side and the lower arm side of the converter 46 is connected to the terminal on the lower arm side opposite to the load 44 of the inverter 48. Further, a capacitor 47 is connected between a terminal on the side opposite to the load 44 of the inverter 48 on the upper arm side and a terminal on the side opposite to the load 44 of the inverter 48 and on the lower arm side. Although not shown in FIG. 34, each of the three terminals on the output side of the inverter 48 is connected to the load 44 as a U phase, a V phase, and a W phase.
　本実施の形態４では、インバータ４８として、実施の形態３の電力変換装置３１に含まれるインバータ３２（図３３参照）を用いることができる。すなわち本実施の形態４の鉄道車両４０は、電力変換装置として、実施の形態３におけるインバータ３２（図３３参照）を含む。 In this Embodiment 4, the inverter 32 (refer FIG. 33) contained in the power converter device 31 of Embodiment 3 can be used as the inverter 48. FIG. That is, railway vehicle 40 of the fourth embodiment includes inverter 32 (see FIG. 33) in the third embodiment as a power conversion device.
　架線４１ａからパンタグラフ４１により集電された交流電力は、その電圧が変圧器４２によって変圧された後、コンバータ４６により所望の直流電力に変換される。コンバータ４６により変換された直流電力は、その電圧が容量４７により平滑化される。容量４７により電圧が平滑化された直流電力は、インバータ４８により交流電力に変換される。インバータ４８により変換された交流電力は、負荷４４に供給される。交流電力が供給された負荷４４が車輪４５を回転駆動することで、鉄道車両が加速される。 The AC power collected from the overhead line 41 a by the pantograph 41 is transformed into desired DC power by the converter 46 after the voltage is transformed by the transformer 42. The DC power converted by the converter 46 is smoothed by the capacitor 47. The DC power whose voltage is smoothed by the capacitor 47 is converted into AC power by the inverter 48. The AC power converted by the inverter 48 is supplied to the load 44. The load 44 supplied with AC power rotates the wheel 45, thereby accelerating the railway vehicle.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態４の鉄道車両４０のインバータ４８として、実施の形態３の電力変換装置３１に含まれるインバータ３２（図３３参照）を用いることができる。インバータ３２に備えられたスイッチ素子３７ｕなどのスイッチ素子には、膜部２２ａ（図１参照）および膜部２２ｂ（図１参照）が形成されている。実施の形態１の半導体装置１によれば、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させ、帰還容量を小さくしつつ、ＪＦＥＴ領域１６の幅を広くすることができ、インバータにおける電力変換の際の損失を小さくすることができるので、大型の冷却装置が設けられなくてもよい。したがって、冷却装置を小型化することなどにより、インバータ３２を、容易に低コスト化、小型化または軽量化することができる。よって、このインバータ３２をインバータ４８として含む鉄道車両４０を、容易に低コスト化、小型化または軽量化することができる。 <Main features and effects of the present embodiment>
As the inverter 48 of the railway vehicle 40 of the fourth embodiment, the inverter 32 (see FIG. 33) included in the power conversion device 31 of the third embodiment can be used. In the switching element such as the switching element 37u provided in the inverter 32, a film part 22a (see FIG. 1) and a film part 22b (see FIG. 1) are formed. According to the semiconductor device 1 of the first embodiment, the strength of the electric field in the insulating film on the JFET region 16 is reduced, the reliability of the insulating film is improved, the feedback capacitance is reduced, and the width of the JFET region 16 is reduced. Since the loss at the time of power conversion in the inverter can be reduced, a large cooling device may not be provided. Therefore, the inverter 32 can be easily reduced in cost, size, or weight by reducing the size of the cooling device. Therefore, the railway vehicle 40 including the inverter 32 as the inverter 48 can be easily reduced in cost, size, or weight.
　なお、インバータ４８としてのインバータ３２（図３３参照）には、スイッチ素子３７ｕなどのスイッチ素子として、実施の形態１の半導体装置１に代え、実施の形態１の第１変形例の半導体装置１ａ、または、実施の形態２の半導体装置１ｂが備えられてもよい。この場合、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させる効果、および、帰還容量を小さくする効果がさらに増加するので、インバータ４８を、さらに容易に低コスト化、小型化または軽量化することができる。よって、このインバータ４８を含む鉄道車両４０を、さらに容易に低コスト化、小型化または軽量化することができる。 Note that, in the inverter 32 (see FIG. 33) as the inverter 48, as a switching element such as the switching element 37u, the semiconductor device 1a of the first modification of the first embodiment is used instead of the semiconductor device 1 of the first embodiment. Alternatively, the semiconductor device 1b of the second embodiment may be provided. In this case, the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased. In addition, the cost, size and weight can be reduced. Therefore, the railway vehicle 40 including the inverter 48 can be more easily reduced in cost, size, or weight.
　さらに、コンバータ４６において、スイッチ素子４９および５０として、実施の形態１の半導体装置１が備えられてもよい。そして、コンバータ４６に、実施の形態１の半導体装置１に代え、実施の形態１の第１変形例の半導体装置１ａ、または、実施の形態２の半導体装置１ｂが備えられてもよい。この場合にも、スイッチ素子４９および５０において、ＪＦＥＴ領域１６上の絶縁膜中の電界の強度を小さくして当該絶縁膜の信頼性を向上させる効果、および、帰還容量を小さくする効果がさらに増加するので、コンバータ４６を、さらに容易に低コスト化、小型化または軽量化することができる。よって、このコンバータ４６を含む鉄道車両４０を、さらに容易に低コスト化、小型化または軽量化することができる。 Furthermore, in the converter 46, the semiconductor device 1 of the first embodiment may be provided as the switch elements 49 and 50. Then, converter 46 may be provided with semiconductor device 1a of the first modification example of the first embodiment or semiconductor device 1b of the second embodiment instead of semiconductor device 1 of the first embodiment. Also in this case, in the switch elements 49 and 50, the effect of reducing the strength of the electric field in the insulating film on the JFET region 16 to improve the reliability of the insulating film and the effect of reducing the feedback capacitance are further increased. Therefore, the converter 46 can be further easily reduced in cost, size, or weight. Therefore, the railway vehicle 40 including the converter 46 can be more easily reduced in cost, size, or weight.
　なお、本実施の形態４では、実施の形態３の電力変換装置を、鉄道車両に適用した例について説明した。しかし、実施の形態３の電力変換装置は、電気自動車または太陽光発電装置など鉄道車両以外の各種の電気機器に適用可能である。例えば実施の形態３の電力変換装置を電気自動車に適用する場合には、電力変換装置を、容易に低コスト化、小型化または軽量化することができるので、この電力変換装置を含む電気自動車を、低コスト化、小型化または軽量化することができる。あるいは、この電力変換装置を含む電気自動車の室内を広くすることができるなど、電気自動車における設計の自由度を高めることができる。 In the fourth embodiment, the example in which the power conversion device of the third embodiment is applied to a railway vehicle has been described. However, the power conversion device according to the third embodiment can be applied to various electric devices other than railroad vehicles such as an electric vehicle or a solar power generation device. For example, when the power conversion device according to the third embodiment is applied to an electric vehicle, the power conversion device can be easily reduced in cost, size, or weight. Therefore, an electric vehicle including the power conversion device can be reduced. Cost reduction, size reduction or weight reduction can be achieved. Alternatively, it is possible to increase the degree of freedom of design in the electric vehicle, for example, the interior of the electric vehicle including the power conversion device can be widened.
　以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、半導体装置およびその製造方法、電力変換装置ならびに鉄道車両に適用して有効である。 The present invention is effective when applied to a semiconductor device, a manufacturing method thereof, a power conversion device, and a railway vehicle.
　１、１ａ、１ｂ　半導体装置
１０　ｎ＋型ＳｉＣ基板
１１　ドレイン電極
１２　ｎ－型エピタキシャル層
１３　ｐ型ボディ領域
１４　ｎ＋型ソース領域
１５　ｐ＋型ボディコンタクト領域
１６　ＪＦＥＴ領域
１７　チャネル領域
１８　ゲート絶縁膜
１８ａ～１８ｃ　部分
１９　ゲート電極
１９ａ　端部
１９ｂ　導電膜
２０　ソース電極
２０ａ　外周端
２１　層間絶縁膜
２１ａ、２１ｂ　ソースコンタクト孔
２２　保護絶縁膜
２２ａ、２２ｂ、２２ｇ　膜部
２２ｃ、２３ｃ　開口部
２２ｄ、２２ｅ　延在部
２２ｆ　交差部
２３　絶縁膜
２４　電界緩和領域
３１　電力変換装置
３２　インバータ
３３　負荷
３４　直流電源
３５　容量
３６ｕ、３６ｖ、３６ｗ、３６ｘ、３６ｙ、３６ｚ　ゲート駆動回路
３７ｕ、３７ｖ、３７ｗ、３７ｘ、３７ｙ、３７ｚ　スイッチ素子
３８　ＭＩＳＦＥＴ
３９　ボディダイオード
４０　鉄道車両
４１　パンタグラフ
４１ａ　架線
４２　変圧器
４３　電力変換装置
４４　負荷
４５　車輪
４５ａ　線路
４６　コンバータ
４７　容量
４８　インバータ
４９～５２　スイッチ素子
ＡＲ１、ＡＲ２、ＡＲ１１　領域
Ｎ１　ドレインノード
Ｎ２　ソースノード
Ｎ３～Ｎ５　出力ノード
ＰＳ１　経路
Ｒ１～Ｒ３　レジスト膜
ＴＨ１～ＴＨ３　厚さ
  1, 1a, 1b Semiconductor device 10 n + type SiC substrate 11 Drain electrode 12 n − type epitaxial layer 13 p type body region 14 n + type source region 15 p + type body contact region 16 JFET region 17 channel region 18 Gate insulating film 18a to 18c portion 19 gate electrode 19a end 19b conductive film 20 source electrode 20a outer peripheral end 21 interlayer insulating film 21a, 21b source contact hole 22 protective insulating films 22a, 22b, 22g film parts 22c, 23c openings 22d, 22e extending Portion 22f Intersection 23 Insulating film 24 Electric field relaxation region 31 Power converter 32 Inverter 33 Load 34 DC power supply 35 Capacitors 36u, 36v, 36w, 36x, 36y, 36z Gate drive circuits 37u, 37v, 37w, 37x, 37y, 37z switch Element 38 MISFET
39 Body diode 40 Railway vehicle 41 Pantograph 41a Overhead line 42 Transformer 43 Power converter 44 Load 45 Wheel 45a Line 46 Converter 47 Capacity 48 Inverter 49 to 52 Switch elements AR1, AR2, AR11 Region N1 Drain node N2 Source nodes N3 to N5 Output Node PS1 path R1 to R3 resist film TH1 to TH3 thickness

Claims (15)

  1. 　第１導電型の半導体基板と、
    　前記半導体基板の下面に形成されたドレイン電極と、
    　前記半導体基板の上面に形成された、前記第１導電型の半導体層と、
    　前記半導体層の上層部に形成され、前記第１導電型と異なる第２導電型の第１半導体領域と、
    　前記第１半導体領域の上層部に形成された、前記第１導電型の第２半導体領域と、
    　前記第１半導体領域の上層部に形成された、前記第２導電型の第３半導体領域と、
    　前記第１半導体領域を挟んで前記第２半導体領域と反対側の前記半導体層の上面上に形成された第１絶縁膜からなる第１膜部と、
    　前記第２半導体領域上に前記第１絶縁膜と同層に形成された第２絶縁膜からなる第２膜部と、
    　前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上に、ゲート絶縁膜を介して形成されたゲート電極と、
    　前記第２半導体領域上および前記第３半導体領域上に形成されたソース電極と、
    　を有し、
    　前記ゲート電極は、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第１膜部の上面上にかけて、連続的に形成されている、半導体装置。     A first conductivity type semiconductor substrate;
    A drain electrode formed on the lower surface of the semiconductor substrate;
    A semiconductor layer of the first conductivity type formed on an upper surface of the semiconductor substrate;
    A first semiconductor region of a second conductivity type different from the first conductivity type formed in an upper layer portion of the semiconductor layer;
    A second semiconductor region of the first conductivity type formed in an upper layer portion of the first semiconductor region;
    A third semiconductor region of the second conductivity type formed in an upper layer portion of the first semiconductor region;
    A first film portion made of a first insulating film formed on an upper surface of the semiconductor layer opposite to the second semiconductor region across the first semiconductor region;
    A second film portion made of a second insulating film formed in the same layer as the first insulating film on the second semiconductor region;
    A gate electrode formed on a top surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film;
    A source electrode formed on the second semiconductor region and the third semiconductor region;
    Have
    The semiconductor device, wherein the gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion.
  2. 　請求項１記載の半導体装置において、
    　前記ゲート電極は、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第２膜部の上面上にかけて、連続的に形成され、
    　前記ゲート電極は、前記第２膜部上で終端されている、半導体装置。     The semiconductor device according to claim 1,
    The gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the second film part,
    The semiconductor device, wherein the gate electrode is terminated on the second film part.
  3. 　請求項１記載の半導体装置において、
    　前記第１絶縁膜および前記第２絶縁膜の各々の誘電率は、前記ゲート絶縁膜の誘電率よりも小さい、半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device, wherein a dielectric constant of each of the first insulating film and the second insulating film is smaller than a dielectric constant of the gate insulating film.
  4. 　請求項１記載の半導体装置において、
    　前記半導体層の上層部に、平面視において、第１方向および前記第１方向と交差する第２方向にマトリクス状に配列するように形成された、４つの前記第１半導体領域と、
    　４つの前記第１半導体領域の各々の上層部にそれぞれ形成された、４つの前記第２半導体領域と、
    　４つの前記第１半導体領域の各々の上層部にそれぞれ形成された、４つの前記第３半導体領域と、
    　を有し、
    　前記第１絶縁膜は、平面視において、前記第１方向に延在する第１延在部と、前記第２方向に延在し、前記第１延在部と交差する第２延在部とを含み、十字状に形成され、
    　マトリクス状に配列された４つの前記第１半導体領域は、十字状の前記第１絶縁膜により区画され、
    　前記第２方向で隣り合う２つの前記第１半導体領域に挟まれた前記第１延在部上、および、前記第１方向で隣り合う２つの前記第１半導体領域に挟まれた前記第２延在部上には、前記ゲート電極が形成されているが、
    　前記第１延在部と前記第２延在部とが交差する交差部上には、前記ゲート電極は形成されていない、半導体装置。     The semiconductor device according to claim 1,
    Four first semiconductor regions formed on the upper layer portion of the semiconductor layer so as to be arranged in a matrix in a first direction and a second direction intersecting the first direction in plan view;
    Four second semiconductor regions formed on the upper layer of each of the four first semiconductor regions;
    Four third semiconductor regions respectively formed in an upper layer portion of each of the four first semiconductor regions;
    Have
    The first insulating film includes a first extension portion extending in the first direction and a second extension portion extending in the second direction and intersecting the first extension portion in plan view. Is formed in a cross shape,
    The four first semiconductor regions arranged in a matrix are partitioned by the cross-shaped first insulating film,
    On the first extension portion sandwiched between two first semiconductor regions adjacent in the second direction, and on the second extension sandwiched between two first semiconductor regions adjacent in the first direction. The gate electrode is formed on the existing portion,
    A semiconductor device, wherein the gate electrode is not formed on an intersecting portion where the first extending portion and the second extending portion intersect.
  5. 　請求項１記載の半導体装置において、
    　前記第１膜部は、前記第１半導体領域を挟んで前記第２半導体領域と反対側の前記半導体層の上面上に、第３絶縁膜を介して形成された前記第１絶縁膜からなり、
    　前記第２膜部は、前記第２半導体領域上に、前記第３絶縁膜と同層に形成された第４絶縁膜を介して形成された前記第２絶縁膜からなり、
    　前記第３絶縁膜の密度は、前記第１絶縁膜の密度よりも大きく、
    　前記第４絶縁膜の密度は、前記第２絶縁膜の密度よりも大きい、半導体装置。     The semiconductor device according to claim 1,
    The first film portion is composed of the first insulating film formed on the upper surface of the semiconductor layer opposite to the second semiconductor region with the first semiconductor region interposed therebetween via a third insulating film,
    The second film portion includes the second insulating film formed on the second semiconductor region via a fourth insulating film formed in the same layer as the third insulating film,
    The density of the third insulating film is greater than the density of the first insulating film,
    The density of the fourth insulating film is a semiconductor device greater than the density of the second insulating film.
  6. 　請求項５記載の半導体装置において、
    　前記半導体層は、前記半導体基板の前記上面側の第１領域、および、前記半導体基板の前記上面側で、かつ、前記第１領域よりも外周側の第２領域で、前記半導体基板の前記上面に形成され、
    　前記第１半導体領域は、前記第１領域で、前記半導体層の上層部に形成されており、
    　前記第１膜部は、前記第１領域で、前記第１半導体領域を挟んで前記第２半導体領域と反対側の前記半導体層の上面上に、前記第３絶縁膜を介して形成された前記第１絶縁膜からなり、
    　前記第２膜部は、前記第１領域で、前記第２半導体領域上に、前記第４絶縁膜を介して形成された前記第２絶縁膜からなり、
    　さらに、
    　前記第２領域で、前記半導体層の上層部に形成された前記第２導電型の第４半導体領域と、
    　前記第４半導体領域上に、前記第３絶縁膜と同層に形成された第５絶縁膜を介して、前記第１絶縁膜と同層に形成された第６絶縁膜からなる第３膜部と、
    　を有し、
    　前記第４半導体領域における前記第２導電型の不純物濃度は、前記第１半導体領域における前記第２導電型の不純物濃度よりも小さく、
    　前記ソース電極は、前記第４半導体領域と電気的に接続されている、半導体装置。     The semiconductor device according to claim 5.
    The semiconductor layer is a first region on the upper surface side of the semiconductor substrate, and a second region on the upper surface side of the semiconductor substrate and on the outer peripheral side of the first region, and the upper surface of the semiconductor substrate. Formed into
    The first semiconductor region is formed in an upper layer portion of the semiconductor layer in the first region,
    The first film portion is formed in the first region on the upper surface of the semiconductor layer opposite to the second semiconductor region with the first semiconductor region interposed therebetween via the third insulating film. A first insulating film;
    The second film portion includes the second insulating film formed on the second semiconductor region via the fourth insulating film in the first region,
    further,
    A second semiconductor region of the second conductivity type formed in an upper layer portion of the semiconductor layer in the second region;
    A third film portion formed of a sixth insulating film formed in the same layer as the first insulating film via a fifth insulating film formed in the same layer as the third insulating film on the fourth semiconductor region When,
    Have
    The impurity concentration of the second conductivity type in the fourth semiconductor region is smaller than the impurity concentration of the second conductivity type in the first semiconductor region,
    The semiconductor device, wherein the source electrode is electrically connected to the fourth semiconductor region.
  7. 　請求項１記載の半導体装置において、
    　前記ゲート電極は、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第１膜部の上面上にかけて、前記ゲート絶縁膜を介して連続的に形成されている、半導体装置。     The semiconductor device according to claim 1,
    The gate electrode is continuously formed through the gate insulating film from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion. A semiconductor device.
  8. 　請求項２記載の半導体装置において、
    　前記ゲート電極は、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第２膜部の上面上にかけて、前記ゲート絶縁膜を介して連続的に形成されている、半導体装置。     The semiconductor device according to claim 2,
    The gate electrode is continuously formed through the gate insulating film from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the second film portion. A semiconductor device.
  9. 　請求項１記載の半導体装置において、
    　前記第１導電型はｎ型であり、
    　前記第２導電型はｐ型である、半導体装置。     The semiconductor device according to claim 1,
    The first conductivity type is n-type;
    The semiconductor device, wherein the second conductivity type is p-type.
  10. 　請求項１記載の半導体装置において、
    　前記半導体基板、前記半導体層、前記第１半導体領域、前記第２半導体領域および前記第３半導体領域は、炭化ケイ素からなる、半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device, wherein the semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide.
  11. 　請求項１記載の半導体装置を備えた電力変換装置。 A power conversion device comprising the semiconductor device according to claim 1.
  12. 　請求項１１記載の電力変換装置を含む鉄道車両。 A railway vehicle including the power conversion device according to claim 11.
  13. 　（ａ）第１導電型の半導体基板の上面に、前記第１導電型の半導体層を形成する工程、
    　（ｂ）前記半導体層の上層部に、前記第１導電型と異なる第２導電型の第１半導体領域を形成する工程、
    　（ｃ）前記第１半導体領域の上層部に、前記第１導電型の第２半導体領域を形成する工程、
    　（ｄ）前記第１半導体領域の上層部に、前記第２導電型の第３半導体領域を形成する工程、
    　（ｅ）前記（ｃ）工程および前記（ｄ）工程の後、前記半導体層上に、第１絶縁膜を形成する工程、
    　（ｆ）前記第１絶縁膜をパターニングすることで、前記第１半導体領域を挟んで前記第２半導体領域と反対側の前記半導体層の上面上に、前記第１絶縁膜からなる第１膜部を形成し、前記第２半導体領域上に、前記第１絶縁膜からなる第２膜部を形成する工程、
    　（ｇ）前記（ｆ）工程の後、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上に、ゲート絶縁膜を介してゲート電極を形成する工程、
    　（ｈ）前記第２半導体領域上および前記第３半導体領域上にソース電極を形成する工程、
    　（ｉ）前記半導体基板の下面にドレイン電極を形成する工程、
    　を有し、
    　前記（ｇ）工程では、前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第１膜部の上面上にかけて、連続的に前記ゲート電極を形成する、半導体装置の製造方法。     (A) forming a first conductivity type semiconductor layer on an upper surface of a first conductivity type semiconductor substrate;
    (B) forming a first semiconductor region of a second conductivity type different from the first conductivity type in an upper layer portion of the semiconductor layer;
    (C) forming a second semiconductor region of the first conductivity type in an upper layer portion of the first semiconductor region;
    (D) forming a third semiconductor region of the second conductivity type in an upper layer portion of the first semiconductor region;
    (E) a step of forming a first insulating film on the semiconductor layer after the step (c) and the step (d);
    (F) A first film portion made of the first insulating film on the upper surface of the semiconductor layer opposite to the second semiconductor region with the first semiconductor region sandwiched by patterning the first insulating film. Forming a second film portion made of the first insulating film on the second semiconductor region,
    (G) After the step (f), forming a gate electrode on the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film;
    (H) forming a source electrode on the second semiconductor region and the third semiconductor region;
    (I) forming a drain electrode on the lower surface of the semiconductor substrate;
    Have
    In the step (g), the gate electrode is continuously formed from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the first film portion. A method for manufacturing a semiconductor device.
  14. 　請求項１３記載の半導体装置の製造方法において、
    　前記（ｇ）工程では、
    　前記第２半導体領域と前記半導体層とに挟まれた前記第１半導体領域の上面上から、前記第２膜部の上面上にかけて、連続的に前記ゲート電極を形成し、
    　前記ゲート電極が、前記第２膜部上で終端されるように、前記ゲート電極を形成する、半導体装置の製造方法。     14. The method of manufacturing a semiconductor device according to claim 13,
    In the step (g),
    Forming the gate electrode continuously from the upper surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer to the upper surface of the second film portion;
    A method of manufacturing a semiconductor device, wherein the gate electrode is formed so that the gate electrode is terminated on the second film portion.
  15. 　請求項１３記載の半導体装置の製造方法において、
    　前記第１導電型はｎ型であり、
    　前記第２導電型はｐ型である、半導体装置の製造方法。
          14. The method of manufacturing a semiconductor device according to claim 13,
    The first conductivity type is n-type;
    The method for manufacturing a semiconductor device, wherein the second conductivity type is a p-type.
PCT/JP2013/073836 2013-09-04 2013-09-04 Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle WO2015033406A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/073836 WO2015033406A1 (en) 2013-09-04 2013-09-04 Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/073836 WO2015033406A1 (en) 2013-09-04 2013-09-04 Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle

Publications (1)

Publication Number Publication Date
WO2015033406A1 true WO2015033406A1 (en) 2015-03-12

Family

ID=52627916

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/073836 WO2015033406A1 (en) 2013-09-04 2013-09-04 Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle

Country Status (1)

Country Link
WO (1) WO2015033406A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017042963A1 (en) * 2015-09-11 2017-03-16 株式会社日立製作所 Semiconductor device, method for manufacturing same, power module, power conversion device, and rail vehicle
JP2017112244A (en) * 2015-12-17 2017-06-22 株式会社日立製作所 Silicon carbide switching element, power module and electric power conversion device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247163A (en) * 1985-08-27 1987-02-28 Matsushita Electric Works Ltd Insulated gate field effect transistor
JPH08288303A (en) * 1995-04-11 1996-11-01 Sharp Corp Vertical field-effect transistor and fabrication thereof
JPH0936352A (en) * 1995-07-21 1997-02-07 Rohm Co Ltd Semiconductor device
JP2001111052A (en) * 1999-08-04 2001-04-20 Fuji Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2002016251A (en) * 2000-06-29 2002-01-18 Toshiba Corp Semiconductor device
JP2002261284A (en) * 2001-02-28 2002-09-13 Hitachi Ltd Semiconductor device
WO2011074237A1 (en) * 2009-12-16 2011-06-23 国立大学法人奈良先端科学技術大学院大学 Sic semiconductor element and manufacturing method for same
JP2011129547A (en) * 2009-12-15 2011-06-30 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247163A (en) * 1985-08-27 1987-02-28 Matsushita Electric Works Ltd Insulated gate field effect transistor
JPH08288303A (en) * 1995-04-11 1996-11-01 Sharp Corp Vertical field-effect transistor and fabrication thereof
JPH0936352A (en) * 1995-07-21 1997-02-07 Rohm Co Ltd Semiconductor device
JP2001111052A (en) * 1999-08-04 2001-04-20 Fuji Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2002016251A (en) * 2000-06-29 2002-01-18 Toshiba Corp Semiconductor device
JP2002261284A (en) * 2001-02-28 2002-09-13 Hitachi Ltd Semiconductor device
JP2011129547A (en) * 2009-12-15 2011-06-30 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
WO2011074237A1 (en) * 2009-12-16 2011-06-23 国立大学法人奈良先端科学技術大学院大学 Sic semiconductor element and manufacturing method for same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017042963A1 (en) * 2015-09-11 2017-03-16 株式会社日立製作所 Semiconductor device, method for manufacturing same, power module, power conversion device, and rail vehicle
JPWO2017042963A1 (en) * 2015-09-11 2018-04-05 株式会社日立製作所 Semiconductor device and method for manufacturing the same, power module, power conversion device, and railcar
JP2017112244A (en) * 2015-12-17 2017-06-22 株式会社日立製作所 Silicon carbide switching element, power module and electric power conversion device

Similar Documents

Publication Publication Date Title
JP6929404B2 (en) Silicon carbide semiconductor device and power conversion device
JP7041086B2 (en) Silicon carbide semiconductor device and power conversion device
US9312332B2 (en) Semiconductor device and method for manufacturing the same
JP7068916B2 (en) Silicon Carbide Semiconductor Device, Power Conversion Device, and Method for Manufacturing Silicon Carbide Semiconductor Device
WO2016104264A1 (en) Semiconductor device
JP6710589B2 (en) Semiconductor device, manufacturing method of semiconductor device, inverter circuit, drive device, vehicle, and elevator
JP6145165B2 (en) Semiconductor device
JPWO2018084020A1 (en) Silicon carbide semiconductor device and power converter
JP7175374B2 (en) power converter
WO2015128975A1 (en) Power module and power conversion device
JP2022016286A (en) Semiconductor device, inverter circuit, drive device, vehicle, and elevator
JP2005223349A (en) High breakdown voltage semiconductor device and electric power transducer using it
JP6564046B2 (en) Semiconductor device and manufacturing method thereof, power conversion device, three-phase motor system, automobile and railway vehicle
JP6592083B2 (en) Semiconductor device, manufacturing method thereof, and power module
WO2015189929A1 (en) Semiconductor device, power module, power conversion device, and semiconductor device manufacturing method
WO2016194116A1 (en) Semiconductor device, substrate and power conversion device
WO2015033406A1 (en) Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle
JP7258239B2 (en) SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER
JP7458257B2 (en) Semiconductor devices, inverter circuits, drive devices, vehicles, and elevators
JP7278902B2 (en) Semiconductor devices, inverter circuits, drive devices, vehicles, and elevators
JP6473512B2 (en) Semiconductor device and method for manufacturing the same, power module, power conversion device, and railcar
WO2016002083A1 (en) Semiconductor device, power module and electric power converter
WO2016038695A1 (en) Semiconductor device, power module, power conversion device, and railroad vehicle
JP7023818B2 (en) Semiconductor devices, inverter circuits, drives, vehicles, and elevators
JP7043750B2 (en) SiC- MOSFET

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13892975

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13892975

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP