WO2015128975A1

WO2015128975A1 - Power module and power conversion device

Info

Publication number: WO2015128975A1
Application number: PCT/JP2014/054757
Authority: WO
Inventors: 久本　大; 大西　正己
Original assignee: 株式会社日立製作所
Priority date: 2014-02-26
Filing date: 2014-02-26
Publication date: 2015-09-03

Abstract

　A power module has a chip group (3) comprising a plurality of semiconductor chips (6), and a chip group input terminal (8) into which a signal to be sent to the chip group (3) is inputted. The chip group input terminal (8) is provided at a position overlapping the chip group (3) in plan view. Each of the semiconductor chips (6) includes a switching element (13) including a gate electrode (15) formed on a semiconductor substrate (12), and an electrode terminal (11) formed on the semiconductor substrate (12) and electrically connected to the gate electrode (15). The electrode terminal (11) is disposed further toward the chip group input terminal (8) relative to the center of the semiconductor substrate (12) in plan view, and electrically connected to the chip group input terminal (8).

Description

Power module and power converter

The present invention relates to a power module and a power converter, and relates to a power module and a power converter provided with a switching element.

An inverter is used as a power conversion device that converts electric power for driving a motor or the like between direct current and alternating current. In a conventional inverter, an element pair consisting of an insulated gate bipolar transistor (IGBT) and a PIN (P-intrinsic-n) diode connected in antiparallel to each other includes an upper arm on the high voltage side, and For example, one pair is provided on each of the lower arms on the low voltage side. Each of the IGBT and the PIN diode is a switching element using silicon (Si). That is, an inverter as a power conversion device includes a power module including a switching element.

The loss at the time of power conversion in the inverter provided with the IGBT and the PIN diode using Si is reduced to a value close to the theoretical value determined from the physical property value of Si. Therefore, it is extremely difficult to further reduce the loss at the time of power conversion in the inverter provided with the switching element using Si.

On the other hand, the breakdown electric field of a so-called wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) is about an order of magnitude larger than that of silicon (Si). In particular, the withstand voltage of a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) as a switching element using SiC is in a wide voltage range of several hundred volts to several kV. Therefore, in the vertical MISFET using SiC, the region for relaxing the electric field in which the parasitic resistance is generated can be reduced as compared with the vertical MISFET as a switching element using Si. It is greatly reduced. Therefore, a large current can be passed through the vertical MISFET as a switching element.

International Publication No. 2010/073991 (Patent Document 1) describes a technique regarding a vertical MISFET using SiC. In such a vertical power MISFET, an n-type drain region, a p-type body region, and an n-type source region are provided between the drain electrode and the source electrode, and gate insulation is provided on the surface of the p-type body region. A gate electrode is provided through the film.

International Publication No. 2010/073991

Since silicon carbide (SiC) is a compound semiconductor, crystal defects are more easily introduced than silicon (Si). When crystal defects are introduced into a semiconductor substrate made of SiC, the switching element formed on the semiconductor substrate in the portion where the crystal defects are introduced varies in performance such as threshold voltage, or has a poor junction breakdown voltage. Manufacturing yield tends to decrease. Therefore, the probability that a crystal defect is introduced and a defect is caused by using a plurality of semiconductor chips each having a relatively small area and electrically connected in parallel to each other instead of one semiconductor chip having a large area. Therefore, the so-called manufacturing yield can be improved.

A large current can be allowed to flow through the power module by flowing a current in parallel to the switching elements provided in each of the plurality of semiconductor chips each having a relatively small area and connected in parallel to each other. .

However, it is difficult to adjust the impedance between the input terminal to which the gate signal sent to the semiconductor chip is input to the power module and the gate electrodes of the switching elements provided in the plurality of semiconductor chips to a desired value. . Therefore, the input waveform of the gate signal sent to the semiconductor chip is disturbed, and the switching element may malfunction or power loss may occur when switching by the switching element, which is disadvantageous for high-speed operation and miniaturization of the power conversion device. Become.

An object of the present invention is to adjust an impedance between an input terminal into which a gate signal sent to a semiconductor chip is input to a power module and gate electrodes of switching elements provided in a plurality of semiconductor chips to a desired value. It is to provide a power module capable of performing the above. An object of the present invention is to provide a power conversion device that includes the power module as described above and can be easily reduced in cost, size, or weight.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

A power module according to a representative embodiment includes a first substrate, a chip group including a plurality of semiconductor chips provided on the first substrate, a first input terminal to which a signal sent to the chip group is input, Is provided. The plurality of semiconductor chips are arranged at a distance from each other in plan view, and the first input terminal is provided at a position overlapping the chip group in plan view. Each of the plurality of semiconductor chips includes a semiconductor substrate, a switching element including a gate electrode formed on the semiconductor substrate, and an electrode terminal formed on the semiconductor substrate and electrically connected to the gate electrode. Have. The electrode terminal is disposed closer to the first input terminal than the center of the semiconductor substrate in plan view, and is electrically connected to the first input terminal.

A power module according to a representative embodiment includes a semiconductor substrate, a switching element including a gate electrode formed on the semiconductor substrate, and an electrode terminal formed on the semiconductor substrate and electrically connected to the gate electrode. And a resistance element formed on the semiconductor substrate. Further, the gate electrode and the electrode terminal are electrically connected via a resistance element.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

According to a typical embodiment, in a power module, an impedance between an input terminal to which a gate signal sent to the semiconductor chip is input to the power module and a gate electrode of a switching element provided in the semiconductor chip is desired. Can be adjusted.

FIG. 3 is a plan view of the power module according to the first embodiment. FIG. 3 is a cross-sectional view of the power module according to the first embodiment. 3 is a plan view of an upper substrate of the power module according to Embodiment 1. FIG. FIG. 3 is a plan view of a chip group in the power module according to the first embodiment. 4 is a plan view of a semiconductor chip in the power module according to the first embodiment. FIG. FIG. 3 is a main-portion cross-sectional view of the semiconductor chip in the power module according to the first embodiment. FIG. 6 is a plan view of another example of a semiconductor chip in the power module according to the first embodiment. 3 is a plan view of a switching element in the power module according to Embodiment 1. FIG. 3 is a plan view of a switching element in the power module according to Embodiment 1. FIG. FIG. 3 is a cross-sectional view of a main part of a switching element in the power module according to the first embodiment. FIG. 10 is a plan view of a first modification of the semiconductor chip in the power module according to the first embodiment. It is a top view of another example among the 1st modifications of the semiconductor chip in the power module of Embodiment 1. FIG. FIG. 11 is a plan view of a second modification of the semiconductor chip in the power module according to the first embodiment. It is a top view of the chip group in the power module of a comparative example. It is a figure which shows the structure of the power converter device of Embodiment 2. FIG. FIG. 6 is a diagram showing a configuration of an electric vehicle as an automobile according to a third embodiment. FIG. 6 is a circuit diagram illustrating an example of a boost converter in an automobile according to a third embodiment. FIG. 10 is a diagram showing a configuration of a railway vehicle according to a fourth embodiment.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Power module>
A power module according to Embodiment 1 of the present invention will be described.

FIG. 1 is a plan view of the power module according to the first embodiment. FIG. 2 is a cross-sectional view of the power module according to the first embodiment. FIG. 3 is a plan view of the upper substrate of the power module according to the first embodiment. FIG. 1 is a view of the power module as viewed from the upper surface side. FIG. 2 is a sectional view taken along line AA in FIG. FIG. 3 is a view of the upper substrate viewed from the lower surface side. In FIG. 1, for easy understanding, the upper substrate 4 (see FIG. 2) is removed and seen through.

As shown in FIGS. 1 to 3, the power module 1 according to the first embodiment includes a lower substrate 2, a plurality of chip groups 3, an upper substrate 4, and a module input terminal 5.

The plurality of chip groups 3 includes a plurality of semiconductor chips 6 provided on the lower substrate 2. The plurality of chip groups 3 are arranged at intervals from each other in plan view. A chip module 7 is formed by the plurality of chip groups 3. The module input terminal 5 is provided at a position overlapping the central portion of the chip module 7 in plan view.

Even if the module input terminal 5 is not provided at a position overlapping the central portion of the chip module 7 in a plan view, if the module input terminal 5 is provided at a position overlapping the chip module 7, the degree will be small, but will be described later. An effect of preventing or suppressing the disturbance of the input waveform of the gate signal can be obtained. Therefore, the module input terminal 5 does not have to be provided at a position overlapping the central portion of the chip module 7 in plan view, and may be provided only at a position overlapping the chip module 7.

Further, the power module 1 according to the first embodiment includes a plurality of chip group input terminals 8. The plurality of chip group input terminals 8 are provided corresponding to each of the plurality of chip groups 3. The chip group input terminal 8 is an input terminal to which a gate signal sent to the chip group 3 is input. The module input terminal 5 is an input terminal to which a signal sent to the plurality of chip group input terminals 8 is input. That is, the module input terminal 5 is an input terminal from which the gate signal sent to the chip group input terminal 8 provided corresponding to each of the plurality of chip groups 3 is input from the outside of the power module 1.

In the plan view, the term “viewed from a direction perpendicular to the upper surface of the lower substrate 2” means. Further, as shown in FIG. 1, two directions parallel to the upper surface of the lower substrate 2 and intersecting each other, preferably orthogonal, are defined as an X-axis direction and a Y-axis direction. At this time, in the plan view, it means a case when viewed from a direction perpendicular to both the X-axis direction and the Y-axis direction.

The lower substrate 2 is made of a conductor such as copper (Cu). Although not shown in FIG. 2, the lower substrate 2 is made of, for example, a drain electrode 31 of each of the plurality of semiconductor chips 6 included in the plurality of chip groups 3 by using a conductive bonding material such as solder or silver paste. 10).

The upper substrate 4 is provided on the chip module 7. That is, the upper substrate 4 is provided on the plurality of chip groups 3.

Moreover, the power module 1 of the first embodiment has a connection member 9. The connection member 9 is formed on the lower surface of the upper substrate 4. The connection member 9 electrically connects the plurality of chip group input terminals 8 and the module input terminals 5.

In the example shown in FIG. 3, each of the module input terminal 5, the chip group input terminal 8, and the connection member 9 is made of a conductive film formed in the same layer on the lower surface of the upper substrate 4. That is, the module input terminal 5, the chip group input terminal 8, and the connection member 9 are integrally formed on the lower surface of the upper substrate 4. Thereby, the plurality of chip group input terminals 8 and the module input terminals 5 are electrically connected via the connection member 9. Further, the module input terminal 5, the chip group input terminal 8 and the connection member 9 can be easily arranged on the chip module 7.

In addition, in this specification, being formed on the lower surface of a certain substrate includes being formed below the lower surface of the substrate.

The upper substrate 4 is provided on the chip module 7 so that the lower surface of the upper substrate 4, that is, the surface on which the connection member 9 is formed faces the upper surface of the lower substrate 2, that is, the surface on which the chip module 7 is mounted. ing. Specifically, with the chip group input terminal 8 formed on the upper substrate 4 and the electrode terminals 11 of the plurality of semiconductor chips 6 included in the chip group 3 facing each other, the lower substrate 2 is connected to the chip module 7. Crimped on top. Alternatively, the chip group input terminal 8 formed on the upper substrate 4 and the electrode terminals 11 of the plurality of semiconductor chips 6 included in the chip group 3 are bonded by sintering bonding or solder bonding. By such a method, the chip group input terminal 8 formed on the upper substrate 4 and the electrode terminals 11 of the plurality of semiconductor chips 6 included in the chip group 3 are electrically connected.

The electrode terminal 11 is electrically connected to the gate electrode 15 (see FIG. 4 described later).

Further, a connection member 10 may be formed on the lower surface of the upper substrate 4. The connection member 10 is electrically connected to each source electrode 36 of the plurality of semiconductor chips 6 included in the plurality of chip groups 3, and connects each source electrode 36 to the outside of the power module 1. It is. As described above, for example, the lower substrate 2 is pressure-bonded onto the chip module 7, whereby the connection member 10 formed on the upper substrate 4 and the source electrodes 36 of each of the plurality of semiconductor chips 6 included in the chip group 3. And are electrically connected.

Preferably, the power module 1 includes

chip groups

3 a, 3 b, 3 c and 3 d as the four chip groups 3. The

chip groups

3a, 3b, 3c and 3d are arranged in a matrix in the X-axis direction and the Y-axis direction, and the module input terminal 5 is provided at a position overlapping the central portion of the chip module 7 in plan view. It has been.

As a result, the connection resistance when connecting the module input terminal 5 and each chip group input terminal 8 of the plurality of chip groups 3 by the connecting member 9 can be reduced between the four

chip groups

3a, 3b, 3c and 3d. Can be adjusted to be close to each other. Accordingly, since the impedance between the module input terminal 5 and each chip group input terminal 8 of each of the plurality of chip groups 3 can be adjusted to be close to each other, each chip group input terminal of each of the plurality of chip groups 3 can be adjusted. It is possible to prevent or suppress the disturbance of the input waveform of the gate signal sent to 8.

At this time, the chip group 3a and the chip group 3b are arranged on opposite sides of the straight line LN1 extending in the Y-axis direction through the center CP1 of the module input terminal 5 in plan view. Further, the chip group 3a and the chip group 3c are arranged on the opposite sides of the straight line LN2 extending in the X-axis direction intersecting the Y-axis direction through the center CP1 of the module input terminal 5 in plan view. Is done. Furthermore, the chip group 3c and the chip group 3d are arranged on opposite sides of the straight line LN1 in plan view.

More preferably, the chip group 3a and the chip group 3b are arranged symmetrically with respect to a straight line LN1 extending in the Y-axis direction through the center CP1 of the module input terminal 5 in plan view. The chip group 3a and the chip group 3c are arranged symmetrically with respect to a straight line LN2 extending in the X-axis direction orthogonal to the Y-axis direction through the center CP1 of the module input terminal 5 in plan view. Is done. Further, the chip group 3c and the chip group 3d are arranged symmetrically with respect to the straight line LN1 in plan view.

chip groups

3a, 3b, 3c and 3d. Can be adjusted to be equal to each other. Therefore, since the impedance between the module input terminal 5 and each chip group input terminal 8 of the plurality of chip groups 3 can be adjusted to be equal to each other, each chip group input of the plurality of chip groups 3 can be adjusted. It can be easily prevented or suppressed that the input waveform of the gate signal sent to the terminal 8 is disturbed.

It is assumed that the chip module 7 is composed of a plurality of chip groups 3 other than four, such as two, three, five or more. Even in this case, preferably, any two of the plurality of chip groups 3 are arranged symmetrically with respect to the center CP1 of the module input terminal 5 in a plan view, or the module They are arranged symmetrically with respect to a straight line passing through the center CP1 of the input terminal 5.

Thereby, the connection resistance when connecting the module input terminal 5 and each chip group input terminal 8 of the plurality of chip groups 3 by the connecting member 9 is made equal between the two chip groups 3. Can be adjusted. Accordingly, since the impedance between the module input terminal 5 and each of these two chip groups 3 can be adjusted to be equal to each other, the signals are sent to the chip group input terminals 8 of each of the plurality of chip groups 3. It can be easily prevented or suppressed that the input waveform of the gate signal is disturbed.

<Chip group and semiconductor chip>
Next, a chip group and a semiconductor chip in the power module according to the first embodiment will be described.

FIG. 4 is a plan view of a chip group in the power module according to the first embodiment. FIG. 5 is a plan view of a semiconductor chip in the power module of the first embodiment. FIG. 6 is a cross-sectional view of main parts of the semiconductor chip in the power module according to the first embodiment. 6 is a cross-sectional view taken along the line BB in FIG. 4 shows a state in which the chip group input terminal 8 is removed and seen through, and the outer periphery of the chip group input terminal 8 is indicated by a two-dot chain line. In FIG. 6, for easy understanding, illustration of an n ⁻ type epitaxial layer 32 (see FIG. 10 described later) formed in the upper layer portion of the semiconductor substrate 12 is omitted.

As shown in FIG. 4, the chip group 3 includes a plurality of semiconductor chips 6. The plurality of semiconductor chips 6 are provided on the lower substrate 2 and are arranged at intervals from each other in plan view. The chip group input terminal 8 is an input terminal to which a gate signal sent to the chip group 3 is input. That is, the chip group input terminal 8 is an input terminal to which a gate signal sent to each electrode terminal 11 of the plurality of semiconductor chips 6 is input from the module input terminal 5, that is, from the outside of the chip group 3.

4 to 6, each of the plurality of semiconductor chips 6 included in the chip group 3 includes a semiconductor substrate 12, a switching element 13, and an electrode terminal 11. The switching element 13 has a gate electrode 15 formed on the semiconductor substrate 12.

The semiconductor substrate 12 has a gate pad region AR1 which is a partial region of the upper surface as the main surface of the semiconductor substrate 12, and a cell array region AR2 which is another region of the upper surface as the main surface of the semiconductor substrate 12.

Preferably, the semiconductor substrate 12 is made of silicon carbide (SiC). As described above, the breakdown electric field of a so-called wide band gap semiconductor such as silicon carbide (SiC) is about one digit larger than the breakdown electric field of silicon (Si). In particular, the withstand voltage of a vertical MISFET using SiC is in a wide voltage range from several hundred volts to several kV. Therefore, in the vertical MISFET using SiC, the on-resistance is significantly reduced as compared with the vertical MISFET using Si. Therefore, a large current can be passed through the switching element 13.

The plurality of semiconductor chips 6 are electrically connected in parallel with each other. By flowing a current in parallel to the switching elements 13 provided in each of the plurality of semiconductor chips 6 each having a relatively small area and connected in parallel to each other, a large current can be passed through the power module 1. A relatively large motor can be driven.

As described above, since silicon carbide (SiC) is a compound semiconductor, crystal defects are more easily introduced than silicon (Si). When crystal defects are introduced into the semiconductor substrate 12 made of SiC, the switching element 13 formed on the semiconductor substrate 12 in the portion where the crystal defects are introduced becomes poor because performance such as threshold voltage varies. Manufacturing yield tends to decrease. Therefore, instead of one semiconductor chip having a large area, by using a plurality of semiconductor chips 6 each having a relatively small area and electrically connected in parallel to each other, a crystal defect is introduced to cause a defect. Since the probability is reduced, so-called manufacturing yield can be improved.

In the gate pad region AR1, an underlying conductive film 17 is formed on the semiconductor substrate 12 via an insulating film 16 made of, for example, a silicon oxide film. The underlying conductive film 17 is made of, for example, a polycrystalline silicon (Si) film. An electrode terminal 11 that is electrically connected to the underlying conductive film 17 is formed on the underlying conductive film 17. The electrode terminal 11 is an electrode terminal for a gate electrode, that is, a gate pad. Therefore, in the gate pad region AR1, the electrode terminal 11 as a gate pad is formed.

In the cell array region AR2, a gate electrode 15 made of a conductive film 18 is formed on the semiconductor substrate 12 via an insulating film 16 made of, for example, a silicon oxide film. The conductive film 18 is a conductive film formed in the same layer as the underlying conductive film 17 and is made of, for example, a polycrystalline silicon (Si) film doped with impurities at a high concentration.

In the gate pad region AR1 and the cell array region AR2, an interlayer insulating film 19 is formed on the semiconductor substrate 12 so as to cover the underlying conductive film 17 and the conductive film 18. In the gate pad area AR1, an opening 20 is formed in the interlayer insulating film 19 so as to penetrate the interlayer insulating film 19 and reach the underlying conductive film 17. In the gate pad region AR 1, the electrode terminal 11 made of the conductive film 21 is formed on the interlayer insulating film 19 including the inside of the opening 20. The conductive film 21 is made of, for example, an aluminum (Al) film, and has an electrical resistivity smaller than that of any of the underlying conductive film 17 and the conductive film 18.

Since the electrode terminal 11 and the underlying conductive film 17 are electrically connected, and the underlying conductive film 17 and the gate electrode 15 are electrically connected, the electrode terminal 11 and the gate electrode 15 are electrically connected. Has been.

As the switching element 13, for example, a vertical MOSFET (MetalMetaOxide Semiconductor Field Effect Transistor) or IGBT as a vertical MISFET can be used. Among these, the structure of the switching element 13 made of a vertical MOSFET will be described later with reference to FIGS.

In the present specification, the term “MOSFET” includes not only a MISFET using an oxide film as a gate insulating film but also a MISFET using an insulating film other than an oxide film as a gate insulating film.

The chip group input terminal 8 is provided at a position overlapping the central portion of the chip group 3 in plan view. The upper substrate 4 (see FIG. 2) is provided on the chip group 3, and the chip group input terminal 8 is formed on the lower surface of the upper substrate 4. With such a configuration, the chip group input terminal 8 can be easily arranged on the chip group 3.

As described above, in the plan view, the term “when viewed from a direction perpendicular to the upper surface of the lower substrate 2” is used. Also, as shown in FIG. 4, two directions that are parallel to the upper surface of the lower substrate 2 and intersect each other, preferably orthogonal, are defined as an x-axis direction and a y-axis direction. At this time, in the plan view, it means a case when viewed from a direction perpendicular to both the x-axis direction and the y-axis direction. Note that the x-axis direction in FIG. 4 and the X-axis direction in FIG. 1 may be the same direction or different directions. Further, the y-axis direction in FIG. 4 and the Y-axis direction in FIG. 1 may be the same direction or different directions.

Even if the chip group input terminal 8 is not provided at a position overlapping the central portion of the chip group 3 in a plan view, if the chip group input terminal 8 is provided at a position overlapping the chip group 3, the degree will be small, but will be described later. The effect of preventing or suppressing the disturbance of the input waveform of the gate signal is obtained. Therefore, the chip group input terminal 8 may not be provided at a position overlapping the central portion of the chip group 3 in a plan view, and may be provided only at a position overlapping the chip group 3.

Preferably, the chip group 3 includes

semiconductor chips

6 a, 6 b, 6 c and 6 d as four semiconductor chips 6. The

semiconductor chips

6a, 6b, 6c, and 6d are arranged in a matrix in the x-axis direction and the y-axis direction, and the chip group input terminal 8 is located at a position that overlaps the central portion of the chip group 3 in plan view. Is provided.

Thereby, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted to be close to each other among the four

semiconductor chips

6a, 6b, 6c and 6d. Therefore, the impedance between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 can be adjusted so as to be close to each other. It is possible to prevent or suppress the disturbance of the input waveform of the gate signal.

At this time, the semiconductor chip 6a and the semiconductor chip 6b are arranged on opposite sides of the straight line LN3 extending in the y-axis direction through the center CP2 of the chip group input terminal 8 in plan view. Further, the semiconductor chip 6a and the semiconductor chip 6c are opposite to each other across a straight line LN4 extending in the x-axis direction intersecting the y-axis direction through the center CP2 of the chip group input terminal 8 in plan view. Be placed. Furthermore, the semiconductor chip 6c and the semiconductor chip 6d are disposed on opposite sides of the straight line LN3 in plan view.

Further, when the chip group 3 includes the

semiconductor chips

6 a, 6 b, 6 c, and 6 d as the four semiconductor chips 6, the power module 1 includes the semiconductor chips 6 that are multiples of four.

More preferably, the semiconductor chip 6a and the semiconductor chip 6b are arranged symmetrically with respect to a straight line LN3 extending in the y-axis direction through the center CP2 of the chip group input terminal 8 in plan view. Further, the semiconductor chip 6a and the semiconductor chip 6c are symmetrical with each other with respect to a straight line LN4 extending in the x-axis direction orthogonal to the y-axis direction through the center CP2 of the chip group input terminal 8 in plan view. Be placed. Furthermore, the semiconductor chip 6c and the semiconductor chip 6d are arranged symmetrically with respect to the straight line LN3 in plan view.

Thereby, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted to be equal to each other among the four

semiconductor chips

6a, 6b, 6c and 6d. Therefore, the impedance between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 can be adjusted to be equal to each other. It is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal to be sent.

As described above, since the chip group 3 includes the four semiconductor chips 6, the four semiconductor chips 6 can be arranged with good symmetry around the center CP2 of the chip group input terminal 8. Therefore, even when the number of chip groups 3 included in the power module 1 increases, the impedance between the module input terminal 5 and each chip group input terminal 8 of the plurality of chip groups 3 is adjusted so as to be close to each other. can do.

It is assumed that the chip group 3 is composed of a plurality of semiconductor chips 6 other than four, such as two, three, five or more. Even in this case, preferably, any two of the plurality of semiconductor chips 6 are arranged symmetrically with respect to the center CP2 of the chip group input terminal 8 in plan view, or They are arranged symmetrically with respect to a straight line passing through the center CP2 of the chip group input terminal 8.

Thereby, the connection resistance between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 can be adjusted to be equal to each other between the two semiconductor chips 6. Therefore, since the impedance between the chip group input terminal 8 and the electrode terminals 11 of the two semiconductor chips 6 can be adjusted to be equal to each other, each electrode terminal of the plurality of semiconductor chips 6 can be adjusted. It is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal sent to 11.

In the first embodiment, each electrode terminal 11 of the plurality of semiconductor chips 6 is arranged closer to the chip group input terminal 8 than the center of the semiconductor substrate 12 in plan view, and is electrically connected to the chip group input terminal 8. Connected.

Thereby, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted to be close to each other among the plurality of semiconductor chips 6. Therefore, the impedance between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 can be adjusted so as to be close to each other. It is possible to prevent or suppress the disturbance of the input waveform of the gate signal.

Preferably, the semiconductor substrate 12 has a quadrangular shape in plan view, and the electrode terminal 11 is formed at a corner CR1 closest to the chip group input terminal 8 among the four corners of the semiconductor substrate 12.

Thereby, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted to be equal among the plurality of semiconductor chips 6. That is, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 is equal among the plurality of semiconductor chips 6. Therefore, the impedance between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 can be adjusted to be equal to each other. It is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal to be sent.

Furthermore, the gate electrode 15 may have a shape that is line symmetric with respect to the diagonal line DG1 passing through the corner portion CR1 in plan view. At this time, when the underlying conductive film 17 is electrically connected to the two

portions

15a and 15b of the gate electrode 15 opposite to each other with respect to the diagonal line DG1 by the same structure, The connection resistance between each of the two

portions

15a and 15b and the electrode terminal 11 can be adjusted to be equal to each other.

Note that “closest to the chip group input terminal 8” means, for example, closest to the center position of the chip group input terminal 8, and “farthest from the chip group input terminal 8” means, for example, that of the chip group input terminal 8. Means farthest from the center position.

On the other hand, consider a case where the semiconductor substrate 12 does not have a quadrangular shape in plan view. In this case, the electrode terminal 11 is formed on the peripheral edge EP1 of the semiconductor substrate 12 that is closest to the chip group input terminal 8. Thereby, the connection resistance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted so as to be close to each other among the plurality of semiconductor chips 6.

Further, the gate electrode 15 is symmetrical with respect to a straight line LN5 that connects the peripheral edge EP1 closest to the chip group input terminal 8 and the peripheral edge EP2 farthest from the chip group input terminal 8 of the semiconductor substrate 12 in plan view. It may have various shapes. At this time, when the underlying conductive film 17 is electrically connected to both of the two

portions

15a and 15b located on the opposite sides of the straight line LN5 in the gate electrode 15 by the same structure, The connection resistance between each of the two

portions

Preferably, the semiconductor chip 6 has a resistance element 22 formed on the semiconductor substrate 12. That is, the semiconductor chip 6 incorporates the resistance element 22. Further, the gate electrode 15 of the switching element 13 and the electrode terminal 11 are electrically connected via a resistance element 22.

The gate electrode 15 is made of a conductive film 18 such as a polycrystalline silicon (Si) film formed on the semiconductor substrate 12. The resistance element 22 includes a conductive film 23 such as a polycrystalline silicon (Si) film formed on the semiconductor substrate 12 in the same layer as the conductive film 18. That is, the resistance element 22 is made of a conductive film 23 such as a polycrystalline silicon (Si) film formed in the same layer as the underlying conductive film 17 and the conductive film 18. By forming the conductive film 23 included in the resistance element 22 in the same layer as the conductive film 18 included in the gate electrode 15, the number of manufacturing steps can be reduced, and the stability of the manufacturing steps can be improved. .

On the other hand, the electrode terminal 11 is made of a conductive film 21 having an electrical resistivity smaller than any of the electrical resistance of the underlying conductive film 17, the conductive film 23, and the conductive film 18, such as aluminum (Al).

When the semiconductor chip 6 has the resistance element 22, the underlying conductive film 17 and the gate electrode 15 are electrically connected via the resistance element 22, so that the electrode terminal 11 and the gate electrode 15 are connected to the underlying conductive film 17 and Electrical connection is made via the resistance element 22.

Therefore, since the variable range of the resistance value of the resistance element 22 is larger than the variable range of the resistance value of the electrode terminal 11, the gate electrode 15, the chip group input terminal 8, The connection resistance between the plurality of semiconductor chips 6 can be easily adjusted so as to be close to each other. Therefore, it is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal sent to each gate electrode 15 of the plurality of semiconductor chips 6.

Preferably, the semiconductor chip 6 has a plurality of resistance elements 22 formed on the semiconductor substrate 12 and connected in parallel to each other. The gate electrode 15 of the switching element 13 and the electrode terminal 11 are electrically connected via a plurality of resistance elements 22 connected in parallel to each other. In this case, the resistance element is divided into a plurality of resistance elements 22 connected in parallel to each other.

With such a configuration, it is possible to reduce the parasitic inductance as compared with the case where the semiconductor chip 6 has one resistance element 22 formed integrally.

For example, the sum of the resistance value of the gate electrode 15 and the combined resistance value of the plurality of resistance elements 22 is taken as the built-in resistance, and the resistance value of the desired built-in resistance is set to 10 to 70Ω. The resistance value of the gate electrode 15 made of polycrystalline silicon (Si) is 20Ω. At this time, by providing one or a plurality of resistance elements 22 such that the resistance value of one resistance element 22 is several Ω, the resistance value of the built-in resistor can be easily adjusted to a desired resistance value.

Note that the power module 1 according to the first embodiment may have only one semiconductor chip 6. In such a case, the semiconductor chip 6 incorporates the resistance element 22, the gate electrode 15 and the electrode terminal 11 are electrically connected via the resistance element 22, and the resistance value of the resistance element 22 is adjusted, whereby the gate The connection resistance between the electrode 15 and the electrode terminal 11 can be adjusted to a desired value. Therefore, it is possible to prevent or suppress the disturbance of the input waveform of the gate signal sent to the electrode terminal 11 of the semiconductor chip 6.

Further, each of the plurality of semiconductor chips 6 may not have a resistance element. An example of the semiconductor chip 6 not having such a resistance element is shown in FIG. FIG. 7 is a plan view of another example of the semiconductor chip in the power module according to the first embodiment.

In the example shown in FIG. 7, since the underlying conductive film 17 and the gate electrode 15 are directly electrically connected, the electrode terminal 11 and the gate electrode 15 are electrically connected only through the underlying conductive film 17. ing.

In the example shown in FIG. 7, for example, an external resistance element is provided between the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 and outside each semiconductor chip 6. May be provided. At this time, the chip group input terminal 8 and each electrode terminal 11 of the plurality of semiconductor chips 6 are electrically connected by respective external resistance elements. In such a case, the connection resistance between the gate electrode 15 and the electrode terminal 11 can be adjusted to a desired value by adjusting the resistance value of the external resistance element.

<Switching element>
Next, the switching element in the power module according to the first embodiment will be described. As described above, the switching element in the power module of the first embodiment is a vertical MOSFET as a vertical MISFET made of silicon carbide (SiC).

In the first embodiment, an example in which a vertical MOSFET is used as a switching element in a power module will be described. However, an IGBT can be used as a switching element in the power module instead of the vertical MOSFET.

8 and 9 are plan views of the switching element in the power module according to the first embodiment. FIG. 10 is a main-portion cross-sectional view of the switching element in the power module according to the first embodiment. 8 and 9 are views of the switching element 13 viewed from the upper surface side, FIG. 8 is an enlarged view of a part of the switching element 13 shown in FIG. 5, and FIG. It is a figure which expands and shows a part of switching element 13 to show. 10 is a cross-sectional view taken along the line CC of FIG.

In FIG. 8, for easy understanding, the source electrode 36 and the interlayer insulating film 19 (see FIG. 10) are removed, that is, seen through, and the source formed in the interlayer insulating film 19 is illustrated. The outer periphery of the contact hole 19a is indicated by a two-dot chain line. 9 shows a state in which the source electrode 36, the interlayer insulating film 19, the insulating film 16 (see FIG. 10) and the gate electrode 15 are removed, that is, seen through, for easy understanding. The outer periphery of the source contact hole 19a formed in the insulating film 19 and the outer periphery of the gate electrode 15 are indicated by a two-dot chain line.

As shown in FIGS. 8 to 10, the switching element 13 in the power module according to the first embodiment is a vertical MOSFET, and includes a semiconductor substrate 12, a drain electrode 31, an n ⁻ -type epitaxial layer 32, and a p-type body region 33. , N ⁺ -type source region 34 and p ⁺ -type body contact region 35. The switching element 13 according to the first embodiment includes an insulating film 16 as a gate insulating film, a gate electrode 15, a source electrode 36, and an interlayer insulating film 19.

The semiconductor substrate 12 is an n-type semiconductor substrate made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. That is, the conductivity type of the semiconductor substrate 12 is n-type. The n-type impurity concentration in the semiconductor substrate 12 is relatively large, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The thickness of the semiconductor substrate 12 is, for example, about 70 to 700 μm.

The drain electrode 31 is an electrode formed on the lower surface of the semiconductor substrate 12. The drain electrode 31 is electrically connected to the semiconductor substrate 12. As the drain electrode 31, for example, a conductive film in which titanium (Ti), nickel (Ni), gold (Au), or the like is stacked can be used. By using such a conductive film, the drain electrode 31 and the semiconductor substrate 12 can be electrically connected with low resistance.

The n ⁻ type epitaxial layer 32 is formed on the upper surface of the semiconductor substrate 12 and is an n type semiconductor layer made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced. . That is, the conductivity type of the n ⁻ type epitaxial layer 32 as the semiconductor layer is n type. The n ^- type impurity concentration in the n ⁻ -type epitaxial layer 32 is smaller than the n-type impurity concentration in the semiconductor substrate 12, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . Further, the thickness of the n ⁻ type epitaxial layer 32 is, for example, about 5 to 70 μm. Since this layer functions as an electric field relaxation layer, the impurity concentration and thickness may be designed so that the breakdown voltage is not reached by the voltage using the switching element. Since SiC has a breakdown electric field about one digit larger than Si, the film thickness can be reduced. Therefore, the resistance of this layer can be reduced, and the on-resistance of the switching element can be greatly reduced.

The n ⁻ type epitaxial layer 32 can be formed by, for example, an epitaxial growth method. Alternatively, for example, a p-type impurity such as aluminum (Al) or boron (B) is implanted into the entire upper surface of the semiconductor substrate 12 by ion implantation, and the n ⁻ -type impurity concentration in the semiconductor substrate 12 is reduced by a method of reducing the n-type impurity concentration. The epitaxial layer 32 can also be formed.

In addition, in this specification, being formed on the upper surface of a certain substrate includes being formed above the upper surface of the substrate.

The p-type body region 33 is formed in the upper layer portion of the n ⁻ -type epitaxial layer 32, and is a p-type semiconductor made of silicon carbide (SiC) in which a p-type impurity such as aluminum (Al) or boron (B) is diffused. It is an area. That is, the conductivity type of the p-type body region 33 as a semiconductor region is p-type. The p-type impurity concentration in the p-type body region 33 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the p-type body region 33 is, for example, about 1 to 2 μm.

The n ⁺ -type source region 34 is formed in the upper layer portion of the p-type body region 33 and is an n-type semiconductor made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. It is an area. That is, the conductivity type of the n ⁺ type source region 34 as a semiconductor region is n type. The n-type impurity concentration in the n ⁺ -type source region 34 is higher than the n-type impurity concentration in the n ⁻ -type epitaxial layer 32, and can be, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . Further, the thickness of the n ⁺ -type source region 34 can be set to about 100 to 700 nm, for example.

The p ⁺ -type body contact region 35 is formed in the upper layer portion of the p-type body region 33 and is, for example, p-type made of silicon carbide (SiC) in which a p-type impurity such as aluminum (Al) or boron (B) is diffused. It is a semiconductor region. That is, the conductivity type of the p ⁺ type body contact region 35 as the semiconductor region is p-type. The p-type impurity concentration in the p ⁺ -type body contact region 35 is higher than the p-type impurity concentration in the p-type body region 33, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . Further, the thickness of the p ⁺ type body contact region 35 is, for example, about 100 to 700 nm.

An upper layer portion of the n ⁻ -type epitaxial layer 32 sandwiched between two adjacent p-type body regions 33 is a JFET (Junction Field Effect Transistor) region 37. That is, the upper layer portion of the n ⁻ -type epitaxial layer 32 opposite to the n ⁺ -type source region 34 across the p-type body region 33 is a JFET region 37. Further, the upper layer portion of the p-type body region 33 sandwiched between the n ⁺ -type source region 34 and the JFET region 37, that is, the p-type body region 33 sandwiched between the n ⁺ -type source region 34 and the n ⁻ -type epitaxial layer 32. The upper layer portion is a channel region 38.

The insulating film 16 as a gate insulating film is an insulating film formed on the upper surface of the p-type body region 33 sandwiched between the n ⁺ -type source region 34 and the n ⁻ -type epitaxial layer 32. The insulating film 16 is made of, for example, silicon oxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or the like. For example, the thermal oxidation method or CVD (Chemical Vapor Deposition) is used. It is formed by law. Further, the thickness of the insulating film 16 is, for example, about several tens of nm.

The gate electrode 15 is an electrode formed on the insulating film 16 as a gate insulating film. That is, the gate electrode 15 is an electrode formed on the upper surface of the p-type body region 33 sandwiched between the n ⁺ -type source region 34 and the n ⁻ -type epitaxial layer 32 via the insulating film 16. As described above, the gate electrode 15 is made of the conductive film 18 (see FIG. 10) such as a polycrystalline silicon (Si) film formed by, for example, the CVD method.

Note that an insulating film 16 as a gate insulating film is formed on the JFET region 37, and a gate electrode 15 is formed on the insulating film 16 formed on the JFET region 37.

The source electrode 36 is an electrode formed on the n ⁺ type source region 34 and the p ⁺ type body contact region 35. As the source electrode 36, for example, a conductive film made of titanium (Ti) or aluminum (Al) can be used. By using such a conductive film, the source electrode 36 can be electrically connected to the n ⁺ type source region 34 and the p ⁺ type body contact region 35 with low resistance.

The interlayer insulating film 19 is formed on the semiconductor substrate 12 including the surface of the gate electrode 15. As a material of the interlayer insulating film 19, for example, PSG (Phospho または Silicate Glass) or silicon oxide can be used.

A source contact hole 19a as an opening is formed in the interlayer insulating film 19. Source contact hole 19 a penetrates interlayer insulating film 19 and reaches the upper surface of n ⁺ -type source region 34 and the upper surface of p ⁺ -type body contact region 35. That is, the upper surface of the n ⁺ -type source region 34 and the upper surface of the p ⁺ -type body contact region 35 are exposed at the bottom surface of the source contact hole 19a.

The source electrode 36 is formed on the interlayer insulating film 19 including the bottom and side surfaces of the source contact hole 19a. With such a structure, the source electrode 36 is electrically connected to the n ⁺ type source region 34 and the p ⁺ type body contact region 35 via the source contact hole 19 a formed in the interlayer insulating film 19. ing.

As shown in FIG. 8 and FIG. 9, two directions that are parallel to the upper surface of the semiconductor substrate 12 and intersect each other, preferably orthogonal, are defined as an x1 axis direction and a y1 axis direction. At this time, in the plan view, it means a case when viewed from a direction perpendicular to both the x1 axis direction and the y1 axis direction. 8 and 9, the x-axis direction in FIG. 4, and the X-axis direction in FIG. 1 may be the same direction or different directions. 8 and 9, the y-axis direction in FIG. 4, and the Y-axis direction in FIG. 1 may be the same direction or different directions.

As shown in FIGS. 8 and 9, switching element 13 has a plurality of p-type body regions 33, a plurality of n ⁺ -type source regions 34, and a plurality of p ⁺ -type body contact regions 35. The plurality of p-type body regions 33 are formed in the upper layer portion of the n ⁻ -type epitaxial layer 32 so as to be arranged in a matrix in the x1 axis direction and the y1 axis direction in plan view. The plurality of n ⁺ -type source regions 34 are formed in the upper layer portion of each of the plurality of p-type body regions 33. The plurality of p ⁺ type body contact regions 35 are respectively formed in the upper layer portions of the plurality of p type body regions 33.

At this time, the gate electrode 15 extends in the y1 axis direction and extends in the x1 axis direction in the plan view, and extends in the x1 axis direction. Each of the extending portions 15d intersects with the existing portions 15c and is arranged in the y1-axis direction, and is formed in a lattice shape. The plurality of p-type body regions 33 arranged in a matrix are partitioned by a lattice-shaped gate electrode 15. Here, each of the plurality of regions AR3 partitioned by the grid-like gate electrode 15 is referred to as a cell.

In the on operation of turning on the vertical MOSFET as the switching element 13 included in the power module 1 of the first embodiment, the gate electrode 15 has a positive gate voltage VGS (VGS> 0 V with respect to the source electrode 36). ) Is applied. At this time, an inversion layer is formed in the upper layer portion of the p-type body region 33 sandwiched between the n ⁺ -type source region 34 and the n ⁻ -type epitaxial layer 32, that is, the channel region 38.

Therefore, electrons flow from the source electrode 36 to the drain electrode 31 through the n ⁺ -type source region 34, the inversion layer formed in the channel region 38, the n ⁻ -type epitaxial layer 32, and the semiconductor substrate 12. That is, current flows from the drain electrode 31 to the source electrode 36 through the semiconductor substrate 12, the n ⁻ type epitaxial layer 32, the inversion layer formed in the channel region 38, and the n ⁺ type source region 34.

On the other hand, in the off operation for turning off the vertical MOSFET, a negative or zero gate voltage VGS (VGS ≦ 0 V) is applied to the gate electrode 15 with respect to the source electrode 36. At this time, the current is interrupted by eliminating the inversion layer formed in the channel region 38.

<First Modification of Semiconductor Chip>
Next, a first modification of the semiconductor chip will be described. FIG. 11 is a plan view of a first modification of the semiconductor chip in the power module according to the first embodiment. FIG. 12 is a plan view of still another example of the first modification of the semiconductor chip in the power module according to the first embodiment.

As shown in FIG. 11 and FIG. 12, the semiconductor chip 6 of the first modification has a wiring 39.

Consider a case where the semiconductor substrate 12 has a quadrangular shape in plan view, and the electrode terminal 11 is formed on the corner CR1 closest to the chip group input terminal 8 among the four corners of the semiconductor substrate 12. At this time, the wiring 39 electrically connects two

portions

15a and 15b located on opposite sides of the gate electrode 15 with the diagonal line DG1 interposed therebetween.

Thus, as shown in FIGS. 11 and 12, even when the underlying conductive film 17 is electrically connected to only one of the two

portions

15a and 15b of the gate electrode 15, these two portions 15a. And the connection resistance between each of 15b and the electrode terminal 11 can be adjusted to be close to each other. Accordingly, since the connection resistance between the electrode terminal 11 and the gate electrode 15 can be adjusted so as to be close to each other between the plurality of semiconductor chips 6, the connection resistance is sent to each gate electrode 15 of the plurality of semiconductor chips 6. It is possible to prevent or suppress the disturbance of the input waveform of the gate signal.

The wiring 39 is made of a conductive film 40. The conductive film 40 is made of, for example, an aluminum (Al) film, and preferably has an electrical resistivity smaller than that of the conductive film 18 included in the gate electrode 15. Further, the wiring 39 is electrically connected to each of the two

portions

15a and 15b of the gate electrode 15 through a plug 39a formed so as to overlap the wiring 39 in plan view. On the other hand, the electrode terminal 11 is electrically connected to the underlying conductive film 17 through the plug 39b.

In addition, when the gate electrode 15 has a shape symmetrical with respect to the diagonal line DG1 passing through the corner portion CR1 in plan view, the wiring 39 is preferably connected to the diagonal line DG1 passing through the corner portion CR1 in plan view. And have a line-symmetric shape.

portions

15a and 15b of the gate electrode 15, these two portions 15a. And the connection resistance between each of 15b and the electrode terminal 11 can be easily adjusted so as to be close to each other. Accordingly, the connection resistance between the electrode terminal 11 and the gate electrode 15 can be easily adjusted so as to be close to each other between the plurality of semiconductor chips 6. It is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal to be sent.

On the other hand, a case is considered in which the semiconductor substrate 12 does not have a quadrangular shape in plan view, and the electrode terminal 11 is formed on the peripheral edge EP1 closest to the chip group input terminal 8 in the semiconductor substrate 12. A straight line connecting the peripheral edge EP1 closest to the chip group input terminal 8 and the peripheral edge EP2 farthest from the chip group input terminal 8 in the semiconductor substrate 12 is defined as a straight line LN5. At this time, the wiring 39 electrically connects the two

portions

15a and 15b located on the opposite sides of the gate electrode 15 across the straight line LN5.

In the example shown in FIG. 11, the wiring 39 is formed on a portion 15 e of the gate electrode 15 positioned around the electrode terminal 11 in a plan view. In the example shown in FIG. 12, the wiring 39 is on the portion 15 f of the gate electrode 15 located on the opposite side to the electrode terminal 11 side in plan view, that is, the outer periphery of the semiconductor substrate 12 in the gate electrode 15. Is formed on a portion 15f along the line.

<Second Modification of Semiconductor Chip>
Next, a second modification of the semiconductor chip will be described. FIG. 13 is a plan view of a second modification of the semiconductor chip in the power module according to the first embodiment. In FIG. 13, for easy understanding, the electrode terminal 11 is removed and seen through, and the outer periphery of the electrode terminal 11 is indicated by a two-dot chain line.

As shown in FIG. 13, in the semiconductor chip of the second modified example, the resistance element 22 is formed at a position overlapping the electrode terminal 11 in plan view.

By forming the resistive element 22 at a position overlapping the electrode terminal 11 in plan view, for example, the length of the resistive element 22 extending in a certain direction can be increased, and the resistance value of the resistive element 22 is increased. be able to. Therefore, the variable range of the resistance element 22 can be further increased. Note that the semiconductor chip 6 of the second modified example may include a plurality of resistance elements 22 connected in parallel as the resistance elements 22.

Moreover, the area of the electrode terminal 11 can be increased by forming the resistance element 22 so as to overlap the electrode terminal 11 in plan view. Therefore, the resistance value of the electrode terminal 11 can be reduced.

Note that the semiconductor chip 6 of the second modified example may also have the wiring 39 as in the semiconductor chip 6 of the first modified example. In the second modified example as well, as in the first modified example, the semiconductor substrate 12 has a quadrangular shape in plan view, and the electrode terminal 11 is the closest to the chip group input terminal 8 among the four corners of the semiconductor substrate 12. When formed on the near corner CR1, the wiring 39 electrically connects two

portions

Thus, as shown in FIG. 13, even when the underlying conductive film 17 is electrically connected to only one of the two

portions

15a and 15b of the gate electrode 15, the two

portions

15a and 15b The connection resistance between each and the electrode terminal 11 can be adjusted to be close to each other. Accordingly, since the connection resistance between the electrode terminal 11 and the gate electrode 15 can be adjusted so as to be close to each other between the plurality of semiconductor chips 6, the connection resistance is sent to each gate electrode 15 of the plurality of semiconductor chips 6. It is possible to prevent or suppress the disturbance of the input waveform of the gate signal.

Note that the electrical resistivity of the conductive film 40 included in the wiring 39 is preferably smaller than the electrical resistivity of the conductive film 18 included in the gate electrode 15. Further, the wiring 39 is electrically connected to each of the two

portions

15a and 15b of the gate electrode 15, the two

portions

15a and 15b The connection resistance between each and the electrode terminal 11 can be easily adjusted to be close to each other. Accordingly, the connection resistance between the electrode terminal 11 and the gate electrode 15 can be easily adjusted so as to be close to each other between the plurality of semiconductor chips 6. It is possible to easily prevent or suppress the disturbance of the input waveform of the gate signal to be sent.

<Impedance between module input terminal and gate electrode>
Next, the impedance between the module input terminal and the gate electrode will be described in comparison with the chip group in the power module of the comparative example. FIG. 14 is a plan view of a chip group in the power module of the comparative example.

As shown in FIG. 14, in the power module 101 of the comparative example, the chip group 103 has a plurality of semiconductor chips 106 and a chip group input terminal 108. The chip group input terminal 108 is an input terminal through which a gate signal sent to each electrode terminal 111 of the plurality of semiconductor chips 106 is input from the module input terminal 105.

As shown in FIG. 14, each of the plurality of semiconductor chips 106 included in the chip group 103 includes a semiconductor substrate 112, a switching element 113, and an electrode terminal 111. The switching element 113 includes a gate electrode 115 formed on the semiconductor substrate 112.

The semiconductor substrate 112 has a gate pad region AR101 that is a partial region of the upper surface as the main surface of the semiconductor substrate 112, and a cell array region AR102 that is another region of the upper surface as the main surface of the semiconductor substrate 112. An electrode terminal 111 is formed in the gate pad region AR101. A gate electrode 115 is formed in the cell array region AR102.

Also in the comparative example, as in the first embodiment, the semiconductor substrate 112 is made of silicon carbide (SiC) in order to flow a large current with a high voltage applied to both ends of the switching element 113. In order to improve the manufacturing yield of the manufactured semiconductor chip 106, a plurality of semiconductor chips 106 having a relatively small area are connected in parallel, and a current is supplied in parallel to the switching element 113 provided in each semiconductor chip 106. Shed. As a result, a large current can flow through the power module 101.

However, the impedance between the module input terminal 105 to which the gate signal sent to the semiconductor chip 106 is input to the power module 101 and the gate electrode 115 of the switching element 113 provided in the semiconductor chip 106 is adjusted to a desired value. It is difficult. For this reason, the input waveform of the gate signal sent to the semiconductor chip 106 is disturbed, and the switching element 113 may malfunction or power loss may occur during switching by the switching element 113, so that the power converter can be operated at high speed or downsized. Disadvantageous.

In the comparative example, the plurality of semiconductor chips 106 are arranged in the x-axis direction, and the chip group input terminal 108 is provided at a position away from the chip group 103. Therefore, the chip group input terminal 108 is not provided at a position overlapping the chip group 103 in plan view. Alternatively, in the comparative example, the electrode terminal 111 is formed on the peripheral portion of the semiconductor substrate 112, but is not formed on the peripheral portion of the semiconductor substrate 112 on the chip group input terminal 108 side.

Further, in the comparative example, as shown in FIG. 14, the impedance R101 between the chip group input terminal 108 and each electrode terminal 111 of the plurality of semiconductor chips 106 is different. Therefore, the input waveform of the gate signal sent to each electrode terminal 111 of the plurality of semiconductor chips 106 may be disturbed. For example, vibration, that is, ringing may occur in the rising waveform of the voltage when switching from the off state to the on state. As described above, if the input waveform of the gate signal is disturbed, the switching element 113 may malfunction or power loss may occur during switching by the switching element 113, which is disadvantageous for high-speed operation and miniaturization of the power conversion device. Become.

In order to prevent such ringing, an external resistor element R102 is provided between the chip group input terminal 108 and the module input terminal 105 and outside the chip group 103, and the chip group input terminal 108, It is also conceivable to electrically connect the module input terminal 105 via an external resistor element R102. However, when the external resistor element R102 is used, for example, the gate signal sent to the chip group input terminal 108, that is, the absolute value of the gate voltage is reduced, and thus the switching element 113 provided in each semiconductor chip 106 is reduced. This is disadvantageous for ensuring the stability of the switching operation. Further, it is necessary to provide an external resistance element outside the chip group 103, and the power module cannot be reduced in size.

<Main features and effects of the present embodiment>
On the other hand, in the power module 1 according to the first embodiment, the chip group input terminal 8 is provided at a position overlapping the chip group 3 in plan view. In addition, the electrode terminal 11 is disposed closer to the chip group input terminal 8 than the center of the semiconductor substrate 12 in a plan view, and is electrically connected to the chip group input terminal 8.

Thereby, the impedance between the chip group input terminal 8 and the electrode terminal 11 can be adjusted to be close to each other among the plurality of semiconductor chips 6. Therefore, the disturbance of the input waveform of the gate signal sent to each electrode terminal 11 of the plurality of semiconductor chips 6 can be prevented or suppressed. For example, it is possible to prevent or suppress the occurrence of vibration, that is, ringing, in the rising waveform of the voltage when switching from the off state to the on state. Therefore, it is possible to prevent or suppress the switching element 13 from malfunctioning or the occurrence of power loss during switching by the switching element 13.

In the first embodiment, since it is not necessary to prevent the ringing described above, an external resistance element is provided between the chip group input terminal 8 and the module input terminal 5 and outside the chip group 3. There is no need. Therefore, when an external resistance element is used, for example, the gate signal sent to the chip group input terminal 8, that is, the absolute value of the gate voltage can be prevented or suppressed. This is advantageous in stabilizing the switching operation of the switching element 13. Further, since it is not necessary to provide an external resistance element outside the chip group 3, the power module can be reduced in size.

Alternatively, in the power module according to the first embodiment, the semiconductor chip 6 includes the resistance element 22 formed on the semiconductor substrate 12. Further, the gate electrode 15 of the switching element 13 and the electrode terminal 11 are electrically connected via a resistance element 22. By adjusting the resistance value of the resistance element 22, the impedance between the gate electrode 15 and the electrode terminal 11 can be adjusted to a desired value. Therefore, it is possible to prevent or suppress the disturbance of the input waveform of the gate signal sent to the electrode terminal 11 of the semiconductor chip 6.

Even when the semiconductor chip 6 includes the resistance element 22, it is not necessary to prevent the above-described ringing, so that it is not necessary to provide an external resistance element outside the semiconductor chip 6. Therefore, when an external resistance element is used, for example, the gate signal sent to the chip group input terminal 8, that is, the absolute value of the gate voltage can be prevented or suppressed. This is advantageous in stabilizing the switching operation of the switching element 13. Further, since it is not necessary to provide an external resistance element outside the semiconductor chip 6, the power module can be reduced in size.

(Embodiment 2)
<Power conversion device>
Next, the power conversion device according to the second embodiment of the present invention will be described. The power converter of Embodiment 2 is an inverter provided with the power module of Embodiment 1.

FIG. 15 is a diagram illustrating a configuration of the power conversion device according to the second embodiment.

As shown in FIG. 15, the power conversion device 41 includes an inverter 42 as a three-phase inverter provided with the power module 1 of the first embodiment, a load 43 such as a motor, a DC power supply 44, and a capacity such as a capacitor. 45. The load 43 is connected to the output side of the inverter 42, and the DC power supply 44 and the capacitor 45 are connected to the input side of the inverter 42.

The inverter 42 includes

gate drive circuits

46u, 46v, 46w, 46x, 46y and 46z, and switching

elements

47u, 47v, 47w, 47x, 47y and 47z.

The inverter 42 includes a drain node N1 and a source node N2 as a pair of DC input terminals.

Switching elements

47u and 47x are connected in series between drain node N1 and source node N2.

Switching elements

47v and 47y are connected in series between drain node N1 and source node N2.

Switching elements

47w and 47z are connected in series between drain node N1 and source node N2. The

switching elements

47u, 47v, and 47w are arranged on the upper arm side, that is, the high voltage side, and the

switching elements

47x, 47y, and 47z are arranged on the lower arm side, that is, the low voltage side.

The inverter 42 includes a U-phase output node N3, a V-phase output node N4, and a W-phase output node N5 as three-phase AC output terminals. The output node N3 is connected to the switching element 47x side of the switching element 47u and the switching element 47u side of the switching element 47x. The output node N4 is connected to the switching element 47y side of the switching element 47v and the switching element 47v side of the switching element 47y. The output node N5 is connected to the switching element 47z side of the switching element 47w and the switching element 47w side of the switching element 47z. Therefore, switching

elements

47u and 47x are U-phase switching elements, switching

elements

47v and 47y are V-phase switching elements, and switching

elements

47w and 47z are W-phase switching elements.

Each of the

switching elements

47u, 47v, 47w, 47x, 47y and 47z includes a MISFET 48 and a body diode 49. In the second embodiment, the power module 1 (see FIG. 1) according to the first embodiment can be used as each of the

switching elements

47u, 47v, 47w, 47x, 47y, and 47z.

At this time, the module input terminal 5 (see FIG. 1) is connected between each of the

gate drive circuits

46u, 46v, 46w, 46x, 46y and 46z and each of the

switching elements

47u, 47v, 47w, 47x, 47y and 47z. Will be located. The MISFET 48 includes a drain electrode 31, a semiconductor substrate 12, an n ⁻ type epitaxial layer 32, a p type body region 33, an n ⁺ type source region 34, a p ⁺ type body contact region 35, an insulating film 16 as a gate insulating film, This is a vertical MOSFET formed by the gate electrode 15 and the source electrode 36 (see FIG. 10). Further, the body diode 49 is a diode formed by the drain electrode 31, the semiconductor substrate 12, the n ⁻ type epitaxial layer 32, the p type body region 33, the p ⁺ type body contact region 35 and the source electrode 36 (see FIG. 10). ).

The gate drive circuit 46u is connected to the gate electrode of the MISFET 48 of the switching element 47u and drives the switching element 47u. The gate drive circuit 46x is connected to the gate electrode of the MISFET 48 of the switching element 47x, and drives the switching element 47x. The gate drive circuit 46v is connected to the gate electrode of the MISFET 48 of the switching element 47v and drives the switching element 47v. The gate drive circuit 46y is connected to the gate electrode of the MISFET 48 of the switching element 47y, and drives the switching element 47y. The gate drive circuit 46w is connected to the gate electrode of the MISFET 48 of the switching element 47w and drives the switching element 47w. The gate drive circuit 46z is connected to the gate electrode of the MISFET 48 of the switching element 47z, and drives the switching element 47z.

One end of each of switching

elements

47u, 47v and 47w provided on the upper arm side of the inverter 42 is connected to the drain node N1 arranged on the input side of the inverter 42 and on the upper arm side. One end of each of the switching

elements

47x, 47y and 47z on the lower arm side of the inverter 42 is connected to the source node N2 arranged on the input side of the inverter 42 and on the lower arm side.

Between the drain node N1 and the source node N2, a DC power supply 44 and a capacitor 45 are connected in parallel to each other. Therefore, a voltage is applied between the drain node N1 and the source node N2 by the DC power supply 44.

Each of the

gate drive circuits

46u, 46v, 46w, 46x, 46y, and 46z has switching

elements

47u, 47v, 47w, 47x, so that the ON state and the OFF state of the corresponding switching element are switched at a preset timing. Each of 47y and 47z is driven. Thus, three-phase AC signals having different phases, that is, U-phase, V-phase, and W-phase AC signals are generated from the voltage that is a DC signal. That is, in each of the

switching elements

47u, 47v, 47w, 47x, 47y, and 47z, power is converted by switching between the on state and the off state. The load 43 is driven by the three-phase AC signal.

As described above, the body module 49 is built in the power module 1 (see FIG. 1), and the return current can be generated through the body diode 49 without using the antiparallel diode, that is, the return diode. It is possible to flow. Therefore, in power converter 41 of this Embodiment 2 which has inverter 42 provided with power module 1 of Embodiment 1 as each of switching

elements

47u, 47v, 47w, 47x, 47y, and 47z, required parts Thus, the power converter 41 can be easily downsized.

<Main features and effects of the present embodiment>
The power module 1 of the first embodiment can be used as each of the

switching elements

47u, 47v, 47w, 47x, 47y, and 47z in the inverter 42 included in the power conversion device 41 of the second embodiment. According to the power module 1 of the first embodiment, the impedance between the input terminal into which the gate signal sent to the semiconductor chip is input to the power module and the gate electrode of the switching element provided in the semiconductor chip is set to a desired value. Can be adjusted.

Therefore, it is possible to prevent or suppress the disturbance of the input waveform of the gate signal sent to each electrode terminal 11 (see FIG. 1) of the semiconductor chip 6, and to reduce the loss during power conversion in the inverter. Therefore, a large cooling device may not be provided. Therefore, the power conversion device 41 can be easily reduced in cost, size, or weight by reducing the size of the cooling device.

(Embodiment 3)
Next, an automobile according to Embodiment 3 of the present invention will be described. The automobile according to the third embodiment is an automobile including the power conversion device according to the second embodiment, and is an automobile such as a hybrid car and an electric car.

FIG. 16 is a diagram illustrating a configuration of an electric vehicle as a vehicle according to the third embodiment. FIG. 17 is a circuit diagram showing an example of a boost converter in the automobile of the third embodiment.

As shown in FIG. 16, a vehicle 50 as an electric vehicle drives a three-phase motor 53 that allows power to be input / output to / from a drive shaft 52 to which a drive wheel 51a and a drive wheel 51b are connected, and a three-phase motor 53. An inverter 54 and a battery 55 are provided. The automobile 50 includes a boost converter 58, a relay 59, and an electronic control unit 60. The boost converter 58 includes a power line 56 to which an inverter 54 is connected, and a power line 57 to which a battery 55 is connected. It is connected to the.

The three-phase motor 53 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 54, the inverter 42 (see FIG. 15) described in the second embodiment can be used.

As shown in FIG. 17, the boost converter 58 has a configuration in which a reactor 61 and a smoothing capacitor 62 are connected to an inverter 63. The inverter 63 is the same as the inverter 42 described in the second embodiment, and the configuration of the switching element 64 and the body diode 65 in the inverter 63 is the same as that of the MISFET 48 and the body diode 49 as the switching elements described in the second embodiment. Each is the same as the configuration.

The electronic control unit 60 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor that detects the rotor position of the three-phase motor 53, a charge / discharge value of the battery 55, and the like. . Electronic control unit 60 then outputs a signal for controlling inverter 54, boost converter 58, and relay 59.

<Main features and effects of the present embodiment>
As the inverter 54 of the automobile 50 of the third embodiment, the inverter 42 (see FIG. 15) included in the power conversion device 41 of the second embodiment can be used. As each of the

switching elements

47u, 47v, 47w, 47x, 47y, and 47z provided in the inverter 42, the power module 1 (see FIG. 1) of the first embodiment can be used. Alternatively, power module 1 of the first embodiment can be used as switching element 64 and body diode 65 provided in inverter 63 in boost converter 58 of automobile 50 of the third embodiment.

According to the power module 1 of the first embodiment, the impedance between the input terminal into which the gate signal sent to the semiconductor chip is input to the power module and the gate electrode of the switching element provided in the semiconductor chip is set to a desired value. Can be adjusted. Thereby, it can prevent or suppress that the input waveform of the gate signal sent to each electrode terminal 11 (refer to Drawing 1) of semiconductor chip 6 is disturbed.

Therefore, in the automobile 50 according to the third embodiment, the loss at the time of power conversion in the inverter 54 and the boost converter 58 can be reduced, so that a large cooling device may not be provided. Therefore, by reducing the size of the cooling device, the inverter 54 and the boost converter 58 can be easily reduced in cost, size, or weight. As a result, the volume of the drive system occupying the vehicle 50 as an electric vehicle can be reduced, and the vehicle 50 as an electric vehicle can be easily reduced in cost, size, or weight. Alternatively, the degree of freedom in design of the vehicle 50 as an electric vehicle can be increased, for example, the interior of the vehicle 50 as the electric vehicle can be widened.

In addition, in this Embodiment 3, the example which applied the motor vehicle containing the power converter device of Embodiment 2 to the electric vehicle was demonstrated. However, the vehicle including the power conversion device of the second embodiment can be similarly applied to a hybrid vehicle that also uses an engine. The hybrid vehicle to which the power conversion device of the second embodiment is applied also has the same effect as the electric vehicle to which the power conversion device of the second embodiment is applied.

(Embodiment 4)
<Railway vehicle>
Next, a railway vehicle according to the fourth embodiment of the present invention will be described. The railway vehicle according to the fourth embodiment is a railway vehicle including the power conversion device according to the second embodiment.

FIG. 18 is a diagram illustrating a configuration of the railway vehicle according to the fourth embodiment.

As shown in FIG. 18, the railway vehicle 70 includes a pantograph 71 as a current collector, a transformer 72, a power converter 73, a load 74 that is an AC motor, and wheels 75. The power conversion device 73 includes a converter 76, a capacitor 77 that is, for example, a capacitor, and an inverter 78.

Converter 76 has switching

elements

79 and 80. The switching element 79 is disposed on the upper arm side, that is, the high voltage side, and the switching element 80 is disposed on the lower arm side, that is, the low voltage side. In FIG. 18, switching

elements

79 and 80 are shown for one phase among a plurality of phases.

The inverter 78 has switching

elements

81 and 82. The switching element 81 is disposed on the upper arm side, that is, the high voltage side, and the switching element 82 is disposed on the lower arm side, that is, the low voltage side. In FIG. 18, the switching

elements

81 and 82 are shown for one of the three phases U phase, V phase, and W phase.

One end of the primary side of the transformer 72 is connected to the overhead line 71 a via the pantograph 71. The other end of the primary side of the transformer 72 is connected to the track 75 a via the wheel 75. One end of the secondary side of the transformer 72 is connected to a terminal on the upper arm side opposite to the load 74 of the converter 76. The other end of the secondary side of the transformer 72 is connected to a terminal on the lower arm side opposite to the load 74 of the converter 76.

The terminal on the load 74 side and upper arm side of the converter 76 is connected to the terminal on the upper arm side opposite to the load 74 of the inverter 78. Further, the terminal on the load 74 side and the lower arm side of the converter 76 is connected to the terminal on the lower arm side opposite to the load 74 of the inverter 78. Further, a capacitor 77 is connected between a terminal on the side opposite to the load 74 of the inverter 78 on the upper arm side and a terminal on the side opposite to the load 74 of the inverter 78 and on the lower arm side. Although not shown in FIG. 18, each of the three terminals on the output side of the inverter 78 is connected to the load 74 as a U phase, a V phase, and a W phase.

In this Embodiment 4, the inverter 42 (refer FIG. 15) contained in the power converter device 41 of Embodiment 2 can be used as the inverter 78. FIG. That is, railway vehicle 70 of the fourth embodiment includes inverter 42 (see FIG. 15) in the second embodiment as a power conversion device.

The AC power collected from the overhead line 71 a by the pantograph 71 is transformed into desired DC power by the converter 76 after the voltage is transformed by the transformer 72. The DC power converted by the converter 76 is smoothed by the capacitor 77. The DC power whose voltage has been smoothed by the capacitor 77 is converted into AC power by the inverter 78. The AC power converted by the inverter 78 is supplied to the load 74. The load 74 supplied with AC power drives the wheel 75 to rotate, thereby accelerating the railway vehicle.

<Main features and effects of the present embodiment>
As the inverter 78 of the railway vehicle 70 of the fourth embodiment, the inverter 42 (see FIG. 15) included in the power conversion device 41 of the second embodiment can be used. As each of the

switching elements

47u, 47v, 47w, 47x, 47y, and 47z provided in the inverter 42, the power module 1 (see FIG. 1) of the first embodiment is provided.

Therefore, in the railway vehicle 70 according to the fourth embodiment, since the loss at the time of power conversion in the inverter 78 can be reduced, a large cooling device may not be provided. Therefore, the inverter 78 can be easily reduced in cost, size, or weight by reducing the size of the cooling device. Therefore, the cost of the railway vehicle 70 including the inverter 78 can be easily reduced, and the energy efficiency when operating the railway can be improved.

Alternatively, the converter 76 may include the power module 1 (see FIG. 1) of the first embodiment as the switching

elements

79 and 80. Also in this case, since the loss at the time of power conversion in the converter 76 can be reduced, the converter 76 can be easily reduced in cost, size, or weight. Therefore, it is possible to easily reduce the cost of the railway vehicle 70 including the converter 76 and improve the energy efficiency when operating the railway.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The present invention is effective when applied to a power module and a power converter.

DESCRIPTION OF SYMBOLS 1 Power module 2

Lower substrate

3, 3a-3d Chip group 4 Upper substrate 5

Module input terminal

6, 6a-6d Semiconductor chip 7 Chip module 8 Chip

group input terminal

9, 10 Connection member 11 Electrode terminal 12 Semiconductor substrate 13 Switching element 15

Gate electrodes

15a, 15b, 15e, 15f

Parts

15c, 15d Extension part 16 Insulating film 17 Underlying conductive film 18 Conductive film 19 Interlayer insulating film 19a Source contact hole 20

Openings

21, 23, 40 Conductive film 22 Resistance element 31 Drain electrode 32 n ⁻ type epitaxial layer 33 p type body region 34 n ⁺ type source region 35 p ⁺ type body contact region 36 source electrode 37 JFET region 38 channel region 39

wiring

39a, 39b plug 41 power conversion device 42 inverter 43 load 44 DC power supply 45 capacity 4 6u, 46v, 46w, 46x, 46y, 46z

Gate drive circuit

47u, 47v, 47w, 47x, 47y, 47z Switching element 48 MISFET
49 Body Diode 50

Automobile

51a, 51b Drive Wheel 52 Drive Shaft 53 Three-Phase Motor 54 Inverter 55

Battery

56, 57 Power Line 58 Boost Converter 59 Relay 60 Electronic Control Unit 61 Reactor 62 Smoothing Capacitor 63 Inverter 64 Switching Element 65 Body Diode 70 Railway vehicle 71 Pantograph 71a Overhead line 72 Transformer 73 Power converter 74 Load 75 Wheel 75a Line 76 Converter 77 Capacity 78 Inverter 79 to 82 Switching element AR1 Gate pad area AR2 Cell array area AR3 Area CP1, CP2 Center CR1 Corner portion DG1 Diagonal line EP1, EP2 Peripheral LN1 to LN5 Straight line N1 Drain node N2 Source node N3 to N5 Output node

Claims

A first substrate;
A chip group composed of a plurality of semiconductor chips provided on the first substrate;
A first input terminal to which a signal sent to the chip group is input;
With
The plurality of semiconductor chips are arranged at intervals from each other in plan view,
The first input terminal is provided at a position overlapping the chip group in plan view,
Each of the plurality of semiconductor chips is
A semiconductor substrate;
A switching element including a gate electrode formed on the semiconductor substrate;
An electrode terminal formed on the semiconductor substrate and electrically connected to the gate electrode;
Have
The power module, wherein the electrode terminal is disposed closer to the first input terminal than the center of the semiconductor substrate in a plan view and is electrically connected to the first input terminal.
The power module according to claim 1,
A second substrate provided on the chip group;
The first input terminal is a power module formed on a lower surface of the second substrate.
The power module according to claim 1,
Each of the plurality of semiconductor chips has a plurality of resistance elements formed on the semiconductor substrate,
The plurality of resistance elements are connected in parallel to each other,
The power module, wherein the gate electrode and the electrode terminal are electrically connected via the plurality of resistance elements.
The power module according to claim 1,
The semiconductor substrate has a quadrangular shape in plan view,
The electrode terminal is formed at a first corner closest to the first input terminal among the four corners of the semiconductor substrate,
The power module, wherein the gate electrode has a shape symmetrical with respect to a diagonal line passing through the first corner when viewed in a plan view.
The power module according to claim 1,
Any two of the plurality of semiconductor chips are arranged point-symmetrically with respect to the center of the first input terminal in plan view, or pass through the center of the first input terminal. A power module arranged symmetrically with respect to one straight line.
The power module according to claim 1,
A chip group comprising a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip as the plurality of semiconductor chips;
The first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are arranged in a matrix in a first direction and a second direction that intersects the first direction in plan view,
The first input terminal is a power module provided at a position overlapping a central portion of the chip group in plan view.
The power module according to claim 6, wherein
The first semiconductor chip and the second semiconductor chip are arranged symmetrically with respect to a second straight line extending in the first direction through the center of the first input terminal in plan view,
The first semiconductor chip and the third semiconductor chip pass through a center of the first input terminal in a plan view with respect to a third straight line extending in the second direction orthogonal to the first direction. Arranged in line symmetry with each other,
The power module, wherein the third semiconductor chip and the fourth semiconductor chip are arranged symmetrically with respect to the second straight line in plan view.
The power module according to claim 2, wherein
A plurality of the chip groups;
A plurality of the first input terminals;
A second input terminal to which a signal sent to the plurality of first input terminals is input;
A connecting member for electrically connecting the plurality of first input terminals and the second input terminal;
With
The plurality of chip groups are arranged spaced apart from each other in plan view,
A chip module is formed by the plurality of chip groups,
The plurality of first input terminals are respectively provided at positions overlapping with central portions of the plurality of chip groups in plan view,
The second input terminal is provided at a position overlapping the central portion of the chip module in plan view,
The second substrate is provided on the chip module;
The power module, wherein the second input terminal and the connection member are formed on a lower surface of the second substrate.
The power module according to claim 8, wherein
The first chip group, the second chip group, the third chip group and the fourth chip group as the plurality of chip groups,
The first chip group, the second chip group, the third chip group, and the fourth chip group are arranged in a matrix in a fourth direction that intersects the third direction and the third direction in plan view. The power module.
The power module according to claim 9, wherein
The first chip group and the second chip group are arranged symmetrically with respect to a fourth straight line extending in the third direction through the center of the second input terminal in plan view,
The first chip group and the third chip group pass through the center of the second input terminal in a plan view with respect to a fifth straight line extending in the fourth direction orthogonal to the third direction. Arranged in line symmetry with each other,
The power module, wherein the third chip group and the fourth chip group are arranged symmetrically with respect to the fourth straight line in plan view.
The power module according to claim 4, wherein
Each of the plurality of semiconductor chips includes a wiring formed on the gate electrode and electrically connecting two portions of the gate electrode that are arranged on the opposite side across the diagonal line.
The power module according to claim 1,
The semiconductor substrate is made of silicon carbide,
The power module, wherein the switching element is a vertical MOSFET.
A power conversion device comprising the power module according to claim 1.
A semiconductor substrate;
A switching element including a gate electrode formed on the semiconductor substrate;
An electrode terminal formed on the semiconductor substrate and electrically connected to the gate electrode;
A resistance element formed on the semiconductor substrate;
Have
The power module, wherein the gate electrode and the electrode terminal are electrically connected via the resistance element.
The power module according to claim 14, wherein
The semiconductor substrate has a quadrangular shape in plan view,
The electrode terminal is formed at a first corner of the four corners of the semiconductor substrate,
The gate electrode has a shape that is line symmetric with respect to a diagonal line passing through the first corner in a plan view;
The power module further includes a wiring that is formed on the gate electrode and electrically connects two portions of the gate electrode that are arranged on the opposite side across the diagonal line.