WO2017042963A1

WO2017042963A1 - Semiconductor device, method for manufacturing same, power module, power conversion device, and rail vehicle

Info

Publication number: WO2017042963A1
Application number: PCT/JP2015/075853
Authority: WO
Inventors: 悠佳清水; 三江子松村; 慎太郎佐藤
Original assignee: 株式会社日立製作所
Priority date: 2015-09-11
Filing date: 2015-09-11
Publication date: 2017-03-16
Also published as: JP6473512B2; JPWO2017042963A1

Abstract

To improve reliability and yield of a power semiconductor device by achieving a stable ohmic contact. In order to solve the above-mentioned problem, this semiconductor device has, in an n^- type epitaxial layer formed on a first main surface of an n⁺ type SiC substrate formed of 4H-SiC, a p type body region, an n⁺ type source region formed in the p type body region, and an n⁺ type 3C-SiC region and a p⁺ type potential fixing region, which are formed in the n⁺ type source region. A barrier metal film is formed in contact with the n⁺ type 3C-SiC region and the p⁺ type potential fixing region, and a source wiring electrode is formed on the barrier metal film.

Description

Semiconductor device and method for manufacturing the same, power module, power conversion device, and railcar

The present invention relates to a semiconductor device and a manufacturing method thereof, a power module, a power conversion device, and a railway vehicle.

As background arts in this technical field, there are JP-A-2003-96802 (Patent Document 1) and JP-A-2013-58601 (Patent Document 2).

Patent Document 1 describes a silicon carbide semiconductor device in which a surface channel layer is formed of 4H or 6H—SiC and a semiconductor layer to be an n ⁺ type source region is formed of 3C—SiC.

Patent Document 2 describes a semiconductor device using 3C—SiC SiC in the source region.

JP 2003-96802 A JP 2013-58601 A

Development of SiC-MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using SiC (silicon carbide), which has a higher breakdown electric field than Si (silicon), as power semiconductor devices for high-voltage power converters such as railways Has been done.

In the SiC-MOSFET, in order to reduce the contact resistance between the source region and the extraction electrode, Ni silicide is formed between them. However, in order to form Ni silicide, it is necessary to react SiC (silicon carbide) and Ni (nickel) at about 1,000 ° C., which is included in SiC (silicon carbide) in the step of forming Ni silicide. Excess C (carbon) discharge occurs. For this reason, it is difficult to form an ohmic contact due to a complicated reaction accompanied by precipitation of carbon clusters, and problems such as a decrease in reliability and a decrease in yield of the SiC-MOSFET arise.

In order to solve the above problems, a semiconductor device according to the present invention includes an n ⁻ type epitaxial layer formed on a first main surface of an n ⁺ type SiC substrate and a plurality of p ⁻ layers formed in the n ⁻ type epitaxial layer. A p-type body region and an n ⁺ -type source region formed in the p-type body region from the upper surface of the n ⁻ -type epitaxial layer, spaced apart from the end side surface of the p-type body region. Moreover, apart from the end portion side surface of the n ⁺ -type source region, n ^- -type from the upper surface of the epitaxial layer to the n ⁺ -type source region, p formed reaches the p-type body region ⁺ -type potential fixing region, at the top of the n ⁺ -type source region between the end side and the p ⁺ -type potential end side of the fixing area of the n ⁺ -type source region, formed apart from the side surface of the n ⁺ -type source region n ⁺ -type 3C-SiC region. Further, a channel region formed in the upper layer part of the p-type body region between the end side surface of the p-type body region and the end side surface of the n ⁺ -type source region, and a gate insulating film formed in contact with the channel region And a gate electrode formed in contact with the gate insulating film. Further, an interlayer insulating film covering the gate electrode and having an opening through which the p ⁺ -type potential fixing region and the n ⁺ -type 3C-SiC region are exposed, and at the bottom surface of the opening, the p ⁺ -type potential fixing region and the n ⁺ -type 3C- A barrier metal film formed on an interlayer insulating film in contact with the SiC region and including the inner wall of the opening, a first electrode formed on the barrier metal film, and formed on the second main surface of the n ⁺ -type SiC substrate A second electrode.

According to the present invention, the reliability and yield of the power semiconductor device are improved.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

FIG. 3 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC-MOSFETs according to Example 1 are arranged. FIG. 3 is a main part sectional view (a sectional view taken along line AA in FIG. 1) showing the SiC-MOSFET according to Example 1; It is a schematic diagram which shows the band structure of SiC. 7 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a first modification of Example 1 are arranged; FIG. FIG. 10 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a second modification of Example 1 are arranged. FIG. 10 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs are arranged according to a third modification of Example 1; FIG. 10 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a fourth modification of Example 1 are arranged. FIG. 10 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a fifth modification of Example 1 are arranged. FIG. 6 is a sectional view showing the principal parts of an example of a manufacturing process of the SiC-MOSFET according to Example 1. FIG. 10 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process following FIG. 9; FIG. 11 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process that follows FIG. 10; 12 is a fragmentary cross-sectional view showing a manufacturing step of the SiC-MOSFET, following FIG. 11. FIG. FIG. 13 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process following FIG. 12. FIG. 14 is an essential part cross-sectional view showing a manufacturing step of the SiC-MOSFET, following FIG. 13; FIG. 10 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC-MOSFETs according to Example 2 are arranged. FIG. 16 is a cross-sectional view of a principal part showing a SiC-MOSFET according to Example 2 (cross-sectional view taken along line BB in FIG. 15). 12 is a sectional view of the substantial part showing one example of manufacturing steps of the SiC-MOSFET according to Example 2. FIG. FIG. 18 is an essential part cross-sectional view showing a manufacturing step of the SiC-MOSFET, following FIG. 17; FIG. 19 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process following FIG. 18; FIG. 20 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process following FIG. 19; FIG. 21 is an essential part cross-sectional view showing a manufacturing step of the SiC-MOSFET, following FIG. 20; FIG. 22 is a main-portion cross-sectional view showing the SiC-MOSFET manufacturing process following FIG. 21; It is a figure which shows the structure of the three-phase motor system by Example 3. FIG. It is a figure which shows the structure of the rail vehicle by Example 4. FIG.

In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

Also, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

≪SiC-MOSFET structure≫

The structure of the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. FIG. 1 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to the first embodiment are arranged. FIG. 2 is a cross-sectional view of a principal part showing the SiC-MOSFET according to the first embodiment (cross-sectional view along the line AA in FIG. 1). The SiC-MOSFET is a planar type DMOS (Double-diffused-Metal-Oxide-Semiconductor) MOSFET.

As shown in FIG. 1 and FIG. 2, n made of 4H—SiC having an impurity concentration lower than that of the n ⁺ type SiC substrate 1 is formed on the surface (first main surface) of the n ⁺ type SiC substrate 1 made of 4H—SiC. ^{A −} type epitaxial layer 2 is formed, and an SiC epitaxial substrate 3 is constituted by the n ⁺ type SiC substrate 1 and the n ⁻ type epitaxial layer 2. The thickness of the n ⁻ type epitaxial layer 2 is, for example, about 5.0 to 100.0 μm. Further, the preferable range of the impurity concentration of the n ⁺ -type SiC substrate 1 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 2 is, for example, 1 × 10 ^14. It is about 1 × 10 ¹⁷ cm ⁻³ . In the first embodiment, the n ⁺ type SiC substrate 1 made of 4H—SiC is used. However, the present invention is not limited to this, and the n ⁺ type SiC substrate 1 made of 6H—SiC can also be used.

In the n ⁻ -type epitaxial layer 2, a plurality of p-type body regions (well regions) 4 having a predetermined depth from the upper surface of the n ⁻ -type epitaxial layer 2 are formed apart from each other. The depth of the p-type body region 4 from the upper surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 1.0 μm. A preferable range of the impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

An n ⁺ type source region 5 is formed in the p type body region 4 with a predetermined depth from the upper surface of the n ⁻ type epitaxial layer 2. The n ⁺ -type source region 5 is formed in the p-type body region 4 so as to be separated from the end side surface of the p-type body region 4, and from the upper surface of the n ⁻ -type epitaxial layer 2 of the n ⁺ -type source region 5. The depth is, for example, about 0.3 to 0.5 μm. A preferable range of the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Further, in the n ⁺ type source region 5, a p ⁺ type potential fixing region 6 having a predetermined depth from the upper surface of the n ⁻ type epitaxial layer 2 and fixing the potential of the p type body region 4 is formed. ing. The depth of the p ⁺ type potential fixing region 6 from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. A preferable range of the impurity concentration of the p ⁺ -type potential fixing region 6 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

A region sandwiched between adjacent p-type body regions 4 is a part that functions as a JFET (Junction Field Effect Transistor) region 7. A preferable range of the impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ . Further, the end side surface of the p-type body region 4 (interface between the JFET region 7 and the p-type body region 4) and the end side surface of the n ⁺ -type source region 5 (p-type body region 4 and n ⁺ -type source region 5 The p-type body region 4 located between the first and second interfaces) functions as the channel region 8.

Of the n ⁻ -type epitaxial layer 2, a region where the p-type body region 4 is not formed is a region functioning as a drift layer that plays a role of securing a breakdown voltage. Further, the n ⁺ type SiC substrate 1 is a region functioning as a drain layer.

Further, in a part of the upper layer portion of the n ⁺ -type source region 5, an n ⁺ -type 3C-SiC region 9 made of 3C—SiC having a predetermined depth from the upper surface of the n ⁻ -type epitaxial layer 2 (FIG. 1). Then, a hatched region with relatively narrow intervals is formed. The n ⁺ -type 3C—SiC region 9 is separated from the end side surface of the n ⁺ -type source region 5 by 0.3 μm or more. In this way, the n ⁺ -type 3C—SiC region 9 is moved away from the channel region 8 so that defects generated when the 3C—SiC is formed do not affect the reliability of the gate insulating film 10 described later. Because. Further, the n ⁺ type 3C—SiC region 9 is not formed in the upper layer portion of the p ⁺ type potential fixing region 6. The depth of the n ⁺ -type 3C—SiC region 9 from the upper surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.05 to 0.2 μm. Further, a preferable range of the impurity concentration of the n ⁺ -type 3C—SiC region 9 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Note that “ ⁻ ” and “ ⁺ ” are signs representing relative impurity concentrations of n-type or p-type conductivity, for example, n-type in the order of “n ⁻ ”, “n”, and “n ⁺ ”. The impurity concentration of the impurity increases, and the impurity concentration of the p-type impurity increases in the order of “p ⁻ ”, “p”, and “p ⁺ ”.

A gate insulating film 10 is formed on the channel region 8, and a gate electrode 11 (a region indicated by relatively wide hatching in FIG. 1) is formed on the gate insulating film 10. The gate electrode 11 is formed in a lattice shape in plan view, and a p-type body region 4 is formed so as to be surrounded by the gate electrode 11.

The gate insulating film 10 and the gate electrode 11 are covered with an interlayer insulating film 12. The n ⁺ type 3C—SiC region 9 and the p ⁺ type potential fixing region 6 are exposed on the bottom surface of the opening 13 formed in the interlayer insulating film 12.

Further, the n ⁺ -type 3C—SiC region 9 and the p ⁺ -type potential fixing region 6 are electrically connected to the source wiring electrode 15 through the barrier metal film 14. The barrier metal film 14 is provided for preventing diffusion of the metal of the main conductive material constituting the source wiring electrode 15. The barrier metal film 14 is made of, for example, titanium nitride / titanium (TiN / Ti) with Ti (titanium), Ta (tantalum), W (tungsten), TiN (titanium nitride), TaN (tantalum nitride), and Ti (titanium) as a lower layer. Or a tantalum nitride / tantalum (TaN / Ta) laminate with Ta (tantalum) as a lower layer. The source wiring electrode 15 is made of, for example, Al (aluminum), Cu (copper), Al (aluminum) -Cu (copper) alloy, or the like. Although illustration is omitted, similarly, the gate electrode 11 is electrically connected to the gate wiring electrode.

A drain wiring electrode 16 is electrically connected to the back surface (second main surface) of the n ⁺ -type SiC substrate 1. A metal silicide layer may be formed on the back surface of n ⁺ -type SiC substrate 1. A source potential is applied to the source wiring electrode 15 from the outside, a drain potential is applied to the drain wiring electrode 16 from the outside, and a gate potential is applied to the gate wiring electrode from the outside.
<< Characteristics of SiC-MOSFET structure >>

Next, the characteristics of the structure of the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. FIG. 3 is a schematic view showing a band structure of SiC.

The SiC-MOSFET according to the first embodiment is characterized in that the n ⁺ -type 3C—SiC region 9 is formed between the n ⁺ -type source region 5 and the barrier metal film 14.

As described above, in the SiC-MOSFET, generally, Ni silicide is formed between the source region (n ⁺ -type source region 5) and the extraction electrode (barrier metal film 14) in order to reduce the contact resistance. . However, in order to form Ni silicide, it is necessary to react SiC (silicon carbide) and Ni (nickel) at about 1,000 ° C., which is included in SiC (silicon carbide) in the step of forming Ni silicide. Excess C (carbon) discharge occurs. For this reason, it becomes difficult to form an ohmic contact due to a complicated reaction accompanied by precipitation of carbon clusters.

However, in the SiC-MOSFET according to the first embodiment, Ni silicide is not formed. For this reason, there is a concern that the contact resistance between the source region (n ⁺ -type source region 5) and the extraction electrode (barrier metal film 14) increases. However, the contact resistance can be reduced by forming the n ⁺ -type 3C—SiC region 9 between the source region (n ⁺ -type source region 5) and the extraction electrode (barrier metal film 14).
FIG. 3 shows band structures of Ti (titanium), 3C—SiC, and 4H—SiC.

As shown in FIG. 3, the valence band levels (E _V ) of 3C—SiC and 4H—SiC are almost the same. In contrast, 3C-SiC forbidden band width _{(E G)} and electron affinity (chi) are each 2.23eV and 4.0 eV, the band gap of the 4H-SiC _{(E G)} and the electron affinity (chi ) Are 3.26 eV and 3.2 eV, respectively, and are different from each other. Considering the case of using Ti (titanium) as the barrier metal film, the work function (φm) of Ti (titanium) is 4.3 eV, so the Fermi level (E _F ) of Ti (titanium) and 3C-SiC of the difference between the level _{(E C)} of the conduction band is smaller than the difference between Ti Fermi level _{(E F)} and 4H-SiC in level of the conduction band (titanium) _{(E C).} Therefore, when the n-type region is made of 3C—SiC, the contact resistance can be reduced compared to the case where the n-type region is made of 4H—SiC.

In the SiC-MOSFET according to the first embodiment, the upper layer of the n ⁺ source region 5 is separated from the channel region 8 by a predetermined distance, for example, 0.3 μm or more so as not to affect the reliability of the gate insulating film 10. An n ⁺ -type 3C—SiC region 9 is formed in the part. On the other hand, the n ⁺ type 3C—SiC region 9 is not formed in the upper layer portion of the p ⁺ type potential fixing region 6. This is because the contact resistance is not reduced even if the n ⁺ -type 3C—SiC region 9 is formed in the upper layer portion of the p ⁺ -type potential fixing region 6.
<< Modification of Example 1 >>

The layout of the SiC-MOSFET in the element formation region is not limited to that shown in FIG. For example, the layout shown in FIGS. 4 and 5 may be used. FIG. 4 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a first modification of the first embodiment are arranged. FIG. 5 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a second modification of the first embodiment are arranged.

In the SiC-MOSFET layout shown in FIG. 1, a plurality of p-type body regions 4 arranged at first intervals along the X direction are arranged along the Y direction orthogonal to the X direction on the surface of the SiC epitaxial substrate 3. Arranged at a second interval, the plurality of p-type body regions 4 are arranged so as to be surrounded by the gate electrodes 11 formed in a lattice shape.

On the other hand, in the layout of the SiC-MOSFET of the first modification shown in FIG. 4, the plurality of p-type body regions 4 arranged at the second interval along the Y direction are positioned at half the second interval. , And are arranged at first intervals along the X direction so as to be alternately positioned. The plurality of p-type body regions 4 are arranged in a so-called staggered arrangement.

In the SiC-MOSFET layout of the second modification shown in FIG. 5, a plurality of p-type body regions 4 extending along the Y direction are arranged apart from each other in the X direction, and along the Y direction. A plurality of extending gate electrodes 11 are arranged between adjacent p-type body regions 4.

Further, the layout of the n ⁺ -type 3C—SiC region 9 is not limited to that shown in FIGS. For example, the layouts shown in FIGS. 6, 7, and 8 may be used. FIG. 6 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a third modification of the first embodiment are arranged. FIG. 7 is a main part plan view showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a fourth modification of the first embodiment are arranged. FIG. 8 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC-MOSFETs according to a fifth modification of the first embodiment are arranged.

In the layout of the SiC-MOSFET shown in FIG. 1 and the SiC-MOSFET of the first modified example shown in FIG. 4, one is separated from the gate electrode 11 around the p ⁺ -type potential fixing region 6 in plan view. An annular n ⁺ -type 3C—SiC region 9 connected to is formed.

In contrast, in the layout of the SiC-MOSFET of the third modification shown in FIG. 6 and the SiC-MOSFET of the fourth modification shown in FIG. 7, the gate electrode is formed around the p ⁺ -type potential fixing region 6 in plan view. A plurality of n ⁺ -type 3C—SiC regions 9 are formed apart from 11, and these are formed apart from each other.

Further, in the layout of the SiC-MOSFET of the second modification example shown in FIG. 5, n ⁺ connected together in parallel with the side surface of the p ⁺ -type potential fixing region 6 extending along the first direction Y. A mold 3C-SiC region 9 is formed.

On the other hand, in the layout of the SiC-MOSFET of the fifth modification shown in FIG. 8, a plurality of n ⁺ -types are provided in parallel with the side surfaces of the p ⁺ -type potential fixing region 6 extending along the first direction Y. 3C-SiC regions 9 are formed apart from each other.
≪SiC-MOSFET manufacturing method≫

A method for manufacturing the SiC-MOSFET according to the first embodiment will be described in the order of steps with reference to FIGS. 9 to 14 are cross-sectional views of relevant parts showing an example of a manufacturing process of the SiC-MOSFET according to the first embodiment.

First, as shown in FIG. 9, an n ⁺ type SiC substrate 1 made of 4H—SiC is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 1. The n-type impurity is, for example, N (nitrogen), and the impurity concentration of the n-type impurity is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . Further, the n ⁺ type SiC substrate 1 has both a Si surface and a C surface, but the surface of the n ⁺ type SiC substrate 1 may be either the Si surface or the C surface.

Next, an n ⁻ type epitaxial layer 2 made of 4H—SiC is formed on the surface of the n ⁺ type SiC substrate 1 by epitaxial growth. In the n ⁻ type epitaxial layer 2, an n type impurity lower than the impurity concentration of the n ⁺ type SiC substrate 1 is introduced. Although the impurity concentration of the n ⁻ -type epitaxial layer 2 depends on the element rating of the SiC-MOSFET, it is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . Further, the thickness of the n ⁻ type epitaxial layer 2 is, for example, about 5.0 to 100.0 μm. Through the above steps, SiC epitaxial substrate 3 composed of n ⁺ type SiC substrate 1 and n ⁻ type epitaxial layer 2 is formed.

Next, p-type impurities such as Al (aluminum) atoms are ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV. As a result, a plurality of p-type body regions 4 are formed in the element formation region of the n ⁻ -type epitaxial layer 2, and although not shown, a floating field limiting ring (FLR) is formed in the peripheral formation region. Form a structure.

The depth of the p-type body region 4 from the upper surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 1.0 μm. Further, the impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . Although the FLR structure is formed at the end of the peripheral formation region, the present invention is not limited to this. As a structure of the termination portion, for example, a junction termination extension (JTE) structure may be used.

Next, an n-type impurity, for example, N (nitrogen) atoms are ion-implanted into the p-type body region 4 at a maximum energy of 120 keV and a temperature of about 25 ° C. An n ⁺ type source region 5 is formed apart from the side surface (interface between the n ⁻ type epitaxial layer 2 and the p type body region 4). Here, ion implantation is performed so that the n ⁺ -type source region 5 is not completely amorphized. The depth of the n ⁺ type source region 5 from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. Further, the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Next, a p-type impurity, for example, Al (aluminum) atoms is ion-implanted into the n ⁺ -type source region 5 at a maximum energy of 150 keV and a temperature of about 350 to 700 ° C. ^{A +} -type potential fixing region 6 is formed. Here, ion implantation is performed so that the p ⁺ -type potential fixing region 6 is not completely amorphized. The depth of the p ⁺ type potential fixing region 6 from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. Further, the impurity concentration of the p ⁺ -type potential fixing region 6 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 10, a mask pattern 17 made of a resist film is formed on the upper surface of the n ⁻ -type epitaxial layer 2. The mask pattern 17 is provided with an opening only in a region where the n ⁺ -type 3C—SiC region 9 is formed. That, ^{p +} -type from a position apart more than 0.3μm in ^{p +} -type potential fixing region 6 side from (the interface with the p-type body region 4 and ^{n +} -type source region 5) the side surface of the ^{n +} -type source region 5 so that n ⁺ -type source region 5 between the end sides of the potential fixing region 6 (the interface with the n ⁺ -type source region 5 and p ⁺ -type potential fixing region 6) is exposed, the openings in the mask pattern 17 is Is provided.

Next, an n-type impurity such as P (phosphorus) atoms is ion-implanted into the n ⁺ -type source region 5 through the mask pattern 17 at a maximum energy of 50 keV and a temperature of about 25 ° C. As a result, the n ⁺ -type amorphous region is located between the end side surface of the p ⁺ -type potential fixing region 6 and a position separated by 0.3 μm or more from the end side surface of the n ⁺ -type source region 5 toward the p ⁺ -type potential fixing region 6 side. Region 9a is formed. Here, ion implantation is performed so that the n ⁺ -type amorphous region 9a is completely amorphized. The depth of the n ⁺ type amorphous region 9a from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.05 to 0.2 μm. The impurity concentration of the n ⁺ -type amorphous region 9a is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Next, after removing the mask pattern 17, although not shown, a C (carbon) film is deposited on the upper surface of the n ⁻ -type epitaxial layer 2 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The thickness of the C (carbon) film is, for example, about 0.03 μm.

Next, as shown in FIG. 11, with the upper surface of the n ⁻ -type epitaxial layer 2 covered with a C (carbon) film, the SiC epitaxial substrate 3 is heat-treated at a temperature of about 1,700 ° C. for about 2 to 3 minutes. Apply. Thereby, each impurity ion-implanted into the n ⁻ -type epitaxial layer 2 is activated. Here, the n ⁺ type amorphous region 9a becomes the n ⁺ type 3C—SiC region 9 containing 3C—SiC. After the heat treatment, the C (carbon) film is removed by, for example, oxygen plasma treatment.

Next, as shown in FIG. 12, a gate insulating film 10 made of SiON (silicon oxynitride) is formed on the upper surface of the n ⁻ type epitaxial layer 2. The gate insulating film 10 is formed by, for example, forming a SiO ₂ (silicon dioxide) film by a CVD method and then performing a heat treatment in an NO (nitrogen monoxide) or N ₂ O (dinitrogen monoxide) atmosphere. The thickness of the gate insulating film 10 is, for example, about 0.05 to 0.15 μm.

Next, a polycrystalline Si (polycrystalline silicon) film is formed on the gate insulating film 10, and the polycrystalline Si (polycrystalline silicon) film is processed by a dry etching method to form the gate electrode 11. The thickness of the gate electrode 11 is, for example, about 0.2 to 0.5 μm.

Next, an interlayer insulating film 12 is formed on the upper surface of the n ⁻ -type epitaxial layer 2 so as to cover the gate insulating film 10 and the gate electrode 11 by, for example, a plasma CVD method. Thereafter, the interlayer insulating film 12 is processed by a dry etching method, and an opening 13 reaching a part of the n ⁺ -type 3C—SiC region 9 and the p ⁺ -type potential fixing region 6 and an opening reaching the gate electrode 11 (illustrated). Is omitted).

Next, as shown in FIG. 13, a barrier metal film 14 is formed on the interlayer insulating film 12 so as to cover the inner wall (bottom surface and side surface) of the opening 13. The barrier metal film 14 is made of, for example, titanium nitride / titanium (TiN / Ti) with Ti (titanium), Ta (tantalum), W (tungsten), TiN (titanium nitride), TaN (tantalum nitride), and Ti (titanium) as a lower layer. Or a tantalum nitride / tantalum (TaN / Ta) laminate with Ta (tantalum) as a lower layer. Subsequently, a conductive film (not shown) is formed on the barrier metal film 14 so as to fill the inside of the opening 13. The conductive film is made of, for example, Al (aluminum), Cu (copper), or Al (aluminum) -Cu (copper) alloy. The thickness of the conductive film is preferably 2.0 μm or more, for example.

Next, the conductive film and the barrier metal film 14 are processed by a dry etching method, and the source wiring electrode 15 and the gate wiring electrode (not shown) made of the conductive film having the barrier metal film 14 in the lower layer are formed. Form. The source wiring electrode 15 is electrically connected to the n ⁺ -type 3C—SiC region 9 and the p ⁺ -type potential fixing region 6, and the gate wiring electrode is electrically connected to the gate electrode 11.

Thereafter, in order to improve the adhesion between the barrier metal film 14 and the n ⁺ -type 3C—SiC region 9, the SiC epitaxial substrate 3 is subjected to a heat treatment at a temperature of about 500 ° C.

Next, a passivation film (not shown) is formed so as to cover the source wiring electrode 15 and the gate wiring electrode. An opening is formed in a portion of the passivation film where a pad region for electrically connecting the source wiring electrode 15 and the gate wiring electrode to the outside is formed.

Next, as shown in FIG. 14, drain wiring electrode 16 is formed on the back surface of n ⁺ -type SiC substrate 1. The thickness of the drain wiring electrode 16 is, for example, about 0.4 μm.

Through the above manufacturing process, the SiC-MOSFET according to the first embodiment is substantially completed.

Thus, in the SiC-MOSFET according to the first embodiment, Ni silicide is not formed between the n ⁺ -type source region 5 and the barrier metal film 14, but the n ⁺ -type 3C-SiC region 9 is formed. Thus, an ohmic contact can be formed, and the contact resistance can be reduced.

Furthermore, as described above, in order to form Ni silicide, it is necessary to react SiC (silicon carbide) and Ni (nickel) at about 1,000 ° C. In the step of forming Ni silicide, SiC (silicon carbide) is required. ) Discharge of surplus C (carbon) contained therein. For this reason, it becomes difficult to form an ohmic contact due to a complicated reaction accompanied by precipitation of carbon clusters, and problems such as a decrease in reliability and a decrease in yield of the SiC-MOSFET arise.

However, since the SiC-MOSFET according to the first embodiment does not form Ni silicide, a stable contact resistance between the n ⁺ type source region 5 and the barrier metal film 14 can be obtained. Therefore, problems such as a decrease in the reliability of the SiC-MOSFET and a decrease in the yield due to the variation in the contact resistance can be avoided. Further, since a stable contact resistance can be obtained even at a high temperature, the reliability of a semiconductor device having an element formation region in which a plurality of SiC-MOSFETs are arranged is improved in a high temperature operation.

≪SiC-MOSFET structure≫

The structure of the SiC-MOSFET according to the second embodiment will be described with reference to FIGS. FIG. 15 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC-MOSFETs according to the second embodiment are arranged. FIG. 16 is a sectional view (a sectional view taken along line BB in FIG. 15) showing the SiC-MOSFET according to the second embodiment. The SiC-MOSFET is a planar type DMOS MOSFET.

The difference from the first embodiment is the structure of the n ⁺ -type source region 5 and the n ⁺ -type 3C—SiC region 9. Since the other structure is almost the same as that of the SiC-MOSFET according to the first embodiment, the description will focus on the differences.

15 and FIG. 16, on consisting of 4H-SiC ^{n +} -type SiC substrate 1 of the surface (first main surface), a low 4H-SiC impurity concentration than ^{n +} -type SiC substrate 1 n ^{A −} type epitaxial layer 2 is formed, and an SiC epitaxial substrate 3 is constituted by the n ⁺ type SiC substrate 1 and the n ⁻ type epitaxial layer 2.

Each of the plurality of p-type body regions (well regions) 4 formed in the n ⁻ -type epitaxial layer 2 includes an n ⁺ -type source region 5, a p ⁺ -type potential fixing region 6, and an n ⁺ -type 3C—SiC. Region 9 is formed.

However, ^{n +} -type source region 5, the upper first 2n located ^- ^- (lower surface -type epitaxial layer 2 n) a 1n ⁺ -type source region 5a and a lower located (n type upper surface side of the epitaxial layer 2) ⁺ which is composed of a source region 5b, both as the 2n ⁺ -type source region 5b is included in the first 1n ⁺ -type source region 5a in a plan view are formed. In other words, the end side surface of the second n ⁺ -type source region 5b is formed inside the end side surface of the first n ⁺ -type source region 5a in plan view. Specifically, when viewed in cross section along the direction of the p-type body region 4 adjacent to each other, opposite the end portion side surface of the 1n ⁺ -type source region 5a, the end portion side surface of the 1n ⁺ -type source region 5a the distance between the side surface of the p-type body region 4 (L1) includes an end portion side surface of the 2n ⁺ -type source region 5b, the p-type body region 4 facing the end portion side surface of the 2n ⁺ -type source region 5b Shorter than the distance (L2) from the side face of the end. Further, when viewed in a cross section along the direction of the p-type body regions 4 adjacent to each other, the end side surface of the first n ⁺ type source region 5a and the end side surface of the p ⁺ type potential fixing region 6 are in contact. The end side surface of the second n ⁺ type source region 5b and the end side surface of the p ⁺ type potential fixing region 6 are not in contact with each other and are separated from each other.

The depth of the second n ⁺ type source region 5b from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. A preferable range of the impurity concentration of the first n ⁺ -type source region 5a and the second n ⁺ -type source region 5b is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Further, ^{n +} -type 3C-SiC region 9 is substantially directly above the first 2n ⁺ -type source region 5b, are formed so as to overlap with the first 2n ⁺ -type source region 5b in a plan view. Therefore, both are formed such that the n ⁺ -type 3C—SiC region 9 is included in the second n ⁺ -type source region 5b in plan view. In other words, the n ⁺ -type 3C—SiC region 9 is formed inside the end side surface of the second n ⁺ -type source region 5b in plan view. The depth of the n ⁺ -type 3C—SiC region 9 from the upper surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.05 to 0.2 μm. Further, a preferable range of the impurity concentration of the n ⁺ -type 3C—SiC region 9 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

and the side surface of the n ⁺ -type 3C-SiC region 9, the distance between the side surface of the 1n ⁺ -type source region 5a facing the end side face of the ^{n +} -type 3C-SiC region 9 (L3), for example 0 About 5 μm.

The n ⁺ type 3C—SiC region 9 and the p ⁺ type potential fixing region 6 are electrically connected to the source wiring electrode 15 through the barrier metal film 14.

In the SiC-MOSFET according to the second embodiment, the n ⁺ -type 3C-SiC region 9 is formed between the n ⁺ -type source region 5 and the barrier metal film 14 in the same manner as the SiC-MOSFET according to the first embodiment. It has the characteristics. Therefore, it is possible to form an ohmic contact by forming the n ⁺ -type 3C—SiC region 9 between the n ⁺ -type source region 5 and the barrier metal film 14 without forming Ni silicide. Contact resistance can be reduced.
≪SiC-MOSFET manufacturing method≫

A manufacturing method of the SiC-MOSFET according to the second embodiment will be described in the order of steps with reference to FIGS. FIGS. 17 to 22 are cross-sectional views of relevant parts showing one example of manufacturing steps of the SiC-MOSFET according to the second embodiment.

First, as shown in FIG. 17, an n ⁺ type SiC substrate 1 made of 4H—SiC is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 1. The n-type impurity is, for example, N (nitrogen), and the impurity concentration of the n-type impurity is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . Further, the n ⁺ type SiC substrate 1 has both a Si surface and a C surface, but the surface of the n ⁺ type SiC substrate 1 may be either the Si surface or the C surface.

Next, p-type impurities such as Al (aluminum) atoms are ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV. As a result, a plurality of p-type body regions 4 are formed in the element formation region of the n ⁻ -type epitaxial layer 2, and although not shown, an FLR structure is formed in the peripheral formation region.

The depth of the p-type body region 4 from the upper surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 1.0 μm. Further, the impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . Although the FLR structure is formed at the end of the peripheral formation region, the present invention is not limited to this. As a structure of the terminal portion, for example, a JTE structure may be used.

Then, p-type impurity in p-type body region 4, for example, Al (aluminum) atom maximum energy 150 keV, and ion-implanted at a temperature of about 350 ~ 700 ° C., in the region to fix the potential of the p-type body region 4 ^{p +} A type potential fixing region 6 is formed. Here, ion implantation is performed so that the p ⁺ -type potential fixing region 6 is not completely amorphized. The depth of the p ⁺ type potential fixing region 6 from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. Further, the impurity concentration of the p ⁺ -type potential fixing region 6 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 18, a mask pattern 18 made of, for example, SiO ₂ (silicon dioxide) is formed on the upper surface of the n ⁻ -type epitaxial layer 2. The mask pattern 18 is provided with an opening only in a region where the first n ⁺ type source region 5a is formed. That is, the p-type body region 4 is exposed between a position away from the end side surface of the p-type body region 4 toward the p ⁺ -type potential fixing region 6 and the end side surface of the p ⁺ -type potential fixing region 6. The mask pattern 18 is provided with an opening.

Next, an n-type impurity such as N (nitrogen) atoms is ion-implanted into the p-type body region 4 through the mask pattern 18 at a maximum energy of 50 keV and a temperature of about 25 ° C. As a result, the first n ^{+ is} added to the p-type body region 4 between the position away from the end side surface of the p-type body region 4 toward the p ⁺ -type potential fixing region 6 and the end side surface of the p ⁺ -type potential fixing region 6. A mold source region 5a is formed. Here, ion implantation is performed so that the first n ⁺ -type source region 5a is not completely amorphized. The impurity concentration of the first n ⁺ -type source region 5a is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 19, an SiO ₂ (silicon dioxide) film is formed on the upper surface of the n ⁻ -type epitaxial layer 2 so as to cover the mask pattern 18, and then the SiO ₂ (silicon dioxide) film is etched back. As a result, sidewalls 19 are formed on the side surfaces of the mask pattern 18. The width (W) of the sidewall 19 is, for example, about 0.5 μm.

Next, an n-type impurity such as P (phosphorus) atoms is ion-implanted into the n ⁺ -type source region 5 through the mask pattern 18 and the sidewall 19 at a maximum energy of 50 keV and a temperature of about 25 ° C. As a result, the n ⁺ -type amorphous region 9a is formed apart from the end side surface of the first n ⁺ -type source region 5a. Here, ion implantation is performed so that the n ⁺ -type amorphous region 9a is completely amorphized. The depth of the n ⁺ type amorphous region 9a from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.05 to 0.2 μm. The impurity concentration of the n ⁺ -type amorphous region 9a is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Next, an n-type impurity, for example, N (nitrogen) atoms are ion-implanted into the p-type body region 4 through the mask pattern 18 and the sidewall 19 at a maximum energy of 120 keV and a temperature of about 25 ° C. Thus, the second n ⁺ type source region 5b is formed deeper than the n ⁺ type amorphous region 9a. Here, ion implantation is performed so that the second n ⁺ -type source region 5b is not completely amorphized. The depth of the second n ⁺ type source region 5b from the upper surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.3 to 0.5 μm. The impurity concentration of the n ⁺ -type source region 5b is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 20, after the mask pattern 18 and the sidewalls 19 are removed by a wet etching method or the like, although not shown in the figure, on the upper surface of the n ⁻ -type epitaxial layer 2, for example, a CCVD method is used. A (carbon) film is deposited. The thickness of the C (carbon) film is, for example, about 0.03 μm.

Next, in a state where the upper surface of the n ⁻ -type epitaxial layer 2 is covered with a C (carbon) film, the SiC epitaxial substrate 3 is subjected to heat treatment at a temperature of about 1,700 ° C. for about 2 to 3 minutes. Thereby, each impurity ion-implanted into the n ⁻ -type epitaxial layer 2 is activated. Here, the n ⁺ type amorphous region 9a becomes the n ⁺ type 3C—SiC region 9 containing 3C—SiC. After the heat treatment, the C (carbon) film is removed by, for example, oxygen plasma treatment.

Thus, the first n ⁺ -type source region 5a is formed by ion implantation through the mask pattern 18, and the n ⁺ -type amorphous region 9a is formed by ion implantation through the subsequent mask pattern 18 and the sidewall 19, so that the first and the side surface of 1n ⁺ -type source region 5a, set to a desired distance distance (L3) between the side surface of the ^{n +} -type 3C-SiC region 9 opposite to the side surface of the 1n ⁺ -type source region 5a can do. Therefore, it is possible to prevent defects generated when forming the n ⁺ -type amorphous region 9a from affecting the reliability of the gate insulating film 10 formed in a later process. Further, the n ⁺ -type 3C—SiC region 9 can be prevented from being formed in the upper layer portion of the p ⁺ -type potential fixing region 6.

Next, a gate insulating film 10 made of SiON (silicon oxynitride) is formed on the upper surface of the n ⁻ type epitaxial layer 2. The gate insulating film 10 is formed by, for example, forming a SiO ₂ (silicon dioxide) film by a CVD method and then performing a heat treatment in an NO (nitrogen monoxide) or N ₂ O (dinitrogen monoxide) atmosphere. The thickness of the gate insulating film 10 is, for example, about 0.05 to 0.15 μm.

Next, an interlayer insulating film 12 is formed on the upper surface of the n ⁻ -type epitaxial layer 2 so as to cover the gate insulating film 10 and the gate electrode 11 by, for example, a plasma CVD method. Thereafter, the interlayer insulating film 12 is processed by a dry etching method to form a part of the first n ⁺ type source region 5a, a part of the n ⁺ type 3C—SiC region 9 and the opening 13 reaching the p ⁺ type potential fixing region 6. In addition, an opening (not shown) reaching the gate electrode 11 is formed.

Next, as shown in FIG. 21, a barrier metal film 14 is formed on the interlayer insulating film 12 so as to cover the inner wall (bottom surface and side surface) of the opening 13. The barrier metal film 14 is made of, for example, titanium nitride / titanium (TiN / Ti) with Ti (titanium), Ta (tantalum), W (tungsten), TiN (titanium nitride), TaN (tantalum nitride), and Ti (titanium) as a lower layer. Or a tantalum nitride / tantalum (TaN / Ta) laminate with Ta (tantalum) as a lower layer. Subsequently, a conductive film (not shown) is formed on the barrier metal film 14 so as to fill the inside of the opening 13. The conductive film is made of, for example, Al (aluminum), Cu (copper), or Al (aluminum) -Cu (copper) alloy. The thickness of the conductive film is preferably 2.0 μm or more, for example.

Next, the conductive film and the barrier metal film 14 are processed by a dry etching method, and the source wiring electrode 15 and the gate wiring electrode (not shown) made of the conductive film having the barrier metal film 14 in the lower layer are formed. Form. The source wiring electrode 15 is electrically connected to the n ⁺ type source region 5, the n ⁺ type 3C-SiC region 9 and the p ⁺ type potential fixing region 6, and the gate wiring electrode is electrically connected to the gate electrode 11. .

Next, as shown in FIG. 22, drain wiring electrode 16 is formed on the back surface of n ⁺ -type SiC substrate 1. The thickness of the drain wiring electrode 16 is, for example, about 0.4 μm.

By the above manufacturing process, the SiC-MOSFET according to the second embodiment is almost completed.

Thus, according to the second embodiment, substantially the same effects as those of the first embodiment can be obtained.

Further, n ⁺ -type and the side surface of the source region 5, n ⁺ -type source region 5 and the side surface of the n ⁺ -type 3C-SiC region 9 opposite to the side surface to ensure a desired distance Therefore, it is possible to prevent defects generated when 3C—SiC is formed from affecting the reliability of the gate insulating film 10. In addition, the n ⁺ -type 3C—SiC region 9 can be prevented from being formed in the upper layer portion of the p ⁺ -type potential fixing region 6. Thereby, the SiC-MOSFET according to the second embodiment is more reliable than the SiC-MOSFET according to the first embodiment.

≪Power module, power converter and three-phase motor system≫

A power module, a power converter, and a three-phase motor system including the power converter according to the third embodiment will be described. The power module of the third embodiment includes a semiconductor device having an element formation region in which the SiC-MOSFETs of the first embodiment are arranged. The power module according to the third embodiment is obtained by applying this semiconductor device to a three-phase inverter circuit.

FIG. 23 is a diagram illustrating a configuration of a three-phase motor system according to the third embodiment.

As shown in FIG. 23, the three-phase motor system 30 includes a power conversion device 31 as an inverter device, a load 32 composed of a three-phase motor, a DC power source 33, and a capacitor 34 composed of a capacitor. Yes. The power conversion device 31 includes a power module 35 as a three-phase inverter circuit and a control circuit 36. The load 32 is connected to output terminals TO1, TO2, and TO3, which are three-phase output terminals of the power module 35. The DC power supply 33 and the capacitor 34 are connected in parallel between the input terminal TI1 and the input terminal TI2, which are the two input terminals of the power module 35.

The power module 35 as a three-phase inverter circuit has switching

elements

37u, 37v, 37w, 37x, 37y and 37z. The

switching elements

37u and 37x are connected in series between the input terminal TI1 and the input terminal TI2. The switching

elements

37v and 37y are connected in series between the input terminal TI1 and the input terminal TI2. The

switching elements

37w and 37z are connected in series between the input terminal TI1 and the input terminal TI2.

Each of the

switching elements

37u, 37v, 37w, 37x, 37y and 37z includes a MOSFET 38 and a body diode 39. As each of the

switching elements

37u, 37v, 37w, 37x, 37y, and 37z, a semiconductor device having an element formation region in which the SiC-MOSFETs of Example 1 described above are arranged can be used. As the body diode 39, a body diode built in the SiC-MOSFET can be used.

The gate electrodes of the plurality of MOSFETs 38 provided in the

switching elements

37u, 37v, 37w, 37x, 37y and 37z, respectively, are control terminals TC1, TC2, TC3, TC4, TC5 which are six control terminals of the power module 35. And TC6, respectively. The control circuit 36 is connected to each of the control terminals TC1, TC2, TC3, TC4, TC5, and TC6. Accordingly, the control circuit 36 is connected to each gate electrode of the plurality of MOSFETs 38 provided in the

switching elements

37u, 37v, 37w, 37x, 37y and 37z, respectively. The control circuit 36 drives the

switching elements

37u, 37v, 37w, 37x, 37y and 37z.

The control circuit 36 switches the

switching elements

37u, 37v, 37w, 37x, 37y, and 37z so that the ON state and the OFF state of the

switching elements

37u, 37v, 37w, 37x, and 37z are alternately switched at preset timings. And 37z are driven. As a result, a U-phase, V-phase, and W-phase three-phase AC voltage is generated from the DC voltage, and the DC power is converted into three-phase AC power. The load 32 is driven by this three-phase AC power.
<Main features and effects of the third embodiment>

As each of the

switching elements

37u, 37v, 37w, 37x, 37y and 37z in the power module 35 included in the power conversion device 31 of the third embodiment, an element formation region in which the SiC-MOSFETs of the first embodiment are arranged is used. The semiconductor device which has can be used.

Since the semiconductor device is composed of a SiC-MOSFET that can obtain a stable operation state even at a high temperature, the reliability of the power module 35 and the power conversion device 31 at a high temperature operation can be improved. Further, even if the semiconductor device is operated at a high current density, it is possible to maintain a stable operation state in which the contact resistance does not fluctuate, so that the semiconductor device can be reduced in size, and accordingly, the power module 35 and the power conversion device 31 can be downsized.

≪Railway vehicle≫

The railway vehicle according to the fourth embodiment will be described. The railway vehicle according to the fourth embodiment is a railway vehicle including the power conversion device according to the third embodiment.

FIG. 24 is a diagram illustrating a configuration of a railway vehicle according to the fourth embodiment.

As shown in FIG. 24, the railway vehicle 60 includes a pantograph 61 as a current collector, a transformer 62, a power converter 63, a load 64 that is an AC motor, and wheels 65. The power conversion device 63 includes a converter device 66, a capacitor 67 that is, for example, a capacitor, and an inverter device 68.

The converter device 66 has switching

elements

69 and 70. The switching element 69 is disposed on the upper arm side, that is, the high voltage side, and the switching element 70 is disposed on the lower arm side, that is, the low voltage side. In FIG. 24, the switching

elements

69 and 70 are shown for one of the three phases U phase, V phase and W phase.

The inverter device 68 has switching

elements

71 and 72. The switching element 71 is disposed on the upper arm side, that is, the high voltage side, and the switching element 72 is disposed on the lower arm side, that is, the low voltage side. In FIG. 24, the switching

elements

71 and 72 are shown for one of the three phases U phase, V phase and W phase.

One end of the primary side of the transformer 62 is connected to the overhead line 61 a via the pantograph 61. The other end of the primary side of the transformer 62 is connected to the line 65 a via the wheel 65. One end of the secondary side of the transformer 62 is connected to a terminal on the upper arm side opposite to the load 64 of the converter device 66. The other end of the secondary side of the transformer 62 is connected to a terminal on the lower arm side opposite to the load 64 of the converter device 66.

The terminal on the load 64 side and the upper arm side of the converter device 66 is connected to the terminal on the upper arm side opposite to the load 64 of the inverter device 68. The terminal on the load 64 side of the converter device 66 on the lower arm side is connected to the terminal on the lower arm side opposite to the load 64 of the inverter device 68. Further, a capacitor 67 is connected between a terminal on the side opposite to the load 64 of the inverter device 68 and on the upper arm side, and a terminal on the side opposite to the load 64 of the inverter device 68 and on the lower arm side. . Although not shown in FIG. 24, each of the three terminals on the output side of the inverter device 68 is connected to the load 64 as a U phase, a V phase, and a W phase.

In the fourth embodiment, as the inverter device 68, the power conversion device 31 of the above-described third embodiment (see FIG. 23) can be used.

The AC power collected by the pantograph 61 from the overhead line 61 a is transformed by the converter device 66 into desired DC power after the voltage is transformed by the transformer 62. The DC power converted by the converter device 66 is smoothed by the capacitor 67. The DC power whose voltage has been smoothed by the capacitor 67 is converted into AC power by the inverter device 68. The AC power converted by the inverter device 68 is supplied to the load 64. The load 64 supplied with AC power rotationally drives the wheels 65, whereby the railway vehicle is accelerated.
≪Main features and effects of the fourth embodiment≫

As the inverter device 68 of the railway vehicle 60 of the fourth embodiment, the power conversion device 31 (see FIG. 23) of the above-described third embodiment can be used. As each of the

switching elements

37u, 37v, 37w, 37x, 37y, and 37z provided in the power conversion device 31, a semiconductor device having an element formation region in which the SiC-MOSFETs of Example 1 described above are arranged can be used. .

Similar to the third embodiment described above, the semiconductor device is composed of a SiC-MOSFET that can obtain a stable operation state even at a high temperature. Therefore, the reliability of the power module 35 and the power conversion device 31 at the high temperature operation is improved. Can be made. Further, even if the semiconductor device is operated at a high current density, it is possible to maintain a stable operation state in which the contact resistance does not fluctuate, so that the semiconductor device can be reduced in size, and accordingly, the power module 35 and the power conversion device 31 can be downsized.

Further, as the switching

elements

71 and 72 provided in the inverter device 68, a semiconductor device having an element formation region in which the SiC-MOSFETs of the first embodiment are arranged can be used. Therefore, the reliability of the inverter device 68 is improved and the size can be reduced. Therefore, in the railway vehicle 60 including the inverter device 68, the energy efficiency when operating the railway can be improved.

Similarly, as the switching

elements

69 and 70 provided in the converter device 66, a semiconductor device having an element formation region in which the SiC-MOSFETs of Example 1 described above are arranged can be used. Also in this case, the reliability of the converter device 66 is improved and the size can be reduced. Therefore, in the railway vehicle 60 including the converter device 66, the energy efficiency when operating the railway can be improved.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 n ⁺ type SiC substrate 2 n ⁻ type epitaxial layer 3 SiC epitaxial substrate 4 p type body region (well region)
5 n ⁺ type source region 5a 1n ⁺ type source region 5b 2n n ⁺ type source region 6 p ⁺ type potential fixing region 7 JFET region 8 channel region 9 n ⁺ type 3C-SiC region 9a n ⁺ type amorphous region 10 Gate insulation Film 11 Gate electrode 12 Interlayer insulating film 13 Opening 14 Barrier metal film 15 Source wiring electrode 16

Drain wiring electrodes

17 and 18 Mask pattern 19 Side wall 30 Three-phase motor system 31 Power converter 32 Load 33 DC power supply 34 Capacity 35 Power module 36

Control circuit

37u, 37v, 37w, 37x, 37y, 37z Switching element 38 MOSFET
39 body diode 60 railway vehicle 61 panda graph 61a overhead line 62 transformer 63 power converter 64 load 65 wheel 65a line 66 converter device 67 capacity 68

inverter devices

69, 70, 71, 72 switching elements T11, T12 input terminals TC1, TC2, TC3, TC4, TC5, TC6 Control terminal TO1, TO2, TO3 Output terminal

Claims

A first conductive substrate having a first main surface and a second main surface opposite to the first main surface, and made of silicon carbide;
The semiconductor layer of the first conductivity type made of silicon carbide formed on the first main surface of the substrate;
A plurality of first semiconductor regions of a second conductivity type different from the first conductivity type formed in the semiconductor layer from the upper surface of the semiconductor layer;
A second semiconductor region of the first conductivity type formed in the first semiconductor region from the upper surface of the semiconductor layer, spaced from the end side surface of the first semiconductor region;
A third semiconductor region of the second conductivity type formed so as to reach the first semiconductor region in the second semiconductor region from the upper surface of the semiconductor layer and spaced from the side surface of the end portion of the second semiconductor region; ,
The upper portion of the second semiconductor region between the end side surface of the second semiconductor region and the end side surface of the third semiconductor region is formed apart from the end side surface of the second semiconductor region. A fourth semiconductor region made of silicon carbide having a 3C crystal structure of the first conductivity type;
A channel region formed in an upper layer portion of the first semiconductor region between the end side surface of the first semiconductor region and the end side surface of the second semiconductor region;
A gate insulating film formed in contact with the channel region;
A gate electrode formed in contact with the gate insulating film;
An interlayer insulating film covering the gate electrode and having an opening through which the third semiconductor region and the fourth semiconductor region are exposed;
A barrier metal film formed on the interlayer insulating film in contact with the third semiconductor region and the fourth semiconductor region at a bottom surface of the opening and including an inner wall of the opening;
A first electrode formed on the barrier metal film;
A second electrode formed on the second main surface of the substrate;
A semiconductor device.
The semiconductor device according to claim 1,
The semiconductor device is a semiconductor device made of silicon carbide having a 4H crystal structure or a 6H crystal structure.
The semiconductor device according to claim 1,
The semiconductor device, wherein an impurity concentration of the fourth semiconductor region is higher than an impurity concentration of the second semiconductor region.
The semiconductor device according to claim 3.
The semiconductor device, wherein an impurity concentration of the fourth impurity region is 1 × 10 20 to 1 × 10 21 cm −3 .
The semiconductor device according to claim 1,
The distance from the edge part side surface of the said 2nd semiconductor region to the edge part side surface of the said 4th semiconductor region is a semiconductor device which is 0.3 micrometer or more.
The semiconductor device according to claim 1,
The semiconductor device, wherein the fourth semiconductor region is not formed in an upper layer portion of the third semiconductor region.
The semiconductor device according to claim 1,
The barrier metal film is a Ti film, a Ta film, a W film, a TiN film, a TaN film, a TiN / Ti laminated film with Ti as a lower layer, or a TaN / Ta laminated film with Ta as a lower layer.
A semiconductor device manufacturing method including the following steps:
(A) forming a first conductive type semiconductor layer made of silicon carbide on a first main surface of a first conductive type substrate made of silicon carbide;
(B) forming a plurality of first semiconductor regions having a first depth from the upper surface of the semiconductor layer and having a second conductivity type different from the first conductivity type in the semiconductor layer;
(C) The second semiconductor region of the first conductivity type having a second depth shallower than the first depth from the upper surface of the semiconductor layer is formed in the end portion of the first semiconductor region in the first semiconductor region. Forming a space apart from the side surface;
(D) A third semiconductor region of the second conductivity type having a third depth shallower than the first depth from the upper surface of the semiconductor layer and reaching the first semiconductor region is formed in the second semiconductor region. Forming the second semiconductor region apart from the side surface of the end,
(E) The first conductive type amorphous region having a fourth depth shallower than the second depth from the upper surface of the semiconductor layer is implanted into the second semiconductor by ion-implanting the first conductive type impurity. Forming an upper layer part of the region apart from an end side surface of the second semiconductor region;
(F) A step of performing a heat treatment after the step (e) so that the amorphous region becomes a fourth semiconductor region made of silicon carbide having a 3C crystal structure;
(G) forming a gate electrode on the upper surface of the first semiconductor region between the end side surface of the first semiconductor region and the end side surface of the second semiconductor region via a gate insulating film;
(H) forming an interlayer insulating film covering the gate electrode on the upper surface of the semiconductor layer, and then forming an opening reaching the third semiconductor region and the fourth semiconductor region in the interlayer insulating film;
(I) forming a barrier metal film in contact with the third semiconductor region and the fourth semiconductor region on the bottom surface of the opening on the interlayer insulating film including the inner wall of the opening;
(J) forming a first electrode on the barrier metal film;
(K) A step of forming a second electrode on a second main surface opposite to the first main surface of the substrate.
The method of manufacturing a semiconductor device according to claim 8.
The method for manufacturing a semiconductor device, wherein the semiconductor layer is made of silicon carbide having a 4H crystal structure or a 6H crystal structure.
The method of manufacturing a semiconductor device according to claim 8.
The barrier metal film is a Ti film, a Ta film, a W film, a TiN film, a TaN film, a TiN / Ti laminated film with Ti as a lower layer, or a TaN / Ta laminated film with Ta as a lower layer. Method.
A semiconductor device manufacturing method including the following steps:
(A) forming a first conductive type semiconductor layer made of silicon carbide on a first main surface of a first conductive type substrate made of silicon carbide;
(B) forming a plurality of first semiconductor regions having a first depth from the upper surface of the semiconductor layer and having a second conductivity type different from the first conductivity type in the semiconductor layer;
(C) The second semiconductor region of the second conductivity type having a second depth shallower than the first depth from the upper surface of the semiconductor layer, and an end portion of the first semiconductor region in the first semiconductor region Forming a space apart from the side surface;
(D) forming a mask pattern on the upper surface of the semiconductor layer, and ion-implanting the first conductivity type impurity into the first semiconductor region from the upper surface of the semiconductor layer via the mask pattern; The third semiconductor region of the first conductivity type having a third depth shallower than the first depth from the upper surface of the semiconductor layer is separated from the side surface of the end portion of the first semiconductor region in the first semiconductor region. Forming the process,
(E) forming a sidewall on the side wall of the opening of the mask pattern, and introducing the first conductivity type impurity into the third semiconductor region from the upper surface of the semiconductor layer via the mask pattern and the sidewall. Forming an amorphous region in the third semiconductor region by separating ions from the side surface of the end portion of the third semiconductor region by ion implantation;
(F) The fourth semiconductor region is formed by ion-implanting the first conductivity type impurity into the first semiconductor region below the amorphous region from the upper surface of the semiconductor layer via the mask pattern and the sidewall. Forming in the first semiconductor region under the amorphous region,
(G) After the step (f), the mask pattern and the sidewall are removed, and then a heat treatment is performed to make the amorphous region a fifth semiconductor region made of silicon carbide having a 3C crystal structure,
(H) forming a gate electrode on the upper surface of the first semiconductor region between the end side surface of the first semiconductor region and the end side surface of the third semiconductor region via a gate insulating film;
(I) forming an opening reaching the second semiconductor region and the fifth semiconductor region in the interlayer insulating film after forming an interlayer insulating film covering the gate electrode on the upper surface of the semiconductor layer;
(J) forming a barrier metal film in contact with the second semiconductor region and the fifth semiconductor region on the bottom surface of the opening on the interlayer insulating film including the inner wall of the opening;
(K) forming a first electrode on the barrier metal film;
(L) A step of forming a second electrode on the second main surface opposite to the first main surface of the substrate.
The method of manufacturing a semiconductor device according to claim 11.
The method for manufacturing a semiconductor device, wherein the semiconductor layer is made of silicon carbide having a 4H crystal structure or a 6H crystal structure.
The method of manufacturing a semiconductor device according to claim 11.
The barrier metal film is a Ti film, a Ta film, a W film, a TiN film, a TaN film, a TiN / Ti laminated film with Ti as a lower layer, or a TaN / Ta laminated film with Ta as a lower layer. Method.
A power module comprising the semiconductor device according to claim 1.
A power converter comprising the power module according to claim 14.
A railway vehicle that drives wheels with a three-phase motor system including the power conversion device according to claim 15.