WO2016002083A1 - Semiconductor device, power module and electric power converter - Google Patents

Abstract

This semiconductor device (1) comprises: a p-type body region (13) that is formed in an upper part of an n^--type epitaxial layer (12); an n⁺-type source region (14) that is formed in an upper part of the p-type body region (13); and a p⁺-type body contact region (15) that is formed in an upper part of the p-type body region (13). This semiconductor device (1) also comprises: a silicide film (SIL1) that is formed on the n⁺-type source region (14) and the p⁺-type body contact region (15); and a source electrode (21) that is formed on the silicide film (SIL1). The silicide film (SIL1) is Schottky-connected to the p⁺-type body contact region (15).

Description

Semiconductor device, power module and power conversion device

The present invention relates to a semiconductor device, a power module, and a power conversion device, and relates to a semiconductor device, a power module, and a power conversion device provided with a switching element.

2. Description of the Related Art An inverter device is used as a power conversion device for high power applications that converts electric power for driving a load for high power applications such as a motor between direct current and alternating current. Such an inverter device as a power converter for high power use includes a power module as an inverter circuit. This power module is a power module as an inverter circuit provided with a plurality of switching elements as semiconductor devices.

In addition, the breakdown electric field of a wide band gap semiconductor such as silicon carbide (SiC) is about 10 times larger than that of silicon (Si). For example, the withstand voltage (hereinafter also simply referred to as a withstand voltage) of a vertical MISFET (Metal Insulator Semiconductor Field Field Effect Transistor) as a switching element made of SiC is in a wide voltage range of several hundred volts to several kV. Therefore, development of a power conversion device including a power module including a vertical MISFET made of SiC has been underway as a power conversion device for high power applications described above.

International Publication No. 2007/013367 (Patent Document 1) describes a technique for a semiconductor element including a semiconductor layer made of silicon carbide. The semiconductor element described in Patent Document 1 includes a field effect transistor having a semiconductor layer made of silicon carbide and a first conductivity type, that is, an n-type drift region formed in the semiconductor layer.

International Publication No. 2007/013367

In the power module as an inverter circuit having a plurality of switching elements as described above, when the load connected to the output terminal of the power module has a large inductance, each of the plurality of switching elements is switched from the on state to the off state. At this time, a return current in a direction opposite to the direction of the on-state current of the switching element flows through the inverter circuit. Therefore, in the inverter circuit, it is necessary to provide a diode connected in parallel with each switching element in order to flow a reflux current.

On the other hand, the vertical MISFET has a body diode built in between the source electrode and the drain electrode, and a reflux current can flow through the body diode. Therefore, in a power module provided with a vertical MISFET as a switching element, it is not necessary to provide an external diode separately from the vertical MISFET.

However, in the case where the vertical MISFET provided in the power module as the inverter circuit is a vertical MISFET made of SiC, a current flowing through the body diode built in the vertical MISFET causes a deterioration in energization. The on-resistance of the type MISFET increases. When such energization deterioration occurs, power loss in the power module as the inverter circuit increases.

An object of the present invention is to provide a semiconductor device capable of preventing or suppressing the deterioration of energization when a reflux current flows through a body diode built in a vertical MISFET made of SiC. An object of the present invention is to provide a power module that includes the semiconductor device as described above and can reduce power loss due to energization deterioration, and a power conversion device including the power module.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to a representative embodiment is formed on a first main surface of a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface, and the first main surface of the semiconductor substrate. A first conductivity type semiconductor layer, and a second conductivity type first semiconductor region that is formed in an upper layer portion of the semiconductor layer and is different from the first conductivity type. The semiconductor device also includes a first conductivity type second semiconductor region formed in the upper layer portion of the first semiconductor region, and a second conductivity type third semiconductor formed in the upper layer portion of the first semiconductor region. And a gate electrode formed on a top surface of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor device is formed on the second main surface of the semiconductor substrate, the first metal film formed on the second semiconductor region and the third semiconductor region, the source electrode formed on the first metal film, and the semiconductor substrate. And a drain electrode. The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide. The first metal film is Schottky connected to the third semiconductor region.

A semiconductor device according to a representative embodiment includes a first conductive type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a first main surface of the semiconductor substrate. Are formed on the first main surface of the semiconductor substrate in a first region of the semiconductor substrate and a second region which is a region on the outer peripheral side of the semiconductor substrate relative to the first region. And a first conductivity type semiconductor layer. The semiconductor device is formed in an upper layer portion of the semiconductor layer in the first region, formed in a first semiconductor region of a second conductivity type different from the first conductivity type, and in an upper layer portion of the first semiconductor region. A first conductivity type second semiconductor region; and a second conductivity type third semiconductor region formed in an upper layer portion of the first semiconductor region. The semiconductor device includes a second conductivity type fourth semiconductor region formed in an upper layer portion of the semiconductor layer and a second conductivity type formed in an upper layer portion of the fourth semiconductor region in the second region. A fifth semiconductor region; and a gate electrode formed on a top surface of the first semiconductor region between the second semiconductor region and the semiconductor layer with a gate insulating film interposed therebetween. Further, the semiconductor device is formed on the first metal film formed on the second semiconductor region and the third semiconductor region, the second metal film formed on the fifth semiconductor region, and the first metal film. A source electrode formed on the second metal film, a contact electrode formed on the second metal film, and a drain electrode formed on the second main surface of the semiconductor substrate. The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are made of silicon carbide, and the concentration of the p-type impurity in the fifth semiconductor region is The concentration is lower than the concentration of the p-type impurity in the three semiconductor regions.

A semiconductor device according to a representative embodiment includes a first conductive type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a first main surface of the semiconductor substrate. Are formed on the first main surface of the semiconductor substrate in a first region of the semiconductor substrate and a second region which is a region on the outer peripheral side of the semiconductor substrate relative to the first region. And a first conductivity type semiconductor layer. The semiconductor device is formed in an upper layer portion of the semiconductor layer in the first region, formed in a first semiconductor region of a second conductivity type different from the first conductivity type, and in an upper layer portion of the first semiconductor region. A first conductivity type second semiconductor region; and a second conductivity type third semiconductor region formed in an upper layer portion of the first semiconductor region. The semiconductor device includes a second conductivity type fourth semiconductor region formed in an upper layer portion of the semiconductor layer and a second conductivity type formed in an upper layer portion of the fourth semiconductor region in the second region. A fifth semiconductor region; and a gate electrode formed on a top surface of the first semiconductor region between the second semiconductor region and the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor device is formed on the second semiconductor region and the third semiconductor region, and includes a first metal film made of a metal silicide and a source electrode made of a first conductive film formed on the first metal film. And a contact electrode made of a second conductive film formed on the fifth semiconductor region, and a drain electrode formed on the second main surface of the semiconductor substrate. The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are made of silicon carbide. The second conductive film is formed in the same layer as the first conductive film, and the contact electrode is in contact with the fifth semiconductor region.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

According to a typical embodiment, in a semiconductor device, it is possible to prevent or suppress the occurrence of deterioration of energization when a reflux current flows through a body diode built in a vertical MISFET made of SiC.

1 is a plan view of a semiconductor device according to a first embodiment. 2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. FIG. 4 is a flowchart showing a part of the manufacturing process of the semiconductor device of First Embodiment; 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. It is a figure which shows the structure of the motor system of Embodiment 1. FIG. It is a graph which shows the result of having measured the specific contact resistance between a p ⁺ type body contact region and a silicide film. It is a graph which shows the result of having measured the current-voltage curve between a p ⁺ type body contact region and a silicide film. It is principal part sectional drawing of the semiconductor device of a comparative example. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 2; FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 3; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. It is a figure which shows the structure of the three-phase motor system of Embodiment 4. FIG. FIG. 10 is a diagram showing a configuration of an electric vehicle as an automobile according to a fifth embodiment. FIG. 10 is a circuit diagram showing a boost converter device in an automobile according to a fifth embodiment. FIG. 10 is a diagram showing a configuration of a railway vehicle according to a sixth embodiment.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

Also, in the following embodiments, when ranges are indicated as A to B, A to B are indicated unless otherwise specified.

(Embodiment 1)
<Semiconductor device>
A semiconductor device according to the first embodiment of the present invention will be described. The semiconductor device according to the first embodiment includes a vertical MISFET made of silicon carbide (SiC).

FIG. 1 is a plan view of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. 2 is a cross section of a portion located in the active region AR1 and the termination region AR2, and is a cross section taken along the line AA in FIG. 1, and a cross section of a portion located in the gate pad region AR3. A cross section along the line BB is shown.

As shown in FIGS. 1 and 2, the semiconductor device 1 of the first embodiment has an n ⁺ type SiC substrate 10 as a semiconductor substrate. The n ⁺ -type SiC substrate 10 is an n-type semiconductor substrate made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. That is, the conductivity type of n ⁺ -type SiC substrate 10 as a semiconductor substrate is n-type. The concentration of the n-type impurity in the n ⁺ -type SiC substrate 10 is relatively large, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The thickness of the n ⁺ type SiC substrate 10 is, for example, about 50 to 500 μm.

The n ⁺ -type SiC substrate 10 has an upper surface 10a as one main surface and a lower surface 10b as the other main surface. The n ⁺ -type SiC substrate 10 is an active region AR1 that is a partial region of the upper surface 10a and another region of the upper surface 10a, and the n ⁺ -type SiC substrate is larger than the active region AR1 in plan view. 10 has a termination region AR2 which is a region on the outer peripheral side, and a gate pad region AR3.

In the present specification, in the plan view, the term “when viewed from a direction perpendicular to the upper surface 10a of the n ⁺ -type SiC substrate 10” is meant.

In the example shown in FIG. 1, the active region AR ^< b> 1 is a region disposed on the center side of the upper surface 10 a of the n ⁺ type SiC substrate 10. In the active region AR1, a plurality of cells CL1 made of vertical MISFETs are formed on the n ⁺ -type SiC substrate 10, and the plurality of cells CL1 are arranged in a matrix, for example, in plan view. Termination region AR2 is a region arranged on the outer peripheral side of upper surface 10a of n ⁺ -type SiC substrate 10 so as to surround active region AR1. A gate pad 19a is disposed in the gate pad region AR3.

As shown in FIGS. 1 and 2, in the active region AR1, the semiconductor device 1 includes an n ⁺ -type SiC substrate 10, an n ⁻ -type epitaxial layer 12, a p-type body region 13 and an n ⁺ -type source region 14. , P ⁺ type body contact region 15. In the active region AR1, the semiconductor device 1 includes a gate insulating film 18, a gate electrode 19, an interlayer insulating film 20, a silicide film SIL1, a source electrode 21, and a drain electrode 22.

On the other hand, in termination region AR2, semiconductor device 1 includes n ⁺ type SiC substrate 10, n ⁻ type epitaxial layer 12, p type body regions 13a and 13b, n ⁺ type source region 14a, and n ⁺ type field stopper. Region 14b, p ⁺ type body contact region 15a, and contact region 15b are provided. In the termination region AR2, the semiconductor device 1 includes a field oxide film FO1, a gate insulating film 18, a gate electrode 19, an interlayer insulating film 20, a silicide film SIL2, a contact electrode 21a, a drain electrode 22, Have

N ⁻ type epitaxial layer 12, p type body region 13 a, n ⁺ type source region 14 a, p ⁺ type body contact region 15 a, gate insulating film 18, and gate electrode 19 form a dummy cell. The dummy cell does not operate as a vertical MISFET, but adjusts the electric field in the cell CL1 formed of adjacent vertical MISFETs.

Furthermore, in gate pad region AR3, semiconductor device 1 has an n ⁺ type SiC substrate 10, an n ⁻ type epitaxial layer 12, and a p type body region 13c. In the gate pad region AR3, the semiconductor device 1 includes a field oxide film FO1, an insulating film 18a, a gate pad 19a, an interlayer insulating film 20, a gate contact electrode GC1, and a drain electrode 22.

The n ⁻ -type epitaxial layer 12 is formed on the upper surface 10a of the n ⁺ -type SiC substrate 10 in the active region AR1, the termination region AR2, and the gate pad region AR3. For example, the n ⁻ -type epitaxial layer 12 includes n (such as nitrogen (N) or phosphorus (P)). This is an n-type semiconductor layer made of silicon carbide (SiC) into which a type impurity is introduced. That is, the conductivity type of the n ⁻ type epitaxial layer 12 as the semiconductor layer is n type. The concentration of the n-type impurity in the n ⁻ -type epitaxial layer 12 is lower than the concentration of the n-type impurity in the n ⁺ -type SiC substrate 10, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . Further, the thickness of the n ⁻ type epitaxial layer 12 is, for example, about 5 to 50 μm.

In the example shown in FIG. 2, the n ⁻ type epitaxial layer 12 is formed directly on the upper surface 10 a of the n ⁺ type SiC substrate 10. However, n ⁻ type epitaxial layer 12 may be formed on upper surface 10a of n ⁺ type SiC substrate 10 via a buffer layer.

The n ⁻ type epitaxial layer 12 can be formed by, for example, an epitaxial growth method. Alternatively, for example, by ion implantation of p-type impurity such as aluminum (Al) or boron (B) was injected on the entire upper surface of the ^{n +} -type SiC substrate 10, reducing the concentration of n-type impurity in the ^{n +} -type SiC substrate 10 The n ⁻ type epitaxial layer 12 can also be formed by the method.

In the following, it is assumed that the n ⁻ type epitaxial layer 12 is formed by, for example, an epitaxial growth method, and the interface between the n ⁺ type SiC substrate 10 and the n ⁻ type epitaxial layer 12 is displayed as the upper surface 10a of the n ⁺ type SiC substrate 10. To do. However, the n ⁻ type epitaxial layer 12 may be formed by, for example, an ion implantation method, and the upper surface of the n ⁻ type epitaxial layer 12 may be displayed as the upper surface 10a of the n ⁺ type SiC substrate 10.

A p-type body region 13 is formed in an upper layer portion of the n ⁻ -type epitaxial layer 12 in the active region AR1. The p-type body region 13 is a p-type semiconductor region made of silicon carbide (SiC) into which a p-type impurity such as aluminum (Al) or boron (B) is introduced. That is, the conductivity type of the p-type body region 13 as a semiconductor region is p-type. The concentration of the p-type impurity in the p-type body region 13 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the p-type body region 13 is, for example, about 1 to 2 μm.

In termination region AR2, p type body regions 13a and 13b are formed in the upper layer portion of n ⁻ type epitaxial layer 12. In the gate pad region AR3, a p-type body region 13c is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12. The p- type body regions 13a, 13b and 13c are p-type semiconductor regions made of silicon carbide (SiC) into which a p-type impurity such as aluminum (Al) or boron (B) is introduced.

The p-type body region 13a is the termination region AR2 and is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12 that is located on the active region AR1 side in plan view. The concentration of the p-type impurity in the p-type body region 13 a can be made the same as the concentration of the p-type impurity in the p-type body region 13, and the thickness of the p-type body region 13 a is equal to the thickness of the p-type body region 13. The same can be done.

The p-type body region 13b is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12 at a portion located on the opposite side of the active region AR1 side in plan view in the termination region AR2. The concentration of the p-type impurity in the p-type body region 13b is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the p-type body region 13b is, for example, about 1 to 2 μm.

The strength of the electric field in the vicinity of the n ⁻ -type epitaxial layer 12 in the termination region AR2 becomes larger than the strength of the electric field in the vicinity of the n ⁻ -type epitaxial layer 12 in the active region AR1, and the breakdown voltage of the semiconductor device 1 may be reduced. . Therefore, preferably, the concentration of p-type impurity in p-type body region 13b is lower than the concentration of p-type impurity in p-type body region 13. Thus, the strength of the electric field in the vicinity of the p-type body region 13b in the termination region AR2 is prevented or suppressed from becoming larger than the strength of the electric field in the vicinity of the p-type body region 13 in the active region AR1, and the semiconductor device 1 The breakdown voltage can be improved.

The concentration of the p-type impurity in the p-type body region 13 c can be made the same as the concentration of the p-type impurity in the p-type body region 13, and the thickness of the p-type body region 13 c can be set to It can be similar to the thickness.

In the active region AR1, an n ⁺ type source region 14 is formed in an upper layer portion of the p type body region 13. The n ⁺ -type source region 14 is an n-type semiconductor region made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. That is, the conductivity type of the n ⁺ type source region 14 as the semiconductor region is n type. The concentration of the n-type impurity in the n ⁺ -type source region 14 is higher than the concentration of the n-type impurity in the n ⁻ -type epitaxial layer 12, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . Further, the thickness of the n ⁺ -type source region 14 is, for example, about 100 to 500 nm.

In the termination region AR2, an n ⁺ type source region 14a is formed in the upper layer portion of the p type body region 13a. The n ⁺ -type source region 14a is an n-type semiconductor region made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. The concentration of the n-type impurity in the n ⁺ -type source region 14a, can be similar to the concentration of the n-type impurity in the ^{n +} -type source region 14, the thickness of the ^{n +} -type source region 14a, ^{n +} -type source region A thickness of 14 can be used.

In the termination region AR2, the n ⁺ -type field stopper region 14b is formed on the upper layer portion of the n ⁻ -type epitaxial layer 12 in a portion located on the outer peripheral side of the n ⁺ -type SiC substrate 10 with respect to the p-type body region 13b in plan view. Is formed. The n ⁺ -type field stopper region 14b is an n-type semiconductor region made of silicon carbide (SiC) into which an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. The concentration of the n-type impurity in the n ⁺ -type field stopper region 14 b is higher than the concentration of the n-type impurity in the n ⁻ -type epitaxial layer 12, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . Further, the thickness of the n ⁺ -type field stopper region 14b is, for example, about 100 to 500 nm.

A p ⁺ type body contact region 15 is formed in an upper layer portion of the p type body region 13 in the active region AR1. The p ⁺ -type body contact region 15 is a p-type semiconductor region made of silicon carbide (SiC) into which a p-type impurity such as aluminum (Al) or boron (B) is introduced. That is, the conductivity type of the p ⁺ -type body contact region 15 as the semiconductor region is p-type. The concentration of the p-type impurity in the p ⁺ -type body contact region 15 is higher than the concentration of the p-type impurity in the p-type body region 13. The thickness of the p ⁺ type body contact region 15 is, for example, about 100 to 500 nm. A suitable concentration of the p-type impurity in the p ⁺ -type body contact region 15 will be described later.

In termination region AR2, p ⁺ type body contact region 15a and contact region 15b are formed in the upper layer portion of p type body region 13a. The p ⁺ type body contact region 15a and the contact region 15b are p type semiconductor regions made of silicon carbide (SiC) into which a p type impurity such as aluminum (Al) or boron (B) is introduced.

The p ⁺ -type body contact region 15a is the termination region AR2 and is formed in the upper layer portion of the p-type body region 13a that is located on the active region AR1 side in plan view. The concentration of the p-type impurity in the p ⁺ -type body contact region 15a is higher than the concentration of the p-type impurity in the p-type body region 13a. Further, the concentration of the p-type impurity in the p ⁺ -type body contact region 15a, can be similar to the concentration of the p-type impurity in the p ⁺ -type body contact region 15, the thickness of the p ⁺ -type body contact region 15a, The thickness can be the same as the thickness of the p ⁺ type body contact region 15.

The contact region 15b is the termination region AR2, and is formed in the upper layer portion of the p-type body region 13a that is located on the opposite side of the active region AR1 in plan view. The concentration of p-type impurity in contact region 15b is higher than the concentration of p-type impurity in p-type body region 13a. Further, the thickness of the contact region 15b is, for example, about 100 to 500 nm. A suitable concentration of the p-type impurity in the contact region 15b will be described later.

In the active region AR1, the upper layer portion of the n ⁻ -type epitaxial layer 12 sandwiched between two adjacent p-type body regions 13 is a JFET (Junction Field Effect Transistor) region 16. In other words, the JFET region 16 is the upper layer portion of the n ⁻ type epitaxial layer 12 that is located on the opposite side of the n ⁺ type source region 14 across the p type body region 13. The upper layer portion of the p-type body region 13 sandwiched between the n ⁺ -type source region 14 and the n ⁻ -type epitaxial layer 12 is a channel region 17.

In termination region AR2, field oxide film FO1 is formed on n ⁻ type epitaxial layer 12, on p type body regions 13a and 13b, on n ⁺ type field stopper region 14b, and on contact region 15b. The field oxide film FO1 is formed on the p-type body region 13c in the gate pad region AR3. As the field oxide film FO1, various films made of, for example, silicon oxide (SiO ₂ ) can be used.

A gate insulating film 18 is formed on the upper surface of the p-type body region 13 in the active region AR1. The gate insulating film 18 is an insulating film formed on the upper surface of the p-type body region 13 sandwiched between the n ⁺ -type source region 14 and the n ⁻ -type epitaxial layer 12. The gate insulating film 18 is made of, for example, silicon oxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or the like, for example, thermal oxidation or CVD (Chemical Vapor Deposition). ) Method. The thickness of the gate insulating film 18 is, for example, about several tens of nm. The gate insulating film 18 is formed in the termination region AR2, for example, on the p-type body region 13 and the field oxide film FO1.

In the gate pad region AR3, an insulating film 18a is formed on the field oxide film FO1. The insulating film 18 a can be made of an insulating film formed in the same layer as the insulating film included in the gate insulating film 18.

A gate electrode 19 is formed on the gate insulating film 18 in the active region AR1. The gate electrode 19 is formed on the upper surface of the p-type body region 13 sandwiched between the n ⁺ -type source region 14 and the n ⁻ -type epitaxial layer 12 via a gate insulating film 18. The gate electrode 19 is made of, for example, polysilicon, and is a conductive film formed by, for example, a CVD method.

In the gate pad region AR3, a gate pad 19a is formed on the insulating film 18a. The gate pad 19 a can be made of a conductive film formed in the same layer as the conductive film included in the gate electrode 19.

A gate electrode 19 and a gate insulating film 18 are formed on the n ⁻ type epitaxial layer 12, the p type body region 13, the n ⁺ type source region 14, and the p ⁺ type body contact region 15 in the active region AR 1. An interlayer insulating film 20 is formed so as to cover it. Interlayer insulating film 20 is in termination region AR2, on n ⁻ type epitaxial layer 12, on p type body region 13a, on n ⁺ type source region 14a, on p ⁺ type body contact region 15a, and in the field oxide film. On FO1, it forms so that the gate insulating film 18 may be covered. The interlayer insulating film 20 is formed on the field oxide film FO1 so as to cover the gate pad 19a and the insulating film 18a in the gate pad region AR3. As a material of the interlayer insulating film 20, for example, PSG (Phospho Silicate Glass) or silicon oxide can be used.

A contact hole 20a as an opening is formed in the interlayer insulating film 20 in the active region AR1. Contact hole 20 a penetrates interlayer insulating film 20 and gate insulating film 18 and reaches the upper surface of n ⁺ -type source region 14 and the upper surface of p ⁺ -type body contact region 15. That is, the upper surface of the n ⁺ type source region 14 and the upper surface of the p ⁺ type body contact region 15 are exposed at the bottom of the contact hole 20a.

A contact hole 20b as an opening is formed in the interlayer insulating film 20 in the termination region AR2. Contact hole 20b penetrates through interlayer insulating film 20, gate insulating film 18 and field oxide film FO1, and reaches the upper surface of contact region 15b. That is, the upper surface of the contact region 15b is exposed at the bottom of the contact hole 20b. As shown in FIG. 2, contact hole 20b passes through interlayer insulating film 20, gate insulating film 18 and field oxide film FO1, and reaches the upper surface of p-type body region 13a adjacent to contact region 15b. May be. That is, the upper surface of the p-type body region 13a adjacent to the contact region 15b may be exposed at the bottom of the contact hole 20b.

In the gate pad region AR3, the interlayer insulating film 20 has a contact hole 20c as an opening. The contact hole 20c penetrates the interlayer insulating film 20 and reaches the upper surface of the gate pad 19a. That is, the upper surface of the gate pad 19a is exposed at the bottom of the contact hole 20c.

In the active region AR1, a silicide film SIL1 made of a metal silicide is formed as a metal film on the n ⁺ type source region 14 and the p ⁺ type body contact region 15 exposed at the bottom of the contact hole 20a. Is formed. A suitable composition of the silicide film SIL1 will be described later.

A silicide film SIL2 made of a metal silicide is formed as a metal film on the contact region 15b exposed at the bottom of the contact hole 20b in the termination region AR2. Silicide film SIL2 may be formed on a portion exposed at the bottom of contact hole 20b and on p-type body region 13a adjacent to contact region 15b. A suitable composition of the silicide film SIL2 will be described later.

In the active region AR1, a source electrode 21 is formed in the contact hole 20a, on the silicide film SIL1, and on the interlayer insulating film 20. The source electrode 21 is an electrode formed on the silicide film SIL1, and is electrically connected to the silicide film SIL1. As the source electrode 21, a conductive film made of, for example, titanium (Ti) or aluminum (Al) can be used. By using such a conductive film, the source electrode 21 and the silicide film SIL1 can be electrically connected with low resistance.

On the other hand, in the termination region AR2, a contact electrode 21a is formed in the contact hole 20b, on the silicide film SIL2, and on the interlayer insulating film 20. The contact electrode 21a is an electrode formed on the silicide film SIL2, and is electrically connected to the silicide film SIL2. As the contact electrode 21a, for example, a conductive film made of titanium (Ti) or aluminum (Al) can be used. By using such a conductive film, the contact electrode 21a and the silicide film SIL2 can be electrically connected with low resistance. As shown in FIG. 2, the contact electrode 21 a may be formed in the same layer as the source electrode 21 or may be electrically connected to the source electrode 21.

In the gate pad region AR3, a gate contact electrode GC1 is formed inside the contact hole 20c and on the interlayer insulating film 20. The gate contact electrode GC1 is an electrode formed on the gate pad 19a and is electrically connected to the gate pad 19a. As the gate contact electrode GC1, for example, a conductive film made of titanium (Ti) or aluminum (Al) can be used. By using such a conductive film, the gate contact electrode GC1 and the gate pad 19a can be electrically connected with low resistance.

A drain electrode 22 is formed on the lower surface 10b of the n ⁺ -type SiC substrate 10 in the active region AR1, the termination region AR2, and the gate pad region AR3. The drain electrode 22 is electrically connected to the n ⁺ type SiC substrate 10. As the drain electrode 22, for example, a conductive film in which titanium (Ti), nickel (Ni), gold (Au), or the like is stacked can be used. By using such a conductive film, the drain electrode 22 and the n ⁺ -type SiC substrate 10 can be electrically connected with low resistance.

Although not shown in FIG. 2, a passivation film is formed on the upper and lower surfaces of the semiconductor device 1 so as to cover the interlayer insulating film 20, the source electrode 21, the contact electrode 21a, the gate contact electrode GC1, and the drain electrode 22. May be. Further, in the passivation film, an opening may be formed in a portion where a pad region for electrically connecting the source electrode 21, the gate contact electrode GC1, and the drain electrode 22 to the outside is formed. .

In the ON operation of turning on the vertical MISFET represented by the cell CL1 in the semiconductor device 1, a positive gate voltage VGS (VGS> 0V) is applied to the source electrode 21 to the gate electrode 19. At this time, an inversion layer is formed in the upper layer portion of the p-type body region 13 sandwiched between the n ⁺ -type source region 14 and the n ⁻ -type epitaxial layer 12, that is, in the channel region 17.

Therefore, electrons flow from the source electrode 21 to the drain electrode 22 through the n ⁺ type source region 14, the inversion layer formed in the channel region 17, the n ⁻ type epitaxial layer 12, and the n ⁺ type SiC substrate 10. That is, current flows from the drain electrode 22 to the source electrode 21 through the n ⁺ -type SiC substrate 10, the n ⁻ -type epitaxial layer 12, the inversion layer formed in the channel region 17, and the n ⁺ -type source region 14.

On the other hand, in the off operation for turning off the vertical MISFET represented by the cell CL1, a negative or zero gate voltage VGS (VGS ≦ 0V) is applied to the gate electrode 19 with respect to the source electrode 21. At this time, the current is interrupted by eliminating the inversion layer formed in the channel region 17.

In the active region AR1, a diode embedded between the source electrode 21 and the drain electrode 22 by the p ⁺ type body contact region 15, the p type body region 13, the n ⁻ type epitaxial layer 12 and the n ⁺ type SiC substrate 10, That is, the body diode 23 is formed. In the termination region AR2, a diode, that is, a body built between the contact electrode 21a and the drain electrode 22 by the contact region 15b, the p-type body region 13a, the n ⁻ -type epitaxial layer 12 and the n ⁺ -type SiC substrate 10 is used. A diode 23a is formed.

As will be described later with reference to FIG. 14, when a plurality of semiconductor devices 1 are included in an inverter circuit, each vertical MISFET represented by a cell CL1 in each semiconductor device 1 is switched from an on state to an off state. A reflux current flows through the body diodes 23 and 23a. In addition, in the semiconductor device 101 of the comparative example which will be described later with reference to FIG.

On the other hand, in the semiconductor device 1 of the first embodiment, the silicide film SIL1 is provided between the p ⁺ type body contact region 15 and the source electrode 21 in the active region AR1. The silicide film SIL1 is Schottky connected to the p ⁺ type body contact region 15.

Thus, when a reflux current flows through the body diode 23 in the active region AR1, holes are not easily supplied from the silicide film SIL1 to the p ⁺ -type body contact region 15, and electrons flow to the vicinity of the source electrode 21. Therefore, recombination of holes and electrons flowing as a reflux current can be prevented or suppressed in various crystal defects existing in the n ⁻ type epitaxial layer 12 and the like in the active region AR1. Accordingly, various crystal defects are prevented or suppressed from expanding in the n ⁻ -type epitaxial layer 12 and the like, and an electrical resistance when an on-current flows through the semiconductor device 1, that is, an on-resistance is prevented or suppressed from increasing. be able to. Therefore, it is possible to prevent or suppress the occurrence of energization deterioration of the semiconductor device 1 when the return current flows through the body diode 23 incorporated in the semiconductor device 1 included in the power module as the inverter circuit.

For example, the work function phi _m silicide film SIL1 is, when the electron affinity χ of the ^{p +} -type body contact region 15, smaller than the sum of the band gap _{E g} of the ^{p +} -type body contact region 15, the silicide film SIL1 , P ⁺ type body contact region 15 and Schottky connection. The electron affinity χ work function phi _m, ^{p +} -type body contact region 15 in such a silicide layer SIL 1, and, for the band gap _{E g} of the ^{p +} -type body contact region 15, X-ray photoelectron spectroscopy (X-ray It can be measured by Photoelectron Spectroscopy (XPS) or Ultraviolet Photoelectron Spectroscopy (UPS).

Alternatively, when the composition of the silicide film SIL1 or the composition of the p ⁺ type body contact region 15 is as follows, the silicide film SIL1 is Schottky connected to the p ⁺ type body contact region 15.

For example, the concentration of the p-type impurity in the ^{p +} -type body contact region 15, preferably to 2 × ¹⁰ 19 ^{cm -3} or more less than 1 × ¹⁰ 20 ^{cm -3,} 2 × ¹⁰ 19 ^{cm -3} or more 7 × 10 More preferably, it is less than ¹⁹ cm ⁻³ . As will be described later with reference to FIGS. 15 and 16, the silicide film SIL1 is made to be p ⁺ type body contact by setting the p type impurity concentration in the p ⁺ type body contact region 15 to be less than 1 × 10 ²⁰ cm ^−3. The area 15 can be connected to the Schottky. Further, by setting the concentration of the p-type impurity in the p ⁺ type body contact region 15 to be less than 7 × 10 ¹⁹ cm ⁻³ , the silicide film SIL1 can be easily Schottky connected to the p ⁺ type body contact region 15. it can.

On the other hand, by setting the concentration of the p-type impurity in the p ⁺ -type body contact region 15 to 2 × 10 ¹⁹ cm ⁻³ or more, the silicide film SIL1 and p ^{+ are formed} by the source electrode 21 when the vertical MISFET is turned on. The potential of p type body region 13 can be adjusted via type body contact region 15.

For example, the silicide film SIL1 preferably includes nickel silicide such as Ni ₂ Si or NiSi, that is, nickel silicide. Thereby, the silicide film SIL1 can be easily Schottky connected to the p ⁺ type body contact region 15. Note that since the p ⁺ type body contact region 15 and the n ⁺ type source region 14 are made of silicon carbide, the silicide film SIL1 also contains carbon.

More preferably, the composition ratio of nickel to the sum of nickel and silicon in the silicide film SIL1 is larger than 0.4 and smaller than 0.7. In other words, the ratio of the number of nickel atoms to the sum of the number of nickel atoms and the number of silicon atoms in the silicide film SIL1 is larger than 0.4 and smaller than 0.7. Thereby, the silicide film SIL1 can be more easily Schottky connected to the p ⁺ type body contact region 15.

Further, in the semiconductor device 1 of the first embodiment, the silicide film SIL2 is provided between the contact region 15b and the contact electrode 21a in the termination region AR2. The silicide film SIL2 is Schottky connected to the contact region 15b.

As a result, when a return current flows through the body diode 23a in the termination region AR2, it is difficult for holes to be supplied from the silicide film SIL2 to the contact region 15b, and electrons flow to the vicinity of the contact electrode 21a. Therefore, in the termination region AR2, recombination of holes and electrons flowing as a reflux current can be prevented or suppressed in various crystal defects existing in the n ⁻ type epitaxial layer 12 and the like. Accordingly, various crystal defects are prevented or suppressed from expanding in the n ⁻ -type epitaxial layer 12 and the like, and an electrical resistance when an on-current flows through the semiconductor device 1, that is, an on-resistance is prevented or suppressed from increasing. be able to. Therefore, it is possible to prevent or suppress the occurrence of deterioration in energization of the semiconductor device 1 when the return current flows through the body diode 23a built in the semiconductor device 1 included in the power module as the inverter circuit.

For example, the concentration of the p-type impurity in the contact regions 15b, 2 × ¹⁰ 19 ^{cm -3} to 1 × ¹⁰ preferably less than ^{20 cm -3, 2 × 10 19} cm -3 or more 7 × ¹⁰ 19 ^{cm -3} More preferably, it is less than. As will be described later with reference to FIGS. 15 and 16, the silicide film SIL2 is Schottky connected to the contact region 15b by setting the concentration of the p-type impurity in the contact region 15b to less than 1 × 10 ²⁰ cm ^−3. Can do. Further, by making the concentration of the p-type impurity in the contact region 15b less than 7 × 10 ¹⁹ cm ⁻³ , the silicide film SIL2 can be easily Schottky connected to the contact region 15b.

On the other hand, by setting the concentration of the p-type impurity in the contact region 15b to 2 × 10 ¹⁹ cm ⁻³ or more, when the vertical MISFET is in the on state, the contact electrode 21a causes the silicide film SIL2 and the contact region 15b to pass through. The potential of p-type body region 13a can be adjusted.

Preferably, the silicide film SIL2 includes nickel silicide such as Ni ₂ Si or NiSi, that is, nickel silicide. Thereby, the silicide film SIL2 can be easily Schottky connected to the contact region 15b. As in the silicide film SIL1, the silicide film SIL2 also contains carbon.

More preferably, the composition ratio of nickel to the sum of nickel and silicon in the silicide film SIL2 is larger than 0.4 and smaller than 0.7. In other words, the ratio of the number of nickel atoms to the sum of the number of nickel atoms and the number of silicon atoms in the silicide film SIL2 is larger than 0.4 and smaller than 0.7. Thereby, the silicide film SIL2 can be more easily Schottky connected to the contact region 15b.

Note that the source electrode 21, p ⁺ -type body contact region 15 only to be connected to the Schottky, between the source electrode 21 and the p ⁺ -type body contact region 15, instead of the silicide film SIL 1, other than the metal silicide A metal film can also be interposed. The contact electrode 21a only needs to be Schottky connected to the contact region 15b, and a metal film other than the metal silicide can be interposed between the contact electrode 21a and the contact region 15b in place of the silicide film SIL2. .

<Manufacturing process of semiconductor device>
Next, an example of a manufacturing process of the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 3 is a flowchart showing a part of the manufacturing process of the semiconductor device of the first embodiment. 4 to 13 are fragmentary cross-sectional views of the semiconductor device of First Embodiment during the manufacturing process thereof. FIG. 3 shows a manufacturing process in the active area AR1.

First, an n ⁺ type SiC substrate 10 is prepared (step S11 in FIG. 3). In step S11, as shown in FIG. 4, an n ⁺ type SiC substrate 10 made of silicon carbide (SiC) into which an n type impurity such as nitrogen (N) or phosphorus (P) is introduced is prepared. As described above, the concentration of the n-type impurity in the n ⁺ -type SiC substrate 10 can be relatively high, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . In addition, the thickness of the n ⁺ -type SiC substrate 10 can be set to, for example, about 50 to 500 μm.

Next, the n ⁻ type epitaxial layer 12 is formed (step S12 in FIG. 3). In this step S12, as shown in FIG. 4, the n ⁻ type epitaxial layer 12 is formed on the upper surface 10a of the n ⁺ type SiC substrate 10 by the epitaxial growth method in the active region AR1, the termination region AR2 and the gate pad region AR3. For example, silicon (Si) atom-containing gas (SiH ₄ gas), chlorine (Cl) atom-containing gas (HCl gas), carbon (C) atom-containing gas (C ₃ H ₈ gas), reducing gas (H ₂ gas), etc. By using the substrate temperature of, for example, about 1500 to 1800 ° C., the n ⁻ type epitaxial layer 12 made of SiC is formed.

An n-type impurity such as nitrogen (N) or phosphorus (P) is introduced into the n ⁻ -type epitaxial layer 12. As described above, n ^- the density of the n-type impurity in the type epitaxial layer 12, for example, 1 × ^{10 15} can be a ~ 1 × ¹⁰ 16 ^{cm -3} approximately, n ^- the thickness of the type epitaxial layer 12, For example, the thickness can be about 5 to 50 μm.

Next, the p-type body region 13 is formed (step S13 in FIG. 3). In step S13, as shown in FIG. 5, first, a resist film RF1 is formed on the n ⁻ type epitaxial layer 12 in the active region AR1. Then, the formed resist film RF1 is exposed and developed using a photolithography technique to penetrate the resist film RF1 in a region where the p-type body region 13 is formed in the active region AR1. Thus, an opening OP1 reaching the n ⁻ type epitaxial layer 12 is formed. At this time, a resist pattern RP1 made of the resist film RF1 in which the opening OP1 is formed is formed, and the n ⁻ type epitaxial layer 12 is exposed at the bottom of the opening OP1.

In the example shown in FIG. 5, when the resist film RF1 is formed in the active region AR1, the resist film RF1 is formed on the n ⁻ type epitaxial layer 12 also in the termination region AR2. When the opening OP1 is formed, an opening OP11 that penetrates the resist film RF1 and reaches the n ⁻ type epitaxial layer 12 is also formed in the termination region AR2 in the region where the p-type body region 13a is formed. At this time, in the termination region AR2, the resist pattern RP1 is made of the resist film RF1 in which the opening OP11 is formed, and the n ⁻ type epitaxial layer 12 is exposed at the bottom of the opening OP11.

In the example shown in FIG. 5, when the resist film RF1 is formed in the active region AR1, the resist film RF1 is formed on the n ⁻ type epitaxial layer 12 also in the gate pad region AR3. Then, when the opening OP1 is formed, the resist film RF1 is removed in the gate pad region AR3.

Next, as shown in FIG. 5, a p-type impurity such as aluminum (Al) or boron (B) is applied to the n ⁻ -type epitaxial layer 12 by ion implantation using the resist pattern RP1 as a mask in the active region AR1. Introduce. As a result, the p-type body region 13 is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12. As described above, the concentration of the p-type impurity in the p-type body region 13 can be set to, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^−3, and the thickness of the p-type body region 13 is set to, for example, 1 It can be about 2 μm.

In the example shown in FIG. 5, when p-type impurities are introduced into the active region AR1, the n ⁻ -type epitaxial layer 12 is also doped with, for example, aluminum (Al) in the termination region AR2 by ion implantation using the resist pattern RP1 as a mask. ) Or p-type impurities such as boron (B) are introduced. As a result, the p-type body region 13a is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12 in the termination region AR2. The concentration of the p-type impurity in the p-type body region 13 a can be made the same as the concentration of the p-type impurity in the p-type body region 13, and the thickness of the p-type body region 13 a is equal to the thickness of the p-type body region 13. The same can be done.

Further, in the example shown in FIG. 5, when the p-type impurity is introduced into the active region AR1, the n ⁻ type epitaxial layer 12 is also formed on the n ⁻ -type epitaxial layer 12 in the gate pad region AR3. Type impurities are introduced. As a result, the p-type body region 13c is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12 in the gate pad region AR3. The concentration of the p-type impurity in the p-type body region 13c can be made the same as the concentration of the p-type impurity in the p-type body region 13, and the thickness of the p-type body region 13c is equal to the thickness of the p-type body region 13. The same can be done.

Next, as shown in FIG. 6, after removing the resist pattern RP1, a resist film RF2 is formed on the n ⁻ type epitaxial layer 12 and the p type body region 13a in the termination region AR2. Then, the formed resist film RF2 is exposed and developed using a photolithography technique to penetrate the resist film RF2 in the region of the termination region AR2 where the p-type body region 13b is formed. Thus, an opening OP2 reaching the n ⁻ type epitaxial layer 12 is formed. At this time, a resist pattern RP2 made of the resist film RF2 in which the opening OP2 is formed is formed, and the n ⁻ type epitaxial layer 12 is exposed at the bottom of the opening OP2.

In the example shown in FIG. 6, when the resist film RF2 is formed in the termination region AR2, the active region AR1 and the gate pad region AR3 are also on the n ⁻ type epitaxial layer 12 and the p type body regions 13 and 13c. Then, a resist film RF2 is formed. When the opening OP1 is formed, no opening is formed in the active region AR1 and the gate pad region AR3, and the n ⁻ -type epitaxial layer 12 and the p- type body regions 13 and 13c are formed in the resist film RF2. Covered.

Next, as shown in FIG. 6, in the termination region AR2, a p-type impurity such as aluminum (Al) or boron (B) is applied to the n ⁻ -type epitaxial layer 12 by ion implantation using the resist pattern RP2 as a mask. Introduce. As a result, a p-type body region 13 b is formed in the upper layer portion of the n ⁻ -type epitaxial layer 12. As described above, the concentration of the p-type impurity in the p-type body region 13b can be set to, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^−3, and the thickness of the p-type body region 13b can be set to, for example, 1 It can be about 2 μm.

Preferably, the concentration of the p-type impurity in the p-type body region 13b is lower than the concentration of the p-type impurity in the p-type body region 13. Thus, the strength of the electric field in the vicinity of the p-type body region 13b in the termination region AR2 is prevented or suppressed from becoming larger than the strength of the electric field in the vicinity of the p-type body region 13 in the active region AR1, and the semiconductor device 1 The breakdown voltage can be improved.

In addition, about the process of forming p-type body area | regions 13, 13a, 13b, and 13c, after these processes, it can heat-process at about 1700 degreeC, for example, and can implant | stimulate the implanted impurity. Further, mask patterns made of various films can be used in place of either the resist pattern made of the resist film RF1 or the resist pattern made of the resist film RF2.

Next, the p ⁺ type body contact region 15 is formed (step S14 in FIG. 3). In step S14, as shown in FIG. 7, after removing the resist pattern RP2, a resist film RF3 is formed on the n ⁻ type epitaxial layer 12 and the p type body region 13 in the active region AR1. Then, by performing exposure and development processing on the formed resist film RF3 using photolithography technology, the resist film RF3 is formed in the active region AR1 in the region where the p ⁺ -type body contact region 15 is formed. Opening OP3 penetrating to reach p-type body region 13 is formed. At this time, a resist pattern RP3 made of the resist film RF3 in which the opening OP3 is formed is formed, and the p-type body region 13 is exposed at the bottom of the opening OP3.

In the example shown in FIG. 7, when the resist film RF3 is formed in the active region AR1, the termination region AR2 is also on the n ⁻ type epitaxial layer 12, the p type body region 13a, and the p type body region 13b. Then, a resist film RF3 is formed. When the opening OP3 is formed, in the termination region AR2, an opening OP31 that penetrates the resist film RF3 and reaches the p-type body region 13a is formed. At this time, in the termination region AR2, the resist pattern RP3 is made of the resist film RF3 in which the opening OP31 is formed, and the p-type body region 13a is exposed at the bottom of the opening OP31.

In the example shown in FIG. 7, when the resist film RF3 is formed in the active region AR1, the resist film RF3 is also formed on the p-type body region 13c in the gate pad region AR3. When the opening OP3 is formed, no opening is formed in the gate pad region AR3, and the p-type body region 13c is covered with the resist film RF3.

Next, as shown in FIG. 7, a p-type impurity such as aluminum (Al) or boron (B) is introduced into the p-type body region 13 by ion implantation using the resist pattern RP3 as a mask in the active region AR1. To do. As a result, the p ⁺ type body contact region 15 is formed in the upper layer portion of the p type body region 13 in the active region AR1.

As described above, ^{p +} the concentration of the p-type impurity in the mold body contact region 15, preferably to 2 × ¹⁰ 19 ^{cm -3} or more less than 1 × ¹⁰ 20 ^{cm -3,} 2 × ¹⁰ 19 ^{cm -3} or more More preferably, it is less than 7 × 10 ¹⁹ cm ⁻³ . Thereby, as described later with reference to FIGS. 15 and 16, the silicide film SIL1 can be Schottky-connected to the p ⁺ type body contact region 15. Further, the thickness of the p ⁺ -type body contact region 15 can be set to about 100 to 500 nm, for example.

Here, Table 1 shows ion implantation conditions for setting the concentration of the p-type impurity in the p ⁺ -type body contact region 15 to 2 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²⁰ cm ⁻³ . That is, the conditions shown in Table 1 are conditions for Schottky connection of the silicide film SIL1 (see FIG. 11 described later) with the p ⁺ type body contact region 15.

Table 1 shows the implantation energy (keV) and dose (cm) in each step when the four steps of Step S21 to Step S24 are sequentially performed to implant ions of aluminum as a p-type impurity in four stages. ^-2 ).

Further, in the example shown in FIG. 7, when the p-type impurity is introduced into the active region AR1, the p-type such as aluminum (Al) or boron (B) is added to the n ⁻ -type epitaxial layer 12 also in the termination region AR2. Impurities are introduced. As a result, in the termination region AR2, the p ⁺ type body contact region 15a is formed in the upper layer portion of the p type body region 13a. The concentration of the p-type impurity in the p ⁺ -type body contact region 15a, ^{the p +} -type body contact region can be similar to the concentration of the p-type impurity at 15, the thickness of the ^{p +} -type body contact region 15a, ^{p +} The thickness of the mold body contact region 15 can be made the same.

Next, as shown in FIG. 8, after removing resist pattern RP3, in termination region AR2, on n ⁻ type epitaxial layer 12, on p type body regions 13a and 13b, and on p ⁺ type body contact region 15a. Then, a resist film RF4 is formed. Then, the formed resist film RF4 is exposed and developed using a photolithography technique, so that the resist film RF4 penetrates the resist film RF4 in the region of the termination region AR2 where the contact region 15b is formed. An opening OP4 reaching the mold body region 13a is formed. At this time, a resist pattern RP4 made of the resist film RF4 in which the opening OP4 is formed is formed, and the p-type body region 13a is exposed at the bottom of the opening OP4.

In the example shown in FIG. 8, when the resist film RF4 is formed in the termination region AR2, the active region AR1 and the gate pad region AR3 are also on the n ⁻ type epitaxial layer 12, the p type body regions 13 and 13c, and A resist film RF4 is formed on the p ⁺ type body contact region 15. When the opening OP4 is formed, no opening is formed in the active region AR1 and the gate pad region AR3, the n ⁻ type epitaxial layer 12, the p type body regions 13 and 13c, and the p ⁺ type body contact. The region 15 is covered with the resist film RF4.

Next, as shown in FIG. 8, in the termination region AR2, a p-type impurity such as aluminum (Al) or boron (B) is introduced into the p-type body region 13a by ion implantation using the resist pattern RP4 as a mask. To do. Thereby, the contact region 15b is formed in the upper layer portion of the p-type body region 13a in the termination region AR2. As described above, the concentration of the p-type impurity in the contact region 15b, it is preferable that a 2 × ¹⁰ 19 ^{cm -3} or more less than 1 × ¹⁰ 20 ^{cm -3,} 2 × ¹⁰ 19 ^{cm -3} or more 7 × ^{10 19} More preferably, it is less than cm ⁻³ . Thereby, as described later with reference to FIGS. 15 and 16, the silicide film SIL2 can be Schottky connected to the contact region 15b. Further, the thickness of the contact region 15b can be set to about 100 to 500 nm, for example.

The conditions for ion implantation for setting the concentration of the p-type impurity in the contact region 15b to 2 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²⁰ cm ⁻³ are shown in Table 1 for Schottky connection. The same conditions can be used.

Next, the n ⁺ type source region 14 is formed (step S15 in FIG. 3). In step S15, as shown in FIG. 9, after removing resist pattern RP4, in active region AR1, on n ⁻ type epitaxial layer 12, on p type body region 13, and on p ⁺ type body contact region 15 Next, a resist film RF5 is formed. Then, the formed resist film RF5 is exposed and developed using a photolithography technique to penetrate the resist film RF5 in the region where the n ⁺ -type source region 14 is formed in the active region AR1. Thus, an opening OP5 reaching the p-type body region 13 is formed. At this time, a resist pattern RP5 made of the resist film RF5 in which the opening OP5 is formed is formed, and the p-type body region 13 is exposed at the bottom of the opening OP5.

In the example shown in FIG. 9, when the resist film RF5 is formed in the active region AR1, even in the termination region AR2, the n ⁻ type epitaxial layer 12, the p type body regions 13a and 13b, and the p ⁺ type body contact region 15a. A resist film RF5 is formed above and on the contact region 15b. When the opening OP5 is formed, in the termination region AR2, the opening OP51 that reaches the p-type body region 13a through the resist film RF5 and the n ⁻ -type epitaxial layer 12 through the resist film RF5 are formed. A reaching opening OP52 is formed. At this time, in the termination region AR2, the resist pattern RP5 is composed of the resist film RF5 in which the opening OP51 and the opening OP52 are formed. The p-type body region 13a is exposed at the bottom of the opening OP51, and the bottom of the opening OP52 The n ⁻ type epitaxial layer 12 is exposed.

In the example shown in FIG. 9, when the resist film RF5 is formed in the active region AR1, the resist film RF5 is formed on the p-type body region 13c also in the gate pad region AR3. When the opening OP5 is formed, no opening is formed in the gate pad region AR3, and the p-type body region 13c is covered with the resist film RF5.

Next, as shown in FIG. 9, n-type impurities such as nitrogen (N) or phosphorus (P) are introduced into the p-type body region 13 by ion implantation using the resist pattern RP5 as a mask in the active region AR1. To do. As a result, an n ⁺ type source region 14 is formed in the upper layer portion of the p type body region 13. As described above, the concentration of n-type impurity in the ^{n +} -type source region 14, for example, be a ^{1 × 10 19 ~ 1 × 10} 20 cm -3 or so, the thickness of the ^{n +} -type source region 14, For example, the thickness can be about 100 to 500 nm.

In the example shown in FIG. 9, when an n-type impurity is introduced into the active region AR1, an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced into the p-type body region 13 also in the termination region AR2. To do. Thereby, in termination region AR2, n ⁺ type source region 14a is formed in the upper layer portion of p type body region 13a, and n ⁺ type field stopper region 14b is formed in the upper layer portion of n ⁻ type epitaxial layer 12. . The concentration of the p-type impurity in the n ⁺ -type source region 14a and the ^{n +} -type field stop region 14b, can be similar to the concentration of the n-type impurity in the ^{n +} -type source region 14, ^{n +} -type source region 14a and n The thickness of the ⁺ type field stopper region 14 b can be made the same as the thickness of the n ⁺ type source region 14.

Note that the steps of forming n ⁺ type source regions 14 and 14a, n ⁺ type field stopper region 14b, p ⁺ type body contact regions 15 and 15a, and contact region 15b are not limited to the steps described above. As long as a resist film that is appropriately patterned is used as a mask, the resist film may be formed in any order. Also, mask patterns made of various films can be used instead of any of the resist pattern made of the resist film RF3, the resist pattern made of the resist film RF4, and the resist pattern made of the resist film RF5. Further, the steps of forming the n ⁺ type source regions 14 and 14a, the n ⁺ type field stopper region 14b, the p ⁺ type body contact regions 15 and 15a, and the contact region 15b are performed after each step or all of the steps. After the process is completed, heat treatment can be performed at about 1700 ° C., for example, to activate the implanted impurities.

Next, the gate insulating film 18 and the gate electrode 19 are formed (Step S16 in FIG. 3). In step S16, first, as shown in FIG. 10, in termination region AR2, on n ⁻ type epitaxial layer 12, on p type body regions 13a and 13b, on n ⁺ type field stopper region 14b, and contact region 15b. A field oxide film FO1 is formed thereon. As the field oxide film FO1, various films made of, for example, silicon oxide (SiO ₂ ) can be used. Further, the field oxide film FO1 can be formed by, for example, a CVD method. Further, when the field oxide film FO1 is formed in the termination region AR2, the field oxide film FO1 is formed on the p-type body region 13c also in the gate pad region AR3.

Next, as shown in FIG. 10, in the active region AR1 and the termination region AR2, on the n ⁻ type epitaxial layer 12, on the p type body regions 13 and 13a, on the n ⁺ type source regions 14 and 14a, and the p ⁺ type body contact. An insulating film 18b is formed on regions 15 and 15a and on field oxide film FO1. As the insulating film 18b, various films made of, for example, silicon oxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or the like can be preferably used. . Alternatively, as the insulating film 18b, a laminated film in which the above various films are suitably laminated can be used. The insulating film 18b can be formed by, for example, a CVD method.

In the example shown in FIG. 10, when the insulating film 18b is formed in the active region AR1 and the termination region AR2, the insulating film 18b is formed on the field oxide film FO1 also in the gate pad region AR3. As described above, the insulating film 18b is formed on the field oxide film FO1 also in the termination region AR2.

Next, a conductive film 19b is formed on the insulating film 18b in the active region AR1 and the termination region AR2. The conductive film 19b is made of, for example, polysilicon in which n-type impurities such as phosphorus (P) or arsenic (As) are diffused at a high concentration, or polysilicon in which p-type impurities such as boron (B) are diffused at a high concentration. A conductive film can be used. The conductive film 19b can be formed by, for example, a CVD method.

In the example shown in FIG. 10, when the conductive film 19b is formed in the active region AR1 and the termination region AR2, the conductive film 19b is formed on the insulating film 18b also in the gate pad region AR3.

Then, as shown in FIG. 10, the conductive film 19b is patterned in the active region AR1 and the termination region AR2, and the gate electrode 19 is formed. In the step of forming the gate electrode 19, the gate electrode 19 made of the conductive film 19b is formed by patterning the conductive film 19b by a photolithography technique and a dry etching technique. The gate electrode 19 is formed on the upper surface of the p-type body region 13 sandwiched between the n ⁺ -type source region 14 and the n ⁻ -type epitaxial layer 12 via the gate insulating film 18 made of the insulating film 18 b.

In the example shown in FIG. 10, when the gate electrode 19 and the gate insulating film 18 are formed in the active region AR1, the conductive film 19b is also patterned in the gate pad region AR3. Thereby, the gate pad 19a made of the conductive film 19b is formed in the gate pad region AR3. The gate pad 19a is formed on the field oxide film FO1 via an insulating film 18a made of an insulating film 18b.

In the active region AR1, the termination region AR2, and the gate pad region AR3, the insulating film 18b may be patterned together when the conductive film 19b is patterned.

Next, the interlayer insulating film 20 is formed (step S17 in FIG. 3). In this step S17, as shown in FIG. 11, in the active region AR1, on the n ⁻ type epitaxial layer 12, on the p type body region 13, on the n ⁺ type source region 14 and on the p ⁺ type body contact region 15 Then, an interlayer insulating film 20 is formed so as to cover the gate electrode 19 and the gate insulating film 18. In step S17, as shown in FIG. 11, in the termination region AR2, on the n ⁻ type epitaxial layer 12, on the p type body region 13a, on the n ⁺ type source region 14a, on the p ⁺ type body contact region 15a. On the field oxide film FO1, an interlayer insulating film 20 is formed so as to cover the gate electrode 19 and the gate insulating film 18. Further, in step S17, as shown in FIG. 11, an interlayer insulating film 20 is formed on the field oxide film FO1 so as to cover the gate pad 19a and the insulating film 18a in the gate pad region AR3. For example, a silicon oxide film can be used as the interlayer insulating film 20 and can be formed by, for example, a CVD method.

Next, a silicide film SIL1 is formed (step S18 in FIG. 3). In step S18, first, as shown in FIG. 11, by using a photolithography technique and an etching technique, contact holes 20a and contacts as openings are formed in the interlayer insulating film 20 in the active region AR1 and the termination region AR2. Hole 20b is formed. At this time, the contact hole 20a and the contact hole 20b are formed so as to penetrate the gate insulating film 18 as well.

In the active region AR1, a contact hole 20a that penetrates through the interlayer insulating film 20 and the gate insulating film 18 and reaches the n ⁺ type source region 14 and the p ⁺ type body contact region 15 is formed. The upper surface of the n ⁺ type source region 14 and the upper surface of the p ⁺ type body contact region 15 are exposed at the bottom of the contact hole 20a.

On the other hand, in the termination region AR2, a contact hole 20b that penetrates the interlayer insulating film 20, the gate insulating film 18 and the field oxide film FO1 and reaches the contact region 15b is formed. The upper surface of the contact region 15b is exposed at the bottom of the contact hole 20b. Note that the upper surface of the p-type body region 13a adjacent to the contact region 15b may be exposed at the bottom of the contact hole 20b.

Next, on the p ⁺ type body contact region 15 exposed at the bottom of the contact hole 20a, on the n ⁺ type source region 14 exposed at the bottom of the contact hole 20a, and on the contact region 15b exposed at the bottom of the contact hole 20b. Then, a metal raw material film is formed using a sputtering method or the like. When the upper surface of the p-type body region 13a adjacent to the contact region 15b is exposed at the bottom of the contact hole 20b, the portion adjacent to the contact region 15b exposed at the bottom of the contact hole 20b. A metal source film is formed on p type body region 13a. As the metal source film, for example, a metal source film made of nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), or the like can be formed.

Next, the n ⁺ -type SiC substrate 10 is subjected to a heat treatment to cause the silicon contained in the p ⁺ -type body contact region 15 exposed at the bottom of the contact hole 20a to react with the metal contained in the metal source film, thereby causing the contact hole to react. The silicon contained in the n ⁺ type source region 14 exposed at the bottom of 20a is reacted with the metal contained in the metal source film. As a result, as shown in FIG. 11, the metal film is formed on the p ⁺ type body contact region 15 exposed at the bottom of the contact hole 20a and on the n ⁺ type source region 14 exposed at the bottom of the contact hole 20a. A silicide film SIL1 made of metal silicide is formed.

At this time, the silicon contained in the contact region 15b exposed at the bottom of the contact hole 20b reacts with the metal contained in the metal source film, and the p adjacent to the contact region 15b exposed at the bottom of the contact hole 20b. The silicon contained in the mold body region 13a is reacted with the metal contained in the metal source film. Thus, as shown in FIG. 11, on the contact region 15b exposed at the bottom of the contact hole 20b and on the p-type body region 13a adjacent to the contact region 15b exposed at the bottom of the contact hole 20b, A silicide film SIL2 made of a metal silicide is formed as a metal film.

Preferably, the metal source film is made of nickel (Ni), and the silicide films SIL1 and SIL2 include nickel silicide such as Ni ₂ Si or NiSi, that is, nickel silicide. Thereby, the silicide film SIL1 can be easily Schottky connected to the p ⁺ type body contact region 15, and the silicide film SIL2 can be easily Schottky connected to the contact region 15b.

Preferably, the composition ratio of nickel to the sum of nickel and silicon in the silicide films SIL1 and SIL2 is larger than 0.4 and smaller than 0.7. Thereby, the silicide film SIL1 can be more easily Schottky connected to the p ⁺ type body contact region 15, and the silicide film SIL2 can be more easily Schottky connected to the contact region 15b.

Next, as shown in FIG. 12, a contact hole 20c as an opening is formed in the interlayer insulating film 20 in the gate pad region AR3 by using a photolithography technique and an etching technique. The contact hole 20c penetrates the interlayer insulating film 20 and reaches the gate pad 19a. The upper surface of the gate pad 19a is exposed at the bottom of the contact hole 20c.

Next, the source electrode 21 is formed (step S19 in FIG. 3). In step 19, as shown in FIG. 13, in the active region AR1, a conductive film made of, for example, titanium (Ti) or aluminum (Al) is formed inside the contact hole 20a and on the interlayer insulating film 20, for example. The source electrode 21 is formed by depositing by vapor deposition or sputtering. That is, the source electrode 21 is formed on the silicide film SIL1.

On the other hand, in step S19, as shown in FIG. 13, in the termination region AR2, a conductive film made of, for example, titanium (Ti) or aluminum (Al) is formed in the contact hole 20b and on the interlayer insulating film 20. The contact electrode 21a is formed by depositing, for example, by vapor deposition or sputtering. That is, the contact electrode 21a is formed on the silicide film SIL2. Note that the contact electrode 21 a may be formed in the same layer as the source electrode 21 or may be electrically connected to the source electrode 21.

On the other hand, in step S19, as shown in FIG. 13, a conductive film made of, for example, titanium (Ti) or aluminum (Al) is formed in the contact pad 20c and on the interlayer insulating film 20 in the gate pad region AR3. Is deposited by, for example, an evaporation method or a sputtering method to form the gate contact electrode GC1.

Next, the drain electrode 22 is formed (step S20 in FIG. 3). In this step S20, in the active region AR1, the termination region AR2, and the gate pad region AR3, for example, a conductive material in which titanium (Ti), nickel (Ni), gold (Au), or the like is laminated on the lower surface 10b of the n ⁺ -type SiC substrate 10. The film is deposited by, for example, vapor deposition or sputtering. Thereby, the drain electrode 22 can be formed on the lower surface 10b of the n ⁺ -type SiC substrate 10 in the active region AR1, the termination region AR2, and the gate pad region AR3. The semiconductor device 1 as shown in FIG. Can be manufactured.

Although not shown in FIG. 2, after the drain electrode 22 is formed, the upper surface of the semiconductor device 1 is covered so as to cover the interlayer insulating film 20, the source electrode 21, the contact electrode 21a, the gate contact electrode GC1, and the drain electrode 22. A passivation film can be formed on the lower surface. Next, an opening is formed in a portion of the formed passivation film where a pad region for electrically connecting the source electrode 21, the gate contact electrode GC1, and the drain electrode 22 to the outside is formed. Can do.

<Power module, power converter and motor system>
Next, the power module, power converter, and motor system of Embodiment 1 will be described. The power module according to the first embodiment includes the semiconductor device according to the first embodiment. FIG. 14 is a diagram illustrating a configuration of the motor system according to the first embodiment.

As shown in FIG. 14, the motor system 30 includes a power conversion device 31 as an inverter device, a load 32 made of a motor or the like, a DC power source 33, and a capacitor 34 made of a capacitor or the like. The power conversion device 31 includes a power module 35 as an inverter circuit and a control circuit 36. The load 32 is connected to two output terminals of the power module 35, which are output terminals TO1 and TO2. The DC power supply 33 and the capacitor 34 are connected in parallel between the input terminal TI1 and the input terminal TI2, which are the two input terminals of the power module 35.

The power module 35 as an inverter circuit has switching elements 37u, 37v, 37x and 37y. The switching elements 37u and 37x are connected in series between the input terminal TI1 and the input terminal TI2. The switching elements 37v and 37y are connected in series between the input terminal TI1 and the input terminal TI2.

Each of the switching elements 37u, 37v, 37x and 37y includes a MISFET 38 and a body diode 39 connected in parallel with the MISFET 38. As each of switching elements 37u, 37v, 37x and 37y, semiconductor device 1 (see FIG. 2) of the first embodiment can be used. At this time, as the body diode 39, the body diode 23 incorporated in each vertical MISFET represented by the cell CL1 in each semiconductor device 1 can be used (see FIG. 2).

The gate electrodes of the plurality of MISFETs 38 provided in the switching elements 37u, 37v, 37x, and 37y are respectively connected to the control terminals TC1, TC2, TC3, and TC4 that are the four control terminals of the power module 35. . The control circuit 36 is connected to each of the control terminals TC1, TC2, TC3, and TC4. Therefore, the control circuit 36 is connected to each gate electrode of the plurality of MISFETs 38 provided in the switching elements 37u, 37v, 37x and 37y, respectively. The control circuit 36 drives the switching elements 37u, 37v, 37x and 37y.

The control circuit 36 switches the switching elements 37u and 37v so that the on state or off state of the pair of switching elements 37u and 37y and the on state or off state of the other pair of switching elements 37v and 37x are alternately switched. , 37x and 37y are driven. Thereby, the power module 35 as an inverter circuit generates an AC voltage from the DC voltage and converts the DC power into AC power. The load 32 is driven by this AC power.

<P-type impurity concentration when Schottky connection>
Next, the concentration of the p-type impurity in the p ⁺ type body contact region 15 when the silicide film SIL1 and the p ⁺ type body contact region 15 are Schottky connected will be described.

In the following, it has a p ⁺ type body contact region 15 made of silicon carbide into which aluminum as a p type impurity having different concentrations Np (cm ⁻³ ) is introduced, and a silicide film SIL1 containing nickel silicide, that is, nickel silicide. Five samples were prepared. For each sample, the specific contact resistance Rc (Ωcm ² ) between the p ⁺ type body contact region 15 and the silicide film SIL1 was measured.

Specifically, in each of the five samples, the concentration Np of aluminum as a p-type impurity in the p ⁺ -type body contact region 15 is set to Np = Np1, Np = Np2, Np = Np3, Np = Np4, and Np = Np5. It was. In any case of Np = Np1, Np = Np2, Np = Np3 and Np = Np4, the concentration Np is 1 × 10 ²⁰ cm ⁻³ or more. In the case of Np = Np5, the concentration Np is less than 1 × 10 ²⁰ cm ^{−3 and} less than 7 × 10 ¹⁹ cm ⁻³ . For each sample, a value obtained by multiplying the contact resistance R and the contact area A in the Kelvin pattern composed of the p ⁺ type body contact region 15 and the silicide film SIL1 was obtained as the specific contact resistance Rc. The result is shown in the graph of FIG.

Further, when the concentration Np is Np = Np4 or Np = Np5, the current I (μA) flowing between the p ⁺ type body contact region 15 and the silicide film SIL1 depends on the voltage V (V), that is, the current voltage. The result of measuring the curve is shown in the graph of FIG.

Incidentally, the density Np of the p-type impurity in the p ⁺ -type body contact region 15, and the average value of the concentration of p-type impurity at each depth position from the surface of the p ⁺ -type body contact region 15 to a depth position of 100nm .

In any case of Np = Np1, Np = Np2, Np = Np3, and Np = Np4, when the p-type impurity concentration Np is 1 × 10 ²⁰ cm ⁻³ or more, as shown in FIG. 15, the specific contact resistance Rc Was 0.005 Ωcm ² or less. In addition, as shown in FIG. 16 as a representative example of Np = Np4, the current-voltage curve has linearity in any of Np = Np1, Np = Np2, Np = Np3, and Np = Np4. Thus, it was found that the silicide film SIL1 is not in Schottky connection with the p ⁺ type body contact region 15 but in ohmic connection.

On the other hand, when Np = Np5, that is, when the concentration Np of the p-type impurity is less than 1 × 10 ²⁰ cm ⁻³ , the specific contact resistance Rc is larger than 0.005 Ωcm ² as shown in FIG. It was. Further, as shown in FIG. 16, when Np = Np5, the current-voltage curve does not have linearity, and the silicide film SIL1 is Schottky-connected to the p ⁺ type body contact region 15. I understood that.

Therefore, as shown in FIG. 15, it is preferable that the concentration Np of the p-type impurity is less than 1 × 10 ²⁰ cm ⁻³ , that is, the specific contact resistance Rc is larger than 0.005 Ωcm ² . Thereby, the silicide film SIL1 can be Schottky connected to the p ⁺ type body contact region 15. Further, it is more preferable that the concentration Np of the p-type impurity is less than 7 × 10 ¹⁹ cm ⁻³ , that is, the specific contact resistance Rc is larger than 0.02 Ωcm ² . Thereby, the silicide film SIL1 can be easily Schottky connected to the p ⁺ type body contact region 15.

Even if the p-type impurity concentration Np is 1 × 10 ²⁰ cm ⁻³ or more, the source is not formed on the p ⁺ -type body contact region 15 via the silicide film as will be described later in the third embodiment. By directly forming a metal film made of the same material as the electrode 21, the metal film can be Schottky connected to the p ⁺ type body contact region 15.

<Energization deterioration due to reflux current>
Next, energization deterioration of the semiconductor device due to the return current flowing through the semiconductor device will be described with reference to FIG. 17 and compared with the semiconductor device of the comparative example. FIG. 17 is a cross-sectional view of main parts of a semiconductor device of a comparative example.

Similar to the semiconductor device 1 of the first embodiment, the semiconductor device 101 of the comparative example includes a vertical MISFET made of silicon carbide. However, in the semiconductor device 101 of the comparative example, as in the case of Np = Np1, Np = Np2, Np = Np3, and Np = Np4 described with reference to FIG. 15, the silicide film SIL1 has the p ⁺ type body contact region. 15 is not Schottky connected, but is ohmic connected. That is, the concentration of the p-type impurity in the p ⁺ -type body contact region 15 of the semiconductor device 101 of the comparative example is 1 × 10 ²⁰ cm ⁻³ or more.

Here, Table 2 shows ion implantation conditions for setting the concentration of the p-type impurity in the p ⁺ -type body contact region 15 to 1 × 10 ²⁰ cm ⁻³ or more. That is, the conditions shown in Table 2 are conditions for making ohmic contact between the silicide film SIL1 and the p ⁺ type body contact region 15.

Table 2 shows the implantation energy (keV) and dose (cm) in each step when the four steps of steps S121 to S124 are sequentially performed to implant ions of aluminum as a p-type impurity in four stages. ^-2 ).

Hereinafter, a case where the semiconductor device 101 of the comparative example is used as a plurality of switching elements 37u, 37v, 37x, and 37y of the power module 35 as the inverter circuit described with reference to FIG.

When the load 32 connected to the output terminals TO1 and TO2 of the power module 35 has a large inductance, when switching each of the plurality of switching elements 37u, 37v, 37x and 37y from the on state to the off state, A reflux current flows in a direction opposite to the direction of the on-current of each switching element. Therefore, in the power module 35 as an inverter circuit, it is necessary to provide a diode connected in parallel with each of the MISFETs 38 of the plurality of switching elements 37u, 37v, 37x, and 37y in order to flow the return current.

On the other hand, the semiconductor device 101 made of a vertical MISFET has body diodes 123 and 123a built between the source electrode 21 or the contact electrode 21a and the drain electrode 22 in the active region AR1 and the termination region AR2. A reflux current can be passed through the body diode 123. Therefore, in the power module 35 provided with the vertical MISFET as the switching elements 37u, 37v, 37x and 37y, it is not necessary to provide an external diode separately from the vertical MISFET.

However, when the vertical MISFET provided in the power module 35 as an inverter circuit is a vertical MISFET made of SiC, a reflux current flows through the body diode 123 built in the vertical MISFET. In FIG. 17, holes flowing as a reflux current are indicated by “h” and a broken arrow, and electrons flowing as a reflux current are indicated by “e” and a solid arrow. Thus, when a reflux current flows through the body diode 123, energization deterioration occurs, and the on-resistance of the vertical MISFET increases. When such energization deterioration occurs, power loss in the power module 35 as an inverter circuit increases.

This is because, when a reflux current flows through the body diode 123 built in the semiconductor device 101 as a vertical MISFET made of SiC, for example, holes flowing in the semiconductor made of SiC are caused by crystal defects in the semiconductor made of SiC. This is because the crystal defect density is increased by recombination with electrons.

For example, when a reflux current flows through the body diode 123 built in the semiconductor device 101 as a vertical MISFET made of SiC, the n ⁻ type epitaxial layer 12, the p type body region 13, and the p ⁺ type body contact region 15 In various crystal defects such as stacking faults existing inside, holes and electrons flowing as a reflux current are recombined. The energy released by recombination of holes and electrons expands various crystal defects such as stacking faults in the n ⁻ -type epitaxial layer 12 and increases the density of crystal defects. Is generated, and an electrical resistance when an on-current flows through the semiconductor device 101, that is, an on-resistance increases.

Therefore, when the semiconductor device 101 of the comparative example is used as a switching element, it is necessary to prevent a large amount of reflux current from flowing through the body diode 123. Therefore, for example, synchronous rectification such as switching each of the plurality of semiconductor devices 101 to the on state in synchronization with the timing at which the reflux current flows through the body diode 123 needs to be performed with extremely high accuracy by the control circuit 36. Therefore, the design margin of the power module 35 as an inverter circuit including the semiconductor device 101 of the comparative example cannot be expanded.

Alternatively, it is necessary to provide an external diode separately from the body diode 123 so as not to allow a large amount of reflux current to flow through the body diode 123 built in the semiconductor device 101. Therefore, the power module 35 as an inverter circuit including the semiconductor device 101 of the comparative example cannot be reduced in size.

In the technique described in Patent Document 1, the semiconductor element includes a field effect transistor and a Schottky electrode. However, in the technique described in Patent Document 1, the Schottky electrode is provided on the upper surface of the first conductivity type, that is, the n-type drift region so as to form a Schottky junction with the upper surface. Therefore, in the technique described in Patent Document 1, since the Schottky electrode is Schottky connected to the n-type semiconductor region, it is possible to prevent holes from being supplied from the Schottky electrode to the semiconductor element. Can not.

In the technique described in Patent Document 1, the Schottky electrode is provided on the upper surface of the drift region along the outer periphery of the region where the field effect transistor is formed. Therefore, the area of the semiconductor element may be increased, and the electric field may be concentrated on the outer periphery of the region where the field effect transistor is formed to increase the strength of the electric field.

Furthermore, in the technique described in Patent Document 1, since the step of forming the Schottky electrode on the upper surface of the n-type drift region needs to be performed separately from the other steps, the number of manufacturing steps of the semiconductor device May increase, and the number of masks used may increase.

In addition, when the vertical MISFET provided in the power module 35 as the inverter circuit is a vertical MISFET made of SiC, the deterioration of energization is also caused by the return current flowing through the body diode 123a built in the termination region AR2. The occurrence is the same as when the return current flows through the body diode 123.

<Main features and effects of the present embodiment>
In the semiconductor device 1 of the first embodiment, the silicide film SIL1 is Schottky connected to the p ⁺ type body contact region 15.

Consider a case where such a semiconductor device 1 according to the first embodiment is used as a plurality of switching elements 37u, 37v, 37x and 37y of the power module 35 as the inverter circuit described with reference to FIG. In such a case, when a reflux current flows through the body diode 23, holes are hardly supplied from the silicide film SIL1 to the p ⁺ -type body contact region 15, and electrons flow to the vicinity of the source electrode 21. Therefore, in various crystal defects existing in the n ⁻ type epitaxial layer 12, the p type body region 13, the p ⁺ type body contact region 15, etc., recombination of holes and electrons flowing as a reflux current is recombined. Can be prevented or suppressed. Therefore, it is possible to prevent or suppress various crystal defects from expanding in the n ⁻ -type epitaxial layer 12, that is, to increase the crystal defect density, and to prevent the conduction deterioration of the semiconductor device 1 or Can be suppressed.

In the first embodiment, even if a reflux current is passed through the body diode 23 built in the semiconductor device 1, current deterioration is unlikely to occur. There is no need to perform synchronous rectification such as switching each of the semiconductor devices 101 to the ON state with such high accuracy by the control circuit 36. Therefore, the design margin of the power module 35 as an inverter circuit including the semiconductor device 1 of the first embodiment and the power conversion device 31 including the power module 35 can be widened, and the power module 35 and the power conversion device can be expanded. The reliability of 31 can be improved.

Alternatively, in the first embodiment, even if a reflux current is passed through the body diode 23 built in the semiconductor device 1, current deterioration is unlikely to occur. Therefore, an external connection is provided separately from the body diode 23 built in the semiconductor device 1. There is no need to provide a diode. Therefore, the power module 35 and the power conversion device 31 can be reduced in size.

Preferably, in the termination region AR2, the silicide film SIL2 is Schottky connected to the contact region 15b. As a result, when a reflux current flows through the body diode 23a built in the semiconductor device 1 included in the power module 35 as an inverter circuit, holes are hardly supplied from the silicide film SIL2 to the contact region 15b, and electrons are not generated. It flows to the vicinity of the contact electrode 21a. This prevents or suppresses recombination of holes and electrons flowing as a reflux current in various crystal defects existing in n ⁻ type epitaxial layer 12, p type body region 13a, contact region 15b, and the like. can do. Therefore, it is possible to prevent or suppress the expansion of various crystal defects such as stacking faults in the n ⁻ -type epitaxial layer 12, that is, increase in the crystal defect density, and the semiconductor device 1 is deteriorated in energization. This can be prevented or suppressed.

In the first embodiment, the silicide film SIL1 is provided with the p ⁺ type body contact region 15 for each vertical MISFET represented by the cell CL1. Therefore, compared to the technique described in Patent Document 1, the area of the semiconductor device is less likely to increase, and the electric field is less likely to concentrate in the termination region AR2.

Further, in the first embodiment, for example p ⁺ -type body contact region 15 may be adjusted to conditions in the p-type impurity is ion-implanted to form a silicide film SIL1 a p ⁺ -type body contact region 15 There is no need to perform a process for Schottky connection separately from other processes. Therefore, compared with the technique described in Patent Document 1, the number of steps is not increased and the number of masks used is not increased in the manufacturing process of the semiconductor device.

The first embodiment can also be applied to the case where the conductivity types of the semiconductor substrate, each semiconductor layer, and each semiconductor region are interchanged between p-type and n-type. Even in such a case, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained, although the degree is less than that in the case where holes flow as the reflux current (the second embodiment and the second embodiment described later). The same applies to 3).

In the first embodiment, instead of the n ⁺ type SiC substrate, a semiconductor substrate made of various semiconductor materials such as silicon (Si) or gallium nitride (GaN) is used, and the n ⁻ type epitaxial layer is made of Si or the like. The present invention is also applicable when a semiconductor layer made of various semiconductor materials such as GaN is used. Even in such a case, the same effect as that of the semiconductor device of the first embodiment can be obtained, although the degree is less than that in the case of using silicon carbide (SiC) as the semiconductor material (the second embodiment and the implementation described later). The same applies to Form 3).

(Embodiment 2)
<Semiconductor device>
Next, a semiconductor device according to the second embodiment of the present invention will be described. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment.

In the semiconductor device 1 of the second embodiment, the concentration of the p-type impurity in the contact region 15b is lower than the concentration of the p-type impurity in the p ⁺ -type body contact region 15. In the semiconductor device 1 of the second embodiment, each part other than the p ⁺ type body contact region 15 and the contact region 15b is the same as each part in the semiconductor device 1 of the first embodiment. Omitted. Here, also for the p ⁺ -type body contact region 15a, is omitted, the concentration of p-type impurity in the p ⁺ -type body contact region 15a is the same as the concentration of the p-type impurity in the p ⁺ -type body contact region 15 be able to.

Similarly to the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the second embodiment also has the p ⁺ type body contact region 15 and the silicide film SIL1 in the active region AR1, and the termination region AR2 Contact region 15b and silicide film SIL2.

On the other hand, in the semiconductor device 1 of the second embodiment, the concentration of the p-type impurity in the contact region 15b is lower than the concentration of the p-type impurity in the p ⁺ -type body contact region 15. In other words, the concentration of the p-type impurity in the p ⁺ -type body contact region 15 is higher than the concentration of the p-type impurity in the contact region 15b.

In the second embodiment, in the termination region AR2, the silicide film SIL2 is Schottky connected to the contact region 15b as in the first embodiment. Similar to the first embodiment, the concentration of the p-type impurity in the contact region 15b in contact with the silicide film SIL2 is less than 1 × 10 ²⁰ cm ⁻³ , so that the silicide film SIL2 is connected to the contact region 15b in a Schottky connection. can do. Similarly to the first embodiment, the silicide film SIL2 can be easily separated from the contact region 15b by reducing the p-type impurity concentration in the contact region 15b in contact with the silicide film SIL2 to less than 7 × 10 ¹⁹ cm ^−3. Can be connected to Schottky.

In the second embodiment, the silicide film SIL2 preferably includes nickel silicide, and more preferably, the composition ratio of nickel with respect to the sum of nickel and silicon in the silicide film SIL2, as in the first embodiment. Is greater than 0.4 and less than 0.7. Thereby, the silicide film SIL2 can be more easily Schottky connected to the contact region 15b.

In the second embodiment, in the active region AR1, unlike the first embodiment, the silicide film SIL1 is not in Schottky connection with the p ⁺ type body contact region 15 but in ohmic connection. Preferably, the p ⁺ -type body contact region 15 in contact with the silicide film SIL1 has a p-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more, so that the silicide film SIL1 is converted into the p ⁺ -type body contact region. 15 and an ohmic connection. In the second embodiment, the composition of the silicide film SIL1 is not particularly limited.

In the active region AR1, the ^{p.sup. +} Type body contact regions 15 are not separated from each other and are arranged in a matrix at relatively small intervals. Therefore, when a reflux current flows through the semiconductor device 1, the current density in the p-type body region 13 at the periphery of each p ⁺ -type body contact region 15 is not so high, and current deterioration is unlikely to occur.

On the other hand, in the termination region AR2, the contact regions 15b are separated from each other. Therefore, when a return current flows through the semiconductor device 1, the currents in the p- type body regions 13a and 13b in the portions located around the contact regions 15b. Density increases, and current deterioration tends to occur.

In the active region AR1, the potential of the p-type body region 13 is accurately adjusted by the source electrode 21 via the silicide film SIL1 and the p ⁺ -type body contact region 15 when the vertical MISFET is in the ON state. It is necessary to improve the switching characteristics of the vertical MISFET. From the viewpoint of improving the switching characteristics of the vertical MISFET, it is desirable that the concentration of the p-type impurity in the p ⁺ -type body contact region 15 is relatively high.

On the other hand, in the termination region AR2, it is not necessary to adjust the potentials of the p- type body regions 13a and 13b by the contact electrode 21a via the silicide film SIL2 and the contact region 15b when the vertical MISFET is on. . Therefore, the concentration of the p-type impurity in the contact region 15b may be relatively low.

In the second embodiment, the concentration of p-type impurity in contact region 15 b is lower than the concentration of p-type impurity in p ⁺ -type body contact region 15. Thereby, in the termination region AR2, the silicide film SIL2 is Schottky connected to the contact region 15b. In the termination region AR2, when a reflux current flows through the body diode 23a, holes are hardly supplied from the silicide film SIL2 to the contact region 15b, and electrons flow to the vicinity of the contact electrode 21a. Therefore, recombination of holes and electrons flowing as a reflux current can be prevented or suppressed in various crystal defects existing in the n ⁻ type epitaxial layer 12 and the like in the termination region AR2.

Therefore, it is possible to prevent or suppress the growth of various crystal defects in the n ⁻ type epitaxial layer 12 and the like, and to prevent or suppress the increase of the on-resistance of the semiconductor device 1. Therefore, it is possible to prevent or suppress the occurrence of deterioration in energization of the semiconductor device 1 when the return current flows through the body diode 23a built in the semiconductor device 1 included in the power module as the inverter circuit. Further, it is not necessary to perform synchronous rectification with high accuracy using a control circuit, and it is not necessary to provide an external diode separately from the body diode 23a built in the semiconductor device 1.

Further, in the second embodiment, the silicide film SIL1 is ohmically connected to the p ⁺ type body contact region 15 in the active region AR1. Therefore, when the vertical MISFET is in the ON state, the potential of the p-type body region 13 is accurately adjusted by the source electrode 21 via the silicide film SIL1 and the p ⁺ -type body contact region 15, thereby switching the vertical MISFET. Characteristics can be improved.

<Manufacturing process of semiconductor device>
In the manufacturing process of the semiconductor device of the second embodiment, the manufacturing process of the semiconductor device of the first embodiment (step S11 of FIG. 3) except for the process of forming the p ⁺ type body contact region 15 (step S14 of FIG. 3). The semiconductor device of the second embodiment can be manufactured by performing the same process as in step S20).

In the manufacturing process of the semiconductor device according to the second embodiment, the ion implantation conditions for forming the p ⁺ type body contact region 15 in the process shown in FIG. 7 in step S14 in FIG. In the illustrated process, the ion implantation conditions for forming the contact region 15b are different. The conditions for ion implantation when forming the p ⁺ -type body contact region 15 can be the conditions for forming an ohmic connection as shown in Table 2, for example. Further, the ion implantation conditions for forming the contact region 15b in the termination region AR2 can be the conditions for forming the Schottky connection shown in Table 1, for example.

At this time, the concentration of the p-type impurity in the p ⁺ -type body contact region 15 can be set to 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and the concentration of the p-type impurity in the contact region 15b is set to 1 × 10 ²⁰ cm ^−3. It can be 2 × 10 ¹⁹ cm ⁻³ or more and less than 1 × 10 ²⁰ cm ⁻³ .

Thereby, in the termination region AR2, the silicide film SIL2 can be schottky connected to the contact region 15b, and in the active region AR1, the silicide film SIL1 can be ohmically connected without being schottky connected to the contact region 15b.

<Power module, power converter and motor system>
The power module, power conversion device, and motor system including the semiconductor device 1 according to the second embodiment are also described with reference to FIG. 14. The power module, power conversion device, and motor including the semiconductor device 1 according to the first embodiment are also described. Can be similar to the system.

(Embodiment 3)
<Semiconductor device>
Next, a semiconductor device according to the third embodiment of the present invention will be described. FIG. 19 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment.

In the semiconductor device 1 according to the third embodiment, in the active region AR1, the source electrode 21 is connected to the p ⁺ type body contact region 15 via the silicide film SIL1, but in the termination region AR2, the contact electrode 21a is formed directly on the contact region 15b.

In the semiconductor device 1 according to the third embodiment, each part other than the structure from the p ⁺ type body contact region 15 to the source electrode 21 and the structure from the contact region 15b to the contact electrode 21a is described in the first embodiment. This is the same as each part of the semiconductor device 1 of FIG. Here, also for the p ⁺ -type body contact region 15a, is omitted, the concentration of p-type impurity in the p ⁺ -type body contact region 15a is the same as the concentration of the p-type impurity in the p ⁺ -type body contact region 15 be able to.

Also in the semiconductor device 1 according to the third embodiment, similarly to the semiconductor device 1 according to the first embodiment, in the active region AR1, the portion exposed at the bottom of the contact hole 20a and on the n ⁺ type source region 14 and p ⁺ On the mold body contact region 15, a silicide film SIL1 made of a metal silicide is formed as a metal film. In the active region AR1, the source electrode 21 made of the conductive film 21b is formed in the contact hole 20a, on the silicide film SIL1, and on the interlayer insulating film 20.

On the other hand, in the semiconductor device 1 of the third embodiment, unlike the semiconductor device 1 of the first embodiment, a silicide film is formed on the contact region 15b of the termination region AR2 exposed at the bottom of the contact hole 20b. It has not been. Therefore, in the semiconductor device 1 of the third embodiment, the contact electrode 21a made of the conductive film 21c is formed on the contact region 15b of the termination region AR2 exposed at the bottom of the contact hole 20b. The electrode 21a is in contact with the contact region 15b. The contact electrode 21a is made of a conductive film 21c formed in the same layer as the conductive film 21b included in the source electrode 21. The contact electrode 21a may be electrically connected to the source electrode 21.

In the third embodiment, as in the second embodiment, in the active region AR1, the silicide film SIL1 is not in Schottky connection with the p ⁺ type body contact region 15, but in ohmic connection. For example, by setting the concentration of the p-type impurity in the p ⁺ -type body contact region 15 in contact with the silicide film SIL1 to 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, the silicide film SIL1 is The p ⁺ type body contact region 15 can be ohmically connected. In the third embodiment, the composition of the silicide film SIL1 is not particularly limited.

On the other hand, in the termination region AR2, the contact electrode 21a is Schottky connected to the contact region 15b. When the contact electrode 21a is formed directly on the contact region 15b, for example, insulation is provided between the contact electrode 21a made of, for example, titanium (Ti) or aluminum (Al) and the contact region 15b made of silicon carbide (SiC). An interfacial layer having a property is formed. Thereby, the contact electrode 21a can be Schottky connected to the contact region 15b.

Similarly to the description in the second embodiment, in the active region AR1, deterioration of energization is unlikely to occur when a return current flows in the semiconductor device 1, but in the termination region AR2, the return current flows in the semiconductor device 1. In addition, energization deterioration is likely to occur. In the active region AR1, it is desirable that the concentration of the p-type impurity in the p ⁺ -type body contact region 15 is relatively high from the viewpoint of improving the switching characteristics of the vertical MISFET, but in the termination region AR2, the concentration in the contact region 15b is desirable. The concentration of the p-type impurity may be relatively low.

In the third embodiment, the contact electrode 21a is Schottky connected to the contact region 15b in the termination region AR2. Thus, in the termination region AR2, when a reflux current flows through the body diode 23a, holes are hardly supplied from the contact electrode 21a to the contact region 15b, and electrons flow to the vicinity of the contact electrode 21a. Therefore, recombination of holes and electrons flowing as a reflux current can be prevented or suppressed in various crystal defects existing in the n ⁻ type epitaxial layer 12 and the like in the termination region AR2.

Therefore, it is possible to prevent or suppress the growth of various crystal defects in the n ⁻ type epitaxial layer 12 and the like, and to prevent or suppress the increase of the on-resistance of the semiconductor device 1. Therefore, it is possible to prevent or suppress the occurrence of deterioration in energization of the semiconductor device 1 when the return current flows through the body diode 23a built in the semiconductor device 1 included in the power module as the inverter circuit. Further, it is not necessary to perform synchronous rectification with high accuracy using a control circuit, and it is not necessary to provide an external diode separately from the body diode 23a built in the semiconductor device 1.

Furthermore, in the third embodiment, the silicide film SIL1 is ohmically connected to the p ⁺ type body contact region 15 in the active region AR1. Therefore, when the vertical MISFET is in the ON state, the potential of the p-type body region 13 is accurately adjusted by the source electrode 21 via the silicide film SIL1 and the p ⁺ -type body contact region 15, thereby switching the vertical MISFET. Characteristics can be improved.

<Manufacturing process of semiconductor device>
Next, an example of a manufacturing process of the semiconductor device according to the third embodiment will be described with reference to the drawings. 20 to 22 are fragmentary cross-sectional views of the semiconductor device according to the third embodiment during the manufacturing steps thereof.

In the manufacturing process of the semiconductor device according to the third embodiment, the manufacturing process of the semiconductor device according to the first embodiment (steps S11 to S20 in FIG. 3), except for steps S14, S18 and S19 in FIG. The semiconductor device of the third embodiment can be manufactured by performing the same process.

Also in the third embodiment, similarly to the first embodiment, the steps S11 to S13 of FIG. 3 are performed, and the n ⁻ type epitaxial layer is formed on the upper surface 10a of the n ⁺ type SiC substrate 10 in the active region AR1 and the termination region AR2. Layer 12 is formed, and p-type body region 13 is formed in the upper layer portion of n ⁻ -type epitaxial layer 12.

Next, the p ⁺ type body contact region 15 is formed (step S14 in FIG. 3). In the third embodiment, among the step S14 in FIG. 3, in the step shown in FIG. 7, the ion implantation conditions for forming the p ⁺ -type body contact region 15, in the first embodiment, the p ⁺ -type The ion implantation conditions for forming the body contact region 15 are different. In the third embodiment, the ion implantation conditions for forming the p ⁺ -type body contact region 15 can be the conditions for forming an ohmic connection as shown in Table 2, for example. At this time, the concentration of the p-type impurity in the p ⁺ -type body contact region 15 can be set to 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less.

In the third embodiment, in the termination region AR2, no silicide film is interposed between the contact electrode 21a and the contact region 15b, and the contact electrode 21a and the contact region 15b come into contact with each other, so that the contact electrode 21a The Schottky connection is made with the contact region 15b. Therefore, the concentration of the p-type impurity in the contact region 15b may be about 2 × 10 ¹⁹ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ and is not particularly limited. Therefore, in step S14 of FIG. 3, the ion implantation conditions for forming the contact region 15b in the process shown in FIG. 8 are not particularly limited.

Next, similarly to Embodiment 1, Steps S15 to S17 of FIG. 3 are performed to form the n ⁺ -type source region 14, the gate insulating film 18 and the gate electrode 19, and the interlayer insulating film 20.

Next, a silicide film SIL1 is formed (step S18 in FIG. 3). In the third embodiment, in this step S18, first, as shown in FIG. 20, by using a photolithography technique and an etching technique, a contact hole as an opening is formed in the interlayer insulating film 20 in the active region AR1. 20a is formed. However, in the third embodiment, unlike the first embodiment, when the contact hole 20a is formed, no contact hole is formed in the termination region AR2.

Next, a metal source film made of, for example, nickel (Ni) is formed on the upper surface of the p ⁺ -type body contact region 15 exposed at the bottom of the contact hole 20a by using a sputtering method or the like, as in the first embodiment. Thereafter, heat treatment is performed on the n ⁺ -type SiC substrate 10. Thus, as shown in FIG. 20, a silicide film SIL1 made of metal silicide is formed on the p ⁺ type body contact region 15 exposed at the bottom of the contact hole 20a. However, in the third embodiment, the composition of the silicide film SIL1 is not particularly limited.

Next, as shown in FIG. 21, a contact hole 20c as an opening is formed in the interlayer insulating film 20 in the gate pad region AR3 by using a photolithography technique and an etching technique. However, in the third embodiment, unlike the first embodiment, when the contact hole 20c is formed, the contact hole 20b is formed in the termination region AR2. Further, no silicide film is formed on the contact region 15b exposed at the bottom of the contact hole 20b and on the p-type body region 13a adjacent to the contact region 15b exposed at the bottom of the contact hole 20b.

In the third embodiment, the step of forming the contact hole 20b, which must be performed separately from the step of forming the contact hole 20a, can be performed by the same process as the process of forming the contact hole 20c. Therefore, even if the step of forming the contact hole 20b is performed separately from the step of forming the contact hole 20a, the number of steps in the semiconductor device manufacturing process does not increase.

Next, the source electrode 21 is formed (step S19 in FIG. 3). In the third embodiment, in this step S19, as shown in FIG. 22, in the active region AR1, the source electrode 21 made of the conductive film 21b is formed in the contact hole 20a and on the interlayer insulating film 20. . In the termination region AR2, a contact electrode 21a made of a conductive film 21c is formed inside the contact hole 20b and on the interlayer insulating film 20. At this time, the contact electrode 21a made of the conductive film 21c is formed on the portion of the contact region 15b exposed at the bottom of the contact hole 20b, and the contact electrode 21a is in contact with the contact region 15b. The contact electrode 21a is made of a conductive film 21c formed in the same layer as the conductive film 21b included in the source electrode 21. The contact electrode 21a may be electrically connected to the source electrode 21. In the gate pad region AR3, the gate contact electrode GC1 is formed as in the first embodiment.

Thereafter, step S20 of FIG. 3 is performed to form the semiconductor device 1 of the third embodiment.

<Power module, power converter and motor system>
The power module, power converter, and motor system provided with the semiconductor device 1 according to the third embodiment are also described with reference to FIG. 14, and the power module, power converter, and motor provided with the semiconductor device 1 according to the first embodiment. Can be similar to the system.

(Embodiment 4)
<Power module, power converter and three-phase motor system>
Next, a power module, a power conversion device, and a three-phase motor system including the power conversion device according to the fourth embodiment will be described. The power module according to the fourth embodiment includes the semiconductor device according to the first embodiment. The power module of the fourth embodiment is different from the power module of the first embodiment in that the semiconductor device of the first embodiment is applied to a three-phase inverter circuit. In the following, the semiconductor devices of the second and third embodiments can be used in place of the semiconductor device of the first embodiment (the same applies to the fifth and sixth embodiments).

FIG. 23 is a diagram illustrating a configuration of a three-phase motor system according to the fourth embodiment. As shown in FIG. 23, the three-phase motor system 30a includes a power conversion device 31a as an inverter device, a load 32a composed of a three-phase motor or the like, a DC power source 33, and a capacitor 34 composed of a capacitor or the like. Yes. The power converter 31a includes a power module 35a as a three-phase inverter circuit and a control circuit 36a. The load 32a is connected to output terminals TO1, TO2, and TO3, which are three-phase output terminals of the power module 35a. The DC power supply 33 and the capacitor 34 are connected in parallel between the input terminal TI1 and the input terminal TI2, which are the two input terminals of the power module 35a.

The power module 35a as an inverter circuit has switching elements 37u, 37v, 37w, 37x, 37y and 37z. The switching elements 37u and 37x are connected in series between the input terminal TI1 and the input terminal TI2. The switching elements 37v and 37y are connected in series between the input terminal TI1 and the input terminal TI2. The switching elements 37w and 37z are connected in series between the input terminal TI1 and the input terminal TI2.

Each of the switching elements 37u, 37v, 37w, 37x, 37y and 37z includes a MISFET 38 and a body diode 39. As each of the switching elements 37u, 37v, 37w, 37x, 37y, and 37z, the semiconductor device 1 according to the first, second, or third embodiment (see FIG. 2, FIG. 18, or FIG. 19) is used. it can. As the body diode 39, body diodes 23 and 23a (see FIG. 2, FIG. 18, or FIG. 19) built in the semiconductor device 1 can be used.

The gate electrodes of the plurality of MISFETs 38 provided in the switching elements 37u, 37v, 37w, 37x, 37y and 37z, respectively, are six control terminals of the power module 35a. Control terminals TC1, TC2, TC3, TC4, TC5 And TC6, respectively. The control circuit 36a is connected to each of the control terminals TC1, TC2, TC3, TC4, TC5, and TC6. Therefore, the control circuit 36a is connected to each gate electrode of the plurality of MISFETs 38 provided in the switching elements 37u, 37v, 37w, 37x, 37y and 37z, respectively. The control circuit 36a drives the switching elements 37u, 37v, 37w, 37x, 37y and 37z.

The control circuit 36a drives each of the switching elements 37u, 37v, 37w, 37x, 37y, and 37z so that the ON state and the OFF state of each switching element are alternately switched at a preset timing. As a result, a U-phase, V-phase, and W-phase three-phase AC voltage is generated from the DC voltage, and the DC power is converted into three-phase AC power. The load 32a is driven by this three-phase AC power.

<Main features and effects of the present embodiment>
As each of the switching elements 37u, 37v, 37w, 37x, 37y, and 37z in the power module 35a included in the power conversion device 31a of the fourth embodiment, the semiconductor of the first embodiment, the second embodiment, or the third embodiment. The device 1 can be used.

As a result, it is possible to prevent or suppress the deterioration of energization of the semiconductor device 1 when the return current flows through the body diodes 23 and 23a incorporated in the semiconductor device 1, so that power loss during power conversion can be prevented. Can be reduced. In addition, since it is not necessary to perform synchronous rectification with high accuracy using the control circuit 36a, the design margin of the power module 35a and the power converter 31a can be expanded, and the reliability of the power module 35a and the power converter 31a is improved. Can be made. Alternatively, since it is not necessary to provide an external diode separately from the body diodes 23 and 23a, the power module 35a and the power conversion device 31a can be reduced in size.

(Embodiment 5)
Next, an automobile according to a fifth embodiment of the present invention will be described. The automobile of the fifth embodiment is an automobile including the power conversion device of the fourth embodiment, and is an automobile such as a hybrid car and an electric car.

FIG. 24 is a diagram showing a configuration of an electric vehicle as a vehicle according to the fifth embodiment. FIG. 25 is a circuit diagram showing the boost converter device in the automobile of the fifth embodiment.

As shown in FIG. 24, an automobile 40 as an electric vehicle drives a three-phase motor 43 that allows power to be input / output to / from a drive shaft 42 to which drive wheels 41a and 41b are connected, and a three-phase motor 43. An inverter device 44 and a battery 45 are provided. In addition, the automobile 40 includes a boost converter device 48, a relay 49, and an electronic control unit 50. The boost converter device 48 includes an electric power line 46 to which an inverter device 44 is connected and electric power to which a battery 45 is connected. It is connected to the line 47.

The three-phase motor 43 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter device 44, the power conversion device 31a (see FIG. 23) described in the fourth embodiment can be used.

As shown in FIG. 25, the boost converter device 48 has a configuration in which a reactor 51 and a smoothing capacitor 52 are connected to an inverter device 53. The inverter device 53 is the same as a part of the inverter circuit included in the power module 35a described in the fourth embodiment. In addition, MISFET 55 and body diode 56 included in switching element 54 in inverter device 53 are the same as MISFET 38 and body diode 39 described in the fourth embodiment.

The electronic control unit 50 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor that detects the rotor position of the three-phase motor 43 or a charge / discharge value of the battery 45. . The electronic control unit 50 outputs a signal for controlling the inverter device 44, the boost converter device 48, and the relay 49.

<Main features and effects of the present embodiment>
As the inverter device 44 of the automobile 40 of the fifth embodiment, the power conversion device 31a (see FIG. 23) of the fourth embodiment can be used. As each of the switching elements 37u, 37v, 37w, 37x, 37y, and 37z provided in the power conversion device 31a, the semiconductor device 1 of the first embodiment, the second embodiment, or the third embodiment (FIG. 2, FIG. 18 or FIG. 19) can be used. Alternatively, semiconductor device 1 of the first, second, or third embodiment is used as switching element 54 provided in inverter device 53 in boost converter device 48 of automobile 40 of the fifth embodiment. Can do.

As a result, it is possible to prevent or suppress the deterioration of energization of the semiconductor device 1 when the return current flows through the body diodes 23 and 23a incorporated in the semiconductor device 1, so that power loss during power conversion can be prevented. Can be reduced. In addition, since it is not necessary to perform synchronous rectification with high accuracy using the control circuit 36, the design margin of the power module 35a and the power converter 31a can be widened, and the reliability of the power module 35a and the power converter 31a is improved. Can be made. Alternatively, since it is not necessary to provide an external diode separately from the body diodes 23 and 23a, the power module 35a and the power conversion device 31a can be reduced in size.

Accordingly, in the automobile 40 of the fifth embodiment, the power loss at the time of power conversion in the inverter device 44 and the boost converter device 48 can be reduced, so that a large cooling device may not be provided. . Therefore, the inverter device 44 and the boost converter device 48 can be easily reduced in cost, size, or weight by reducing the size of the cooling device. As a result, the volume of the drive system occupying the automobile 40 as an electric vehicle can be reduced, and the automobile 40 as an electric car can be easily reduced in cost, size, or weight. Alternatively, the degree of freedom in design of the vehicle 40 as an electric vehicle can be increased, for example, the interior of the vehicle 40 as the electric vehicle can be widened.

In addition, in this Embodiment 5, the example which applied the motor vehicle containing the power converter device 31a of Embodiment 4 to the electric vehicle was demonstrated. However, the vehicle including the power conversion device 31a of the fourth embodiment can be similarly applied to a hybrid vehicle that also uses an engine. Further, the hybrid vehicle to which the power conversion device 31a of the fourth embodiment is applied has the same effect as the electric vehicle to which the power conversion device of the fourth embodiment is applied.

(Embodiment 6)
<Railway vehicle>
Next, a railway vehicle according to a sixth embodiment of the present invention will be described. The railway vehicle according to the sixth embodiment is a railway vehicle including the power conversion device according to the fourth embodiment.

FIG. 26 is a diagram illustrating a configuration of the railway vehicle according to the sixth embodiment. As shown in FIG. 26, the railway vehicle 60 includes a pantograph 61 as a current collector, a transformer 62, a power converter 63, a load 64 that is an AC motor, and wheels 65. The power conversion device 63 includes a converter device 66, a capacitor 67 that is, for example, a capacitor, and an inverter device 68.

The converter device 66 has switching elements 69 and 70. The switching element 69 is disposed on the upper arm side, that is, the high voltage side, and the switching element 70 is disposed on the lower arm side, that is, the low voltage side. In FIG. 26, the switching elements 69 and 70 are shown for one phase among a plurality of phases.

The inverter device 68 has switching elements 71 and 72. The switching element 71 is disposed on the upper arm side, that is, the high voltage side, and the switching element 72 is disposed on the lower arm side, that is, the low voltage side. In FIG. 26, the switching elements 71 and 72 are shown for one of the three phases U phase, V phase and W phase.

One end of the primary side of the transformer 62 is connected to the overhead line 61 a via the pantograph 61. The other end of the primary side of the transformer 62 is connected to the line 65 a via the wheel 65. One end of the secondary side of the transformer 62 is connected to a terminal on the upper arm side opposite to the load 64 of the converter device 66. The other end of the secondary side of the transformer 62 is connected to a terminal on the lower arm side opposite to the load 64 of the converter device 66.

The terminal on the load 64 side and the upper arm side of the converter device 66 is connected to the terminal on the upper arm side opposite to the load 64 of the inverter device 68. The terminal on the load 64 side of the converter device 66 on the lower arm side is connected to the terminal on the lower arm side opposite to the load 64 of the inverter device 68. Further, a capacitor 67 is connected between a terminal on the side opposite to the load 64 of the inverter device 68 and on the upper arm side, and a terminal on the side opposite to the load 64 of the inverter device 68 and on the lower arm side. . Although not shown in FIG. 26, each of the three terminals on the output side of the inverter device 68 is connected to the load 64 as a U phase, a V phase, and a W phase.

In the sixth embodiment, the power conversion device 31a of the fourth embodiment (see FIG. 23) can be used as the inverter device 68.

The AC power collected from the overhead wire 61 a by the pantograph 61 is transformed by the converter device 66 into desired DC power after the voltage is transformed by the transformer 62. The DC power converted by the converter device 66 is smoothed by the capacitor 67. The DC power whose voltage has been smoothed by the capacitor 67 is converted into AC power by the inverter device 68. The AC power converted by the inverter device 68 is supplied to the load 64. The load 64 supplied with AC power rotationally drives the wheels 65, whereby the railway vehicle is accelerated.

<Main features and effects of the present embodiment>
As inverter device 68 of railway vehicle 60 of the sixth embodiment, power conversion device 31a (see FIG. 23) of the fourth embodiment can be used. As each of the switching elements 37u, 37v, 37w, 37x, 37y, and 37z provided in the power conversion device 31a, the semiconductor device 1 of the first embodiment, the second embodiment, or the third embodiment (FIG. 2, FIG. 18 or FIG. 19) can be used.

As a result, it is possible to prevent or suppress the deterioration of energization of the semiconductor device 1 when the return current flows through the body diodes 23 and 23a incorporated in the semiconductor device 1, so that power loss during power conversion can be prevented. Can be reduced. In addition, since it is not necessary to perform synchronous rectification with high accuracy using the control circuit 36, the design margin of the power module 35a and the power converter 31a can be widened, and the reliability of the power module 35a and the power converter 31a is improved. Can be made. Alternatively, since it is not necessary to provide an external diode separately from the body diodes 23 and 23a, the power module 35a and the power conversion device 31a can be reduced in size.

Accordingly, in the railway vehicle 60 of the sixth embodiment, the power loss at the time of power conversion in the inverter device 68 can be reduced, so that a large cooling device may not be provided. Therefore, the inverter device 68 can be easily reduced in cost, size, or weight by reducing the size of the cooling device. Therefore, it is possible to easily reduce the cost of the railway vehicle 60 including the inverter device 68 and improve the energy efficiency when operating the railway.

Alternatively, as switching elements 69 and 70 provided in converter device 66, semiconductor device 1 of the first, second, or third embodiment (see FIG. 2, FIG. 18, or FIG. 19) can be used. . Also in this case, since the power loss at the time of power conversion in the converter device 66 can be reduced, the converter device 66 can be easily reduced in cost, size, or weight. Therefore, it is possible to easily reduce the cost of the railway vehicle 60 including the converter device 66 and improve the energy efficiency when operating the railway.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The present invention is effective when applied to a semiconductor device, a power module, and a power conversion device.

1 semiconductor device 10 ^{n +} -type SiC substrate 10a upper surface 10b lower surface 12 n ^- - type epitaxial layer 13,13a, 13b, 13c p- type body region 14, 14a n ⁺ -type source region 14b ^{n +} -type field stop region 15, 15a p ⁺ Type body contact region 15b Contact region 16 JFET region 17 Channel region 18 Gate insulating film 18a, 18b Insulating film 19 Gate electrode 19a Gate pads 19b, 21b, 21c Conductive film 20 Interlayer insulating films 20a, 20b, 20c Contact hole 21 Source electrode 21a Contact electrode 22 Drain electrode 23, 23a Body diode 30 Motor system 30a Three- phase motor system 31, 31a Power converter 32, 32a Load 33 DC power supply 34 Capacity 35, 35a Power module 36, 36a Control circuit 37u, 37v, 37w, 37x, 37y, 37z switching element 38 MISFET
39 body diode 40 automobile 41a, 41b drive wheel 42 drive shaft 43 three-phase motor 44 inverter device 45 battery 46, 47 power line 48 boost converter device 49 relay 50 electronic control unit 51 reactor 52 smoothing capacitor 53 inverter device 54 switching element 55 MISFET
56 Body diode 60 Railway vehicle 61 Pantograph 61a Overhead line 62 Transformer 63 Power conversion device 64 Load 65 Wheel 65a Line 66 Converter device 67 Capacity 68 Inverter device 69 to 72 Switching element AR1 Active area AR2 Termination area AR3 Gate pad area CL1 Cell FO1 Field Oxide film GC1 Gate contact electrodes OP1, OP11, OP2, OP3, OP31 Openings OP4, OP5, OP51, OP52 Openings RF1 to RF5 Resist films RP1 to RP5 Resist patterns SIL1, SIL2 Silicide films TC1 to TC6 Control terminals TI1, TI2 Input Terminals TO1 to TO3 Output terminals

Claims (15)

1. A first conductivity type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
   A semiconductor layer of the first conductivity type formed on the first main surface of the semiconductor substrate;
   A first semiconductor region of a second conductivity type different from the first conductivity type formed in an upper layer portion of the semiconductor layer;
   A second semiconductor region of the first conductivity type formed in an upper layer portion of the first semiconductor region;
   A third semiconductor region of the second conductivity type formed in an upper layer portion of the first semiconductor region;
   A gate electrode formed on a top surface of the first semiconductor region in a portion sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film;
   A first metal film formed on the second semiconductor region and the third semiconductor region;
   A source electrode formed on the first metal film;
   A drain electrode formed on the second main surface of the semiconductor substrate;
   Have
   The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide,
   The semiconductor device, wherein the first metal film is Schottky connected to the third semiconductor region.
2. The semiconductor device according to claim 1,
   The semiconductor device, wherein the concentration of the p-type impurity in the third semiconductor region is less than 1 × 10 ²⁰ cm ⁻³ .
3. The semiconductor device according to claim 2,
   The first metal film is a semiconductor device containing nickel silicide.
4. The semiconductor device according to claim 3.
   The semiconductor device in which the composition ratio of nickel to the sum of nickel and silicon in the first metal film is greater than 0.4.
5. The semiconductor device according to claim 1,
   The semiconductor layer is a first region of the first main surface of the semiconductor substrate and a region of the first main surface of the semiconductor substrate, and is a region closer to the outer periphery of the semiconductor substrate than the first region The second region is formed on the first main surface of the semiconductor substrate,
   The first semiconductor region is formed in an upper layer portion of the semiconductor layer in the first region,
   The semiconductor device further includes:
   A second semiconductor region of the second conductivity type formed in an upper layer of the semiconductor layer in the second region;
   A fifth semiconductor region of the second conductivity type formed in an upper layer portion of the fourth semiconductor region;
   A second metal film formed on the fifth semiconductor region;
   A contact electrode formed on the second metal film;
   Have
   The fourth semiconductor region and the fifth semiconductor region are made of silicon carbide,
   The semiconductor device, wherein the second metal film is Schottky connected to the fifth semiconductor region.
6. The semiconductor device according to claim 5.
   The semiconductor device, wherein the concentration of the p-type impurity in the fifth semiconductor region is less than 1 × 10 ²⁰ cm ⁻³ .
7. The semiconductor device according to claim 6.
   The semiconductor device, wherein the second metal film includes nickel silicide.
8. The semiconductor device according to claim 7.
   In the semiconductor device, the composition ratio of nickel to the sum of nickel and silicon in the second metal film is greater than 0.4.
9. A power module comprising the semiconductor device according to claim 1.
10. A power converter comprising the power module according to claim 9.
11. A first conductivity type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
    The first region of the first main surface of the semiconductor substrate and the second region of the first main surface of the semiconductor substrate, which is a region closer to the outer periphery of the semiconductor substrate than the first region The semiconductor layer of the first conductivity type formed on the first main surface of the semiconductor substrate,
    A first semiconductor region of a second conductivity type different from the first conductivity type formed in an upper layer portion of the semiconductor layer in the first region;
    A second semiconductor region of the first conductivity type formed in an upper layer portion of the first semiconductor region;
    A third semiconductor region of the second conductivity type formed in an upper layer portion of the first semiconductor region;
    A second semiconductor region of the second conductivity type formed in an upper layer of the semiconductor layer in the second region;
    A fifth semiconductor region of the second conductivity type formed in an upper layer portion of the fourth semiconductor region;
    A gate electrode formed on a top surface of the first semiconductor region in a portion sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film;
    A first metal film formed on the second semiconductor region and the third semiconductor region;
    A second metal film formed on the fifth semiconductor region;
    A source electrode formed on the first metal film;
    A contact electrode formed on the second metal film;
    A drain electrode formed on the second main surface of the semiconductor substrate;
    Have
    The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are made of silicon carbide,
    The semiconductor device, wherein the concentration of the p-type impurity in the fifth semiconductor region is lower than the concentration of the p-type impurity in the third semiconductor region.
12. The semiconductor device according to claim 11.
    The concentration of the p-type impurity in the fifth semiconductor region is less than 1 × 10 ²⁰ cm ⁻³ ;
    The semiconductor device, wherein the concentration of the p-type impurity in the third semiconductor region is 1 × 10 ²⁰ cm ⁻³ or more.
13. The semiconductor device according to claim 12, wherein
    The semiconductor device, wherein the second metal film includes nickel silicide.
14. The semiconductor device according to claim 13.
    In the semiconductor device, the composition ratio of nickel to the sum of nickel and silicon in the second metal film is greater than 0.4.
15. A first conductivity type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
    The first region of the first main surface of the semiconductor substrate and the second region of the first main surface of the semiconductor substrate, which is a region closer to the outer periphery of the semiconductor substrate than the first region The semiconductor layer of the first conductivity type formed on the first main surface of the semiconductor substrate,
    A first semiconductor region of a second conductivity type different from the first conductivity type formed in an upper layer portion of the semiconductor layer in the first region;
    A second semiconductor region of the first conductivity type formed in an upper layer portion of the first semiconductor region;
    A third semiconductor region of the second conductivity type formed in an upper layer portion of the first semiconductor region;
    A second semiconductor region of the second conductivity type formed in an upper layer of the semiconductor layer in the second region;
    A fifth semiconductor region of the second conductivity type formed in an upper layer portion of the fourth semiconductor region;
    A gate electrode formed on a top surface of the first semiconductor region in a portion sandwiched between the second semiconductor region and the semiconductor layer via a gate insulating film;
    A first metal film formed on the second semiconductor region and the third semiconductor region and made of a metal silicide;
    A source electrode made of a first conductive film formed on the first metal film;
    A contact electrode made of a second conductive film formed on the fifth semiconductor region;
    A drain electrode formed on the second main surface of the semiconductor substrate;
    Have
    The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are made of silicon carbide,
    The second conductive film is formed in the same layer as the first conductive film,
    The semiconductor device, wherein the contact electrode is in contact with the fifth semiconductor region.

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