JP2012234848A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2012234848A
JP2012234848A JP2011100276A JP2011100276A JP2012234848A JP 2012234848 A JP2012234848 A JP 2012234848A JP 2011100276 A JP2011100276 A JP 2011100276A JP 2011100276 A JP2011100276 A JP 2011100276A JP 2012234848 A JP2012234848 A JP 2012234848A
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
effect transistor
layer
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011100276A
Other languages
Japanese (ja)
Inventor
Shigeru Watanabe
茂 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2011100276A priority Critical patent/JP2012234848A/en
Publication of JP2012234848A publication Critical patent/JP2012234848A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a field effect transistor and a regenerative element, in which switching loss is reduced by excellent recovery characteristics.SOLUTION: The semiconductor device includes a field effect transistor and a regenerative element. The field effect transistor includes a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type arranged on the surface of the first semiconductor layer, a third semiconductor layer having a first conductivity type arranged on the surface of the second semiconductor layer, a gate electrode arranged via an insulating film which is arranged contiguously to the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, a first metal layer, and a second metal layer. The regenerative element has an anode terminal to be connected electrically with the first metal layer, and a cathode terminal to be connected electrically with the second metal layer.

Description

本発明は、電界効果型トランジスタと回生素子とを含む半導体装置に関する。 The present invention relates to a semiconductor device including a field effect transistor and a regenerative element.

ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）は、代表的な電界効果型トランジスタとして知られ、例えばＤＣ−ＤＣコンバータ等のスイッチング電源装置におけるスイッチング素子に適用される。ＭＯＳＦＥＴは、第１導電型のドリフト領域と第２導電型のベース領域と第１導電型のソース領域とを備える。また、ＭＯＳＦＥＴは、ドリフト領域とベース領域とから形成され、回生素子として利用可能な寄生ダイオード（ｐｎダイオード）を備える。しかしながら、寄生ダイオードは逆回復時間（ｔｒｒ）等のリカバリ特性が悪いため、寄生ダイオードを回生素子として使用した場合、ＭＯＳＦＥＴにおけるスイッチング損失が増大し、スイッチング電源装置の変換効率が低下してしまう。 A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is known as a typical field effect transistor, and is applied to a switching element in a switching power supply device such as a DC-DC converter. The MOSFET includes a first conductivity type drift region, a second conductivity type base region, and a first conductivity type source region. The MOSFET includes a parasitic diode (pn diode) that is formed of a drift region and a base region and can be used as a regenerative element. However, since the parasitic diode has poor recovery characteristics such as reverse recovery time (trr), when the parasitic diode is used as a regenerative element, the switching loss in the MOSFET increases and the conversion efficiency of the switching power supply device decreases.

特許文献１は、寄生ダイオードのリカバリ特性を改善するために、プロトン照射によってＭＯＳＦＥＴのドリフト領域内にライフタイムキラー領域が形成された半導体装置を開示する。また、特許文献２は、寄生ダイオードの動作を抑制するために、寄生ダイオードに流れる電流を阻止するショットキバリアダイオード（ＳＢＤ：Schottky Barrier Diode）が形成された半導体装置を開示する。 Patent Document 1 discloses a semiconductor device in which a lifetime killer region is formed in a drift region of a MOSFET by proton irradiation in order to improve recovery characteristics of a parasitic diode. Patent Document 2 discloses a semiconductor device in which a Schottky Barrier Diode (SBD) that blocks a current flowing through the parasitic diode is formed in order to suppress the operation of the parasitic diode.

特開２０００−２６９２３４号公報JP 2000-269234 A 特開２００６−０６６７７０号公報JP 2006-0667770 A

特許文献１に示される半導体装置によれば、寄生ダイオードの逆回復時間が短くなる反面、ライフタイムキラー領域によってＭＯＳＦＥＴのオン抵抗が増大してしまう。また、特許文献２に示される半導体装置によれば、寄生ダイオードに電流が流れにくく、比較的リカバリ特性の良いＳＢＤに電流が流れるため、ＭＯＳＦＥＴのスイッチング損失が低減される。しかしながら、ＳＢＤに流れる電流が大きくなると寄生ダイオードが導通するため、スイッチング損失を十分に低減しているとは言えない。 According to the semiconductor device disclosed in Patent Document 1, the reverse recovery time of the parasitic diode is shortened, but the on-resistance of the MOSFET is increased by the lifetime killer region. Further, according to the semiconductor device disclosed in Patent Document 2, since current does not easily flow through the parasitic diode and current flows through the SBD having relatively good recovery characteristics, the switching loss of the MOSFET is reduced. However, when the current flowing through the SBD increases, the parasitic diode becomes conductive, so it cannot be said that the switching loss is sufficiently reduced.

本発明は、電界効果型トランジスタと回生素子とを含み、優れたリカバリ特性によりスイッチング損失が低減された半導体装置を提供することを目的とする。 An object of the present invention is to provide a semiconductor device that includes a field effect transistor and a regenerative element and has reduced switching loss due to excellent recovery characteristics.

本発明の一態様によれば、電界効果型トランジスタと回生素子とを含み、
前記電界効果型トランジスタは、第１の導電型を有する第１の半導体層と、前記第１の半導体層の表面に配置された第２導電型を有する第２の半導体層と、前記第２の半導体層の表面に配置された前記第１導電型を有する第３の半導体層と、前記第１の半導体層と前記第２の半導体層と前記第３の半導体層とに隣接するように配置された絶縁膜と、前記絶縁膜を介して前記第２の半導体層に対向するように配置されたゲート電極と、前記第２の半導体層とショットキ接合を形成するとともに前記第３の半導体層とオーミック接合を形成する第１の金属層と、前記第１の半導体層とオーミック接合を形成する第２の金属層と、を備え、
前記ショットキ接合は、前記第１の半導体層と前記第２の半導体層とが形成するｐｎ接合に流れる電流を阻止する整流方向を有し、
前記回生素子は、前記第１の金属層と電気的に接続されるアノード端子と、前記第２の金属層と電気的に接続されるカソード端子と、を備えることを特徴とする。 According to one aspect of the present invention, a field effect transistor and a regenerative element are included,
The field effect transistor includes a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type disposed on a surface of the first semiconductor layer, and the second semiconductor layer. A third semiconductor layer having the first conductivity type disposed on a surface of the semiconductor layer; and disposed adjacent to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. An insulating film; a gate electrode disposed to face the second semiconductor layer through the insulating film; and a Schottky junction with the second semiconductor layer and an ohmic contact with the third semiconductor layer A first metal layer that forms a junction; and a second metal layer that forms an ohmic junction with the first semiconductor layer;
The Schottky junction has a rectifying direction that blocks a current flowing through a pn junction formed by the first semiconductor layer and the second semiconductor layer;
The regenerative element includes an anode terminal electrically connected to the first metal layer and a cathode terminal electrically connected to the second metal layer.

本発明によれば、電界効果型トランジスタと回生素子とを含み、優れたリカバリ特性によりスイッチング損失が低減された半導体装置を提供できる。 According to the present invention, it is possible to provide a semiconductor device including a field-effect transistor and a regenerative element and having reduced switching loss due to excellent recovery characteristics.

本発明の実施形態に係る半導体装置の平面図及び等価回路図である。It is the top view and equivalent circuit schematic of the semiconductor device which concern on embodiment of this invention. 本発明の実施形態に係る半導体装置が備える電界効果型トランジスタの構造断面図である。It is a structure sectional view of a field effect transistor with which a semiconductor device concerning an embodiment of the present invention is provided. 比較例に係る半導体装置の等価回路図である。It is an equivalent circuit diagram of a semiconductor device according to a comparative example. 本発明の実施形態及び比較例に係る半導体装置のリカバリ特性を示す波形図である。It is a wave form diagram which shows the recovery characteristic of the semiconductor device which concerns on embodiment and comparative example of this invention. 本発明の実施形態の変形例に係る半導体装置が備える電界効果型トランジスタの構造断面図である。It is a structure sectional view of a field effect transistor with which a semiconductor device concerning a modification of an embodiment of the present invention is provided. 本発明の実施例に係るスイッチング電源装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the switching power supply device which concerns on the Example of this invention.

次に、図面を参照して、本発明の実施形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、各層の厚みの比率等は現実のものとは異なることに留意すべきである。従って、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the ratio of the thickness of each layer is different from the actual one. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

また、以下に示す実施形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の実施形態は、構成部品の材質、形状、構造、配置等を下記の者に特定するものではない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention are materials, shapes, structures, arrangements, etc. of components. Is not specified to the following persons. The technical idea of the present invention can be variously modified within the scope of the claims.

図１は、本発明の実施形態に係る半導体装置の平面図（ａ）及び等価回路図（ｂ）である。図２は、本発明の実施形態に係る半導体装置が備える電界効果型トランジスタの構造断面図である。本実施形態に係る半導体装置１００は、電界効果型トランジスタ１と回生素子２とを備える。電界効果型トランジスタ１は、第１の半導体層１１と第２の半導体層１２と第３の半導体層１３と絶縁膜１５とゲート電極１６と第１の金属層１８と第２の金属層１９とを備える。回生素子２は、アノード端子２１とカソード端子２２とを備える。 FIG. 1 is a plan view (a) and an equivalent circuit diagram (b) of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a structural cross-sectional view of a field effect transistor included in the semiconductor device according to the embodiment of the present invention. The semiconductor device 100 according to the present embodiment includes a field effect transistor 1 and a regenerative element 2. The field effect transistor 1 includes a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, an insulating film 15, a gate electrode 16, a first metal layer 18, and a second metal layer 19. Is provided. The regenerative element 2 includes an anode terminal 21 and a cathode terminal 22.

本実施形態に係る電界効果型トランジスタ１は、シリコン（Ｓｉ）で構成される縦型のＭＯＳＦＥＴ（Metal-Oxide-Semiconductor
Field-Effect Transistor）である。なお、電界効果型トランジスタ１は、Ｓｉ以外の例えばシリコンカーバイド（ＳｉＣ）又は窒化ガリウム（ＧａＮ）等の材料で構成されても良い。 The field effect transistor 1 according to the present embodiment is a vertical MOSFET (Metal-Oxide-Semiconductor) made of silicon (Si).
Field-Effect Transistor). The field effect transistor 1 may be made of a material other than Si, such as silicon carbide (SiC) or gallium nitride (GaN).

第１の半導体層１１は、ＭＯＳＦＥＴのドレイン層に相当し、Ｎ＋型のドレイン領域１１ａと、ドレイン領域１１ａの表面上に形成され且つドレイン領域１１ａよりも低いＮ型不純物濃度を有するＮ−型のドリフト領域１１ｂと、から構成される。 The first semiconductor layer 11 corresponds to the drain layer of the MOSFET, and is an N + type drain region 11a and an N− type impurity region formed on the surface of the drain region 11a and having an N type impurity concentration lower than that of the drain region 11a. And a drift region 11b.

第２の半導体層１２は、ＭＯＳＦＥＴのベース層に相当し、第１の半導体層１１の表面上に形成されたＰ型の第１のベース領域１２ａと、第１のベース領域１２ａの表面上に形成され且つ第１のベース領域１２ａよりも低いＰ型不純物濃度を有するＰ−型の第２のベース領域１２ｂと、から構成される。本実施形態における第１のベース領域１２ａは、ドリフト領域１１ｂに隣接するように形成され、ドリフト領域１１ｂとの間にｐｎ接合（第１の寄生ダイオードＤ１）を形成する。 The second semiconductor layer 12 corresponds to the base layer of the MOSFET. The P-type first base region 12a formed on the surface of the first semiconductor layer 11 and the surface of the first base region 12a. And a P-type second base region 12b formed and having a P-type impurity concentration lower than that of the first base region 12a. The first base region 12a in the present embodiment is formed adjacent to the drift region 11b, and forms a pn junction (first parasitic diode D1) with the drift region 11b.

第３の半導体層１３は、ＭＯＳＦＥＴのソース層に相当し、第２の半導体層１２の表面領域において複数の島状に形成されたＮ型の第１のソース領域１３ａと、第１のソース領域１３ａの表面領域において島状に形成され且つ第１のソース領域１３ａよりも高いＮ型不純物濃度を有するＮ＋型の第２のソース領域１３ｂと、から構成される。複数の第１のソース領域１３ａのそれぞれは、第２のベース領域１２ｂによって包囲される。また、第１のソース領域１３ａは、第２のベース領域１２ｂに隣接するように形成され、第２のベース領域１２ｂとの間にｐｎ接合（第２の寄生ダイオードＤ２）を形成する。 The third semiconductor layer 13 corresponds to the source layer of the MOSFET, and an N-type first source region 13 a formed in a plurality of island shapes in the surface region of the second semiconductor layer 12, and the first source region The N + type second source region 13b is formed in an island shape in the surface region 13a and has an N type impurity concentration higher than that of the first source region 13a. Each of the plurality of first source regions 13a is surrounded by the second base region 12b. The first source region 13a is formed adjacent to the second base region 12b, and forms a pn junction (second parasitic diode D2) with the second base region 12b.

第１の半導体層１１と第２の半導体層１２と第３の半導体層１３とは、一方及び他方の主面を有する半導体基板を構成する。半導体基板の一方の主面には、第２のベース領域１２ｂと第１のソース領域１３ａと第２のソース領域１３ｂとが露出し、半導体基板の他方の主面にはドレイン領域１１ａが露出する。 The first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 constitute a semiconductor substrate having one and the other main surfaces. The second base region 12b, the first source region 13a, and the second source region 13b are exposed on one main surface of the semiconductor substrate, and the drain region 11a is exposed on the other main surface of the semiconductor substrate. .

電界効果型トランジスタ１は、トレンチゲート型のＭＯＳＦＥＴであって、半導体基板の一方の主面側から第３の半導体層１３と第２の半導体層１２とを貫通して第１の半導体層１１に到達するトレンチ１４を備える。トレンチ１４の底面及び側面は、第１の半導体層１１と第２の半導体層１２と第３の半導体層１３とに隣接する絶縁膜１５で覆われる。絶縁膜１５は、酸化シリコン（ＳｉＯｘ）、窒化シリコン（ＳｉＮ）又は酸化アルミニウム（Ａｌ２Ｏ３）等からなる。また、トレンチ１４の内部には、絶縁膜１５を介して第１の半導体層１１と第２の半導体層１２と第３の半導体層１３とに対向するゲート電極１６が形成される。なお、ゲート電極１６は、少なくとも第２の半導体層１２と対向するように形成され、ポリシリコン（多結晶シリコン）又はアルミニウム（Ａｌ）等の材料からなる。 The field effect transistor 1 is a trench gate type MOSFET, and penetrates the third semiconductor layer 13 and the second semiconductor layer 12 from one main surface side of the semiconductor substrate to form the first semiconductor layer 11. A reaching trench 14 is provided. The bottom and side surfaces of the trench 14 are covered with an insulating film 15 adjacent to the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13. The insulating film 15 is made of silicon oxide (SiO x ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), or the like. A gate electrode 16 is formed inside the trench 14 so as to face the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 with an insulating film 15 interposed therebetween. The gate electrode 16 is formed so as to face at least the second semiconductor layer 12 and is made of a material such as polysilicon (polycrystalline silicon) or aluminum (Al).

第１の金属層１８は、第２の半導体層１２とショットキ接合（第３の寄生ダイオードＤ３）を形成するとともに第３の半導体層１３とオーミック接合を形成する。詳細には、第１の金属層１８は、半導体基板の一方の主面上に形成され、第２のベース領域１２ｂにショットキ接続され、第１のソース領域１３ａと第２のソース領域１３ｂとにオーミック接続される。第１の金属層１８とゲート電極１６とは、層間絶縁膜１７により電気的に絶縁される。第１の金属層１８は、電界効果型トランジスタ１におけるソース電極であり、Ａｌまたはチタン（Ｔｉ）等の金属からなる。層間絶縁膜１７は、ＳｉＯｘ、ＳｉＮ又はＡｌ２Ｏ３等からなる。 The first metal layer 18 forms a Schottky junction (third parasitic diode D3) with the second semiconductor layer 12, and forms an ohmic junction with the third semiconductor layer 13. Specifically, the first metal layer 18 is formed on one main surface of the semiconductor substrate, is Schottky connected to the second base region 12b, and is connected to the first source region 13a and the second source region 13b. Ohmic connected. The first metal layer 18 and the gate electrode 16 are electrically insulated by the interlayer insulating film 17. The first metal layer 18 is a source electrode in the field effect transistor 1 and is made of a metal such as Al or titanium (Ti). The interlayer insulating film 17 is made of SiO x , SiN, Al 2 O 3 or the like.

第２の金属層１９は、第１の半導体層１１とオーミック接合を形成する。詳細には、第２の金属層１９は、半導体基板の他方の主面上に形成され、ドレイン領域１１ａにオーミック接続される。第２の金属層１９は、電界効果型トランジスタ１におけるドレイン電極であり、金（Ａｕ）、ニッケル（Ｎｉ）またはＡｌ等の金属からなる。 The second metal layer 19 forms an ohmic junction with the first semiconductor layer 11. Specifically, the second metal layer 19 is formed on the other main surface of the semiconductor substrate and is ohmically connected to the drain region 11a. The second metal layer 19 is a drain electrode in the field effect transistor 1 and is made of a metal such as gold (Au), nickel (Ni), or Al.

ここで、本実施形態に係る電界効果型トランジスタ１が有する３つの寄生ダイオードについて説明する。第１の寄生ダイオードＤ１は、第２の半導体層１２をアノードとし、第１の半導体層１１をカソードとするダイオードであって、電界効果型トランジスタ１のオフ時に第１の半導体層１１から第２の半導体層１２に向かって流れる電流を阻止する。第２の寄生ダイオードＤ２は、第２の半導体層１２をアノードとし、第３の半導体層１３をカソードとするダイオードであって、電界効果型トランジスタ１のオフ時に第３の半導体層１３から第２の半導体層１２に向かって流れる電流を阻止する。第３の寄生ダイオードＤ３は、第２の半導体層１２をアノードとし、第１の金属層１８をカソードとするＳＢＤ（Schottky Barrier Diode）であって、電界効果型トランジスタ１のオフ時に第１の金属層１８から第２の半導体層１２に向かって流れる電流を阻止する。即ち、第２及び第３の寄生ダイオードＤ２，Ｄ３の整流方向は、第１の寄生ダイオードＤ１の整流方向と反対向きである。そのため、電界効果型トランジスタ１は、そのオフ時に第１の金属層１８と第２の金属層１９との間に流れる電流は、第１乃至第３の寄生ダイオードにより阻止される。 Here, three parasitic diodes included in the field effect transistor 1 according to the present embodiment will be described. The first parasitic diode D1 is a diode having the second semiconductor layer 12 as an anode and the first semiconductor layer 11 as a cathode. The first parasitic diode D1 is a second diode from the first semiconductor layer 11 when the field effect transistor 1 is turned off. Current flowing toward the semiconductor layer 12 is blocked. The second parasitic diode D2 is a diode having the second semiconductor layer 12 as an anode and the third semiconductor layer 13 as a cathode, and is connected to the second semiconductor layer 13 from the third semiconductor layer 13 when the field effect transistor 1 is turned off. Current flowing toward the semiconductor layer 12 is blocked. The third parasitic diode D3 is an SBD (Schottky Barrier Diode) having the second semiconductor layer 12 as an anode and the first metal layer 18 as a cathode, and the first metal when the field effect transistor 1 is turned off. The current flowing from the layer 18 toward the second semiconductor layer 12 is blocked. That is, the rectification direction of the second and third parasitic diodes D2 and D3 is opposite to the rectification direction of the first parasitic diode D1. Therefore, in the field effect transistor 1, current flowing between the first metal layer 18 and the second metal layer 19 when the transistor 1 is turned off is blocked by the first to third parasitic diodes.

本実施形態に係る回生素子２は、Ｓｉから構成される周知のＦＲＤ（Fast Recovery Diode）であり、例えばＦＭＤ−Ｇ２６Ｓを適用することができる。なお、回生素子２としてＭＰＳ（Merged PiN Schottky）ダイオード、ＳＢＤ又はｐｎダイオードを適用しても良い。また、回生素子２は、Ｓｉ以外のＳｉＣ又はＧａＮ等の材料で構成されても良く、電界効果型トランジスタ１と異なる材料で構成されても良い。 The regenerative element 2 according to the present embodiment is a well-known FRD (Fast Recovery Diode) made of Si, and for example, FMD-G26S can be applied. Note that an MPS (Merged PiN Schottky) diode, SBD, or pn diode may be applied as the regenerative element 2. Further, the regenerative element 2 may be made of a material such as SiC or GaN other than Si, or may be made of a material different from that of the field effect transistor 1.

回生素子２は、第１の寄生ダイオードＤ１に比べ短いｔｒｒ（逆回復時間）及び低いＶｆ（順方向電圧）等の特性を有する半導体素子が用いられる。回生素子２の整流方向は、第２及び第３の寄生ダイオードＤ２，Ｄ３の整流方向と反対向きである。 The regenerative element 2 is a semiconductor element having characteristics such as a shorter trr (reverse recovery time) and lower Vf (forward voltage) than the first parasitic diode D1. The rectification direction of the regenerative element 2 is opposite to the rectification direction of the second and third parasitic diodes D2 and D3.

図１（ａ）に示すように、半導体装置１００は、第１のリードフレームＬ１、第２のリードフレームＬ２、及び第３のリードフレームＬ３と、第２のリードフレームＬ２上に配置された電界効果型トランジスタ１及び回生素子２と、各半導体素子とリードとを接続する第１のワイヤＷ１、第２のワイヤＷ２、及び第３のワイヤＷ３と、これらを封止するモールドパッケージＭＰと、から構成される。また、電界効果型トランジスタ１は、ゲート電極１６と電気的に接続される第１のパッドＰ１と、第１の金属層１８と電気的に接続される第２のパッドＰ２と、を備え、回生素子２は、アノード端子２２と電気的に接続される第３のパッドＰ３を備える。 As shown in FIG. 1A, the semiconductor device 100 includes an electric field disposed on the first lead frame L1, the second lead frame L2, the third lead frame L3, and the second lead frame L2. The effect transistor 1 and the regenerative element 2, the first wire W1, the second wire W2, and the third wire W3 that connect each semiconductor element and the lead, and the mold package MP that seals them. Composed. Further, the field effect transistor 1 includes a first pad P1 electrically connected to the gate electrode 16 and a second pad P2 electrically connected to the first metal layer 18, and regeneratively. The element 2 includes a third pad P3 that is electrically connected to the anode terminal 22.

第１のリードフレームＬ１は、第１のワイヤＷ１を介して第１のパッドＰ１と電気的に接続され、半導体装置１００のゲート端子を構成する。第２のリードフレームＬ２は、電界効果型トランジスタ１及び回生素子２を機械的に支持するとともに、はんだ等の導電性接着層（図示せず）を介して電界効果型トランジスタ１の第２の金属層１９及び回生素子２のカソード端子２１に電気的に接続され、半導体装置１００のドレイン端子を構成する。第３のリードフレームＬ３は、第２のワイヤＷ２を介して第２のパッドＰ２と電気的に接続されるとともに、第３のワイヤＷ３を介して第３のパッドＰ３と電気的に接続され、半導体装置１００のソース端子を構成する。第１乃至第３のリードフレームは、銅（Ｃｕ）等の金属からなり、第１乃至第３のワイヤは、それぞれＡｌ、Ａｕ又はＣｕ等からなる。回生素子２は、第１の寄生ダイオードＤ１と同一の整流方向を有し、電界効果型トランジスタ１に対して並列接続される。 The first lead frame L1 is electrically connected to the first pad P1 via the first wire W1, and constitutes a gate terminal of the semiconductor device 100. The second lead frame L2 mechanically supports the field effect transistor 1 and the regenerative element 2 and also has a second metal of the field effect transistor 1 through a conductive adhesive layer (not shown) such as solder. It is electrically connected to the layer 19 and the cathode terminal 21 of the regenerative element 2 and constitutes the drain terminal of the semiconductor device 100. The third lead frame L3 is electrically connected to the second pad P2 via the second wire W2, and is electrically connected to the third pad P3 via the third wire W3. A source terminal of the semiconductor device 100 is configured. The first to third lead frames are made of metal such as copper (Cu), and the first to third wires are made of Al, Au, Cu, or the like. The regenerative element 2 has the same rectification direction as the first parasitic diode D1, and is connected in parallel to the field effect transistor 1.

本実施形態に係る半導体装置１００の効果について説明する。半導体装置１００の特性上の利点を説明するために、図１及び図３に示した構造の半導体装置を用いて行った実験の結果を示す。図３は、Ｓｉからなる従来の電界効果型トランジスタ２０１（例えば２ＳＫ２７０１）とＳｉからなるＦＲＤ２０２（例えばＦＭＤ−Ｇ２６Ｓ）とを並列接続した、比較例に係る半導体装置３００の等価回路図である。電界効果型トランジスタ２０１は、ドリフト領域とベース領域とから形成され、且つ、寄生ダイオードＤ１と略同一のリカバリ特性を有する寄生ダイオードＤ２０１を有する。 The effect of the semiconductor device 100 according to the present embodiment will be described. In order to explain the advantages of the characteristics of the semiconductor device 100, results of experiments conducted using the semiconductor device having the structure shown in FIGS. 1 and 3 are shown. FIG. 3 is an equivalent circuit diagram of a semiconductor device 300 according to a comparative example in which a conventional field effect transistor 201 (for example, 2SK2701) made of Si and an FRD 202 (for example, FMD-G26S) made of Si are connected in parallel. The field effect transistor 201 includes a parasitic diode D201 that is formed of a drift region and a base region and has substantially the same recovery characteristics as the parasitic diode D1.

図４は、本発明の実施形態及び比較例に係る半導体装置のリカバリ特性を示す波形図である。リカバリ特性の測定として、それぞれの半導体装置が備える回生素子を順方向バイアスし約７．５Ａの電流を流した状態から、約１００Ｖの逆方向バイアスを印加した時のアノード・カソード間に流れる電流（Ａ）と印加される電圧（Ｖ）とを測定した。 FIG. 4 is a waveform diagram showing recovery characteristics of the semiconductor device according to the embodiment and the comparative example of the present invention. As a measurement of the recovery characteristics, the current flowing between the anode and the cathode when a reverse bias of about 100 V is applied from a state in which a regenerative element included in each semiconductor device is forward-biased and a current of about 7.5 A flows. A) and the applied voltage (V) were measured.

リカバリ特性を測定した結果、図１に示す半導体装置１００の逆回復時間（ｔｒｒ）は約５０ｎｓであった（図４（ａ））。この特性は、回生素子２単体による逆回復時間と略等しく、電界効果型トランジスタ１の寄生ダイオードがキャンセルされているため、回生素子２の特性が支配的になっていることに起因する。一方、図３に示す半導体装置３００の逆回復時間は約４００ｎｓであった（図４（ｂ））。この特性は、電界効果型トランジスタ２０１即ち寄生ダイオードＤ２０１単体による逆回復時間と略等しく、電界効果型トランジスタ２０１のリカバリ特性が支配的になっていることに起因する。従って、本実施形態に係る半導体装置１００は、優れたリカバリ特性を有し、逆回復時間が短くなることにより、スイッチング損失が低減されるとともに、ノイズ発生を抑制することができる。また、半導体装置１００に流れるリカバリ電流のピーク値は、半導体装置３００のリカバリ電流の約１／６程度に低減されるため、半導体装置１００は回生動作時の損失及びノイズ発生を低減することができる。 As a result of measuring the recovery characteristics, the reverse recovery time (trr) of the semiconductor device 100 shown in FIG. 1 was about 50 ns (FIG. 4A). This characteristic is substantially equal to the reverse recovery time of the regenerative element 2 alone, and is caused by the characteristic of the regenerative element 2 being dominant because the parasitic diode of the field effect transistor 1 is canceled. On the other hand, the reverse recovery time of the semiconductor device 300 shown in FIG. 3 was about 400 ns (FIG. 4B). This characteristic is substantially equal to the reverse recovery time of the field effect transistor 201, that is, the parasitic diode D201 alone, and is caused by the fact that the recovery characteristic of the field effect transistor 201 is dominant. Therefore, the semiconductor device 100 according to the present embodiment has excellent recovery characteristics, and the reverse recovery time is shortened, whereby switching loss is reduced and noise generation can be suppressed. Further, since the peak value of the recovery current flowing through the semiconductor device 100 is reduced to about 1/6 of the recovery current of the semiconductor device 300, the semiconductor device 100 can reduce loss and noise generation during the regenerative operation. .

また、寄生ダイオードＤ２０１に電流が流れないように、電界効果型トランジスタ２０１のドレイン電極に寄生ダイオードＤ２０１の逆阻止ダイオードを外付けすることで、半導体装置３００のリカバリ特性を改善することができる。しかしながら、半導体装置３００を構成する部品点数が増加し、リードフレーム形状が複雑になり且つワイヤ本数が増加してしまう。本発明の実施形態に係る半導体装置１００は、これらの部品点数増加などを伴わず小型且つ安価なパッケージ構造により、優れたリカバリ特性を有する半導体装置を提供することができる。 Further, the recovery characteristic of the semiconductor device 300 can be improved by externally attaching a reverse blocking diode of the parasitic diode D201 to the drain electrode of the field effect transistor 201 so that no current flows through the parasitic diode D201. However, the number of parts constituting the semiconductor device 300 increases, the lead frame shape becomes complicated, and the number of wires increases. The semiconductor device 100 according to the embodiment of the present invention can provide a semiconductor device having excellent recovery characteristics by a small and inexpensive package structure without increasing the number of parts.

図５は、本発明の実施形態の変形例に係る半導体装置が備える電界効果型トランジスタの構造断面図である。本変形例に係る電界効果型トランジスタ１０１は、第１の半導体層１１１と第２の半導体層１１２と第３の半導体層１１３と絶縁膜１１５とゲート電極１１６と第１の金属層１１８と第２の金属層１１９とを備える。 FIG. 5 is a structural cross-sectional view of a field effect transistor included in a semiconductor device according to a modification of the embodiment of the present invention. The field effect transistor 101 according to this modification includes a first semiconductor layer 111, a second semiconductor layer 112, a third semiconductor layer 113, an insulating film 115, a gate electrode 116, a first metal layer 118, and a second semiconductor layer 111. Metal layer 119.

電界効果型トランジスタ１０１は、プレーナ型のＭＯＳＦＥＴであって、第１の半導体層１１１と第２の半導体層１１２と第３の半導体層１１３とを有する半導体基板の一方の主面上に形成されたゲート絶縁膜１１５と、ゲート絶縁膜１１５上に形成されたゲート電極１１６と、を備える。ゲート絶縁膜１１５及びゲート電極１１６は、第１の半導体層１１１と第２の半導体層１１２と第３の半導体層１１３とに対向するように形成される。また、第３の半導体層１１３は、Ｎ＋型のソース領域のみで構成されるが、図１に示す電界効果型トランジスタ１と同様に第１及び第２のソース領域から構成されても良い。 The field effect transistor 101 is a planar MOSFET, and is formed on one main surface of a semiconductor substrate having a first semiconductor layer 111, a second semiconductor layer 112, and a third semiconductor layer 113. A gate insulating film 115 and a gate electrode 116 formed on the gate insulating film 115 are provided. The gate insulating film 115 and the gate electrode 116 are formed so as to face the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113. The third semiconductor layer 113 includes only the N + type source region, but may include the first and second source regions in the same manner as the field effect transistor 1 illustrated in FIG.

本変形例に係る電界効果型トランジスタ１０１は、第１のベース領域１１２ａとドリフト領域１１１ｂとからなる第１の寄生ダイオードと、第２のベース領域１１２ｂとソース領域１１３とからなる第２の寄生ダイオードと、第２のベース領域１１２ｂと第１の金属層１１８とからなる第３の寄生ダイオードと、を備える。また、電界効果型トランジスタ１のそれらと同様、第２及び第３の寄生ダイオードの整流方向は、第１の寄生ダイオードの整流方向と反対向きである。 The field effect transistor 101 according to this modification includes a first parasitic diode composed of a first base region 112a and a drift region 111b, and a second parasitic diode composed of a second base region 112b and a source region 113. And a third parasitic diode composed of the second base region 112b and the first metal layer 118. Further, like those of the field effect transistor 1, the rectification direction of the second and third parasitic diodes is opposite to the rectification direction of the first parasitic diode.

本変形例に係る電界効果型トランジスタ１０１によれば、本発明の実施形態に係る電界効果型トランジスタ１と同様の効果を得ることができる。 According to the field effect transistor 101 according to this modification, it is possible to obtain the same effect as that of the field effect transistor 1 according to the embodiment of the present invention.

図６は、本発明の実施例に係るスイッチング電源装置の構成を示す回路図である。スイッチング電源装置は、本発明の実施形態に係る半導体装置１００と、リアクトルＬと、コンデンサＣと、を備える。ハーフブリッジ回路を構成する２つの半導体装置１００が直流電源Ｖｄｄとグランドとの間に直列に接続され、接続点とグランドとの間にリアクトルＬとコンデンサＣとの直列回路が接続され、コンデンサＣと並列に負荷Ｒが接続される。本実施例に係るスイッチング装置は、同期整流方式のＤＣ−ＤＣコンバータであるが、半導体装置１００は、例えば周知のフルブリッジ回路、三相交流回路、昇圧チョッパ回路、フライバック回路等に適用することができる。また、半導体装置１００は、上記の変形例に係る電界効果型トランジスタ１０１を用いた半導体装置でも良い。 FIG. 6 is a circuit diagram showing a configuration of the switching power supply device according to the embodiment of the present invention. The switching power supply device includes a semiconductor device 100 according to an embodiment of the present invention, a reactor L, and a capacitor C. Two semiconductor devices 100 constituting a half-bridge circuit are connected in series between the DC power supply Vdd and the ground, and a series circuit of a reactor L and a capacitor C is connected between the connection point and the ground. A load R is connected in parallel. Although the switching device according to the present embodiment is a synchronous rectification type DC-DC converter, the semiconductor device 100 is applied to, for example, a well-known full bridge circuit, a three-phase AC circuit, a boost chopper circuit, a flyback circuit, or the like. Can do. Further, the semiconductor device 100 may be a semiconductor device using the field effect transistor 101 according to the above modification.

本実施例に係るスイッチング電源装置によれば、スイッチング素子として用いられる半導体装置１００におけるスイッチング損失が小さいため、スイッチング電源装置の電力変換効率が改善される。 According to the switching power supply according to the present embodiment, since the switching loss in the semiconductor device 100 used as a switching element is small, the power conversion efficiency of the switching power supply is improved.

以上の実施形態で説明された構成、形状、大きさおよび配置関係については、本発明が理解・実施できる程度に概略的に示したものにすぎない。従って本発明は、説明された実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。 The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

１、１０１ 電界効果型トランジスタ
２ 回生素子
１１ 第１の半導体層
１１ａ ドレイン領域
１１ｂ ドリフト領域
１２ 第２の半導体層
１２ａ 第１のベース領域
１２ｂ 第２のベース領域
１３ 第３の半導体層
１３ａ 第１のソース領域
１３ｂ 第２のソース領域
１４ トレンチ
１５ ゲート絶縁膜
１６ ゲート電極
１７ 層間絶縁膜
１８ 第１の金属層
１９ 第２の金属層
２１ カソード端子
２２ アノード端子
Ｄ１ 第１の寄生ダイオード
Ｄ２ 第２の寄生ダイオード
Ｄ３ 第３の寄生ダイオード
１００ 半導体装置
1, 101 Field effect transistor 2 Regenerative element 11 First semiconductor layer 11a Drain region 11b Drift region 12 Second semiconductor layer 12a First base region 12b Second base region 13 Third semiconductor layer 13a First Source region 13b Second source region 14 Trench 15 Gate insulating film 16 Gate electrode 17 Interlayer insulating film 18 First metal layer 19 Second metal layer 21 Cathode terminal 22 Anode terminal D1 First parasitic diode D2 Second parasitic Diode D3 Third parasitic diode 100 Semiconductor device

Claims (4)

電界効果型トランジスタと回生素子とを含み、
前記電界効果型トランジスタは、第１の導電型を有する第１の半導体層と、
前記第１の半導体層の表面に配置された第２導電型を有する第２の半導体層と、
前記第２の半導体層の表面に配置された前記第１導電型を有する第３の半導体層と、
前記第１の半導体層と前記第２の半導体層と前記第３の半導体層とに隣接するように配置された絶縁膜と、
前記絶縁膜を介して前記第２の半導体層に対向するように配置されたゲート電極と、
前記第２の半導体層とショットキ接合を形成するとともに前記第３の半導体層とオーミック接合を形成する第１の金属層と、
前記第１の半導体層とオーミック接合を形成する第２の金属層と、を備え、
前記ショットキ接合は、前記第１の半導体層と前記第２の半導体層とが形成するｐｎ接合に流れる電流を阻止する整流方向を有し、
前記回生素子は、前記第１の金属層と電気的に接続されるアノード端子と、
前記第２の金属層と電気的に接続されるカソード端子と、を備えることを特徴とする半導体装置。 Including a field effect transistor and a regenerative element,
The field effect transistor includes: a first semiconductor layer having a first conductivity type;
A second semiconductor layer having a second conductivity type disposed on a surface of the first semiconductor layer;
A third semiconductor layer having the first conductivity type disposed on a surface of the second semiconductor layer;
An insulating film disposed adjacent to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
A gate electrode disposed to face the second semiconductor layer with the insulating film interposed therebetween;
A first metal layer forming a Schottky junction with the second semiconductor layer and forming an ohmic junction with the third semiconductor layer;
A second metal layer forming an ohmic junction with the first semiconductor layer,
The Schottky junction has a rectifying direction that blocks a current flowing through a pn junction formed by the first semiconductor layer and the second semiconductor layer;
The regenerative element includes an anode terminal electrically connected to the first metal layer;
A semiconductor device comprising: a cathode terminal electrically connected to the second metal layer. 電界効果型トランジスタと回生素子とを含み、
前記電界効果型トランジスタは、第１の導電型を有する第１の半導体層と、
前記第１の半導体層の表面において互いに離間するように配置された第２導電型を有する複数の第２の半導体層と、
前記第２の半導体層の表面に配置された前記第１導電型を有する第３の半導体層と、
前記第１の半導体層と前記第２の半導体層と前記第３の半導体層とに隣接するように配置された絶縁膜と、
前記絶縁膜を介して前記第２の半導体層に対向するように配置されたゲート電極と、
前記第２の半導体層とショットキ接合を形成するとともに前記第３の半導体層とオーミック接合を形成する第１の金属層と、
前記第１の半導体層とオーミック接合を形成する第２の金属層と、を備え、
前記ショットキ接合は、前記第１の半導体層と前記第２の半導体層とが形成するｐｎ接合に流れる電流を阻止する整流方向を有し、
前記回生素子は、前記第１の金属層と電気的に接続されるアノード端子と、
前記第２の金属層と電気的に接続されるカソード端子と、を備えることを特徴とする半導体装置。 Including a field effect transistor and a regenerative element,
The field effect transistor includes: a first semiconductor layer having a first conductivity type;
A plurality of second semiconductor layers having a second conductivity type disposed so as to be spaced apart from each other on a surface of the first semiconductor layer;
A third semiconductor layer having the first conductivity type disposed on a surface of the second semiconductor layer;
An insulating film disposed adjacent to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
A gate electrode disposed to face the second semiconductor layer with the insulating film interposed therebetween;
A first metal layer forming a Schottky junction with the second semiconductor layer and forming an ohmic junction with the third semiconductor layer;
A second metal layer forming an ohmic junction with the first semiconductor layer,
The Schottky junction has a rectifying direction that blocks a current flowing through a pn junction formed by the first semiconductor layer and the second semiconductor layer;
The regenerative element includes an anode terminal electrically connected to the first metal layer;
A semiconductor device comprising: a cathode terminal electrically connected to the second metal layer. 前記回生素子の逆回復時間は、前記ｐｎ接合の逆回復時間よりも短いことを特徴とする請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1, wherein a reverse recovery time of the regenerative element is shorter than a reverse recovery time of the pn junction. 前記第３の半導体層と前記第２の半導体層とを貫通して前記第１の半導体層に到達するトレンチを備えることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。

4. The semiconductor device according to claim 1, further comprising a trench that penetrates through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer. 5. .

JP2011100276A 2011-04-28 2011-04-28 Semiconductor device Pending JP2012234848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011100276A JP2012234848A (en) 2011-04-28 2011-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011100276A JP2012234848A (en) 2011-04-28 2011-04-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2012234848A true JP2012234848A (en) 2012-11-29

Family

ID=47434922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011100276A Pending JP2012234848A (en) 2011-04-28 2011-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2012234848A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014167978A (en) * 2013-02-28 2014-09-11 Toshiba Corp Semiconductor device
WO2014162969A1 (en) * 2013-04-03 2014-10-09 三菱電機株式会社 Semiconductor device
WO2014196164A1 (en) * 2013-06-05 2014-12-11 株式会社デンソー Silicon carbide semiconductor device and method for manufacturing same
CN104934473A (en) * 2014-03-17 2015-09-23 株式会社东芝 Semiconductor device
WO2016002083A1 (en) * 2014-07-04 2016-01-07 株式会社日立製作所 Semiconductor device, power module and electric power converter
JP2016167537A (en) * 2015-03-10 2016-09-15 富士電機株式会社 Vertical mosfet
JP2016225560A (en) * 2015-06-03 2016-12-28 トヨタ自動車株式会社 Semiconductor device
JP6215510B1 (en) * 2016-11-11 2017-10-18 新電元工業株式会社 MOSFET and power conversion circuit
WO2018087896A1 (en) * 2016-11-11 2018-05-17 新電元工業株式会社 Mosfet and power conversion circuit
JP6362154B1 (en) * 2017-05-26 2018-07-25 新電元工業株式会社 MOSFET and power conversion circuit
JP2019175984A (en) * 2018-03-28 2019-10-10 豊田合成株式会社 Semiconductor device
JP2020013836A (en) * 2018-07-13 2020-01-23 富士電機株式会社 Semiconductor device and semiconductor circuit device
TWI692924B (en) * 2017-11-17 2020-05-01 日商新電元工業股份有限公司 Power conversion circuit
WO2021235020A1 (en) * 2020-05-20 2021-11-25 日立Astemo株式会社 Power semiconductor element
WO2023127253A1 (en) * 2021-12-27 2023-07-06 富士電機株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024690A (en) * 2004-07-07 2006-01-26 Toshiba Corp Semiconductor device for electric power
JP2009295641A (en) * 2008-06-02 2009-12-17 Sanken Electric Co Ltd Field-effect semiconductor device, and method for manufacturing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024690A (en) * 2004-07-07 2006-01-26 Toshiba Corp Semiconductor device for electric power
JP2009295641A (en) * 2008-06-02 2009-12-17 Sanken Electric Co Ltd Field-effect semiconductor device, and method for manufacturing

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014167978A (en) * 2013-02-28 2014-09-11 Toshiba Corp Semiconductor device
WO2014162969A1 (en) * 2013-04-03 2014-10-09 三菱電機株式会社 Semiconductor device
US9577086B2 (en) 2013-04-03 2017-02-21 Mitsubishi Electric Corporation Semiconductor device
WO2014196164A1 (en) * 2013-06-05 2014-12-11 株式会社デンソー Silicon carbide semiconductor device and method for manufacturing same
JP2014236189A (en) * 2013-06-05 2014-12-15 株式会社デンソー Silicon carbide semiconductor device and manufacturing method therefor
US9608104B2 (en) 2013-06-05 2017-03-28 Denso Corporation Silicon carbide semiconductor device and method for manufacturing same
CN104934473A (en) * 2014-03-17 2015-09-23 株式会社东芝 Semiconductor device
WO2016002083A1 (en) * 2014-07-04 2016-01-07 株式会社日立製作所 Semiconductor device, power module and electric power converter
JP2016167537A (en) * 2015-03-10 2016-09-15 富士電機株式会社 Vertical mosfet
JP2016225560A (en) * 2015-06-03 2016-12-28 トヨタ自動車株式会社 Semiconductor device
WO2018087896A1 (en) * 2016-11-11 2018-05-17 新電元工業株式会社 Mosfet and power conversion circuit
US10290734B2 (en) 2016-11-11 2019-05-14 Shindengen Electric Manufacturing Co., Ltd. MOSFET and power conversion circuit
JP6215510B1 (en) * 2016-11-11 2017-10-18 新電元工業株式会社 MOSFET and power conversion circuit
WO2018087943A1 (en) * 2016-11-11 2018-05-17 新電元工業株式会社 Mosfet and power conversion circuit
US10468480B1 (en) 2016-11-11 2019-11-05 Shindengen Electric Manufacturing Co., Ltd. MOSFET and power conversion circuit
JP6362153B1 (en) * 2016-11-11 2018-07-25 新電元工業株式会社 MOSFET and power conversion circuit
JP6362152B1 (en) * 2016-11-11 2018-07-25 新電元工業株式会社 MOSFET and power conversion circuit
WO2018087899A1 (en) * 2016-11-11 2018-05-17 新電元工業株式会社 Mosfet and power conversion circuit
TWI647854B (en) * 2016-11-11 2019-01-11 日商新電元工業股份有限公司 Metal Oxide Half Field Effect Transistor (MOSFET) and power conversion circuit
WO2018216222A1 (en) * 2017-05-26 2018-11-29 新電元工業株式会社 Mosfet and power conversion circuit
JP6362154B1 (en) * 2017-05-26 2018-07-25 新電元工業株式会社 MOSFET and power conversion circuit
TWI692924B (en) * 2017-11-17 2020-05-01 日商新電元工業股份有限公司 Power conversion circuit
JP2019175984A (en) * 2018-03-28 2019-10-10 豊田合成株式会社 Semiconductor device
JP2020013836A (en) * 2018-07-13 2020-01-23 富士電機株式会社 Semiconductor device and semiconductor circuit device
JP7172216B2 (en) 2018-07-13 2022-11-16 富士電機株式会社 Semiconductor devices and semiconductor circuit devices
WO2021235020A1 (en) * 2020-05-20 2021-11-25 日立Astemo株式会社 Power semiconductor element
WO2023127253A1 (en) * 2021-12-27 2023-07-06 富士電機株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
JP2012234848A (en) Semiconductor device
JP5319084B2 (en) Semiconductor device
US9799729B2 (en) Method of manufacturing a semiconductor device with field electrode structures, gate structures and auxiliary diode structures
US9324645B2 (en) Method and system for co-packaging vertical gallium nitride power devices
JPWO2020031971A1 (en) SiC semiconductor device
US9324809B2 (en) Method and system for interleaved boost converter with co-packaged gallium nitride power devices
JP2018182242A (en) Semiconductor device and method of manufacturing the same
US8937317B2 (en) Method and system for co-packaging gallium nitride electronics
WO2020213603A1 (en) Sic semiconductor device
US10818789B2 (en) Semiconductor device and semiconductor circuit device
CN112786680B (en) Cell structure of silicon carbide MOSFET device and power semiconductor device
US20140061672A1 (en) Semiconductor device
JP4719472B2 (en) Silicon carbide static induction transistor
JP2014187086A (en) Semiconductor device
WO2020032204A1 (en) SiC SEMICONDUCTOR DEVICE
TWI645540B (en) Semiconductor device
JP2013016627A (en) Nitride semiconductor device
JP6550995B2 (en) Semiconductor device
CN113054016B (en) Cell structure of silicon carbide MOSFET device and power semiconductor device
JP7274974B2 (en) semiconductor equipment
JP7167533B2 (en) Semiconductor devices and semiconductor circuit devices
JP6047429B2 (en) Semiconductor device and power conversion device using the same
JP2011023527A (en) Semiconductor device
CN113053992B (en) Cell structure of silicon carbide MOSFET device and power semiconductor device
JP7168544B2 (en) SiC semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20141112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20141205

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20150428