WO2021235020A1 - Power semiconductor element - Google Patents

Power semiconductor element Download PDF

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Publication number
WO2021235020A1
WO2021235020A1 PCT/JP2021/004254 JP2021004254W WO2021235020A1 WO 2021235020 A1 WO2021235020 A1 WO 2021235020A1 JP 2021004254 W JP2021004254 W JP 2021004254W WO 2021235020 A1 WO2021235020 A1 WO 2021235020A1
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Prior art keywords
power semiconductor
wiring
layer
gate
passivation layer
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PCT/JP2021/004254
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French (fr)
Japanese (ja)
Inventor
拓真 白頭
直樹 櫻井
隆文 大島
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日立Astemo株式会社
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Publication of WO2021235020A1 publication Critical patent/WO2021235020A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a power semiconductor device.
  • IGBT Insulation-to-PWM
  • IGBT passivation structure and materials in order to improve the efficiency of HEV / EV motor drive. Is made.
  • Patent Document 1 discloses a configuration in which the base electrode 106 is insulated from the emitter electrode 113 by an insulating film 111 which is an interlayer insulating film, and is exposed at a portion where the emitter electrode 113 is not formed.
  • the power semiconductor element in the present invention includes a semiconductor layer, a first wiring region and a second wiring region provided on one surface side of the semiconductor layer, respectively, and the first wiring region and the second wiring region.
  • a metal electrode layer to be formed is provided on the semiconductor substrate.
  • the solder wettability of the power semiconductor element is improved, it is possible to realize both the improvement of the solder quality and the improvement of the yield of the power semiconductor module.
  • FIG. 1 is a diagram showing a mounting portion of a power semiconductor element and a lead frame.
  • the power semiconductor element will be described with an IGBT as a representative example.
  • the IGBT and the diode mounting portion include a solder 1, an IGBT 2 which is a power semiconductor element, a diode 3, an IGBT front surface side lead frame 4 (hereinafter, front surface lead frame 4), an IGBT back surface side lead frame 5 (hereinafter, back surface lead frame 5), and the like. It is composed of.
  • the IGBT and the diode mounting portion are provided inside the power semiconductor module of the power converter.
  • solder 1 which is a metal bonding material is soldered to the IGBT 2 and the diode 3.
  • the IGBT 2 used in the present invention may be another device such as a SiC- MOSFET as long as it has a gate wiring.
  • the present invention is formed so as to cover the lead frames 4 and 5 on the solder 1, and the IGBT chip can be mounted on a power semiconductor module for double-sided cooling. That is, the upper and lower surfaces of the IGBT chip are soldered to the lead frame. The lead frames on the upper and lower surfaces are connected to the cooler and can dissipate heat on both sides of the semiconductor substrate.
  • FIG. 2 is a cross-sectional view showing a solder-mounted portion of a power semiconductor element represented by the prior art.
  • the IGBT 2A is composed of a first emitter wiring 6, a second emitter wiring 7, a metal electrode layer 8A (hereinafter referred to as an electrode layer 8A), a passivation layer 9A, a gate wiring portion 10, and a silicon layer 16.
  • the emitter side of the IGBT 2A which is a conventional technique, is shown on the upper part of the paper.
  • the solder 1 is shown only on the upper part of the paper surface in FIG. 2, the solder 1 is also applied from the lower side of the electrode layer 8A on the lower part of the paper surface. That is, the lead frames 4 and 5, which are conductor plates, are arranged so as to face the electrode layer 8A of the IGBT 2 to form a power semiconductor module.
  • the first emitter wiring 6 and the second emitter wiring 7 are a first wiring region and a second wiring region provided as emitters on one surface side of the IGBT 2A which is a semiconductor layer.
  • a collector electrode is formed on the other surface side of the IGBT 2A.
  • the silicon layer 16 is trench gate processed and ions are injected.
  • a plurality of gate trenches 15 are provided on one surface side of the silicon layer 16.
  • the gate trench 15 has a trench gate electrode provided therein via an insulating layer.
  • the silicon layer 16 is partitioned into a plurality of transistor cell portions by the plurality of gate trenches 15. Since p, p +, and n + described in the transistor cell portion of FIG. 2 are the same for other transistor cell portions, the description thereof will be omitted. Further, since the structure of the silicon layer 16 is the same in FIGS. 3 and 5 described later, the description thereof will be omitted.
  • the first emitter wiring 6, the second emitter wiring 7, and the gate wiring portion 10 are formed by etching the wiring of the Al material installed on the silicon layer 16 which is a semiconductor layer.
  • the surface of the first emitter wiring 6 and the second emitter wiring 7 is sputtered with a composite containing the metals Ti, Ni, and Ag, and the electrode layer 8A is formed so as to cover the surface thereof.
  • the electrode layer 8A is on the emitter side of the IGBT 2A, and the electrode layer 8A is also formed on the collector side on the opposite side.
  • the IGBT 2A In the IGBT 2A, a large number of minute cells are laid out on the chip in the emitter wirings 6 and 7.
  • the IGBT cell in the central portion has a delay in switching as compared with the end portion of the chip of the IGBT 2. Therefore, in order for each IGBT cell to respond without delay when the IGBT 2 is turned on / off, a low-resistance Al material wiring is passed through the center so as to penetrate vertically in the IGBT emitter region, and this is used as the gate wiring portion 10. . Details will be described later in FIG. As a result, the entire cell of the IGBT can be turned on / off without delay.
  • the gate wiring portion 10 is a gate finger wiring formed between the first wiring region and the second wiring region described above, in which polyimide is placed on the wiring of the Al material.
  • the gate wiring unit (gate finger wiring) 10 electrically connects an electrode pad, which will be described later, with a plurality of trench gate electrodes.
  • the trench gate 15 has a structure in which polyvinyl is embedded in silicon.
  • an Al electrode By forming an Al electrode on the layer above the plurality of trench gates 15 and etching them, the emitter electrode portion and the gate electrode portion are separated, and the first emitter wiring 6, the second emitter wiring 7 and the gate wiring are separated. It forms a part 10.
  • the passivation layer 9A is an insulating film made of polyimide and is provided so as to cover the gate wiring portion 10.
  • the gate wiring portion 10 in the central portion of the IGBT 2A is covered with the passivation layer 9A, and the solder 1 is placed on the passivation layer 9A.
  • the solder 1 may be peeled off around the passivation layer 9A.
  • the polyimide constituting the passivation layer 9A and the solder 1 have very poor bondability and are difficult to stick to each other.
  • peeling 12 occurs between the passivation layer 9A covering the gate wiring portion 10 and the solder 1. That is, the polyimide of the passivation layer 9A does not get wet with the solder 1, and the solder wettability of the IGBT 2A is deteriorated.
  • the peeled portion spreads between the emitter electrode layer 8A and the solder 1 starting from the peeling 12 generated in the IGBT 2A, which has an adverse effect. That is, the insufficient solder wettability caused by the peeling 12 in a chain reaction causes the deterioration of the quality of the solder 1 and the deterioration of the yield of the power semiconductor module.
  • FIG. 3 is a cross-sectional view showing a solder mounting portion of a power semiconductor element according to the first embodiment of the present invention.
  • the structure of the silicon layer 16 is the same as that in FIG.
  • the electrode layer 8 formed on the surfaces of the emitter wirings 6 and 7 in the prior art of FIG. 2 is further formed on the surface of the passivation layer 9 as shown in FIG.
  • the material of the passivation layer 9 is not polyimide but silicon nitride (SiN). Then, the front surface lead frame 4 and the back surface lead frame 5 are adhered to each other from both sides of the substrate of the IGBT 2 by the solder 1.
  • SiN silicon nitride
  • another material may be used as long as it can be insulated.
  • the gate wiring portion 10 is insulated by the passivation layer 9, and the electrode layer 8 containing the metals Ti, Ni, and Ag in a composite manner is formed on the passivation layer 9 made of SiN material by sputtering.
  • the solder 1 is metal-bonded to the electrode layer 8, so that the solder 1 is uniformly wetted, and good bonding between the semiconductor element 2 and the lead frames 4 and 5 can be obtained. Further, since the metal material 8 that is seamlessly wetted with the solder 1 is formed on the first emitter wiring 6, the second emitter wiring 7, and the passivation layer 9, the conductivity connecting the separated emitter wirings 6 and 7 is connected. Not only is it a sex material, but the solder wettability of the IGBT 2 is improved. By improving the solder wettability of the IGBT 2, the mountability of the solder 1 is improved, the solder quality is also improved, and the yield of the power semiconductor module can be improved.
  • FIG. 4 is a plan view of the solder mounting portion of the power semiconductor element of FIG.
  • the front side of the paper surface is the emitter side of the IGBT 2, which corresponds to the back side of the collector chip of the IGBT 2.
  • the emitter side of the IGBT 2 is composed of a cathode 17, a mirror emitter 18, a gate 19, an anode 20, a Kelvin emitter 21, and the above-mentioned emitter electrode layers 6 and 7.
  • the emitter electrode layers 6 and 7 are configured by laying out a plurality of chips of the IGBT 2 and are provided on one surface of the silicon layer 16 to form a pad on one surface.
  • a temperature sense diode is sandwiched between the anode 20 and the cathode 17.
  • the gate wiring unit 10 penetrates the inside of the pad of the IGBT up and down so that each IGBT cell can respond without delay when the IGBT 2 is turned on / off.
  • the portion corresponding to the gate wiring portion 10 of the IGBT 2 is sprayed with metal spatter. Therefore, the pad is not divided by the polyimide of the passivation layer 9, which is a conventional technique, and the pad has electrodes on the entire surface. This improves the solder wettability.
  • the guard ring wiring 14 made of Al material, which is configured around the pad of the IGBT 2, is covered with polyimide for insulation.
  • the metal electrode layers 8 and 8A may contain a material such as Au as long as they have solder wettability. Further, in joining the lead frames 4 and 5 to the IGBTs 2 and 2A, the joining material may be an Ag sinter material or a Cu sinter material instead of the solder 1.
  • the pad portion in which the IGBT cells are spread may be divided into two by the gate wiring portion 10, or may be divided into three through two gate wiring portions 10. Further, three or more gate wiring portions 10 may be provided.
  • the power semiconductor element 2 includes a semiconductor layer 16, a first wiring region 6 and a second wiring region 7 provided on one surface side of the semiconductor layer 16, respectively, and the first wiring region 6.
  • the gate finger wiring 10 formed between the second wiring region 7 and the passage layer 9 provided so as to cover the gate finger wiring 10, the first wiring region 6, the passage layer 9, and the above.
  • a metal electrode layer 8 formed so as to cover the surface of the second wiring region 7 is provided on the semiconductor substrate. Since this is done, the solder wettability of the power semiconductor element is improved, so that it is possible to achieve both the improvement of the solder quality and the improvement of the yield of the power semiconductor module.
  • a plurality of transistor cell portions partitioned by the gate trench 15 and a gate electrode pad provided on one surface of the semiconductor layer 16 are provided, and the gate finger wiring 10 includes a gate electrode pad and a plurality of trench gate electrodes. Is electrically connected. Since this is done, the configuration of the power semiconductor element can be realized regardless of the arrangement of the insulating material.
  • the passivation layer 9 of the power semiconductor element 2 is made of silicon nitride. Since this is done, the solder mountability of the solder 1 is improved, and the reliability of the power semiconductor module is improved.
  • a drain electrode or a collector electrode is formed on the other surface side of the power semiconductor element 2. Since this is done, the reliability of the power semiconductor module is improved without being limited to the characteristics of the electrode on the side opposite to the emitter electrode.
  • the power semiconductor module includes a power semiconductor element 2, a conductor plate 4 arranged so as to face the metal electrode layer 8 of the power semiconductor element 2, and a metal electrode layer 8 and a conductor plate 4 of the power semiconductor element 2.
  • the metal joining material 1 to be joined is provided. Since this is done, the solder mountability is improved and the reliability of the power semiconductor module is improved.
  • FIG. 5 is a block diagram of a solder mounting portion of the power semiconductor device 2B according to the second embodiment of the present invention.
  • the basic configuration is the same as that of the first embodiment described with reference to FIG.
  • the passivation layer when a thermal stress such as a power cycle is applied, the passivation layer is in direct contact with the solder 1 due to the difference in linear expansion coefficient between the solder 1 and the passivation layer 9. There is a concern that damage such as cracks will occur in 9. This is because the passivation layer 9 made of the SiN material is formed relatively hard.
  • a second passivation layer 13 formed of polyimide which is a material different from that of the first passivation layer 9B, is formed between the metal emitter layer 8B and the first passivation layer 9B to be bonded to the solder 1. put in. This protects the first passivation layer 9B from thermal stress, mitigates damage, and improves the reliability of the power semiconductor module. This is due to the fact that the polyimide 13 is a resin material and is relatively soft, and the thermal stress and stress generated in the temperature cycle and the power cycle can be alleviated on the substrate of the IGBT 2.
  • a second passivation layer 13 different from the passivation layer 9 is formed between the passivation layer 9 of the power semiconductor element 2 and the metal electrode layer 8. Since this is done, thermal stress and stress can be relaxed on the substrate of the IGBT 2.
  • the second passivation layer 13 of the power semiconductor element 2 is made of polyimide. Since this is done, the first passivation layer 9 is protected from thermal stress, damage is mitigated, and the reliability of the power semiconductor module is improved.
  • the present invention can also be applied to the case where another power semiconductor element is used.
  • the same structure as described in each embodiment can be realized by replacing the emitter wirings 6 and 7 in FIGS. 3 and 5 with the source wiring of the MOSFET.
  • the present invention is applied to a power semiconductor device having a plurality of wiring regions provided on one surface side of the semiconductor layer and having a gate finger wiring and a passivation layer provided between the wiring regions. can do.

Abstract

To achieve both improved solder quality and improved yield of power semiconductor modules. This power semiconductor element is equipped with: on a semiconductor substrate, a semiconductor layer; a first wiring region and a second wiring region provided on one surface side of the semiconductor layer, respectively; a gate finger wiring formed between the first wiring region and the second wiring region; a passivation layer provided so as to cover the gate finger wiring; and a metal electrode layer formed so as to cover the surfaces of the first wiring region, the passivation layer, and the second wiring region.

Description

パワー半導体素子Power semiconductor device
　本発明は、パワー半導体素子に関する。 The present invention relates to a power semiconductor device.
　電力変換装置に搭載されるパワー半導体素子（ＩＧＢＴやＳｉＣ－ＭＯＳＦＥＴなど）は、ＨＥＶ／ＥＶモータ駆動の効率化のため、例えば、ＩＧＢＴパッシベーション構造や材料などに改良が加えられており、日々技術発展が成されている。 Power semiconductor devices (IGBT, SiC-PWM, etc.) mounted on power converters are being improved on a daily basis, for example, in the IGBT passivation structure and materials in order to improve the efficiency of HEV / EV motor drive. Is made.
　本願発明の背景技術として、下記の特許文献１が知られている。特許文献１では、ベース電極１０６は層間絶縁膜である絶縁膜１１１によりエミッタ電極１１３と絶縁され、エミッタ電極１１３が形成されていない箇所で露出されている構成が開示されている。 The following Patent Document 1 is known as a background technique of the present invention. Patent Document 1 discloses a configuration in which the base electrode 106 is insulated from the emitter electrode 113 by an insulating film 111 which is an interlayer insulating film, and is exposed at a portion where the emitter electrode 113 is not formed.
特開２０１３－０４１９８５号公報Japanese Unexamined Patent Publication No. 2013-041985
　特許文献１の構成では、絶縁膜１１１がポリイミドである場合に、半田付けするときに絶縁膜１１１は半田に濡れずに品質低下するため、半田の品質向上が課題であった。 In the configuration of Patent Document 1, when the insulating film 111 is polyimide, the quality of the insulating film 111 deteriorates without getting wet with the solder when soldering, so that the quality of the solder has been improved.
　本発明におけるパワー半導体素子は、半導体層と、前記半導体層の一方の表面側にそれぞれ設けられる第１の配線領域および第２の配線領域と、前記第１の配線領域と前記第２の配線領域との間に形成されるゲートフィンガー配線と、前記ゲートフィンガー配線を覆うように設けられるパッシベーション層と、前記第１の配線領域と前記パッシベーション層と前記第２の配線領域との表面を覆って形成される金属電極層と、を半導体基板上に備えている。 The power semiconductor element in the present invention includes a semiconductor layer, a first wiring region and a second wiring region provided on one surface side of the semiconductor layer, respectively, and the first wiring region and the second wiring region. A gate finger wiring formed between the two, a passion layer provided so as to cover the gate finger wiring, and a surface of the first wiring region, the passion layer, and the second wiring region. A metal electrode layer to be formed is provided on the semiconductor substrate.
　本発明によれば、パワー半導体素子の半田濡れ性が向上するため、半田の品質向上とパワー半導体モジュールの歩留り向上との両立を実現させることができる。 According to the present invention, since the solder wettability of the power semiconductor element is improved, it is possible to realize both the improvement of the solder quality and the improvement of the yield of the power semiconductor module.
パワー半導体素子とリードフレームの実装部分を表す図である。It is a figure which shows the mounting part of a power semiconductor element and a lead frame. 従来技術に代表されるパワー半導体素子の半田実装部分の構成図である。It is a block diagram of the solder mounting part of the power semiconductor element represented by the prior art. 本発明の第１の実施形態に係るパワー半導体素子の半田実装部分の図である。It is a figure of the solder mounting part of the power semiconductor element which concerns on 1st Embodiment of this invention. 図３の平面図である。It is a plan view of FIG. 本発明の第２の実施形態に係るパワー半導体素子の半田実装部分の図である。It is a figure of the solder mounting part of the power semiconductor element which concerns on 2nd Embodiment of this invention.
　以下、図面を用いて本発明の第１の実施形態に係るパワー半導体素子の構成について図１～図４を用いて説明する。 Hereinafter, the configuration of the power semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4.
（第１の実施形態およびパワー半導体素子の構成）
　図１は、パワー半導体素子とリードフレームの実装部分を表す図である。なお、以下本発明では、パワー半導体素子はＩＧＢＴを代表例にして説明する。 (First Embodiment and Configuration of Power Semiconductor Device)
FIG. 1 is a diagram showing a mounting portion of a power semiconductor element and a lead frame. Hereinafter, in the present invention, the power semiconductor element will be described with an IGBT as a representative example.
　ＩＧＢＴおよびダイオード実装部は、半田１、パワー半導体素子であるＩＧＢＴ２、ダイオード３、ＩＧＢＴ表面側リードフレーム４（以下、表面リードフレーム４）、ＩＧＢＴ裏面側リードフレーム５（以下、裏面リードフレーム５）、により構成されている。ＩＧＢＴおよびダイオード実装部は、電力変換装置のパワー半導体モジュールの内部に備えられている。 The IGBT and the diode mounting portion include a solder 1, an IGBT 2 which is a power semiconductor element, a diode 3, an IGBT front surface side lead frame 4 (hereinafter, front surface lead frame 4), an IGBT back surface side lead frame 5 (hereinafter, back surface lead frame 5), and the like. It is composed of. The IGBT and the diode mounting portion are provided inside the power semiconductor module of the power converter.
　表面リードフレーム４と裏面リードフレーム５は、ＩＧＢＴ２とダイオード３に金属接合材である半田１が半田付けされる。なお、本発明で用いるＩＧＢＴ２は、ゲート配線を持つ構成ならばＳｉＣ－ＭＯＳＦＥＴなど他のデバイスでもよい。 In the front surface lead frame 4 and the back surface lead frame 5, solder 1 which is a metal bonding material is soldered to the IGBT 2 and the diode 3. The IGBT 2 used in the present invention may be another device such as a SiC- MOSFET as long as it has a gate wiring.
　また、本発明は半田１の上にリードフレーム４，５を覆うように形成され、ＩＧＢＴチップを両面冷却のパワー半導体モジュールに実装することができる。つまり、ＩＧＢＴチップの上下面は、リードフレームに半田付けされる。上下面のリードフレームは冷却器につながっており半導体基板の両面を放熱することができる。 Further, the present invention is formed so as to cover the lead frames 4 and 5 on the solder 1, and the IGBT chip can be mounted on a power semiconductor module for double-sided cooling. That is, the upper and lower surfaces of the IGBT chip are soldered to the lead frame. The lead frames on the upper and lower surfaces are connected to the cooler and can dissipate heat on both sides of the semiconductor substrate.
　図２は、従来技術に代表されるパワー半導体素子の半田実装部分を示す断面図である。 FIG. 2 is a cross-sectional view showing a solder-mounted portion of a power semiconductor element represented by the prior art.
　ＩＧＢＴ２Ａは、第１のエミッタ配線６、第２のエミッタ配線７、金属電極層８Ａ（以下、電極層８Ａ）、パッシベーション層９Ａ、ゲート配線部１０、シリコン層１６で構成されている。 The IGBT 2A is composed of a first emitter wiring 6, a second emitter wiring 7, a metal electrode layer 8A (hereinafter referred to as an electrode layer 8A), a passivation layer 9A, a gate wiring portion 10, and a silicon layer 16.
　従来技術であるＩＧＢＴ２Ａのエミッタ側は、紙面上部に表されている。なお図２では、半田１は紙面上部のみに図示されているが、紙面下部の電極層８Ａの下側からも半田１が塗布されている。つまり、ＩＧＢＴ２の電極層８Ａと対向して導体板であるリードフレーム４および５が配置されてパワー半導体モジュールが構成されている。 The emitter side of the IGBT 2A, which is a conventional technique, is shown on the upper part of the paper. Although the solder 1 is shown only on the upper part of the paper surface in FIG. 2, the solder 1 is also applied from the lower side of the electrode layer 8A on the lower part of the paper surface. That is, the lead frames 4 and 5, which are conductor plates, are arranged so as to face the electrode layer 8A of the IGBT 2 to form a power semiconductor module.
　第１のエミッタ配線６および第２のエミッタ配線７は、半導体層であるＩＧＢＴ２Ａの一方の表面側にエミッタとして設けられる第１の配線領域および第２の配線領域である。
ＩＧＢＴ２Ａの他方の表面側にはコレクタ電極が形成される。 The first emitter wiring 6 and the second emitter wiring 7 are a first wiring region and a second wiring region provided as emitters on one surface side of the IGBT 2A which is a semiconductor layer.
A collector electrode is formed on the other surface side of the IGBT 2A.
　シリコン層１６はトレンチゲート加工され、イオンが注入されている。ゲートトレンチ１５は、シリコン層１６の一方の表面側に複数設けられる。ゲートトレンチ１５は、その中に絶縁層を介して設けられるトレンチゲート電極を有している。この複数のゲートトレンチ１５により、シリコン層１６が複数のトランジスタセル部に区画されている。なお、図２のトランジスタセル部に記載のｐ，ｐ+，ｎ+は他のトランジスタセル部も同様なので、記載は省略する。また、後述の図３や図５についてはシリコン層１６の構成は同様のため、記載は省略する。 The silicon layer 16 is trench gate processed and ions are injected. A plurality of gate trenches 15 are provided on one surface side of the silicon layer 16. The gate trench 15 has a trench gate electrode provided therein via an insulating layer. The silicon layer 16 is partitioned into a plurality of transistor cell portions by the plurality of gate trenches 15. Since p, p +, and n + described in the transistor cell portion of FIG. 2 are the same for other transistor cell portions, the description thereof will be omitted. Further, since the structure of the silicon layer 16 is the same in FIGS. 3 and 5 described later, the description thereof will be omitted.
　第１のエミッタ配線６と第２のエミッタ配線７とゲート配線部１０とは、半導体層であるシリコン層１６の上に設置されたＡｌ素材の配線を、エッチング加工することで形成される。第１のエミッタ配線６と第２のエミッタ配線７は、その表面を金属であるＴｉとＮｉとＡｇとを複合含有したスパッタが散布され、覆われるように電極層８Ａが形成されている。なお、この電極層８ＡはＩＧＢＴ２Ａのエミッタ側であり、それとは反対側のコレクタ側にも電極層８Ａが形成されている。 The first emitter wiring 6, the second emitter wiring 7, and the gate wiring portion 10 are formed by etching the wiring of the Al material installed on the silicon layer 16 which is a semiconductor layer. The surface of the first emitter wiring 6 and the second emitter wiring 7 is sputtered with a composite containing the metals Ti, Ni, and Ag, and the electrode layer 8A is formed so as to cover the surface thereof. The electrode layer 8A is on the emitter side of the IGBT 2A, and the electrode layer 8A is also formed on the collector side on the opposite side.
　ＩＧＢＴ２Ａは、エミッタ配線６および７内にチップ上で多数の微小なセルがレイアウトされている。ＩＧＢＴチップの面積すべてを高抵抗のポリシリコンのトレンチゲート１５のみでゲートを充放電して駆動すると、ＩＧＢＴ２のチップの端部と比べて中央部のＩＧＢＴセルはスイッチング時に遅れが生じる。そのため、ＩＧＢＴ２のオン／オフ時に各ＩＧＢＴセルが遅れなく応答できるように、ＩＧＢＴエミッタ領域内を上下に貫通するように低抵抗のＡｌ素材の配線を中央に通し、これをゲート配線部１０とする。詳細は図４で後述する。これにより、ＩＧＢＴのセル全体を遅れなくオン／オフすることができる。 In the IGBT 2A, a large number of minute cells are laid out on the chip in the emitter wirings 6 and 7. When the entire area of the IGBT chip is charged and discharged by charging and discharging the gate only with the high-resistance polysilicon trench gate 15, the IGBT cell in the central portion has a delay in switching as compared with the end portion of the chip of the IGBT 2. Therefore, in order for each IGBT cell to respond without delay when the IGBT 2 is turned on / off, a low-resistance Al material wiring is passed through the center so as to penetrate vertically in the IGBT emitter region, and this is used as the gate wiring portion 10. .. Details will be described later in FIG. As a result, the entire cell of the IGBT can be turned on / off without delay.
　ゲート配線部１０はＡｌ素材の配線の上にポリイミドがのっており、前述した第１の配線領域と第２の配線領域との間に形成されるゲートフィンガー配線である。ゲート配線部（ゲートフィンガー配線）１０は、後述の電極パッドと複数のトレンチゲート電極とを電気的に接続している。 The gate wiring portion 10 is a gate finger wiring formed between the first wiring region and the second wiring region described above, in which polyimide is placed on the wiring of the Al material. The gate wiring unit (gate finger wiring) 10 electrically connects an electrode pad, which will be described later, with a plurality of trench gate electrodes.
　トレンチゲート１５は、シリコンにポリシリコンを埋めている構成になっている。複数のトレンチゲート１５の上の層にＡｌ電極を形成し、エッチング加工することで、エミッタ電極部分とゲート電極部分に分離して、第１のエミッタ配線６と第２のエミッタ配線７とゲート配線部１０とを形成している。パッシベーション層９Ａは、ポリイミドが素材となっている絶縁膜であり、ゲート配線部１０を覆うように設けられる。 The trench gate 15 has a structure in which polyvinyl is embedded in silicon. By forming an Al electrode on the layer above the plurality of trench gates 15 and etching them, the emitter electrode portion and the gate electrode portion are separated, and the first emitter wiring 6, the second emitter wiring 7 and the gate wiring are separated. It forms a part 10. The passivation layer 9A is an insulating film made of polyimide and is provided so as to cover the gate wiring portion 10.
　従来技術では、ＩＧＢＴ２Ａの中央部にあるゲート配線部１０が、パッシベーション層９Ａにより覆われて、その上に半田１がある構成になっている。しかし、この構成では、リードフレーム４および５とＩＧＢＴ２Ａとの半田付け後に、パッシベーション層９Ａの周囲で半田１が剥離してしまうおそれがある。これは、パッシベーション層９Ａを構成しているポリイミドと半田１とは接合性が非常に悪く、互いにくっつきにくいことに起因している。これにより、ゲート配線部１０を覆っているパッシベーション層９Ａと半田１との間に剥離１２が起こる。つまり、パッシベーション層９Ａのポリイミドが半田１に濡れず、ＩＧＢＴ２Ａの半田濡れ性を悪化させている。 In the prior art, the gate wiring portion 10 in the central portion of the IGBT 2A is covered with the passivation layer 9A, and the solder 1 is placed on the passivation layer 9A. However, in this configuration, after soldering the lead frames 4 and 5 and the IGBT 2A, the solder 1 may be peeled off around the passivation layer 9A. This is because the polyimide constituting the passivation layer 9A and the solder 1 have very poor bondability and are difficult to stick to each other. As a result, peeling 12 occurs between the passivation layer 9A covering the gate wiring portion 10 and the solder 1. That is, the polyimide of the passivation layer 9A does not get wet with the solder 1, and the solder wettability of the IGBT 2A is deteriorated.
　これにより、パワー半導体モジュールを実装し稼働した際に、ＩＧＢＴ２Ａ内に発生した剥離１２を起点にして、剥離部分がエミッタ電極層８Ａと半田１との間にまで広がり悪影響がでてしまう。つまり、剥離１２によって連鎖的に起こる不十分な半田濡れ性が、半田１の品質悪化とパワー半導体モジュールの歩留りの悪化との要因となっている。 As a result, when the power semiconductor module is mounted and operated, the peeled portion spreads between the emitter electrode layer 8A and the solder 1 starting from the peeling 12 generated in the IGBT 2A, which has an adverse effect. That is, the insufficient solder wettability caused by the peeling 12 in a chain reaction causes the deterioration of the quality of the solder 1 and the deterioration of the yield of the power semiconductor module.
　図３は、本発明の第１の実施形態に係るパワー半導体素子の半田実装部を示す断面図である。なお、シリコン層１６の構成は図２と同じである。 FIG. 3 is a cross-sectional view showing a solder mounting portion of a power semiconductor element according to the first embodiment of the present invention. The structure of the silicon layer 16 is the same as that in FIG.
　本実施形態の半導体素子２では、図２の従来技術においてエミッタ配線６および７の表面に形成されている電極層８を、図３のようにさらにパッシベーション層９の表面にも形成している。またパッシベーション層９の素材はポリイミドではなく窒化シリコン（ＳｉＮ）で構成されている。そのうえで、ＩＧＢＴ２の基板の両面から表面リードフレーム４と裏面リードフレーム５とを、半田１により接着させている。なお、パッシベーション層９の素材に使われるＳｉＮは、絶縁できるのであれば他の素材を用いてもよい。 In the semiconductor element 2 of the present embodiment, the electrode layer 8 formed on the surfaces of the emitter wirings 6 and 7 in the prior art of FIG. 2 is further formed on the surface of the passivation layer 9 as shown in FIG. The material of the passivation layer 9 is not polyimide but silicon nitride (SiN). Then, the front surface lead frame 4 and the back surface lead frame 5 are adhered to each other from both sides of the substrate of the IGBT 2 by the solder 1. As the SiN used as the material of the passivation layer 9, another material may be used as long as it can be insulated.
　つまり、ＩＧＢＴ２はゲート配線部１０をパッシベーション層９で絶縁し、ＳｉＮ素材のパッシベーション層９上に金属であるＴｉとＮｉとＡｇとを複合含有した電極層８をスパッタによって形成している。そうすることで、従来技術で示したように、ゲート配線部１０の上の半田１とパッシベーション層９であるポリイミドとの剥離部分で生まれる半田未濡れによる不良が無くなり、半田濡れ性を向上させている。 That is, in the IGBT 2, the gate wiring portion 10 is insulated by the passivation layer 9, and the electrode layer 8 containing the metals Ti, Ni, and Ag in a composite manner is formed on the passivation layer 9 made of SiN material by sputtering. By doing so, as shown in the prior art, defects due to unwetting of the solder generated at the peeled portion between the solder 1 on the gate wiring portion 10 and the polyimide which is the passivation layer 9 are eliminated, and the solder wettability is improved. There is.
　これにより、半田１が電極層８と金属結合することで、半田１が均一に濡れるようになり、半導体素子２とリードフレーム４および５との良好な接合が得られる。さらに、第１のエミッタ配線６と第２のエミッタ配線７とパッシベーション層９に、切れ目なく半田１に濡れる金属材料８が形成されているため、分離されたエミッタ配線６，７の間をつなぐ導電性材料となるだけでなく、ＩＧＢＴ２の半田濡れ性が向上する。ＩＧＢＴ２の半田濡れ性の向上により、半田１の実装性を向上させており、半田品質も向上しパワー半導体モジュールの歩留り向上を実現できる。 As a result, the solder 1 is metal-bonded to the electrode layer 8, so that the solder 1 is uniformly wetted, and good bonding between the semiconductor element 2 and the lead frames 4 and 5 can be obtained. Further, since the metal material 8 that is seamlessly wetted with the solder 1 is formed on the first emitter wiring 6, the second emitter wiring 7, and the passivation layer 9, the conductivity connecting the separated emitter wirings 6 and 7 is connected. Not only is it a sex material, but the solder wettability of the IGBT 2 is improved. By improving the solder wettability of the IGBT 2, the mountability of the solder 1 is improved, the solder quality is also improved, and the yield of the power semiconductor module can be improved.
　図４は、図３のパワー半導体素子の半田実装部の平面図である。 FIG. 4 is a plan view of the solder mounting portion of the power semiconductor element of FIG.
　紙面手前側の面がＩＧＢＴ２のエミッタ側であり、ＩＧＢＴ２のコレクタチップの裏側にあたる。ＩＧＢＴ２のエミッタ側は、カソード１７、ミラーエミッタ１８、ゲート１９、アノード２０、ケルビンエミッタ２１と、前述したエミッタ電極層６および７によって構成されている。 The front side of the paper surface is the emitter side of the IGBT 2, which corresponds to the back side of the collector chip of the IGBT 2. The emitter side of the IGBT 2 is composed of a cathode 17, a mirror emitter 18, a gate 19, an anode 20, a Kelvin emitter 21, and the above-mentioned emitter electrode layers 6 and 7.
　エミッタ電極層６および７は、ＩＧＢＴ２の複数のチップが敷き詰められて構成されており、シリコン層１６の一方の表面に設けられ、一面のパッド状になっている。アノード２０とカソード１７は、間に温度センスダイオードを挟んでいる。前述したように、ゲート配線部１０は、ＩＧＢＴ２のオン／オフ時に各ＩＧＢＴセルが遅れなく応答できるように、ＩＧＢＴのパッド内を上下に貫通している。 The emitter electrode layers 6 and 7 are configured by laying out a plurality of chips of the IGBT 2 and are provided on one surface of the silicon layer 16 to form a pad on one surface. A temperature sense diode is sandwiched between the anode 20 and the cathode 17. As described above, the gate wiring unit 10 penetrates the inside of the pad of the IGBT up and down so that each IGBT cell can respond without delay when the IGBT 2 is turned on / off.
　従来技術とは異なり、ＩＧＢＴ２のゲート配線部１０にあたる部分は、金属スパッタ散布が施されている。そのため、従来技術であったパッシベーション層９のポリイミドによりパッドが分断されるということはなく、一面全体に電極があるパッドになる。これにより、半田濡れ性向上させている。なお、ＩＧＢＴ２のパッド周辺に構成されているＡｌ素材のガードリング配線１４は、絶縁のためにポリイミドによって覆われている。 Unlike the prior art, the portion corresponding to the gate wiring portion 10 of the IGBT 2 is sprayed with metal spatter. Therefore, the pad is not divided by the polyimide of the passivation layer 9, which is a conventional technique, and the pad has electrodes on the entire surface. This improves the solder wettability. The guard ring wiring 14 made of Al material, which is configured around the pad of the IGBT 2, is covered with polyimide for insulation.
　以上、第１の実施形態を説明したが、金属電極層８および８Ａは、半田濡れ性があればＡｕなどの材料を含有させてもよい。また、リードフレーム４，５とＩＧＢＴ２および２Ａとの接合において、接合材料は半田１ではなくＡｇシンター材やＣｕシンター材でもよい。 Although the first embodiment has been described above, the metal electrode layers 8 and 8A may contain a material such as Au as long as they have solder wettability. Further, in joining the lead frames 4 and 5 to the IGBTs 2 and 2A, the joining material may be an Ag sinter material or a Cu sinter material instead of the solder 1.
　また、図４のように本実施形態ではゲート配線は１本だけであるが、２本引く構成としてもよい。つまり、ＩＧＢＴセルが敷き詰められているパッド部分がゲート配線部１０によって２分割される構成でもよいし、ゲート配線部１０を２本通して３分割される構成でもよい。さらに、３本以上のゲート配線部１０を設けるようにしてもよい。 Further, as shown in FIG. 4, in this embodiment, there is only one gate wiring, but a configuration in which two wires are drawn may be used. That is, the pad portion in which the IGBT cells are spread may be divided into two by the gate wiring portion 10, or may be divided into three through two gate wiring portions 10. Further, three or more gate wiring portions 10 may be provided.
　以上説明した本発明の第１の実施形態によれば、以下の作用効果を奏する。 According to the first embodiment of the present invention described above, the following effects are exhibited.
（１）パワー半導体素子２は、半導体層１６と、前記半導体層１６の一方の表面側にそれぞれ設けられる第１の配線領域６および第２の配線領域７と、前記第１の配線領域６と前記第２の配線領域７との間に形成されるゲートフィンガー配線１０と、前記ゲートフィンガー配線１０を覆うように設けられるパッシベーション層９と、前記第１の配線領域６と前記パッシベーション層９と前記第２の配線領域７との表面を覆って形成される金属電極層８と、を半導体基板上に備えている。このようにしたので、パワー半導体素子の半田濡れ性が向上するため、半田の品質向上とパワー半導体モジュールの歩留り向上との両立を実現させることができる。 (1) The power semiconductor element 2 includes a semiconductor layer 16, a first wiring region 6 and a second wiring region 7 provided on one surface side of the semiconductor layer 16, respectively, and the first wiring region 6. The gate finger wiring 10 formed between the second wiring region 7 and the passage layer 9 provided so as to cover the gate finger wiring 10, the first wiring region 6, the passage layer 9, and the above. A metal electrode layer 8 formed so as to cover the surface of the second wiring region 7 is provided on the semiconductor substrate. Since this is done, the solder wettability of the power semiconductor element is improved, so that it is possible to achieve both the improvement of the solder quality and the improvement of the yield of the power semiconductor module.
（２）パワー半導体素子２の半導体層１６の一方の表面側に設けられた複数のゲートトレンチ１５と、複数のゲートトレンチ１５中に絶縁層を介してそれぞれ設けられる複数のトレンチゲート電極と、複数のゲートトレンチ１５によって区画される複数のトランジスタセル部と、半導体層１６の一方の表面に設けられたゲート電極パッドと、を備え、ゲートフィンガー配線１０は、ゲート電極パッドと複数のトレンチゲート電極とを電気的に接続する。このようにしたので、絶縁素材の配置に関係なく、パワー半導体素子の構成を実現できる。 (2) A plurality of gate trenches 15 provided on one surface side of the semiconductor layer 16 of the power semiconductor element 2, a plurality of trench gate electrodes each provided in the plurality of gate trenches 15 via an insulating layer, and a plurality of gate trenches. A plurality of transistor cell portions partitioned by the gate trench 15 and a gate electrode pad provided on one surface of the semiconductor layer 16 are provided, and the gate finger wiring 10 includes a gate electrode pad and a plurality of trench gate electrodes. Is electrically connected. Since this is done, the configuration of the power semiconductor element can be realized regardless of the arrangement of the insulating material.
（３）パワー半導体素子２のパッシベーション層９は、窒化シリコンで構成されている。
このようにしたので、半田１の半田実装性が高まり、パワー半導体モジュールの信頼性が向上する。 (3) The passivation layer 9 of the power semiconductor element 2 is made of silicon nitride.
Since this is done, the solder mountability of the solder 1 is improved, and the reliability of the power semiconductor module is improved.
（４）パワー半導体素子２の他方の表面側にはドレイン電極またはコレクタ電極が形成される。このようにしたので、エミッタ電極とは反対側の電極の特性に限定されずに、パワー半導体モジュールの信頼性が向上する。 (4) A drain electrode or a collector electrode is formed on the other surface side of the power semiconductor element 2. Since this is done, the reliability of the power semiconductor module is improved without being limited to the characteristics of the electrode on the side opposite to the emitter electrode.
（５）パワー半導体モジュールは、パワー半導体素子２と、パワー半導体素子２の金属電極層８と対向して配置される導体板４と、パワー半導体素子２の金属電極層８と導体板４とを接合する金属接合材１とを備える。このようにしたので、半田実装性が高まり、パワー半導体モジュールの信頼性が向上する。 (5) The power semiconductor module includes a power semiconductor element 2, a conductor plate 4 arranged so as to face the metal electrode layer 8 of the power semiconductor element 2, and a metal electrode layer 8 and a conductor plate 4 of the power semiconductor element 2. The metal joining material 1 to be joined is provided. Since this is done, the solder mountability is improved and the reliability of the power semiconductor module is improved.
（第２の実施形態）
　図５は、本発明の第２の実施形態に係るパワー半導体素子２Ｂの半田実装部の構成図である。基本構成は図３で説明した第１の実施形態と同様である。 (Second embodiment)
FIG. 5 is a block diagram of a solder mounting portion of the power semiconductor device 2B according to the second embodiment of the present invention. The basic configuration is the same as that of the first embodiment described with reference to FIG.
　第１の実施形態において、パワーサイクルなどの熱ストレスが印加されたときに、半田１とパッシベーション層９との線膨張係数差により、半田１と直に接触している場合は熱ストレスでパッシベーション層９にクラックなどのダメージが発生することが懸念される。これは、ＳｉＮ素材でできたパッシベーション層９が比較的固く形成されていることに起因する。 In the first embodiment, when a thermal stress such as a power cycle is applied, the passivation layer is in direct contact with the solder 1 due to the difference in linear expansion coefficient between the solder 1 and the passivation layer 9. There is a concern that damage such as cracks will occur in 9. This is because the passivation layer 9 made of the SiN material is formed relatively hard.
　それを防ぐために、半田１と接合する金属エミッタ層８Ｂと第１のパッシベーション層９Ｂとの間に、第１のパッシベーション層９Ｂとは異なる素材であるポリイミドで形成された第２のパッシベーション層１３を入れる。これにより、熱ストレスから第１のパッシベーション層９Ｂを保護してダメージを緩和させ、パワー半導体モジュールの信頼性を向上させる。これは、ポリイミド１３が樹脂材で比較的やわらかいことに起因しており、温度サイクルやパワーサイクルで発生する熱ストレス・応力をＩＧＢＴ２の基板上で緩和できる。 In order to prevent this, a second passivation layer 13 formed of polyimide, which is a material different from that of the first passivation layer 9B, is formed between the metal emitter layer 8B and the first passivation layer 9B to be bonded to the solder 1. put in. This protects the first passivation layer 9B from thermal stress, mitigates damage, and improves the reliability of the power semiconductor module. This is due to the fact that the polyimide 13 is a resin material and is relatively soft, and the thermal stress and stress generated in the temperature cycle and the power cycle can be alleviated on the substrate of the IGBT 2.
　以上説明した本発明の第２の実施形態によれば、以下の作用効果を奏する。 According to the second embodiment of the present invention described above, the following effects are exhibited.
（６）パワー半導体素子２のパッシベーション層９と金属電極層８との間には、パッシベーション層９とは異なる第２のパッシベーション層１３が形成される。このようにしたので、熱ストレスと応力をＩＧＢＴ２の基板上で緩和できる。 (6) A second passivation layer 13 different from the passivation layer 9 is formed between the passivation layer 9 of the power semiconductor element 2 and the metal electrode layer 8. Since this is done, thermal stress and stress can be relaxed on the substrate of the IGBT 2.
（７）パワー半導体素子２の第２のパッシベーション層１３は、ポリイミドで構成されている。このようにしたので、熱ストレスから第１のパッシベーション層９を保護してダメージを緩和させ、パワー半導体モジュールの信頼性を向上させる。 (7) The second passivation layer 13 of the power semiconductor element 2 is made of polyimide. Since this is done, the first passivation layer 9 is protected from thermal stress, damage is mitigated, and the reliability of the power semiconductor module is improved.
　なお、上記の各実施形態では、パワー半導体素子としてＩＧＢＴを用いた場合の例を説明したが、他のパワー半導体素子を用いた場合にも本発明を適用可能である。例えばＩＧＢＴに替えてＭＯＳＦＥＴを用いた場合、図３，５のエミッタ配線６，７をＭＯＳＦＥＴのソース配線に置き換えることで、各実施形態で説明したのと同様の構造を実現できる。
これ以外にも、半導体層の一方の表面側にそれぞれ設けられる複数の配線領域を有し、各配線領域の間にゲートフィンガー配線とパッシベーション層が設けられるパワー半導体素子であれば、本発明を適用することができる。 In each of the above embodiments, an example in which the IGBT is used as the power semiconductor element has been described, but the present invention can also be applied to the case where another power semiconductor element is used. For example, when a MOSFET is used instead of the IGBT, the same structure as described in each embodiment can be realized by replacing the emitter wirings 6 and 7 in FIGS. 3 and 5 with the source wiring of the MOSFET.
In addition to this, the present invention is applied to a power semiconductor device having a plurality of wiring regions provided on one surface side of the semiconductor layer and having a gate finger wiring and a passivation layer provided between the wiring regions. can do.
　なお、以上の説明はあくまでも一例であり、発明を解釈する際、上記実施の形態の記載事項と特許請求の範囲の記載事項の対応関係に何ら限定も拘束もされない。また、発明の技術的思想を逸脱しない範囲で、削除・他の構成に置換・他の構成の追加をすることが可能であり、その態様も本発明の範囲内に含まれる。 The above explanation is merely an example, and when interpreting the invention, there is no limitation or limitation on the correspondence between the matters described in the above-described embodiment and the matters described in the claims. Further, it is possible to delete, replace with another configuration, or add another configuration without departing from the technical idea of the invention, and the embodiment thereof is also included in the scope of the present invention.
　１…半田、２…ＩＧＢＴ、３…ダイオード、４…ＩＧＢＴ表面側リードフレーム、５…ＩＧＢＴ裏面側リードフレーム、６…第１のエミッタ配線、７…第２のエミッタ配線、８，８Ａ…金属電極層、９，９Ａ…第１のパッシベーション層、１０…ゲート配線部、１２…剥離部分、１３…第２のパッシベーション層、１４…ガードリング配線、１５…ゲートトレンチ、１６…シリコン層、１７…カソード、１８…ミラーエミッタ、１９…ゲート、２０…アノード、２１…ケルビンエミッタ 1 ... solder, 2 ... IGBT, 3 ... diode, 4 ... IGBT front side lead frame, 5 ... IGBT back side lead frame, 6 ... first emitter wiring, 7 ... second emitter wiring, 8, 8A ... metal electrode Layers, 9, 9A ... 1st passage layer, 10 ... Gate wiring part, 12 ... Peeling part, 13 ... Second passage layer, 14 ... Guard ring wiring, 15 ... Gate trench, 16 ... Silicon layer, 17 ... Cathode , 18 ... Mirror Emitter, 19 ... Gate, 20 ... Anode, 21 ... Kelvin Emitter

Claims (7)

  1. 　半導体層と、
    　前記半導体層の一方の表面側にそれぞれ設けられる第１の配線領域および第２の配線領域と、
    　前記第１の配線領域と前記第２の配線領域との間に形成されるゲートフィンガー配線と、
    　前記ゲートフィンガー配線を覆うように設けられるパッシベーション層と、
    　前記第１の配線領域と前記パッシベーション層と前記第２の配線領域との表面を覆って形成される金属電極層と、
    　を半導体基板上に備えた
    　パワー半導体素子。     With the semiconductor layer,
    A first wiring region and a second wiring region provided on one surface side of the semiconductor layer, respectively,
    A gate finger wiring formed between the first wiring area and the second wiring area, and
    A passivation layer provided so as to cover the gate finger wiring,
    A metal electrode layer formed so as to cover the surfaces of the first wiring region, the passivation layer, and the second wiring region.
    A power semiconductor device equipped on a semiconductor substrate.
  2. 　請求項１に記載のパワー半導体素子であって、
    　前記半導体層の前記一方の表面側に設けられた複数のゲートトレンチと、
    　前記複数のゲートトレンチ中に絶縁層を介してそれぞれ設けられる複数のトレンチゲート電極と、
    　前記複数のゲートトレンチによって区画される複数のトランジスタセル部と、
    　前記半導体層の前記一方の表面に設けられたゲート電極パッドと、を備え、
    　前記ゲートフィンガー配線は、前記ゲート電極パッドと前記複数のトレンチゲート電極とを電気的に接続するパワー半導体素子。     The power semiconductor device according to claim 1.
    A plurality of gate trenches provided on the one surface side of the semiconductor layer, and
    A plurality of trench gate electrodes provided in the plurality of gate trenches via an insulating layer, and a plurality of trench gate electrodes.
    A plurality of transistor cell portions partitioned by the plurality of gate trenches,
    A gate electrode pad provided on one surface of the semiconductor layer is provided.
    The gate finger wiring is a power semiconductor element that electrically connects the gate electrode pad and the plurality of trench gate electrodes.
  3. 　請求項１に記載のパワー半導体素子であって、
    　前記パッシベーション層は、窒化シリコンで構成されているパワー半導体素子。     The power semiconductor device according to claim 1.
    The passivation layer is a power semiconductor device made of silicon nitride.
  4. 　請求項１に記載のパワー半導体素子であって、
    　前記パワー半導体素子の他方の表面側には電極が形成されるパワー半導体素子。     The power semiconductor device according to claim 1.
    A power semiconductor device in which an electrode is formed on the other surface side of the power semiconductor device.
  5. 　請求項１に記載のパワー半導体素子であって、
    　前記パッシベーション層と前記金属電極層との間には、前記パッシベーション層とは異なる第２のパッシベーション層が形成されるパワー半導体素子。     The power semiconductor device according to claim 1.
    A power semiconductor device in which a second passivation layer different from the passivation layer is formed between the passivation layer and the metal electrode layer.
  6. 　請求項５に記載のパワー半導体素子であって、
    　前記第２のパッシベーション層は、ポリイミドで構成されているパワー半導体素子。     The power semiconductor device according to claim 5.
    The second passivation layer is a power semiconductor element made of polyimide.
  7. 　請求項１乃至６のいずれかに記載のパワー半導体素子と、
    　前記パワー半導体素子の前記金属電極層と対向して配置される導体板と、
    　前記パワー半導体素子の前記金属電極層と前記導体板とを接合する金属接合材と、を備えたパワー半導体モジュール。     The power semiconductor device according to any one of claims 1 to 6.
    A conductor plate arranged so as to face the metal electrode layer of the power semiconductor element,
    A power semiconductor module comprising a metal bonding material for bonding the metal electrode layer of the power semiconductor element and the conductor plate.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023120353A1 (en) * 2021-12-21 2023-06-29 ローム株式会社 Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011049393A (en) * 2009-08-27 2011-03-10 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2011066377A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same
JP2012234848A (en) * 2011-04-28 2012-11-29 Sanken Electric Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011066377A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same
JP2011049393A (en) * 2009-08-27 2011-03-10 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2012234848A (en) * 2011-04-28 2012-11-29 Sanken Electric Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023120353A1 (en) * 2021-12-21 2023-06-29 ローム株式会社 Semiconductor device

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