JP2023101032A - Power semiconductor device - Google Patents

Abstract

To attain increased quality of a solder and an increased yield of a power semiconductor module at the same time.SOLUTION: A power semiconductor device includes: a semiconductor layer; a first wire region and a second wire region formed in one surface side of the semiconductor layer; a gate finger wire formed between the first wire region and the second wire region; a passivation layer covering the gate finger wire; and a metal electrode layer covering the first wire region and the surface between the passivation layer and the second wire region, on a semiconductor substrate.SELECTED DRAWING: Figure 3

Description

The present invention relates to power semiconductor devices.

Power semiconductor devices (IGBTs, SiC-MOSFETs, etc.) installed in power converters are being improved, for example, in IGBT passivation structures and materials, in order to improve the efficiency of HEV/EV motor driving, and the technology is developing day by day. is made.

The following patent document 1 is known as a background art of the present invention. Patent Document 1 discloses a configuration in which the base electrode 106 is insulated from the emitter electrode 113 by an insulating film 111, which is an interlayer insulating film, and is exposed where the emitter electrode 113 is not formed.

JP 2013-041985 A

In the configuration of Patent Document 1, when the insulating film 111 is made of polyimide, the quality of the insulating film 111 is degraded because the insulating film 111 does not get wet with the solder during soldering.

A power semiconductor device according to the present invention includes a semiconductor layer, a first wiring region and a second wiring region respectively provided on one surface side of the semiconductor layer, and the first wiring region and the second wiring region. a passivation layer provided to cover the gate finger wiring; and a surface of the first wiring region, the passivation layer, and the second wiring region. and a metal electrode layer formed on the semiconductor substrate.

According to the present invention, since the solder wettability of the power semiconductor element is improved, it is possible to achieve both the improvement of solder quality and the improvement of the yield of the power semiconductor module.

It is a figure showing the mounting part of a power semiconductor element and a lead frame. FIG. 2 is a configuration diagram of a solder-mounted portion of a power semiconductor device represented by conventional technology; It is a figure of the solder mounting part of the power semiconductor element which concerns on the 1st Embodiment of this invention. FIG. 4 is a plan view of FIG. 3; It is a figure of the solder mounting part of the power semiconductor element which concerns on the 2nd Embodiment of this invention.

1 to 4, the configuration of a power semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.

(Configuration of First Embodiment and Power Semiconductor Device)
FIG. 1 is a diagram showing a mounting portion of a power semiconductor element and a lead frame. In addition, in the present invention, an IGBT will be described as a typical example of the power semiconductor element.

The IGBT and diode mounting portion includes solder 1, IGBT 2 which is a power semiconductor element, diode 3, IGBT front side lead frame 4 (hereinafter referred to as front side lead frame 4), IGBT back side lead frame 5 (hereinafter referred to as back side lead frame 5), It is composed of The IGBT and diode mounting portion are provided inside the power semiconductor module of the power converter.

The front lead frame 4 and the back lead frame 5 are soldered to the IGBT 2 and the diode 3 with solder 1, which is a metal bonding material. The IGBT 2 used in the present invention may be another device such as SiC-MOSFET as long as it has a gate wiring.

Further, the present invention is formed so as to cover the lead frames 4 and 5 on the solder 1, and the IGBT chip can be mounted on the double-sided cooling power semiconductor module. That is, the upper and lower surfaces of the IGBT chip are soldered to the lead frame. The lead frames on the upper and lower surfaces are connected to a cooler and can dissipate heat from both sides of the semiconductor substrate.

FIG. 2 is a cross-sectional view showing a solder-mounted portion of a power semiconductor device represented by the prior art.

The IGBT 2A is composed of a first emitter wiring 6, a second emitter wiring 7, a metal electrode layer 8A (hereinafter referred to as electrode layer 8A), a passivation layer 9A, a gate wiring portion 10, and a silicon layer 16. FIG.

The emitter side of the prior art IGBT 2A is shown at the top of the page. In FIG. 2, the solder 1 is shown only in the upper part of the paper, but the solder 1 is also applied from below the electrode layer 8A in the lower part of the paper. That is, the lead frames 4 and 5, which are conductor plates, are arranged to face the electrode layer 8A of the IGBT 2 to form a power semiconductor module.

A first emitter wiring 6 and a second emitter wiring 7 are a first wiring region and a second wiring region provided as emitters on one surface side of the IGBT 2A, which is a semiconductor layer. A collector electrode is formed on the other surface side of the IGBT 2A.

The silicon layer 16 is trench gated and implanted with ions. A plurality of gate trenches 15 are provided on one surface side of the silicon layer 16 . The gate trench 15 has a trench gate electrode provided therein via an insulating layer. The plurality of gate trenches 15 partition the silicon layer 16 into a plurality of transistor cell portions. Note that p, p+, and n+ described in the transistor cell portion of FIG. 2 are the same in other transistor cell portions, so their description is omitted. 3 and 5, which will be described later, are omitted because the structure of the silicon layer 16 is the same.

The first emitter wiring 6, the second emitter wiring 7, and the gate wiring section 10 are formed by etching wiring of Al material placed on the silicon layer 16, which is a semiconductor layer. An electrode layer 8A is formed so as to cover the surfaces of the first emitter wiring 6 and the second emitter wiring 7 with a sputter containing a composite of metals Ti, Ni, and Ag. This electrode layer 8A is on the emitter side of the IGBT 2A, and another electrode layer 8A is also formed on the opposite collector side.

The IGBT 2A has a large number of minute cells laid out on the chip within the emitter wirings 6 and 7 . If the entire area of the IGBT chip is driven by charging/discharging the gate only with the high-resistance polysilicon trench gate 15, the IGBT cells in the central portion of the IGBT2 chip will have a delay in switching compared to the edge portions of the chip. Therefore, in order for each IGBT cell to respond without delay when the IGBT 2 is turned on and off, a low-resistance Al material wire is passed through the center of the IGBT emitter region so as to penetrate vertically, and this is used as the gate wiring portion 10 . . Details will be described later with reference to FIG. This allows the entire IGBT cell to be turned on/off without delay.

The gate wiring portion 10 is a gate finger wiring formed between the first wiring region and the second wiring region, wherein polyimide is placed on a wiring made of Al material. A gate wiring portion (gate finger wiring) 10 electrically connects an electrode pad (to be described later) and a plurality of trench gate electrodes.

The trench gate 15 has a structure in which polysilicon is embedded in silicon. An Al electrode is formed in a layer above the plurality of trench gates 15 and etched to separate the emitter electrode portion and the gate electrode portion into a first emitter wiring 6, a second emitter wiring 7 and a gate wiring. forming part 10 . The passivation layer 9A is an insulating film made of polyimide, and is provided so as to cover the gate wiring section 10 .

In the prior art, the gate wiring portion 10 in the central portion of the IGBT 2A is covered with the passivation layer 9A, and the solder 1 is placed thereon. However, in this configuration, after soldering the lead frames 4 and 5 and the IGBT 2A, the solder 1 may peel off around the passivation layer 9A. This is because the polyimide constituting the passivation layer 9A and the solder 1 have very poor bonding properties and are difficult to stick to each other. As a result, peeling 12 occurs between the passivation layer 9A covering the gate wiring portion 10 and the solder 1. Next, as shown in FIG. In other words, the polyimide of the passivation layer 9A does not get wet with the solder 1, degrading the solder wettability of the IGBT 2A.

As a result, when the power semiconductor module is mounted and operated, the delamination 12 generated in the IGBT 2A will spread to between the emitter electrode layer 8A and the solder 1, causing an adverse effect. In other words, the insufficient solder wettability that occurs in a chain reaction due to the peeling 12 is a factor in the deterioration of the quality of the solder 1 and the deterioration of the yield of the power semiconductor module.

FIG. 3 is a cross-sectional view showing a solder-mounted portion of the power semiconductor device according to the first embodiment of the present invention. The structure of the silicon layer 16 is the same as that shown in FIG.

In the semiconductor element 2 of this embodiment, the electrode layer 8 formed on the surfaces of the emitter wirings 6 and 7 in the prior art of FIG. 2 is further formed on the surface of the passivation layer 9 as shown in FIG. The material of the passivation layer 9 is silicon nitride (SiN) instead of polyimide. In addition, the front lead frame 4 and the back lead frame 5 are bonded by solder 1 from both sides of the substrate of the IGBT 2 . It should be noted that SiN used as the material for the passivation layer 9 may be replaced by other materials as long as they can be insulated.

That is, the IGBT 2 insulates the gate wiring portion 10 with the passivation layer 9, and forms the electrode layer 8 containing Ti, Ni, and Ag in combination on the passivation layer 9 made of SiN material by sputtering. By doing so, as shown in the prior art, defects due to non-wetting of the solder generated at the peeled portion between the solder 1 on the gate wiring portion 10 and the polyimide that is the passivation layer 9 are eliminated, and the solder wettability is improved. there is

As a result, the solder 1 is metallically bonded to the electrode layer 8, so that the solder 1 is evenly wetted, and good bonding between the semiconductor element 2 and the lead frames 4 and 5 is obtained. Furthermore, since the metal material 8 that is seamlessly wetted by the solder 1 is formed on the first emitter wiring 6, the second emitter wiring 7, and the passivation layer 9, the conductive connection between the separated emitter wirings 6 and 7 is formed. In addition to being a flexible material, the solder wettability of the IGBT 2 is improved. By improving the solder wettability of the IGBT 2, the mountability of the solder 1 is improved, the quality of the solder is also improved, and the yield of the power semiconductor module can be improved.

4 is a plan view of a solder-mounted portion of the power semiconductor device of FIG. 3. FIG.

The surface on the front side of the paper is the emitter side of the IGBT 2 and corresponds to the back side of the collector chip of the IGBT 2 . The emitter side of the IGBT 2 is composed of a cathode 17, a mirror emitter 18, a gate 19, an anode 20, a Kelvin emitter 21, and the emitter electrode layers 6 and 7 described above.

The emitter electrode layers 6 and 7 are constructed by laying a plurality of chips of the IGBT 2, are provided on one surface of the silicon layer 16, and form a pad-like surface. Anode 20 and cathode 17 sandwich a temperature sensing diode therebetween. As described above, the gate wiring portion 10 penetrates vertically through the pad of the IGBT so that each IGBT cell can respond without delay when the IGBT 2 is turned on/off.

Unlike the prior art, the portion corresponding to the gate wiring portion 10 of the IGBT 2 is sputtered with metal. Therefore, the pad is not divided by the polyimide of the passivation layer 9, which is conventional technology, and the pad has electrodes over the entire surface. This improves solder wettability. The guard ring wiring 14 made of Al material and formed around the pad of the IGBT 2 is covered with polyimide for insulation.

Although the first embodiment has been described above, the metal electrode layers 8 and 8A may contain a material such as Au as long as it has solder wettability. Also, in the bonding between the lead frames 4 and 5 and the IGBTs 2 and 2A, the bonding material may be an Ag sinter material or a Cu sinter material instead of the solder 1. FIG.

Also, as shown in FIG. 4, only one gate line is provided in this embodiment, but two lines may be drawn. In other words, the pad portion where the IGBT cells are spread may be divided into two parts by the gate wiring part 10, or may be divided into three parts by passing two gate wiring parts 10 through them. Furthermore, three or more gate wiring portions 10 may be provided.

According to the first embodiment of the present invention described above, the following effects are obtained.

(1) The power semiconductor element 2 includes a semiconductor layer 16, a first wiring region 6 and a second wiring region 7 provided on one surface side of the semiconductor layer 16, and the first wiring region 6. A gate finger wiring 10 formed between the second wiring region 7, a passivation layer 9 provided so as to cover the gate finger wiring 10, the first wiring region 6, the passivation layer 9 and the and a metal electrode layer 8 formed to cover the surface of the second wiring region 7 on the semiconductor substrate. Since the power semiconductor element has improved solder wettability, it is possible to achieve both improved solder quality and increased yield of the power semiconductor module.

(2) a plurality of gate trenches 15 provided on one surface side of the semiconductor layer 16 of the power semiconductor element 2; a plurality of trench gate electrodes provided in the plurality of gate trenches 15 via an insulating layer; and a gate electrode pad provided on one surface of the semiconductor layer 16. The gate finger wiring 10 includes the gate electrode pad and the plurality of trench gate electrodes. electrically connected. With this configuration, the configuration of the power semiconductor element can be realized regardless of the arrangement of the insulating material.

(3) The passivation layer 9 of the power semiconductor element 2 is made of silicon nitride. As a result, the solder mountability of the solder 1 is improved, and the reliability of the power semiconductor module is improved.

(4) A drain electrode or a collector electrode is formed on the other surface side of the power semiconductor element 2 . Since this is done, the reliability of the power semiconductor module is improved without being limited by the characteristics of the electrode on the side opposite to the emitter electrode.

(5) The power semiconductor module includes the power semiconductor element 2, the conductor plate 4 arranged to face the metal electrode layer 8 of the power semiconductor element 2, and the metal electrode layer 8 of the power semiconductor element 2 and the conductor plate 4. and a metal bonding material 1 to be bonded. As a result, solder mountability is improved, and the reliability of the power semiconductor module is improved.

(Second embodiment)
FIG. 5 is a configuration diagram of a solder-mounted portion of a power semiconductor device 2B according to the second embodiment of the present invention. The basic configuration is the same as that of the first embodiment described with reference to FIG.

In the first embodiment, when thermal stress such as a power cycle is applied, due to the difference in the coefficient of linear expansion between the solder 1 and the passivation layer 9, if the solder 1 is in direct contact with the passivation layer due to the thermal stress. There is concern that damage such as cracks may occur in 9 . This is because the passivation layer 9 made of SiN material is relatively hard.

In order to prevent this, a second passivation layer 13 made of polyimide, which is a material different from that of the first passivation layer 9B, is provided between the metal emitter layer 8B and the first passivation layer 9B, which are bonded to the solder 1. put in. This protects the first passivation layer 9B from thermal stress, mitigates damage, and improves the reliability of the power semiconductor module. This is because the polyimide 13 is a resin material and is relatively soft, so that thermal stress and stress generated by temperature cycles and power cycles can be relieved on the substrate of the IGBT 2 .

According to the second embodiment of the present invention described above, the following effects are obtained.

(6) A second passivation layer 13 different from the passivation layer 9 is formed between the passivation layer 9 and the metal electrode layer 8 of the power semiconductor element 2 . By doing so, the thermal stress and stress can be relieved on the substrate of the IGBT2.

(7) The second passivation layer 13 of the power semiconductor element 2 is made of polyimide. By doing so, the first passivation layer 9 is protected from thermal stress, the damage is alleviated, and the reliability of the power semiconductor module is improved.

In each of the above-described embodiments, an example in which an IGBT is used as a power semiconductor element has been described, but the present invention can also be applied when other power semiconductor elements are used. For example, when MOSFETs are used instead of IGBTs, the same structure as described in each embodiment can be realized by replacing the emitter wirings 6 and 7 in FIGS. 3 and 5 with the source wirings of the MOSFETs. In addition to this, the present invention can be applied to any power semiconductor device having a plurality of wiring regions provided on one surface side of a semiconductor layer and having gate finger wirings and a passivation layer provided between the wiring regions. can do.

The above description is merely an example, and when interpreting the invention, there is no limitation or restriction on the corresponding relationship between the descriptions of the above embodiments and the descriptions of the claims. In addition, it is possible to delete, replace with another configuration, or add another configuration without departing from the technical idea of the invention, and such aspects are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1... Solder 2... IGBT 3... Diode 4... IGBT surface side lead frame,
5... IGBT backside lead frame, 6... first emitter wiring,
7... second emitter wiring, 8, 8A... metal electrode layer,
9, 9A... First passivation layer, 10... Gate wiring portion, 12... Stripped portion,
13... Second passivation layer, 14... Guard ring wiring, 15... Gate trench,
16... Silicon layer, 17... Cathode, 18... Mirror emitter, 19... Gate,
20... Anode, 21... Kelvin emitter

Claims (7)

a semiconductor layer;
a first wiring region and a second wiring region respectively provided on one surface side of the semiconductor layer;
a gate finger wire formed between the first wiring region and the second wiring region;
a passivation layer provided to cover the gate finger wiring;
a metal electrode layer formed to cover surfaces of the first wiring region, the passivation layer, and the second wiring region;
on a semiconductor substrate. The power semiconductor device according to claim 1,
a plurality of gate trenches provided on the one surface side of the semiconductor layer;
a plurality of trench gate electrodes respectively provided in the plurality of gate trenches via an insulating layer;
a plurality of transistor cell portions partitioned by the plurality of gate trenches;
a gate electrode pad provided on the one surface of the semiconductor layer;
The power semiconductor element, wherein the gate finger wiring electrically connects the gate electrode pad and the plurality of trench gate electrodes. The power semiconductor device according to claim 1,
The power semiconductor device, wherein the passivation layer is made of silicon nitride. The power semiconductor device according to claim 1,
A power semiconductor element having an electrode formed on the other surface side of the power semiconductor element. The power semiconductor device according to claim 1,
A power semiconductor device, wherein a second passivation layer different from the passivation layer is formed between the passivation layer and the metal electrode layer. A power semiconductor device according to claim 5,
The power semiconductor device, wherein the second passivation layer is made of polyimide. A power semiconductor device according to any one of claims 1 to 6;
a conductor plate disposed facing the metal electrode layer of the power semiconductor element;
A power semiconductor module comprising a metal bonding material for bonding the metal electrode layer of the power semiconductor element and the conductor plate.

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