JP2009117755A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing breakage of an interlayer insulating film and breakage of an electrode due to bonding while securing bonding strength, and improving electrical characteristics, and to provide a manufacturing method thereof. <P>SOLUTION: A semiconductor element 1 mounted on the semiconductor device is provided with an interlayer insulating film 12 having an extending section 121 which covers a gate electrode 116 and extends in a first direction, a connecting section 122 which connects, at fixed intervals in the first direction, the extending sections 121 adjacent to each other in a second direction, and an opening section 123 which has its opening shape defined by the extending section 121 and the connecting section 122 and exposes the main surface of a base region 112 and the main surface of an emitter region 113. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which external wiring is connected to an electrode of a semiconductor element and a manufacturing method thereof.

  Semiconductor elements such as IGBTs (insulated gate bipolar transistors) and power MOSFETs (metal oxide semiconductor field effect transistors) are incorporated in semiconductor devices. This type of semiconductor element is a switching device that can control a large current at high speed.

  A semiconductor element such as an IGBT includes a collector region, a base region, an emitter region, a gate insulating film, and a gate electrode. The collector region is formed by epitaxial growth on one main surface of the substrate or diffusion on one main surface portion of the substrate. The base region is formed on the other main surface portion of the substrate. The emitter region is formed on the surface portion of the base region. The gate insulating film is formed at least on the surface of the base region, and the gate electrode is formed on the gate insulating film.

  A semiconductor device employs a stripe-structure IGBT having a high breakdown voltage and a small gate capacitance by forming gate electrodes in a stripe shape. In an IGBT employing this structure, the gate electrode extends on the main surface of the substrate in the gate length direction, and a plurality of gate electrodes are arranged at regular intervals in the gate width direction. A part of the surface of the emitter region and the base region is exposed in a stripe shape in the gate length direction so as to sandwich the electrode. An emitter electrode (emitter wiring) is electrically connected to the emitter region and the base region where the surface is exposed. The emitter electrode is formed on an interlayer insulating film sandwiched between the gate electrode, and the interlayer insulating film covers the gate electrode and corresponds to a region where the above-mentioned emitter region and base region are partially exposed (corresponding to Striped openings (contact openings) in the gate length direction. That is, in the cross-section cut in the gate width direction, the planar shape of the convex interlayer insulating film having a gap between adjacent interlayer insulating films due to the above-described opening is a stripe shape similar to the planar shape of the gate electrode. An IGBT adopting such a stripe structure can increase the contact area between the emitter region and the base region and the emitter electrode and increase the current capacity, thereby reducing the occurrence of electric field concentration and increasing the current. In addition, a high breakdown voltage can be realized.

  The emitter electrode of the IGBT is electrically connected to the emitter lead (external terminal) through a bonding wire, and the gate lead is also electrically connected to the gate electrode through the bonding wire. In the collector region, for example, a collector electrode provided on the other main surface of the substrate is electrically connected to a collector lead. Bonding wires are generally bonded by thermocompression bonding using ultrasonic vibration using a wire bonding apparatus. The IGBT is resin-sealed together with the inner part of each lead and assembled as a semiconductor device.

This type of semiconductor device is described in, for example, Patent Document 1 and Patent Document 2 below.
Japanese Patent Laid-Open No. 10-22322 JP 2002-222826 A

  However, in the semiconductor device described above, no consideration has been given to the following points. When a bonding wire is bonded directly to the emitter electrode directly above the IGBT having a stripe structure by the energy of ultrasonic vibration, the interlayer insulating film and the gate electrode of the IGBT (cell) below it are peeled off or broken. Specifically, in the IGBT, since the planar shape of the gate electrode and the interlayer insulating film has a stripe shape elongated in the gate length direction, the mechanical strength of the gate electrode and the interlayer insulating film is weak, and the bonding area with the base In addition, since the shape protrudes from the main surface of the substrate, the interlayer insulating film and the gate electrode are peeled off or broken when the bonding wire is bonded. In particular, the above problem is likely to occur when stress in the gate width direction is generated in the interlayer insulating film.

  In addition, when the trench structure is adopted in the IGBT due to the miniaturization of the IGBT, the planar area (gate width dimension) of the gate electrode is reduced on the main surface of the substrate. With this reduction, the interlayer insulating film on the gate electrode is reduced. The planar area (width dimension from the contact opening to the adjacent contact opening in the gate width direction) is reduced. That is, since the adhesion area between the main surface of the substrate and the interlayer insulating film is further reduced, the interlayer insulating film and the gate electrode are significantly peeled off or broken. Furthermore, if the bonding wire diameter is increased in order to cope with a large current in a semiconductor device, the energy of ultrasonic vibration necessary for bonding increases, so that the interlayer insulation film and the gate electrode are more exfoliated and broken. .

  When such an interlayer insulating film or gate electrode is peeled off or broken, an insulation failure occurs between the emitter electrode (emitter region) and the gate electrode. When the degree is poor, the emitter electrode and the gate electrode are electrically short-circuited.

  In order to suppress peeling and destruction of the interlayer insulating film and the gate electrode, there are a method of weakening the ultrasonic power of the bonding apparatus (during the bonding process) and a method of reducing the pressing load. However, when such a method is adopted, sufficient bonding strength (mechanical bonding strength) cannot be obtained between the emitter electrode and the bonding wire. When the bonding strength is insufficient, the bonding wire peels off from the emitter electrode during resin sealing in the semiconductor manufacturing process or during actual operation of the semiconductor device.

  In addition, in order to suppress peeling and destruction of the interlayer insulating film and gate electrode on the semiconductor element side, a method in which no IGBT (cell) is arranged in the bonding wire bonding region, and the emitter electrode is formed of a thick aluminum film There is a way to do it. However, in the former method, since no cell exists in a part of the substrate, the on-voltage which is the main electrical characteristic of the IGBT is remarkably increased or the size of the semiconductor element is increased. In the latter method, the impact at the time of bonding of the bonding wire can be absorbed by the emitter electrode, or the impact can be prevented from propagating under the emitter electrode. However, in the semiconductor manufacturing process, the manufacturing cost increases as the raw material cost increases and the electrode film formation time increases. Furthermore, an increase in the thickness of the emitter electrode leads to an increase in film stress due to the difference in linear expansion coefficient between the emitter electrode and the portion in contact with the emitter electrode due to the operation of the semiconductor element, and an unnecessary stress is applied to the IGBT. Changes in the physical characteristics.

  The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent the breakdown of an interlayer insulating film and the electrode due to bonding while securing bonding strength. Furthermore, this invention is providing the semiconductor device with the favorable electrical property of a semiconductor element, and its manufacturing method. Furthermore, this invention is providing the semiconductor device which can reduce manufacturing cost, and its manufacturing method.

  In order to solve the above problems, a first feature according to an embodiment of the present invention is that, in a semiconductor device, the first side and the second side that face each other in the first direction intersect the first direction. A plurality of substrates having a third side and a fourth side facing each other in the second direction; a plurality of substrates arranged in the second direction on the substrate; the first main surface being exposed; A first semiconductor region having one conductivity type, a plurality of first semiconductor regions disposed in the second direction in the first semiconductor region, and the second main surface exposed at the first main surface of the first semiconductor region And a second semiconductor region having a second conductivity type opposite to the first conductivity type, and another first semiconductor region adjacent to the second semiconductor region of the first semiconductor region in the second direction. A control electrode disposed between the second semiconductor region and the other second semiconductor region, covering the control electrode and extending in the first direction The first main surface of the first semiconductor region having an opening shape defined by the extending portion, the connecting portion that connects the extending portions adjacent to each other in the second direction in the first direction, and the extending portion and the connecting portion. And an interlayer insulating film having an opening exposing the second main surface of the second semiconductor region, and the first insulating layer disposed on the interlayer insulating film and through the opening of the interlayer insulating film. And an electrode electrically connected to the main surface and the second main surface of the second semiconductor region.

  In the semiconductor device according to the first feature, between the second semiconductor region of the first semiconductor region and another second semiconductor region of the other first semiconductor region adjacent in the second direction, A hole extending through the first semiconductor region from the first main surface of the first semiconductor region to the substrate side and extending in the first direction; an insulating surface disposed on a side surface of the hole and a bottom surface of the hole; The control electrode is preferably embedded in the hole with an insulating film interposed therebetween.

  In the semiconductor device according to the first feature, the semiconductor device is disposed between the second semiconductor region of the first semiconductor region and the other second semiconductor region of the other first semiconductor region adjacent in the second direction. And a third semiconductor region having the second main surface exposed and having the second conductivity type, and an insulating film disposed on the third main surface of the third semiconductor region. The control electrode is preferably disposed on the third main surface of the third semiconductor region with an insulating film interposed.

  In the semiconductor device according to the first feature, the interlayer insulating film is preferably configured in a mesh shape by extending portions, connecting portions, and openings.

  In the semiconductor device according to the first feature, the connecting portion of the interlayer insulating film is preferably disposed in a region immediately below the bonding area of the electrode.

  In the semiconductor device according to the first feature, it is preferable that an external wiring of either a wire or a clip lead is electrically connected to the electrode.

  A second feature of the embodiment of the present invention is that, in the method of manufacturing a semiconductor device, the first side facing in the first direction and the second direction intersecting the first side with the second side. A substrate having a third side and a fourth side facing each other, a plurality of substrates arranged in the second direction on the substrate and arranged with the first main surface exposed, and having the first conductivity type A first semiconductor region having a first semiconductor region, a plurality of first semiconductor regions disposed in the second direction in the first semiconductor region, and the second main surface exposed at the first main surface of the first semiconductor region; A second semiconductor region having a second conductivity type opposite to the conductivity type; another second semiconductor region adjacent to the second semiconductor region of the first semiconductor region in the second direction; Forming a control electrode disposed between the semiconductor region and extending in the first direction covering the control electrode An opening shape is defined by the extending portion, the connecting portion connecting the extending portions adjacent to each other in the second direction at a constant interval, and the extending portion and the connecting portion, and the first main region of the first semiconductor region Forming an interlayer insulating film having an opening exposing the surface and the second main surface of the second semiconductor region, and the first semiconductor disposed on the interlayer insulating film and through the opening of the interlayer insulating film Forming an electrode electrically connected to the first main surface of the region and the second main surface of the second semiconductor region, and forming an external wiring electrically connected to the electrode on the electrode A process.

  In the method of manufacturing a semiconductor device according to the second feature, the step of forming an interlayer insulating film is a step of forming an interlayer insulating film in which a connecting portion is provided in a region immediately below the bonding area, and a step of forming external wiring Is preferably a step of forming an external wiring electrically connected to the electrode in the bonding area.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can prevent the destruction of the interlayer insulation film and the destruction of an electrode accompanying bonding, and its manufacturing method can be provided, ensuring bonding strength. Furthermore, according to the present invention, it is possible to provide a semiconductor device having good electrical characteristics of a semiconductor element and a method for manufacturing the same. Furthermore, according to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can reduce manufacturing costs.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
The first embodiment of the present invention describes an example in which the present invention is applied to a semiconductor element made of an IGBT having a trench structure, a power semiconductor device on which the semiconductor element is mounted, and a manufacturing method thereof.

[Device structure of semiconductor element (IGBT)]
As shown in FIGS. 1 and 4, the semiconductor element 1 mounted on the semiconductor device according to the first embodiment includes a first side 101 and a second side 102 that face each other in the first direction. A substrate 111 having a third side 103 and a fourth side 104 facing each other in a second direction intersecting with the direction of the substrate 104 (see FIGS. 1 and 4 in particular), and a plurality of substrates 111 in the second direction on the substrate 111. A first semiconductor region 112 (see FIG. 1 and FIG. 2 in particular) having a first conductivity type, which is disposed with the first main surface exposed, and in the first semiconductor region 112 The second main surface is exposed in the second direction, the second main surface is exposed at the first main surface of the first semiconductor region 112, and has a second conductivity type opposite to the first conductivity type. The second semiconductor region 113, the second semiconductor region 113 of the first semiconductor region 112, and the second semiconductor region 113 A gate electrode (control electrode) 116 disposed between the other second semiconductor region 113 adjacent to the other first semiconductor region 112 and the first direction covering the gate electrode 116 in the first direction An opening shape is defined by the extending portion 121 extending in the first direction, the connecting portion 122 connecting the extending portions 121 adjacent to each other in the second direction at a constant interval, and the extending portion 121 and the connecting portion 122. An interlayer insulating film 12 (see particularly FIGS. 1 and 3) having an opening 123 exposing the first main surface of the semiconductor region 112 and the second main surface of the second semiconductor region 113; and an interlayer insulating film The electrode 13 is disposed on the electrode 12 and electrically connected to the first main surface of the first semiconductor region 112 and the second main surface of the second semiconductor region 113 through the opening 123 of the interlayer insulating film 12. And.

  The semiconductor element 1 is an IGBT 11, and the IGBT 11 is composed of an IGBT having a trench gate structure in the first embodiment, as shown in FIGS. That is, the IGBT 11 includes a p-type second semiconductor region 110 (hereinafter referred to as a collector region 110) that is a collector region (or a drain region), and an n-type base region and an n-type first semiconductor region. A substrate 111 (hereinafter referred to as base region 111), a p-type first semiconductor region 112 (hereinafter referred to as base region 112) that is a p-type base region, and an n-type second semiconductor that is an emitter region. Semiconductor region 113 (hereinafter referred to as emitter region 113), hole (trench) 114, gate insulating film 115, gate electrode 116, collector electrode (first electrode), emitter electrode (second electrode) 13. Here, the “gate electrode” is used in the sense of an electrode capable of controlling the flow of the main current, and may be a semiconductor region, a diffusion region, an electrode, or the like as long as the electrode can control the flow of the main current. Is included.

  As shown in FIG. 4, the base region (substrate) 111 includes a first side 101 and a second side 102 that face each other in the first direction, and a third side 103 and a fourth side that face each other in the second direction. The side 104 is configured by a planar rectangular shape. The base region 111 is a semiconductor chip that is cut out by a dicing process after the IGBT (cell) 11 is manufactured by a silicon single crystal wafer in the manufacturing process of the semiconductor element 1. Although the planar shape of the base region 111 is not necessarily limited to this planar shape, the base region 111 has the first side 101 and the second side 102 as long sides, and the third side 103 and the fourth side 104. It is comprised by the planar rectangle which makes short side.

  Here, in the first embodiment, the “first direction” is the vertical direction in FIGS. 2, 3, and 4, and is the “Y direction”. Further, the “second direction” is the left-right direction in the figure and is the “X direction”.

  As shown in FIG. 1, an n-type silicon single crystal substrate is used for the base region 111 in the first embodiment. A p-type second semiconductor region 110 formed by diffusing p-type impurities by an epitaxial growth method or a diffusion method is disposed on one main surface (on the lower surface in FIG. 1) of the silicon single crystal substrate. Has been. This p-type second semiconductor region 110 functions as a collector region of the IGBT 11.

  The p-type base region 112 is formed by diffusing p-type impurities on the main surface of the n-type base region 111 by an impurity diffusion method. The emitter region (or source region) 113 is formed by diffusing n-type impurities in the main surface portion of the p-type base region 112.

  As shown in FIG. 1, the hole 114 extends from the main surface of the emitter region 113 in the depth direction (substrate side), passes through the p-type base region 112, and reaches the n-type base region 111. I have. Further, as shown in FIG. 2, the longitudinal direction of the hole 114 extends in the first direction from the first side 101 to the second side 102, and the hole 114 extends from the third side 103 to the fourth side. A plurality of lines are arranged at regular intervals in the second direction toward the side 104. The planar shape of the hole 114 is a stripe shape. The hole 114 is formed by using anisotropic etching such as reactive ion etching (RIE).

  The gate insulating film 115 is disposed along the inner wall and the bottom surface of the hole 114. For the gate insulating film 115, for example, a silicon oxide film formed by using a film forming method such as a thermal oxidation method or a CVD method can be practically used. The gate insulating film 115 may be a silicon nitride film or a composite film in which a silicon oxide film and a silicon nitride film are combined.

  The gate electrode 116 is embedded in the hole 114 with the gate insulating film 115 interposed. In the first embodiment, for the gate electrode 116, for example, a silicon polycrystalline film into which an n-type impurity for ensuring conductivity is introduced can be used practically. The gate electrode 116 is formed by using an etching method or a chemical mechanical polishing (CMP) method after being embedded in the hole 114. As shown in FIG. 2, since the planar shape of the hole 114 is formed in a striped shape elongated in the first direction, the planar shape of the gate electrode 116 is striped in the first direction according to the planar shape of the hole 114. Is formed.

  As shown in FIG. 2, a surface region where a connecting portion 122 of an interlayer insulating film 121 described later is not formed is exposed on the surface of the emitter region 113 formed so as to sandwich the gate electrode 116. Similarly, the surface region in which the later-described interlayer insulating film 12 (the connecting portion 122) is not formed is exposed on the surface of the p-type base region 112. Therefore, each of the emitter region 113 and the p-type base region 112 disposed between the gate electrodes 116 adjacent in the second direction is the same as the extending direction of the gate electrode 116 except in the bonding area described later. A plurality of emitter regions 113 and p-type base regions 112 are arranged in the second direction. The planar shape of each of the emitter region 113 and the p-type base region 112 is formed in a stripe shape except in a bonding area described later.

  As shown in FIGS. 1 to 4, the planar shape of the interlayer insulating film 12 according to the first embodiment is arranged in the second direction at a constant interval in the bonding area of the first electrode 13. In a mesh shape having an extending portion 121 provided between the second electrode 13 extending in the direction of the gate electrode 116 and the gate electrode 116, a connecting portion 122 connecting the adjacent central portions 121, and an opening 123. is there. Further, the planar shape of the interlayer insulating film 12 is a stripe shape in which only the circular center part 121 provided between the second electrode 13 and the gate electrode 116 is formed outside the bonding area of the first electrode 13. is there.

  The “mesh shape” of the interlayer insulating film 12 is disposed on the gate electrode 116 (hole 114), extends in the same direction as the first direction in which the gate electrode 116 extends, and is similar to the gate electrode 116. Extending portions 121 having a stripe shape in a planar shape and arranged in the second direction at regular intervals, and connecting portions 122 integrally connected to each other between the extending portions 121 adjacent in the second direction. And an opening 123 formed in a region surrounded by two extending portions 121 adjacent in the second direction and two connecting portions 122 adjacent in the first direction. Since the connecting portion 122 connects the extending portions 121 adjacent to each other in the second direction at a constant interval in the first direction, the second electrode in the extending portion 121 of the interlayer insulating film 12 and the gate electrode 116 immediately below the extending portion 121. The mechanical strength in the 13 bonding areas can be improved. In particular, it is possible to prevent the extending portion 121 of the interlayer insulating film 12 and the gate electrode 116 immediately below it from being cracked or peeled off due to stress generated during bonding (for example, ultrasonic vibration energy). On the other hand, the connecting portion 122 of the interlayer insulating film 12 is provided between the extending portions 121 adjacent in the second direction, but the connecting portion 122 is provided in the bonding area, and in the bonding area. Since the opening 123 is disposed as much as possible so as to have a mesh shape, the reduction of the contact area and current capacity between the emitter region 113 and the second electrode 13 is suppressed, and the electric field concentration is prevented. Can do. Further, these effects can be achieved only by changing the opening pattern of the interlayer insulating film 12, and since a manufacturing process is not added, the manufacturing becomes easy and the manufacturing cost does not increase. In the first embodiment, a silicon oxide film, specifically, a phosphor glass (PSG) film can be practically used as the interlayer insulating film 12, and the film thickness of the phosphor glass film is, for example, 0.5 μm−3.0. It is set to μm.

  The implementation dimensions of an example of each part related to the interlayer insulating film 12 and the structure of the interlayer insulating film 12 are as follows, for example.

1. Hole width of hole 114: 0.5 μm-3.0 μm
2. Arrangement pitch of holes 114: 2.0 μm-20.0 μm
3. Width of the extended portion 121 of the interlayer insulating film 12: 1.0 μm−4.0 μm
4). Width of connecting portion 122 of interlayer insulating film 12: 1.0 μm-19.0 μm
5). Arrangement pitch of connecting parts 122 in the first direction: 2.0 μm−20.0 μm
6). Size of the opening 123 of the interlayer insulating film 12: 1.0 μm × 1.0 μm-19.0 μm × 1.0 μm
7). Bonding area size: 50 μm × 50 μm-2 mm × 2 mm
In the first embodiment, the planar shape of the interlayer insulating film 12 further includes openings 123 arranged at regular intervals in the first direction as shown in FIG. It is desirable that the adjacent openings 123 be adopted so as to have an offset mesh shape. The offset amount is, for example, a half arrangement pitch.

  Here, the “bonding area of the second electrode 13” in which the planar shape of the interlayer insulating film 12 is set to a mesh shape electrically connects the second electrode (emitter electrode) 13 and the emitter lead. This is the region where the bonding wire (32) is bonded. A protective film 14 is disposed on the second electrode 13, and an opening 141 through which the bonding wire (32) passes is disposed in the protective film 14, and the bonding area of the second electrode 13 is protected by this protection film 14. In the region of the opening 141 provided in the membrane 14.

  Outside the bonding area of the second electrode 13, the planar shape of the interlayer insulating film 12 is a stripe shape as described above. Specifically, the interlayer insulating film 12 is disposed on the gate electrode 116 (hole 114) and extends in the same direction as the first direction in which the gate electrode 116 extends, and is similar to the arrangement interval of the gate electrodes 116. Are formed in a region surrounded by a stretched portion 121 having a stripe shape in a planar shape and a stretched portion 121 adjacent to each other in the second direction. A plurality of openings 124 having a planar stripe shape arranged in the second direction at regular intervals. Outside the bonding area of the second electrode 13, there is no need to increase the mechanical strength against the stress generated during bonding, so the connecting portion 122 is disposed between the extending portions 121 adjacent in the second direction. Absent. Since the area of the opening 124 can be increased as a result of the connection portion 122 not being provided, a contact area and a current capacity between the emitter region 113 and the second electrode 13 are ensured, and electric field concentration is prevented. be able to. Further, these effects can be achieved only by changing the opening pattern of the interlayer insulating film 12, and since a manufacturing process is not added, the manufacturing becomes easy and the manufacturing cost does not increase.

  The second electrode (emitter electrode) 13 is disposed on the interlayer insulating film 12 and is electrically connected to the emitter region 113 and the p-type base region 112 of the IGBT 11. Within the bonding area of the second electrode 13, the second electrode 13 is connected to the IGBT 11 through the opening 123 of the interlayer insulating film 12, and outside the bonding area of the second electrode 13, the second electrode 13 is connected to the interlayer It is connected to the IGBT 11 through the opening 124 of the insulating film 12. The second electrode 13 is used as an emitter electrode (or source electrode), and an aluminum alloy film can be used for the second electrode 13, for example. The aluminum alloy film is aluminum to which additives such as Si for preventing alloy spikes and Cu for preventing migration are added.

  As shown in FIG. 1, the protective film 14 is disposed on the second electrode 13 in the entire region on the main surface of the substrate 10. As shown in FIGS. 1 to 4, the protective film 14 is provided with an opening 141 in a bonding area on the second electrode 13 in the element region. In addition, as shown in FIG. 4, the bonding electrode 13 </ b> G for electrically connecting to the gate electrode 116 of the IGBT 11 is exposed to the protective film 14 through the opening 142 of the protective film 14 in the element region. The bonding electrode 13 </ b> G of the gate electrode 116 is made of the same conductive material in the same conductive layer as the second electrode 13. As shown in FIG. 4, the opening 141 of the protective film 14 is disposed in the central portion of the base region (substrate) 111, and the opening 142 is disposed in the vicinity of the third side 103 of the base region 111. The planar area of the opening 142 is smaller than the planar area of the opening 141. For the protective film 14, for example, a resin film such as PIF (poly-imide film) or a PSG film can be used practically.

[Assembly structure of semiconductor device]
As shown in FIG. 4, the semiconductor device 201 includes a semiconductor element 1 and a first lead (collector lead) having a die bonding region 21 </ b> D for mounting the semiconductor element 1 and extending in a first direction (Y direction). ) 21, a second lead (gate lead) 22 adjacent to the left side of the first lead 21 and extending in the first direction, and adjacent to the right side of the first lead 21 and extending in the first direction. A third lead (emitter lead) 23, a bonding wire 31 that electrically connects the second lead 22 and the bonding electrode 13 G of the semiconductor element 1, and the third lead 23 and the semiconductor element 1. A bonding wire 32 that electrically connects the bonding area of the second electrode 13 and the sealing body 4 are provided.

  For the first lead 21, the second lead 22, and the third lead 23, a Cu plate, an Fe—Ni alloy plate, or the like can be used. Here, although the resistance component and the inductance component of the metal plate or alloy plate are smaller than those of the wire wiring, the stress generated at the junction between the metal plate or alloy plate and the bonding area is large. However, in the first embodiment, since the connecting portion 122 is provided in the interlayer insulating film 12 in the bonding area of the second electrode 13, the mechanical strength in the bonding area of the second electrode 13 is high. Therefore, in the semiconductor device 201, it is possible to prevent the interlayer insulating film 12 and the gate electrode 116 from peeling while reducing the resistance component and the inductance component.

  Although not shown in detail in FIGS. 1 and 4, the first electrode on the back surface of the semiconductor element 1 is electrically and mechanically interposed in the die bond area 21 </ b> D of the first lead 21 with a conductive adhesive interposed therebetween. Connected.

  The bonding wire 31 is electrically connected to the bonding electrode 13G through the opening 142 formed in the protective film 14 of the semiconductor element 1. Similarly, the bonding wire 32 is electrically connected to the electrode 13 through the opening 141 formed in the protective film 14 on the substrate 10. For example, a wire such as Au, Lu, or Al can be practically used as the bonding wires 31 and 32, and this wire is bonded by using ultrasonic bonding together with ultrasonic vibration using a bonding apparatus.

  For example, an epoxy resin is used for the sealing body 4. This epoxy resin is molded by, for example, a molding method. Inside the sealing body 4, the semiconductor element 1, the first lead 21, the second lead 22, the third lead 23, the inner portions (part) of each, and the bonding wires 31 and 32 are hermetically sealed. . Outer portions (parts) of the first lead 21, the second lead 22, and the third lead 23 protrude outside the sealing body 4.

[Features of semiconductor devices]
As shown in FIGS. 1 to 4, in the semiconductor device 201 according to the first embodiment, the planar structure of the interlayer insulating film 12 in the bonding area is configured in a mesh shape, and the second structure of the interlayer insulating film 12 is formed. Since the mechanical strength of the extending portion 121 adjacent to the direction is enhanced by the connecting portion 122, the bonding strength of the interlayer insulating film 12 at the time of bonding is secured, and the breakdown of the interlayer insulating film 12 and the electrode accompanying the bonding are performed. Destruction of the gate electrode 116 or the second electrode 13 can be prevented, for example.

  Furthermore, in the semiconductor device 201 according to the first embodiment, since the connecting portions 122 of the interlayer insulating film 12 are arranged at regular intervals in the second direction, a sufficient plane area of the opening 123 is ensured. be able to. Therefore, a sufficient contact area, which is an original characteristic of the IGBT 11 having a stripe structure, can be sufficiently ensured, electric field concentration can be reduced, a sufficient breakdown voltage can be ensured, and the electrical resistance of the semiconductor element 1 can be secured. A semiconductor device 201 with favorable characteristics can be provided.

  Further, in the semiconductor device 201 according to the first embodiment, since the planar shape of the interlayer insulating film 12 outside the bonding area is configured by a stripe shape, the electrical characteristics of the semiconductor element 1 are ensured as described above. can do.

  Further, in the semiconductor device 201 according to the first embodiment, the planar shape of the interlayer insulating film 12 for producing such an effect can be dealt with by simply changing the pattern of the manufacturing mask. In particular, it is not necessary to increase the number of manufacturing steps, and the manufacturing cost can be reduced. Furthermore, the film thickness of the second electrode 13 and the bonding electrode 13G does not need to be increased for bonding, so that the manufacturing cost can be reduced also in this respect.

[Modification]
In the semiconductor device 1 according to the modification of the first embodiment, the planar shape of the interlayer insulating film 12 of the IGBT 11, particularly in the bonding area, is arranged at regular intervals in the first direction as shown in FIG. 5. The opening 123 and the opening 123 adjacent to the second direction side with respect to the opening 123 are configured in a mesh shape formed as needed so as to be on the same straight line. That is, when the connecting portion 122 is viewed in the second direction, it is formed in a straight line, and when viewed in the first direction, it is repeatedly formed at regular intervals. The planar shape of the interlayer insulating film 12 according to the modification is as follows. The arrangement pitch of 122 and the opening 123 is unoffset.

  In the semiconductor device 201 according to the modified example configured as described above, the same effect as that obtained by the semiconductor device 201 according to the first embodiment described above can be obtained.

  In the semiconductor device 201 according to the first embodiment, the planar shape of the interlayer insulating film 12 is a mesh shape only in the bonding area of the semiconductor element 1, but the present invention is limited to such a structure. Instead, the planar shape of the interlayer insulating film 12 inside and outside the bonding area may be a mesh shape.

(Second Embodiment)
In the second embodiment of the present invention, an example in which the present invention is applied to a semiconductor element composed of an IGBT having a planar structure, a power semiconductor device on which the semiconductor element is mounted, and a manufacturing method thereof will be described.

[Device structure of semiconductor element (IGBT)]
As shown in FIG. 6, the semiconductor element 1 mounted on the semiconductor device 201 according to the second embodiment is composed of an IGBT 11 having a planar structure. That is, the IGBT 11 includes a collector region (p-type second semiconductor region) 110, an n-type base region (n-type first semiconductor region or substrate) 111, and a p-type base region (p-type first semiconductor region). Semiconductor region) 112, emitter region (n-type second semiconductor region) 113, gate insulating film 115, gate electrode 116, collector electrode (first electrode), emitter electrode (second electrode) 13. The basic cross-sectional structure of the semiconductor element 1 is the same as the cross-sectional structure of the semiconductor element 1 of the semiconductor device 201 according to the first embodiment, but the hole 114 shown in FIG. 1 is not provided. That is, in the semiconductor element 1, the gate electrode 116 is disposed in a planar structure on the main surface of the base region 111 with the gate insulating film 115 interposed therebetween, and the base region 112 and the emitter are formed by a double diffusion structure using the gate electrode 116 as a mask. A region 113 is provided.

  Similar to the semiconductor device 201 according to the first embodiment shown in FIGS. 1 to 4 described above, the interlayer insulating film 12 is disposed on the gate electrode 116 and extends in the first direction. Extending portions 121 extending in the same direction and arranged at a constant interval in the second direction as in the arrangement interval of the gate electrodes 116, and extending portions 121 adjacent to each other in the second direction. A region surrounded by a connecting portion 122 that is integrally connected to each other, two extending portions 121 that are adjacent in the second direction, and two connecting portions 122 that are adjacent in the first direction And an opening 123 formed therein. That is, at least in the bonding area of the second electrode 13, the planar shape of the interlayer insulating film 12 is configured by a mesh shape.

[Features of semiconductor devices]
As shown in FIG. 6, in the semiconductor device 201 according to the second embodiment, the interlayer insulation in the bonding area of the second electrode 13 is similar to the semiconductor device 201 according to the first embodiment described above. Since the planar structure of the film 12 is configured in a mesh shape, and the extending portions 121 adjacent to each other in the second direction of the interlayer insulating film 12 are connected by the connecting portions 122, the mechanical strength is enhanced. While securing the bonding strength of the insulating film 12, it is possible to prevent the interlayer insulating film 12 and the electrodes (for example, the gate electrode 116 and the second electrode 13) from being damaged due to bonding.

  Furthermore, in the semiconductor device 201 according to the second embodiment, since the connecting portions 122 of the interlayer insulating film 12 are arranged at regular intervals in the second direction, the planar area (contact area) of the opening 123 is reduced. It can be secured sufficiently. Therefore, since the contact area and current capacity, which are the original characteristics of the semiconductor element 1 having the stripe structure, can be sufficiently secured, electric field concentration can be reduced, and a sufficient breakdown voltage can be secured. A semiconductor device 201 in which the electrical characteristics of the element 1 are favorable can be provided.

  Further, in the semiconductor device 201 according to the second embodiment, the planar shape of the interlayer insulating film 12 outside the bonding area of the second electrode 13 is configured in the stripe shape shown in FIG. 1 electrical characteristics can be ensured.

  Further, in the semiconductor device 201 according to the second embodiment, the planar shape of the interlayer insulating film 12 for producing such an effect can be dealt with only by changing the pattern of the manufacturing mask. In particular, it is not necessary to increase the number of manufacturing steps, and the manufacturing cost can be reduced.

(Third embodiment)
The third embodiment of the present invention relates to the semiconductor device 201 according to the first embodiment and the second embodiment described above, and includes the semiconductor element 1, the second lead 22, and the third lead 23. An example in which the connection method between them is changed will be described.

  In the semiconductor device 201 according to the third embodiment, as shown in FIGS. 7 and 8, the bonding electrode 13G of the semiconductor element 1 and the second lead 22 are electrically connected by the clip lead 22C, The second electrode 13 and the third lead 23 are electrically connected by the clip lead 23C. A solder paste 35 is used for connection between the clip lead 22C and each of the bonding electrode 13G and the second lead 22, and the both are electrically and mechanically connected. Similarly, a solder paste 36 is used for connection between the clip lead 23C and each of the second electrode 13 and the third lead 23, and both are electrically and mechanically connected.

  For the clip leads 22C and 23C, for example, a metal plate such as a Cu plate or an alloy plate such as an Fe-Ni alloy plate can be used. For the solder pastes 35 and 36, for example, Pb-Sn solder or Pb-free solder such as Sn-3 wt% Ag-0.5 wt% Cu can be used. In the connection of the clip lead 22C via the solder paste 35 to the bonding electrode 13G and the connection of the clip lead 22C via the solder paste 35 to the second lead 22, as in the bonding of the bonding wire 31, heat is applied to ultrasonic vibration. It is carried out by a bonding method using pressure bonding together. Similarly, for the connection of the clip lead 23C via the solder paste 36 to the second electrode 13 and the connection of the clip lead 23C via the solder paste 36 to the third lead 23, a heating method using a heater or the like, or a bonding wire Similar to the bonding of 32, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

  Further, in order to improve the bondability between the bonding electrode 13G and the solder paste 35, and similarly improve the bondability between the second electrode 13 and the solder paste 36, each of the bonding electrode 13G and the second electrode 13 is provided. A wettability improving film may be formed on the surface. As this wettability improving film, for example, a composite layer in which a Ni layer is laminated on a Ti layer can be used practically.

  The semiconductor device 201 according to the third embodiment configured as described above has the same effect as that obtained by the semiconductor device 201 according to the first embodiment and the second embodiment described above. be able to.

  Furthermore, the resistance component and the inductance component of the metal plates and alloy plates of the clip leads 22C and 23C are characterized by being smaller than that of the wire wiring. On the other hand, although the stress generated at the joint between the metal plate or alloy plate and the bonding area increases, in the third embodiment, the connecting portion 122 is provided in the interlayer insulating film 12 in the bonding area of the second electrode 13. Therefore, the mechanical strength in the bonding area of the second electrode 13 can be increased. Therefore, in the semiconductor device 201, it is possible to prevent the interlayer insulating film 12 and the gate electrode 116 from peeling while reducing the resistance component and the inductance component.

(Other embodiments)
As described above, the present invention has been described with reference to the first embodiment, its modifications, the second embodiment, and the third embodiment. However, the discussion and the drawings that form a part of this disclosure are the present invention. It does not limit. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, in the above-described embodiment and the like, the semiconductor device 201 on which the semiconductor element 1 made of the IGBT 11 is mounted has been described as an example. However, the present invention is not limited to the IGBT 11 and is a power transistor (power MOSFET). The present invention can be applied to a semiconductor element comprising the above and a semiconductor device on which the semiconductor element is mounted. Further, the present invention can be applied not only to a trench structure but also to a semiconductor element composed of a power transistor having a planar structure and a semiconductor device having the semiconductor element mounted thereon.

It is a principal part expanded sectional view when a bonding wire is provided in the semiconductor element mounted in the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2 is an enlarged plan view of a main part of the semiconductor element shown in FIG. 1 (a part of the IGBT excluding the protective film, bonding wire, second electrode, and interlayer insulating film in FIG. 1). FIG. 2 is an enlarged plan view of a main part of an interlayer insulating film in the semiconductor element shown in FIG. 1. 1 is a plan view showing an internal structure of a semiconductor device according to a first embodiment of the present invention. It is an enlarged plan view of the principal part of an interlayer insulation film in the semiconductor element concerning the modification of a 1st embodiment. It is a principal part expanded sectional view when a bonding wire is provided in the semiconductor element mounted in the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the internal structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 8 is an enlarged cross-sectional view of a main part when a clip lead is provided in the semiconductor element of the semiconductor device shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 201 ... Semiconductor device 110 ... Collector area | region 101 ... 1st edge | side 102 ... 2nd edge | side 103 ... 3rd edge | side 104 ... 4th edge | side 1 ... Semiconductor element 11 ... IGBT
111, 112 ... Base region 113 ... Emitter region 114 ... Hole 115 ... Gate insulating film 116 ... Gate electrode 12 ... Interlayer insulating film 121 ... Extension part 122 ... Connection part 123, 124 ... Opening part 13 ... Second electrode 13G ... Bonding Electrode 14 ... Protective film 141, 142 ... Opening 21 ... First lead 22 ... Second lead 23 ... Third lead 31, 32 ... Bonding wire 22C, 23C ... Clip lead 35, 36 ... Solder paste 4 ... Sealing body

Claims (8)

A substrate having a first side and a second side facing each other in a first direction and a third side and a fourth side facing each other in a second direction intersecting the first direction;
A plurality of first semiconductor regions disposed on the substrate in the second direction and having a first main surface exposed, the first semiconductor region having a first conductivity type;
A plurality of the first semiconductor regions are arranged in the second direction, and a second main surface is exposed on the first main surface of the first semiconductor region, opposite to the first conductivity type. A second semiconductor region having the second conductivity type;
Control disposed between the second semiconductor region of the first semiconductor region and the other second semiconductor region of the other first semiconductor region adjacent in the second direction. Electrodes,
An extending portion that covers the control electrode and extends in the first direction, a connecting portion that connects the extending portions adjacent to each other in the second direction at a constant interval, and the extending portion and the connection An interlayer insulating film having an opening defined by a portion and having an opening exposing the first main surface of the first semiconductor region and the second main surface of the second semiconductor region;
Electrically disposed on the interlayer insulating film and electrically through the opening of the interlayer insulating film to the first main surface of the first semiconductor region and the second main surface of the second semiconductor region; Connected electrodes;
A semiconductor device comprising: The first semiconductor region between the second semiconductor region of the first semiconductor region and the other second semiconductor region of the other first semiconductor region adjacent in the second direction. A hole extending from the first main surface of the first semiconductor region to the substrate side through the first semiconductor region and extending in the first direction;
An insulating film disposed on a side surface of the hole and a bottom surface of the hole, and
The semiconductor device according to claim 1, wherein the control electrode is embedded in the hole with the insulating film interposed. A third semiconductor region disposed between the second semiconductor region of the first semiconductor region and the other second semiconductor region of the other first semiconductor region adjacent in the second direction; A third semiconductor region having a second conductivity type, the main surface of which is exposed;
An insulating film disposed on the third main surface of the third semiconductor region,
2. The semiconductor device according to claim 1, wherein the control electrode is disposed on the third main surface of the third semiconductor region with the insulating film interposed therebetween.   4. The semiconductor device according to claim 1, wherein the interlayer insulating film is configured in a mesh shape by the extending portion, the connecting portion, and the opening. 5.   5. The semiconductor device according to claim 1, wherein the connecting portion of the interlayer insulating film is disposed in a region immediately below a bonding area of the electrode.   6. The semiconductor device according to claim 1, wherein an external wiring of either a wire or a clip lead is electrically connected to the electrode. A substrate having a first side and a second side facing each other in the first direction and a third side and a fourth side facing each other in a second direction intersecting the first direction; A first semiconductor region having a first conductivity type disposed in a plurality of in the second direction and having a first main surface exposed, and the first semiconductor region in the first semiconductor region A second conductive surface having a second conductivity type opposite to the first conductivity type, wherein a second main surface is exposed on the first main surface of the first semiconductor region. And between the second semiconductor region of the first semiconductor region and the other second semiconductor region of the other first semiconductor region adjacent to the second direction. Forming a disposed control electrode; and
An extending portion that covers the control electrode and extends in the first direction, a connecting portion that connects the extending portions adjacent to each other in the second direction at a constant interval, and the extending portion and the connection Forming an interlayer insulating film having an opening defined by the portion and having an opening exposing the first main surface of the first semiconductor region and the second main surface of the second semiconductor region. When,
Electrically disposed on the interlayer insulating film and electrically through the opening of the interlayer insulating film to the first main surface of the first semiconductor region and the second main surface of the second semiconductor region; Forming a connected electrode;
Forming an external wiring electrically connected to the electrode on the electrode;
A method for manufacturing a semiconductor device, comprising:   The step of forming the interlayer insulating film is a step of forming an interlayer insulating film for disposing the connecting portion in a region immediately below the bonding area, and the step of forming the external wiring electrically connects the electrodes in the bonding area. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the external wiring is connected to a semiconductor device.