JP7002998B2 - Semiconductor devices and their manufacturing methods, power conversion devices, three-phase motor systems, automobiles, and railroad vehicles - Google Patents

Description

The present invention relates to a power semiconductor device composed of a plurality of power semiconductor devices, a method for manufacturing the same, a power conversion device, a three-phase motor system, an automobile, and a railroad vehicle.

A power metal insulating film semiconductor field effect transistor (MISFET), which is one of the power semiconductor devices, has conventionally been a power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET). Was the mainstream.

However, a power MISFET using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) (hereinafter referred to as a SiC power MISFET) can have a higher withstand voltage and a lower loss than a Si power MISFET. .. For this reason, particular attention has been paid to the field of power-saving or environment-friendly inverter technology.

Compared with the Si power MISFET, the SiC power MISFET can reduce the on-resistance with the same withstand voltage. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength of about 7 times larger than that of silicon (Si), and the epitaxial layer as a drift layer can be made thinner. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and further reduction of on-resistance is desired from the viewpoint of highly efficient use of energy. ing.

In a SiC power MISFET, a DMOS (Double diffused Metal Oxide Semiconductor) structure using a substrate surface of a 4H-SiC substrate as a channel is generally used (Patent Document 1). Generally, the channel mobility of the Si (0001) plane used as the channel plane in SiC MOSFET is extremely low, about 1/5 as compared with Si MISFET. Therefore, the channel parasitic resistance was large, which was a big problem. As an effective means for reducing this channel parasitic resistance, the use of the (11-20) plane and the (1-100) plane where high channel mobility can be obtained is being studied. In order to utilize a surface with high channel mobility such as the (11-20) surface and the (1-100) surface, it is necessary to form a MOS having a trench type structure on the substrate of the (0001) surface.

According to Patent Document 2, a structure is proposed in which a trench is formed up to the drift layer so as to penetrate the p ⁺ type body layer that supports the withstand voltage, and the channel current flows in the vertical direction with respect to the substrate. However, the dielectric breakdown strength of SiC is as large as about 7 times that of Si, and at the time of blocking, the electric field applied to the gate insulating film formed in the lower part of the trench is also 7 times that of Si. As a result, the withstand voltage of the gate insulating film is exceeded, resulting in dielectric breakdown. In order to avoid the destruction of the gate insulating film during blocking, Patent Document 2 proposes a structure that relaxes the gate insulating film electric field. However, in a structure like Patent Document 2, since the drain current path is narrowed, the parasitic resistance becomes large and sufficient performance cannot be obtained.

Therefore, Patent Document 3 discloses a structure in which a trench is formed inside without being exposed from the p ⁺ type body layer. In this case, the channel current flows parallel to the substrate. However, since the n ⁺⁺ type high concentration source diffusion layer connected to the source electrode is formed as the same layer from the p ⁺ type body layer to the JFET region outside the p ⁺ type body layer across the trench, it has high electrostatic capacity. The potential reaches the side surface of the trench via the n ⁺⁺ type high concentration source diffusion layer on the JFET region side exposed from the p ⁺ type body layer. As a result, a high electric field exceeding dielectric breakdown is applied to the gate insulating film on the trench side at the time of blocking, leading to breakdown.

Patent Document 4 discloses a structure in which a trench is formed inside without being exposed from the p ⁺ type body layer as in Patent Document 3. However, apart from the n ⁺⁺ type high concentration source diffusion layer connected to the source electrode, the high concentration source diffusion layer extends from the p ^{+ type body layer to the n type JFET region outside the p + type} body layer across the trench. An n ⁺ type current diffusion layer having a lower concentration than that of the current diffusion layer is formed. Further, above the n ⁺ type current diffusion layer, a p ⁺ type electric field relaxation layer that relaxes the electric field is formed so as to connect the p ⁺ type body layer. This p ⁺ type electric field relaxation layer makes it possible to increase the concentration of the n ⁺ type current diffusion layer to such an extent that it does not become a parasitic resistance. That is, this p ⁺ type electric field relaxation layer suppresses the intrusion of the electrostatic potential into the n ⁺ type current diffusion layer, and reduces the gate insulating film electric field applied to the gate insulating film on the trench side at the time of blocking. be able to. As a result, both low on-resistance and high reliability can be achieved.

In Patent Document 4, a p ⁺ type electric field relaxation layer is provided on the n ⁺ type current diffusion layer at the drain end. On the other hand, in Patent Document 5, a p-type layer is provided on the n-type source diffusion layer at the end of the source. However, in Patent Document 5, a trench is formed up to the drift layer so as to penetrate the p-type body layer that supports the pressure resistance, and the structure in which the trench is covered with the p-type body layer as in Patent Documents 3 and 4 is At the time of blocking, a high electric field exceeding the dielectric breakdown is applied to the gate insulating film at the trench end on the drain side, leading to breakdown.

Japanese Patent No. 6168732 Japanese Unexamined Patent Publication No. 2009-260253 JP-A-2015-32813 International Publication No. 2016/116998 International Publication No. 2016/129068

However, in the technique disclosed in Patent Document 4, the channel length is determined by the positions of the n ⁺⁺ type high-concentration source diffusion layer and the n ⁺ type current diffusion layer, and the channel length is due to the misalignment of the two layers at the time of exposure. Variation becomes a problem. The variation in the channel length becomes the variation in the threshold voltage and the on-resistance between the chips, and the variation in the performance between the chips installed in the power module. When the performance varies among the chips in the power module, a high load is generated in the chip with inferior performance, local heat generation is generated in the power module, and the reliability of the power module is impaired.

Further, since the channel length is determined by combining the two layers at the time of exposure, it is necessary to give a large margin to the channel length. As a result, it becomes difficult to reduce the channel resistance by shortening the channel.
Further, when it is turned on, the electric field is concentrated on the upper edge portion of the trench on the source side, so that the threshold voltage is lowered and the problem of off-leakage occurs.
Therefore, in order to solve the above problems, the inventors of the present application have examined an n ⁺ type current diffusion layer, a p ⁺ type electric field relaxation layer, and a peripheral structure thereof.

An object of the present invention is to provide a power semiconductor device and a method for manufacturing the same, which can be expected to have high performance and high reliability by suppressing channel length variation and having a structure capable of shortening the channel. Further, a compact, high-performance, highly reliable power conversion device using the semiconductor device, and a three-phase motor system using the power conversion device will be provided. Furthermore, it provides light weight, high performance, and high reliability of automobiles and railroad vehicles using the three-phase motor system.

In a preferred example of the semiconductor device of the present invention, a first conductive type semiconductor substrate having a first impurity concentration, a back surface electrode formed on the back surface side of the semiconductor substrate, and the semiconductor substrate formed on the semiconductor substrate. The first region of the first conductive type having a second impurity concentration lower than the first impurity concentration and the first region formed in the first region of the first conductive type and formed on the surface side of the semiconductor substrate. It is sandwiched between a second region of the second conductive type opposite to the conductive type and a plurality of adjacent second regions, and within the third region of the first conductive type and the second region of the second conductive type. The fourth region of the first conductive type and the fourth region of the first conductive type are adjacent to each other and electrically connected to each other, and the concentration of the first region is lower than that of the fourth region of the first conductive type. The sixth region of the first conductive type, the sixth region of the first conductive type, and the fifth region, which are electrically connected to the fifth region of the conductive type and are electrically connected to the third region and have the same concentration as the fifth region of the first conductive type. A trench extending to the second region and the sixth region, shallower than the second region, and having a bottom surface in contact with the second region, and a gate insulating film formed on the inner wall of the trench. And a gate electrode formed on the gate insulating film.
Here, the equal concentration means that the difference is within ± 10%, and the equal concentration of the first current diffusion layer and the second current diffusion layer means that the concentration is the same in the cross section of the first current diffusion layer. It means that the difference between the concentration at the position of and the concentration at the center position in the cross section of the second current diffusion layer is within ± 10%.

Further, in a preferred example of the method for manufacturing a semiconductor device of the present invention, the first conductive type silicon carbide semiconductor substrate on which the first conductive type epitaxial layer is formed is prepared, and the first conductive type is formed in the epitaxial layer. A second conductive type body layer opposite to the mold is formed, the first conductive type JFET region sandwiched between a plurality of adjacent body layers is formed, and the second conductive type body layer is formed. The first conductive type source region is formed, adjacent to and electrically connected to the first conductive type source region, and the first current of the first conductive type is lower in concentration than the first conductive type source region. A diffusion layer is formed, electrically connected to the JFET region, and one photomask is used to form the first conductive type first current diffusion layer and the first conductive type second current diffusion layer. A trench that is shallower than the body layer, has a bottom surface in contact with the body layer, and has side surfaces extending in contact with the first current diffusion layer, the body layer, and the second current diffusion layer, is formed on the inner wall of the trench. It is characterized by having each step of forming an insulating film and forming a gate electrode on the insulating film.

That is, as a feature of the manufacturing method, the resist mask formed by simultaneously exposing the first conductive type first current diffusion layer and the first conductive type second current diffusion layer with the same photomask. This is a step of simultaneously forming the first conductive type impurities by ion-implanting them.

According to the present invention, it is possible to provide a high-performance and highly reliable power semiconductor device. As a result, it is possible to realize high performance of power conversion devices, three-phase motor systems, automobiles, and railroad vehicles.

FIG. 3 is a top view of a main part of a semiconductor chip on which a silicon carbide semiconductor device composed of a plurality of SiC power MISFETs according to the first embodiment of the present invention is mounted. It is a bird's-eye view of the main part of the SiC power MISFET according to the first embodiment of the present invention. It is a process drawing explaining the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is sectional drawing of the main part of the silicon carbide semiconductor device for explaining the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1 of this invention. Following FIG. 4, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 5, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 6, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 7, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. It is a top view of the main part in the manufacturing process of the silicon carbide semiconductor device following FIG. FIG. 8 is a cross-sectional view of a main part of the cutting line AA'in FIG. 9A during the manufacturing process of the silicon carbide semiconductor device following FIG. FIG. 8 is a cross-sectional view of a main part of the cutting line BB'in FIG. 9A during the manufacturing process of the silicon carbide semiconductor device following FIG. 9 is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same location as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device, following FIGS. 9A to 9C. Following FIG. 10, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 11, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 12, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 13, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 14, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 15, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. Following FIG. 16, it is a cross-sectional view of a main part of the silicon carbide semiconductor device at the same position as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device. It is a bird's-eye view of the main part of the SiC power MISFET according to the second embodiment of the present invention. It is sectional drawing of the main part of the SiC power MISFET according to Embodiment 2 of this invention. It is sectional drawing of the main part of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device according to the second embodiment of the present invention. It is a bird's-eye view of the main part of the SiC power MISFET according to the third embodiment of the present invention. It is a top view of the main part in the manufacturing process of the silicon carbide semiconductor device following FIG. FIG. 21 is a cross-sectional view of a main part of the cutting line AA'in FIG. 22A during the manufacturing process of the silicon carbide semiconductor device, following FIG. 21. FIG. 21 is a cross-sectional view of a main part of the cutting line BB'in FIG. 22A during the manufacturing process of the silicon carbide semiconductor device following FIG. 21. It is sectional drawing of the main part of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device at the cutting line AA'position of FIG. 22A according to the third embodiment of the present invention. It is sectional drawing of the main part of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device at the cutting line BB'position of FIG. 22A according to the third embodiment of the present invention. FIG. 3 is a circuit diagram of a power conversion device (inverter) equipped with any one of the first to third embodiments according to the fourth embodiment of the present invention. FIG. 3 is a circuit diagram of a power conversion device (inverter) equipped with any one of the first to third embodiments according to the fifth embodiment of the present invention. It is a block diagram of the electric vehicle which carries any of Embodiments 4 and 5 according to Embodiment 6 of this invention. It is a circuit diagram of the boost converter which carries out any of Embodiments 4 and 5 according to Embodiment 6 of this invention. It is a block diagram of the railroad vehicle which carries any of Embodiments 4 and 5 according to Embodiment 7 of this invention.

In the following embodiments, where it is necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, one of which is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc.

Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easier to see even if they are plan views. Further, in all the drawings for explaining the following embodiments, those having the same function are designated by the same reference numerals in principle, and the repeated description thereof will be omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

≪Silicon carbide semiconductor device≫
The structure of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a top view of a main part of a semiconductor chip on which a silicon carbide semiconductor device composed of a plurality of SiC power MISFETs is mounted, and FIG. 2 is a bird's-eye view of the main part of the SiC power MISFET. It is a SiC power MOSFET that constitutes a silicon carbide semiconductor device.

As shown in FIG. 1, the semiconductor chip 1 on which the silicon carbide semiconductor device is mounted has an active region (SiC power MISFET formation) located below the source wiring electrode 2 in which a plurality of n-channel type SiC power MISFETs are connected in parallel. It is composed of a region (region, element forming region) and a peripheral forming region surrounding the active region in a plan view. The peripheral forming region includes a plurality of p-type floating field limiting rings (FLRs) 3 formed so as to surround the active region in a plan view, and a plurality of the above-mentioned plurality in a plan view. An n ⁺⁺ type guard ring 4 formed so as to surround the p-type floating field limiting ring 3 is formed.

On the surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as SiC epitaxial substrate), a gate electrode of a SiC power MISFET, an n ⁺⁺ type source region, and an n ⁺ type first current diffusion layer. , P ⁺ type first electric field relaxation layer, n ⁺ type second current diffusion layer, p ⁺ type second electric field relaxation layer, p ⁺ type body layer, trench, channel region on the side surface of the trench, etc. are formed. , An n ⁺ type drain region of the SiC power MISFET is formed on the back surface side of the SiC epitaxial substrate.

By forming a plurality of p-type floating field limiting rings 3 around the active region, the maximum electric field portion sequentially shifts to the outer p-type floating field limiting ring 3 when off. Since the outermost p-type floating field limiting ring 3 yields, the silicon carbide semiconductor device can have a high withstand voltage. FIG. 1 illustrates an example in which three p-shaped floating field limiting rings 3 are formed, but the present invention is not limited thereto. Further, the n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

The plurality of SiC power MISFETs 6 formed in the active region have a stripe pattern in a plan view, and the gate electrodes of all the SiC power MISFETs are gated by the lead wiring (gate bus line) connected to each stripe pattern. It is electrically connected to the wiring electrode 8.

Further, the plurality of SiC power MISFETs are covered with the source wiring electrodes 2, and the source and potential fixing layers of the body layers of the respective SiC power MISFETs are connected to the source wiring electrodes 2. The source wiring electrode 2 is connected to the external wiring through the source opening 7 provided in the insulating film. The gate wiring electrode 8 is formed so as to be separated from the source wiring electrode 2, and is connected to the gate electrode of each SiC power MISFET. The gate wiring electrode 8 is connected to the external wiring through the gate opening 5. Further, the n ⁺ type drain region formed on the back surface side of the n-type SiC epitaxial substrate is electrically connected to the drain wiring electrode (not shown) formed on the entire back surface of the n-type SiC epitaxial substrate. is doing.

Next, the structure of the SiC power MISFET according to the first embodiment will be described with reference to FIG.
Although not shown, the surface (first main surface) of the n ⁺ type SiC substrate 107 made of silicon carbide (SiC) is made of silicon carbide (SiC) having a lower impurity concentration than the n ⁺ type SiC substrate. An n ^- type epitaxial layer 101 is formed. The n ^- type epitaxial layer 101 functions as a drift layer. The thickness of the n ^- type epitaxial layer 101 is, for example, about 5 to 50 μm.

A p ⁺ type body layer (well region) 102 is formed in the epitaxial layer 101 having a predetermined depth from the surface of the epitaxial layer 101. An n ^- type JFET region 124 is formed between adjacent p ⁺ type body layers 102.
Although not shown, a p ⁺⁺ type body layer potential fixing region 109 is formed.
Further, an n ⁺⁺ type source region 103 having a predetermined depth from the surface of the epitaxial layer 101 and containing nitrogen as an impurity is formed in the p ⁺ type body layer 102.

The p ⁺ type body layer 102 has the same depth as the n ⁺ type first current diffusion layer 122 and the n ⁺ type first current diffusion layer 122, and has the same depth as the n ⁺ type second current diffusion layer 105. Is formed. The n ⁺ type first current diffusion layer 122 is adjacent to the n ⁺⁺ type source region 103, ^and a part of the n ⁺ type second current diffusion layer 105 is adjacent to the p ⁺ type body layer 102. It extends to the JFET region 124.

A p + type first electric field relaxation layer 123 is formed on the n ⁺ type first current diffusion layer 122, and a p ⁺ type second electric field relaxation layer 123 is formed on the n ⁺ type second current diffusion layer 105 ^. Layer 119 is formed. The p ⁺ type first electric field relaxation layer 123 and the p ⁺ type second electric field relaxation layer 119 have the same depth.

A trench 106 is formed extending from the n ⁺ type first current diffusion layer 122 to the p ⁺ type body layer 102 and extending over the n ⁺ type second current diffusion layer 105. The bottom surface of the trench 106 is in contact with the p ⁺ type body layer 102. A gate insulating film 110 (not shown in FIG. 2) is formed on the surface of the trench 106. A gate electrode 111 (not shown in FIG. 2) is formed on the gate insulating film 110.

The depth (first depth) of the p ⁺ type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. The depth (third depth) of the n ⁺⁺ type source region 103 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1 μm. The depth (fourth depth) of the n ⁺ type first current diffusion layer 122 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1 μm. The depth of the n ⁺ type second current diffusion layer 105 from the surface of the epitaxial layer 101 is the same as that of the n ⁺ type first current diffusion layer 122 (fourth depth). The depth (fifth depth) of the p ⁺ type first electric field relaxation layer 123 from the surface of the epitaxial layer 101 is, for example, about 0.01 to 0.5 μm. The depth of the p ⁺ type second electric field relaxation layer 119 from the surface of the epitaxial layer 101 is the same as that of the p ⁺ type first electric field relaxation layer 123 (fifth depth).

The depth (sixth depth) of the trench 106 from the surface of the epitaxial layer 101 is shallower than the depth (first depth) of the p ⁺ type body layer 102 from the surface of the epitaxial layer 101, for example, 0. It is about 1 to 1.5 μm. The length in the direction parallel to the channel length of the trench (trench length) is, for example, about 1 to 3 μm. The length (trench width) in the direction parallel to the channel width in the direction parallel to the substrate of the trench is, for example, about 0.1 to 2 μm. The trench spacing in the direction parallel to the channel width is, for example, about 0.1 to 2 μm. Although not shown, the depth (second depth) of the p ⁺⁺ type body layer potential fixing region 109 (see FIG. 8) from the surface of the epitaxial layer 101 is, for example, about 0.1 to 0.5 μm.

In addition, " ^- " and " ⁺ " are codes indicating the relative impurity concentrations of n-type or p-type conductive type, for example, "n-" ^, "n", "n ⁺ ", "n ⁺⁺ ". The impurity concentration of the n-type impurity increases in this order.

Although not shown, the preferred range of the impurity concentration of the n ⁺ type SiC substrate 107 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^-3 . The preferable range of the impurity concentration of the n ^- type epitaxial layer 101 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 . The preferable range of the impurity concentration of the p ⁺ type body layer 102 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^-3 . Further, the preferable range of the impurity concentration of the n ⁺⁺ type source region 103 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 . The preferred range of impurity concentrations in the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 is, for example, 5 × 10 ¹⁶ to 5 × 10 ¹⁸ cm ^-3 . The preferred range of impurity concentrations in the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type second electric field relaxation layer 119 is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 . The preferred range of impurity concentration in the n ^- type JFET region 124 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 . Although not shown, the preferred range of the impurity concentration in the p ⁺⁺ type body layer potential fixing region 109 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 . The channel region is the surface of the trench 106 and the surface of the p ⁺ -shaped body layer 102 sandwiched between the trench 106. The n ^- type JFET region 124 is a region sandwiched between each pair of the n ⁺ type second current diffusion region 105 and the p-type body layer 102.

Although not shown, the gate insulating film 110 is formed on the channel region, and the gate electrode 111 is formed on the gate insulating film 110.

Next, the features of the configuration of the SiC power MISFET according to the first embodiment will be described with reference to FIG. 2 described above.
As shown in FIG. 2 described above, since the side surface of the trench 106 is the channel region, higher channel mobility can be expected as compared with the channel region on the surface of the SiC epitaxial layer 101. Further, since the channel length is determined by the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 formed by using the same mask, the n ⁺⁺ type as described in Patent Document 4 is used. The variation in channel length is small compared to the structure determined by the alignment of the n ⁺ type current diffusion layer, which has a lower concentration than the high-concentration source diffusion layer and the high-concentration source diffusion layer. As a result, the variation in the threshold voltage and the on-resistance between the chips can be reduced. Further, since the channel length is determined by one layer, it is not necessary to give a large margin to the channel length as compared with the case where it is determined by two layers. As a result, it is possible to reduce the channel resistance by shortening the channel. Further, since the p ⁺ type first electric field relaxation layer 123 exists not only on the n ⁺ type second current diffusion layer 105 but also on the n ⁺ type first current diffusion layer 122, the upper part of the source side trench. The edge is covered with a p ⁺ type first electric field relaxation layer 123. Therefore, even if the electric field is concentrated on the upper edge portion of the trench when it is turned on, the threshold voltage does not decrease and off-leakage can be suppressed.

From the above, the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 are formed so as to define the channel length with the same mask, and the p ⁺ type first electric field relaxation layer 123 is further formed. By forming the p ⁺ type second electric field relaxation layer 119, it is possible to reduce the variation in channel length and shorten the channel. Further, even if the electric field is concentrated on the upper edge portion of the trench when it is turned on, the threshold voltage does not decrease and the problem of off-leakage does not occur. Therefore, as compared with the structure in Patent Document 4, there is no variation in performance between chips in the power module, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, the problem of erroneous arcs that occur during switching does not occur.

<< Manufacturing method of silicon carbide semiconductor device >>
The method for manufacturing a silicon carbide semiconductor device according to the first embodiment of the present invention will be described in order of steps with reference to FIGS. 3 to 17. FIG. 3 is a process diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment. 4 to 8 and 9 (b) to 17 are cross-sectional views of a main part of a silicon carbide semiconductor device in which a part of a SiC power MOSFET forming region (element forming region) is enlarged. FIG. 9A is a top view of a main part of a semiconductor chip on which a silicon carbide semiconductor device configured by a SiC power MISFET is mounted.

<Process P1>
First, as shown in FIG. 4, an n ⁺ type 4H-SiC substrate 107 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 107. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^-3 . Further, the n ⁺ type SiC substrate 107 has both Si and C surfaces, but the surface of the n ⁺ type SiC substrate 107 may be either the Si surface or the C surface.

Next ^, an n− type epitaxial layer 101 of silicon carbide (SiC) is formed on the surface (first main surface) of the n ⁺ type SiC substrate 107 by an epitaxial growth method. An n-type impurity lower than the impurity concentration of the n ⁺ -type SiC substrate 107 is introduced into the n ^- type epitaxial layer 101. The impurity concentration of the n ^- type epitaxial layer 101 depends on the element rating of the SiC power MISFET, and is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 . The thickness of the n ^- type epitaxial layer 101 is, for example, 5 to 50 μm. By the above steps, the SiC epitaxial substrate 104 composed of the n ⁺ type SiC substrate 107 ^and the n− type epitaxial layer 101 is formed.

<Process P2>
Next, there is a predetermined depth (seventh depth) from the back surface (second main surface) of the n ⁺ type SiC substrate 107, and the n ⁺ type drain region is formed on the back surface of the n ⁺ type SiC substrate 107. Form 108. The impurity concentration of the n ⁺ type drain region 108 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 .

Next, as shown in FIG. 5 ^, a mask M11 is formed on the surface of the n− type epitaxial layer 101. The thickness of the mask M11 is, for example, about 1.0 to 3.0 μm. The width of the mask M1 in the element forming region is, for example, about 1.0 to 5.0 μm. As the mask material, an inorganic material SiO ₂ film, Si film, SiN film, an organic material resist film, and a polyimide film can be used.

Next, a p-type impurity, for example, an aluminum atom (Al), is ion-implanted into the n ^- type epitaxial layer 101 through the mask M11. As a result, the p ⁺ type body layer 102 is formed in the element forming region of the n ⁻ type epitaxial layer 101. Further, a JFET region 124 is formed by shielding ion implantation with a mask M11 between adjacent p ⁺ type body layers 102. Although not shown, a p ⁺ type floating field limiting ring 3 is formed around the element forming region at the same time. The structure of the terminal portion is not limited to this, and may be, for example, a junction termination extension (JTE) structure.

The depth (first depth) of the p ⁺ type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the p ⁺ type body layer 102 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^-3 . The maximum impurity concentration of the p ⁺ type body layer 102 is, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 .

Next, as shown in FIG. 6, after removing the mask M11, the mask M12 is formed. The mask M12 is formed of, for example, a resist film. The mask M12 is formed by drawing on a resist film by simultaneously exposing each pattern with the same photomask. The thickness of the mask M12 is, for example, about 1.0 to 3.0 μm. The channel length is determined by the length of the mask M12, and is, for example, about 0.1 to 2 μm.

Next, n-type impurities such as nitrogen atoms (N) are ion-implanted into the n ^- type epitaxial layer 101 and the p ⁺ type body layer 102 through the mask M12. As a result, the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 are formed in the element forming region of the n ⁻ type epitaxial layer 101 and the p ⁺ type body layer 102.

The depth (fourth depth) from the surface of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 is, for example, about 0.1 to 1.0 μm. The impurity concentrations of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 are, for example, in the range of 5 × 10 ¹⁶ to 5 × 10 ¹⁸ cm ^-3 .

Subsequently, p-type impurities such as Al atoms are ion-implanted on the surfaces of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 through the mask M12. As a result, the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type second electric field relaxation layer 119 are formed on the surfaces of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105. ..

The depth (fifth depth) from the surface of the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type second electric field relaxation layer 119 is, for example, about 0.01 to 0.5 μm. The impurity concentrations of the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type second electric field relaxation layer 119 are, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 .

Next, as shown in FIG. 7, after removing the mask M12, the mask M13 is formed. The mask M13 is formed of, for example, a resist film. The thickness of the mask M13 is, for example, about 1 to 4 μm. The mask M13 opens the n ⁺⁺ type source region 103 forming portion adjacent to the n ⁺ type first current diffusion layer 122. Further, although not shown, the mask M13 is also provided with an opening in a region where the guard ring 4 is formed on the outer periphery of the floating field limiting ring 3. N-type impurities such as nitrogen atom (N) and phosphorus atom (P) are ion-implanted into the p ⁺ type body layer 102 through the mask M13 to form the n ⁺⁺ type source region 103, which is not shown. However, an n ⁺⁺ type guard ring 4 is formed in the peripheral forming region.

The depth (third depth) from the surface of the n ⁺⁺ type source region 103 is, for example, about 0.1 to 1 μm. The impurity concentration of the n ⁺⁺ type source region 103 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 .

Next, as shown in FIG. 8, the mask M13 is removed to form the mask 14. The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, about 0.5 to 3 μm. The mask M14 opens only the potential fixing region 109 forming portion of the p ⁺⁺ type body layer. A p-type impurity is ion-implanted into the p-type body layer 102 through the mask M14 to form a potential fixed region 109 of the p ⁺⁺ type body layer. The depth (second depth) of the p ⁺⁺ type body layer potential fixing region 109 from the surface of the p ⁺ type body layer 102 is, for example, about 0.1 to 0.5 μm. The impurity concentration in the potential fixing region 109 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 .

<Process P3>
Next, after removing the mask M14, although not shown, a carbon (C) film is deposited on the front surface and the back surface of the SiC epitaxial substrate 104 by, for example, a plasma CVD method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front surface and the back surface of the SiC epitaxial substrate 104 with this carbon (C) film, the SiC epitaxial substrate 104 is heat-treated at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. This activates each impurity ion-implanted into the SiC epitaxial substrate 104. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

<Process P4>
Next, as shown in FIGS. 9A to 9C, a hard mask for trench processing and a mask 125A that also serves as a field oxide film are formed. The mask 125A is formed of, for example, a silicon dioxide (SiO ₂ ) film.

9 (a) is a top view of the main part, FIG. 9 (b) is a cross-sectional view of the main part at the cutting line AA'position of FIG. 9 (a), and FIG. 9 (c) is the cutting line BB'of FIG. 9 (a). It is a cross-sectional view of a main part of a position. The thickness of the mask 125A is, for example, about 0.5 to 3 μm. The mask 125A is provided with an opening portion in the region where the trench 106 is formed in a later step.

Next, as shown in FIG. 9 (c), the n ⁺ type first current diffusion layer 122, the p ⁺ type first electric field relaxation layer 123, and the p ⁺ type body layer 102 are subjected to the dry etching process. , The n ⁺ type second current diffusion layer 105 and the p ⁺ type second electric field relaxation layer 119 form a trench 106 extending to the n + type second current diffusion layer 105.
The depth of the trench to be formed is shallower than the depth of the p ⁺ type body layer 102. The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length X (see FIG. 9A) in the direction parallel to the channel length direction of the trench is, for example, about 1 to 3 μm. The width Y1, which is the length in the direction orthogonal to the channel length direction of the trench, is, for example, about 0.1 to 2 μm. The spacing Y2 between the trenches in the direction orthogonal to the channel length direction is, for example, about 0.1 to 2 μm.

<Process P5>
Next, as shown in FIG. 10, a gate insulating film 110 is formed on the surface of the epitaxial layer 101 and the surface of the trench 106 while leaving the field oxide film 125. The gate insulating film 110 is made of, for example, a SiO ₂ film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

Next, as shown in FIG. 11, an n-type or p-type polycrystalline silicon (Si) film 111A is formed on the gate insulating film 110. The thickness of the n-type or p-type polycrystalline silicon (Si) film 111A is, for example, about 0.01 to 4 μm.

Next, as shown in FIG. 12, the polycrystalline silicon (Si) film 111A is processed by a dry etching method using a mask M17 (photoresist film) to form a gate electrode 111.

<Process P6>
Next, as shown in FIG. 13, an interlayer insulating film 112 is formed on the surface of the n− type epitaxial layer 101 so as ^to cover the gate electrode 111 and the gate insulating film 110, for example, by plasma CVD method.

Next, as shown in FIG. 14, the interlayer insulating film 112 and the gate insulating film 110 are processed by a dry etching method using a mask M18 (photoresist film), and a part of the n ⁺⁺ type source region 103 and p. It forms an opening CNT_S that reaches the ⁺⁺ type body layer potential fixing region 109.

Next, as shown in FIG. 15, after removing the mask M18, a part of the n ⁺⁺ type source region 103 exposed on the bottom surface of the opening CNT_S and the p ⁺⁺ type body layer potential fixing region 109, respectively. The metal silicide layer 113 is formed on the surface of the above.

First, although not shown, nickel (Ni) is used as the first metal film by, for example, a sputtering method so as to cover the inside (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT_S on the surface of the epitaxial layer 101. ) Is deposited. The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, a silicidation heat treatment at 600 to 1000 ° C. is performed to react the first metal film with the epitaxial layer 101 at the bottom surface of the opening CNT_S to form a metal silicide layer 113, for example, a nickel silicide (NiSi) layer. It is formed on a part of the n ⁺⁺ type source region 103 exposed on the bottom surface of the opening CNT_S and on the respective surfaces of the p ⁺⁺ type body layer potential fixing region 109. Subsequently, the unreacted first metal film is removed by a wet etching method. For the wet etching method, for example, sulfuric acid hydrogen peroxide is used.

Next, although not shown, the interlayer insulating film 112 is processed using a mask (photoresist film) to form an opening CNT_G that reaches the gate electrode 111.

Next, as shown in FIG. 16, the opening CNT_S reaching the metal silicide layer 113 formed on the respective surfaces of a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109, and From the third metal film 114, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film on the interlayer insulating film 112 including the inside of the opening CNT_G (not shown) reaching the gate electrode 111. A laminated film is deposited. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the third metal film 114, it is electrically connected to a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109 via the metal silicide layer 113 in CNT_S. The source wiring electrode 2 to be connected and the gate wiring electrode 8 electrically connected to the gate electrode 111 through the opening CNT_G are formed.

Next, although not shown, a SiO ₂ film or a polyimide film is deposited as a passivation film so as to cover the gate wiring electrode 8 and the source wiring electrode 2.

Next, although not shown, the passivation film is processed to form a passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited in the n ⁺ type drain region 108 by, for example, a sputtering method. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 17, by performing a laser silicidizing heat treatment, the second metal film reacts with the n ⁺ type drain region 108, and the metal silicide layer covers the n ⁺ type drain region 108. Form 115. Subsequently, the drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. A laminated film of a Ti film, a Ni film, and a gold (Au) film is deposited on the drain wiring electrode 116 by 0.5 to 1 μm.

After that, external wiring is electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively.

As described above, according to the first embodiment, as shown in FIG. 6, the channel length is between the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 formed by the mask M12. Is stipulated. Therefore, as compared with the structure in Patent Document 4, it is possible to reduce the variation in channel length and shorten the channel. Further, as shown in FIG. 6, on the surface of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 with the mask M12, the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type The second electric field relaxation layer 119 is formed. Therefore, since the source side trench upper edge becomes the p ⁺ type first electric field relaxation layer 123, even if the electric field is concentrated on the trench upper edge portion at the time of turning on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, there is no variation in performance between chips in the power module, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, the problem of erroneous arcs that occur during switching does not occur.

The difference between the second embodiment and the first embodiment described above is that the n-type JFET region 224 has a high concentration and the p ⁺ type second, as shown in the bird's-eye view of the main part of the SiC power MISFET in FIG. The point is that the p ⁺ type second electric field relaxation layer 219 is formed by extending the electric field relaxation layer to the upper part of the JFET region 224. By increasing the concentration of the n-type JFET region 224, the JFET resistance, which is a parasitic resistance, can be reduced. However, if the concentration in the JFET region 224 is increased, the electric field above the JFET becomes higher. Therefore, the oxide film on the upper part of the JFET region 224 is protected by forming the p ⁺ type second electric field relaxation layer 219 in which the p ⁺ type second electric field relaxation layer extends to the upper part of the JFET region 224. As a result, it is possible to obtain high reliability while reducing the on-resistance.

<< Manufacturing method of silicon carbide semiconductor device >>
A method for manufacturing a silicon carbide semiconductor device according to the second embodiment will be described with reference to FIGS. 19 and 20. 19 and 20 show an enlarged part of the SiC power MOSFET forming region (element forming region) of the silicon carbide semiconductor device of the present embodiment.

The same applies to the above-described first embodiment and the p ⁺⁺ type body layer potential fixing region 209 forming step. FIG. 19 is a step of forming the p ⁺ type second electric field relaxation layer 219 in which the n-type JFET region 224 and the p ⁺ type second electric field relaxation layer extend to the upper part of the JFET region 224. As shown in FIG. 19, the mask M20 is formed. The mask M20 is formed of, for example, a resist film. The thickness of the mask M20 is, for example, about 1 to 4 μm. The mask M20 opens an n-type JFET region forming portion. An n-type impurity, for example, a nitrogen atom (N) or a phosphorus atom (P), is ion-implanted into the n ^- type epitaxial layer 201 through the mask M20 to form an n-type JFET region 224.

The depth (seventh depth) from the surface of the n-type JFET region 224 is, for example, about 0.5 to 2.0 μm. The impurity concentration in the n-type JFET region 224 is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 .

Next, a p-type impurity, for example, an Al atom is ion-implanted on the surface of the n-type JFET region 224 through the mask M20. As a result, a p ^{+ type second electric field relaxation layer 219 is formed on the surface of the n-type JFET region 224 by extending the p + type} second electric field relaxation layer to the upper part of the JFET region 224.

The depth (seventh depth) from the surface of the p ⁺ type second electric field relaxation layer 219 is, for example, about 0.01 to 0.5 μm. The impurity concentration of the p ⁺ type second electric field relaxation layer 219 is, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 .

The remaining steps are the same as those in the first embodiment described above, and by performing the remaining steps, the second embodiment shown in the cross-sectional view of the main part of FIG. 20 is completed.

As described above, according to the second embodiment, it is possible to reduce the variation in channel length and shorten the channel as compared with the structure in Patent Document 4, as in the first embodiment. Further, since the upper edge of the trench on the source side is the p ⁺ type first electric field relaxation layer 223, even if the electric field is concentrated on the upper edge of the trench when it is turned on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, there is no variation in performance between chips in the power module, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, the problem of erroneous arcs that occur during switching does not occur. In addition, since the n-type JFET region 224 has a high concentration, the JFET resistance, which is a parasitic resistance, can be reduced. Further, since there is a p ⁺ type second electric field relaxation layer 219 in which the p ⁺ type second electric field relaxation layer extends to the upper part of the JFET region 224, even if the n-type JFET region 224 has a high concentration, During blocking, a high electric field leading to dielectric breakdown is not applied to the field oxide film 225 above the JFET. Therefore, it is possible to provide a silicon carbide semiconductor device having higher performance and higher reliability.

The difference between the third embodiment and the first embodiment described above is that the trench 306 is an n ⁺ type first current diffusion layer 322 and a p ⁺ type, as shown in the bird's-eye view of the main part of the SiC power MISFET in FIG. It is a point that the n ⁺⁺ type high concentration source region 303 is reached through the first electric field relaxation layer 323 of the above. Since the trench 306 reaches the n ⁺⁺ type high concentration source region 303, the surface of the n ⁺ type first current diffusion layer 322 becomes an accumulation layer when the SiC power MISFET is on, and the trench 306 becomes a storage layer from the high concentration source region 303. The parasitic resistance of the low-concentration n ⁺ type first current diffusion layer 322 becomes negligibly small. Therefore, it is possible to further reduce the on-resistance.

<< Manufacturing method of silicon carbide semiconductor device >>
A method for manufacturing a silicon carbide semiconductor device according to the third embodiment will be described with reference to FIGS. 22 (a) and 23 (b). 22 and 23 show an enlarged part of the SiC power MOSFET forming region (element forming region) of the silicon carbide semiconductor device of the present embodiment.

The same applies to the above-described first embodiment and the impurity activation step P3. Next, as shown in FIGS. 22 (a) to 22 (c), a hard mask for trench processing and a mask 325A that also serves as a field oxide film are formed. The mask 325A is formed of, for example, a silicon dioxide (SiO ₂ ) film.

22 (a) is a top view of the main part, FIG. 22 (b) is a cross-sectional view of the main part at the cutting line AA'position of FIG. 22 (a), and FIG. 22 (c) is the cutting line BB'of FIG. 22 (a). It is a cross-sectional view of a main part of a position. The thickness of the mask 325A is, for example, about 0.5 to 3 μm. The mask 325A is provided with an opening portion in the region where the trench 306 is formed in a later step. The difference from the first embodiment is that, as shown in FIG. 22 (c), the opening portion penetrates the n ⁺ type first current diffusion layer 322 and the p ⁺ type first electric field relaxation layer 323 to form an n ⁺⁺ type. It is a point that reaches the high concentration source region 303.

Next, using a dry etching process, the trench 306 penetrates the n ⁺ type first current diffusion layer 322 and the p ⁺ type first electric field relaxation layer 323 and extends to the n ⁺⁺ type high concentration source region 303. Further, it extends to the p ⁺ type body layer 302, the n ⁺ type second current diffusion layer 305, and the p ⁺ type second electric field relaxation layer 319.

The depth of the formed trench is shallower than the depth of the p ⁺ type body layer 302. The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length X (trench length) in the direction parallel to the channel length direction of the trench is, for example, about 1 to 4 μm. The length Y1 (trench width) in the direction parallel to the channel width direction parallel to the substrate of the trench is, for example, about 0.1 to 2 μm. The trench spacing Y2 in the direction parallel to the channel width direction parallel to the substrate is, for example, about 0.1 to 2 μm.

The remaining steps are the same as those in the first embodiment described above, and by performing the remaining steps, FIGS. 23 (a) and 22 (a) corresponding to the cutting line AA'position in FIG. 22 (a). The third embodiment shown in the cross-sectional view of the main part of FIG. 23 (b) corresponding to the position of the cutting line BB'is completed.

As described above, according to the third embodiment, it is possible to reduce the variation in channel length and shorten the channel as compared with the structure in Patent Document 4, as in the first embodiment. Further, since the upper edge of the trench on the source side is the p ⁺ type first electric field relaxation layer 323, even if the electric field is concentrated on the upper edge of the trench when it is turned on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, there is no variation in performance between chips in the power module, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, the problem of erroneous arcs that occur during switching does not occur. In addition, as shown in FIG. 23 (b), since the trench 306 reaches the n ⁺⁺ type high concentration source region 303, the concentration is lower than that of the high concentration source region 303 when the SiC power MISFET is on. The surface of the n ⁺ type first current diffusion layer 322 becomes an accumulation layer, and the parasitic resistance of the n ⁺ type first current diffusion layer 322 becomes negligibly small. Therefore, it is possible to provide a higher performance silicon carbide semiconductor device.

The semiconductor device having the SiC power MISFET described in the above-described first to third embodiments can be used as the power conversion device. The power conversion device according to the fourth embodiment will be described with reference to FIG. 24. FIG. 24 is a circuit diagram showing an example of the power conversion device (inverter) according to the fourth embodiment.

As shown in FIG. 24, the inverter 802 has a SiC power MISFET 804 which is a switching element and a diode 805. In each single phase, the SiC power MISFET 804 and the diode 805 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of the load (for example, motor) 801 (upper arm), and the input potential of the load 801 The SiC power MISFET element 804 and the diode 805 are also connected in antiparallel to the ground potential (GND) (lower arm). That is, in the load 801 each single phase is provided with two SiC power MISFETs 804 and two diodes 805, and three phases are provided with six switching elements 804 and six diodes 805. A control circuit 803 is connected to the gate electrode of each SiC power MISFET 804, and the SiC power MISFET 804 is controlled by this control circuit 803. Therefore, the load 801 can be driven by controlling the current flowing through the SiC power MISFET 804 constituting the inverter 802 with the control circuit 803.

The functions of the SiC power MISFET 804 constituting the inverter 802 will be described below. In order to control and drive the load 801 for example, the motor needs to input a sine wave of a desired voltage to the load 801. The control circuit 803 controls the SiC power MISFET 804 and performs a pulse width modulation operation that dynamically changes the pulse width of the rectangular wave. The output square wave is smoothed by passing through the inductor to become a pseudo-desired sine wave. The SiC power MISFET 804 has a function of creating a rectangular wave for performing this pulse width modulation operation.

As described above, according to the fourth embodiment, by using the semiconductor device described in the above-described first to third embodiments for the SiC power MISFET 804, for example, the SiC power MISFET 804 has a higher performance and is an inverter. It is possible to improve the performance of such power conversion devices. Further, since the SiC power MISFET 804 has long-term reliability, the years of use of a power conversion device such as an inverter can be extended.

Further, as the power conversion device, a three-phase motor system can be used. The load 801 shown in FIG. 24 described above is a three-phase motor, and by using a power conversion device provided with the semiconductor device described in the first to third embodiments described above for the inverter 802, the three-phase motor is used. It is possible to improve the performance of the system and extend the number of years of use.

The semiconductor device having the SiC power MISFET described in the above-described first to third embodiments can be used as a power conversion device. The power conversion device according to the fifth embodiment will be described with reference to FIG. 25. FIG. 25 is a circuit diagram showing an example of a power conversion device (inverter) according to the fifth embodiment.

As shown in FIG. 25, the inverter 902 has a SiC power MISFET 904 which is a switching element. In each single phase, a SiC power MISFET 904 is connected between the power supply voltage (Vcc) and the input potential of the load (eg, motor) 901 (upper arm), and the input potential of the load 901 and the ground potential (GND). A SiC power MISFET element 904 is also connected between them (lower arm). That is, in the load 901, two SiC power MISFETs 904 are provided in each single phase, and six switching elements 904 are provided in three phases. A control circuit 903 is connected to the gate electrode of each SiC power MISFET 904, and the SiC power MISFET 904 is controlled by this control circuit 903. Therefore, the load 901 can be driven by controlling the current flowing through the SiC power MISFET 904 constituting the inverter 902 with the control circuit 903.

The functions of the SiC power MISFET 904 constituting the inverter 902 will be described below. Also in this embodiment, as one of the functions of the SiC power MISFET, it has a function of creating a rectangular wave for performing a pulse width modulation operation as in the fourth embodiment. Further, in the present embodiment, the SiC power MISFET also plays the role of the diode 805 of the fourth embodiment. In the inverter 902, when the load 901 includes an inductance as in a motor, for example, when the SiC power MISFET 904 is turned off, the energy stored in the inductance must be released (reflux current). In the fourth embodiment, the diode 805 plays this role. On the other hand, in the fifth embodiment, the SiC power MISFET 904 plays this role. That is, synchronous rectification drive is used. Here, the synchronous rectification drive is a method of turning on the gate of the SiC power MISFET 904 at the time of reflux to reverse-conduct the SiC power MISFET 904.

Therefore, the conduction loss at reflux is determined not by the characteristics of the diode but by the characteristics of the SiC power MISFET 904. Further, when the synchronous rectification drive is performed, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiC power MISFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiC power MISFET 904 is driven. However, SiC has a shorter carrier mileage than Si, and the loss during non-operation time is small. For example, it is equivalent to the case where the diode 805 of the fourth embodiment is a SiC Schottky barrier diode.

As described above, according to the fifth embodiment, by using the semiconductor device described in the above-described first to third embodiments for the SiC power MISFET 904, for example, the SiC power MISFET 904 has a high performance and is refluxed. The loss of time can also be reduced. Moreover, since a diode is not used, a power conversion device such as an inverter can be miniaturized. Further, since the SiC power MISFET 904 has long-term reliability, the years of use of a power conversion device such as an inverter can be extended.

Further, the power conversion device can be used for a three-phase motor system. The load 901 shown in FIG. 25 described above is a three-phase motor, and by using a power conversion device provided with the semiconductor device described in the first to third embodiments described above for the inverter 902, the three-phase motor is used. It is possible to improve the performance of the system and extend the number of years of use.

The three-phase motor system described in the above-described fourth embodiment or the above-mentioned embodiment 5 can be used for automobiles such as hybrid automobiles, electric vehicles, and fuel cell vehicles. The automobile using the three-phase motor system according to the sixth embodiment will be described with reference to FIGS. 26 and 27. FIG. 26 is a schematic diagram showing an example of the configuration of the electric vehicle according to the sixth embodiment, and FIG. 27 is a circuit diagram showing an example of the boost converter according to the sixth embodiment.

As shown in FIG. 26, the electric vehicle has a three-phase motor 1003 capable of inputting and outputting power to a drive shaft 1002 to which the drive wheels 1001a and the drive wheels 1001b are connected, and an inverter 1004 for driving the three-phase motor 1003. And a battery 1005. Further, the electric vehicle includes a boost converter 1008, a relay 1009, and an electronic control unit 1010, and the boost converter 1008 includes a power line 1006 to which the inverter 1004 is connected and a power line 1007 to which the battery 1005 is connected. Is connected to.

The three-phase motor 1003 is a synchronous generator motor including a rotor in which a permanent magnet is embedded and a stator in which a three-phase coil is wound. As the inverter 1004, the inverter described in the above-described fourth embodiment or the above-mentioned embodiment 5 can be used.

As shown in FIG. 27, the boost converter 1008 has a configuration in which a reactor 1011 and a smoothing capacitor 1012 are connected to an inverter 1013. The inverter 1013 is, for example, the same as the inverter described in the above-described fifth embodiment, and the element configuration in the inverter is also the same. In the sixth embodiment, for example, it is shown by a diagram composed of the SiC power MISFET 1014 as in the fifth embodiment.

The electronic control unit 1010 of FIG. 26 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor that detects the rotor position of the three-phase motor 1003, a charge / discharge value of the battery 1005, and the like. Receive. Then, a signal for controlling the inverter 1004, the boost converter 1008, and the relay 1009 is output.

As described above, according to the sixth embodiment, the power conversion device described in the above-described fourth embodiment and the above-mentioned embodiment 5 can be used for the inverter 1004 and the boost converter 1008, which are the power conversion devices. Further, the three-phase motor system described in the above-described fourth embodiment or the above-mentioned embodiment 5 can be used for the three-phase motor system including the three-phase motor 1003 and the inverter 1004. This makes it possible to save energy, size, weight, and space for electric vehicles.

Although the electric vehicle has been described in the sixth embodiment, the three-phase motor system of each of the above-described embodiments is similarly applied to the hybrid vehicle in which the engine is also used and the fuel cell vehicle in which the battery 1005 is a fuel cell stack. Can be applied.

The three-phase motor system described in the above-described 4th embodiment and the above-mentioned 5th embodiment can be used for a railway vehicle. A railway vehicle using the three-phase motor system according to the seventh embodiment will be described with reference to FIG. 28. FIG. 28 is a circuit diagram showing an example of a converter and an inverter provided in a railway vehicle according to the seventh embodiment.

As shown in FIG. 28, electric power is supplied to the railroad vehicle from the overhead line OW (for example, 25 kV) via the pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 1109 and converted from alternating current to direct current by the converter 1107. Further, it is converted from direct current to alternating current by the inverter 1102 via the capacitor 1108 to drive the three-phase motor which is the load 1101. The element configuration in the converter 1107 may be a combination of a SiC power MISFET and a diode as in the fourth embodiment described above, or a single SiC power MISFET as in the fifth embodiment described above. In the seventh embodiment, for example, the figure configured by the SiC power MISFET 1104 as in the fifth embodiment is shown. In FIG. 28, the control circuit described in the above-described fourth embodiment or the above-mentioned embodiment 5 is omitted. Further, in the figure, the reference numeral RT indicates a railroad track, and the reference numeral WH indicates a wheel.

As described above, according to the seventh embodiment, the power conversion device described in the above-described fourth embodiment or the above-mentioned embodiment 5 can be used for the converter 1107. Further, as the three-phase motor system including the load 1101, the inverter 1102, and the control circuit, the three-phase motor system described in the above-described fourth embodiment or the above-mentioned embodiment 5 can be used. As a result, it is possible to save energy in railway vehicles, and to reduce the size and weight of underfloor parts.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

For example, the material, conductive type, manufacturing conditions, etc. of each part are not limited to the description of the above-described embodiment, and it goes without saying that many modifications are possible for each. Here, for convenience of explanation, the conductive type of the semiconductor substrate and the semiconductor film has been fixed and described, but the present invention is not limited to the conductive type described in the above-described embodiment.

1: Semiconductor chip 2: Source wiring electrode (SiC power MISFET forming area, element forming area) 3: p-type floating field limiting ring, 4: n ⁺⁺ type guard ring, 5: Gate opening Unit, 6: SiC power MISFET, 7: source opening, 8: gate wiring electrode, 101, 201, 301: n ^- type epitaxial layer, 102, 202, 302: p ⁺ type body layer, 103, 203. , 303: n ⁺⁺ type source region, 122,222,322: n ⁺ type first current diffusion layer, 123,223,323: p ⁺ type first electric circuit relaxation layer, 119,219,319: p ⁺ Type 2 second electric circuit relaxation layer, 105,205,305: n ⁺ type second current diffusion layer, 124,224,324: n ^- type JFET region, 106,206,306: Trench, 107,207,307 : N ⁺ type SiC substrate, 108, 208, 308: n ⁺ type drain region, 109, 209, 309: p ⁺⁺ type body layer potential fixing region, 110, 210, 310: Gate insulating film, 111, 211 , 311: Gate electrode, 112,212,312: Capacitor insulating film, 113,213,313: Metal silicide layer, 114,214,314: Third metal film, 115,215,315: Metal silicide layer, 116,216 , 316: Drain wiring electrode, 801: Load, 802: Inverter, 803: Control circuit, 804: SiCMISFET, 805: Diode, 901: Load, 902: Inverter, 903: Control circuit, 904: SiCMISFET, 905 :, 1001a , 1001b: Drive wheel, 1002: Drive shaft, 1003: 3-phase motor, 1004: Inverter, 1005: Battery, 1006: Power line, 1007: Power line, 1008: Boost converter, 1009: Relay, 1010: Electronic control unit, 1011: Reactor, 1012: Capacitor for smoothing, 1013: Inverter, 1014: SiCMISFET, 1101: Load, 1102: Inverter, 1104: SiCMISFET, 1107: Converter, 1108: Capacitor, 1109: Transformer, OW: Overhead wire OW, RT: Line , WH: Wheel, Vcc: Power supply voltage, GND: Ground potential.

Claims (16)

A first conductive type semiconductor substrate having a first impurity concentration and
The back electrode formed on the back side of the semiconductor substrate and
The first region of the first conductive type having a second impurity concentration lower than the first impurity concentration formed on the semiconductor substrate,
The second region of the second conductive type, which is formed in the first region of the first conductive type and is formed on the surface side of the semiconductor substrate, which is opposite to the first conductive type.
It is sandwiched between a plurality of adjacent second regions, and the first conductive type third region and
The fourth region of the first conductive type formed in the second region of the second conductive type, and the fourth region of the first conductive type.
Adjacent to the fourth region of the first conductive type, electrically connected to the fifth region of the first conductive type having a lower concentration than the fourth region of the first conductive type,
A sixth region of the first conductive type, which is electrically connected to the third region and has a concentration equal to that of the fifth region of the first conductive type.
A trench extending to the fifth region, the second region, and the sixth region, shallower than the second region, and having a bottom surface in contact with the second region.
The gate insulating film formed on the inner wall of the trench and
A semiconductor device having a gate electrode formed on the gate insulating film. In the semiconductor device according to claim 1,
A seventh region of the second conductive type formed on the fifth region of the first conductive type and electrically connected to the second region of the second conductive type.
The eighth region of the second conductive type, which is formed on the sixth region of the first conductive type, is electrically connected to the second region of the second conductive type, and has the same concentration as the seventh region. Further, a semiconductor device characterized by having. In the semiconductor device according to claim 1,
The impurity concentration in the fourth region of the first conductive type is in the range of 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 .
The impurity concentration in the fifth region of the first conductive type and the sixth region of the first conductive type are equal, and the impurity concentration is in the range of 5 × 10 ¹⁶ cm ^-3 to 5 × 10 ¹⁸ cm ^-3 . A featured semiconductor device. In the semiconductor device according to claim 2,
The 7th region of the 2nd conductive type and the 8th region of the 2nd conductive type have the same impurity concentration, and the impurity concentration is in the range of 1 × 10 ¹⁷ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 . A semiconductor device characterized by. The first conductive type silicon carbide semiconductor substrate on which the first conductive type epitaxial layer is formed is prepared.
A second conductive type body layer opposite to the first conductive type is formed in the epitaxial layer.
The first conductive type JFET region sandwiched between a plurality of adjacent body layers is formed.
The source region of the first conductive type is formed in the body layer of the second conductive type, and the source region is formed.
Adjacent to the first conductive type source region and electrically connected to form the first conductive type first current diffusion layer at a lower concentration than the first conductive type source region.
It is electrically connected to the JFET region, and the first conductive type first current diffusion layer and the first conductive type second current diffusion layer are formed by using one mask.
A trench that is shallower than the body layer, has a bottom surface in contact with the body layer, and has side surfaces in contact with the first current diffusion layer, the body layer, and the second current diffusion layer, and extends.
An insulating film is formed on the inner wall of the trench to form an insulating film.
A method for manufacturing a semiconductor device, which comprises forming a gate electrode on the insulating film. In the method for manufacturing a semiconductor device according to claim 5,
In the step of forming the first conductive type first current diffusion layer and the first conductive type second current diffusion layer, the first conductive type impurities are transferred through a resist mask formed by simultaneously exposing with the same photomask. A method for manufacturing a semiconductor device, which comprises a process of implanting ions and forming them at the same time. In the method for manufacturing a semiconductor device according to claim 5,
On the first current diffusion layer of the first conductive type, the first electric field relaxation layer of the second conductive type is formed so as to be electrically connected to the body layer of the second conductive type.
The second conductive type body layer is electrically connected to the second conductive type body layer on the first conductive type second current diffusion layer, and the concentration is equal to that of the first electric field relaxation layer. A method for manufacturing a semiconductor device, which comprises further forming a layer. In the method for manufacturing a semiconductor device according to claim 7,
In the step of forming the second conductive type first electric field relaxation layer and the second conductive type second electric field relaxation layer, the first conductive type impurities are implanted via a resist mask formed by simultaneously exposing with the same photomask. After ion implantation to form the first current diffusion layer and the second current diffusion layer at the same time, the second conductive type impurities are ion-implanted through the resist mask, and the first electric field relaxation layer and the second electric field relaxation layer are simultaneously implanted. A method for manufacturing a semiconductor device, which is a step of forming a second electric field relaxation layer. In the semiconductor device according to claim 2,
The third region of the first conductive type is the ninth region of the first conductive type formed at a concentration higher than the impurity concentration of the first region of the first conductive type.
The eighth region of the second conductive type is formed so as to extend from the sixth region of the first conductive type to the third region of the first conductive type, and is electrically connected to the second region of the second conductive type. A semiconductor device, characterized in that it is a tenth region of the second conductive type, which is specifically connected. In the semiconductor device according to claim 1,
The trench extends to the fourth region in addition to the fifth region, the second region, and the sixth region, is shallower than the second region, and has a bottom surface of the second region. A semiconductor device characterized by being a trench in contact with. In the semiconductor device according to claim 10,
A seventh region of the second conductive type formed on the fifth region of the first conductive type and electrically connected to the second region of the second conductive type.
The eighth region of the second conductive type, which is formed on the sixth region of the first conductive type, is electrically connected to the second region of the second conductive type, and has the same concentration as the seventh region. Further, a semiconductor device characterized by having. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the material of the semiconductor substrate is silicon carbide. A power conversion device having the semiconductor device according to claim 1 as a switching element. A three-phase motor system for driving a three-phase motor by converting DC power into AC power with the power conversion device according to claim 13. An automobile in which wheels are driven by the three-phase motor system according to claim 14. A railway vehicle in which wheels are driven by the three-phase motor system according to claim 14.

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