JP2015032813A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which has high withstand voltage and supports a high threshold voltage and low on-resistance at the same time.SOLUTION: A silicon carbide semiconductor device comprises trenches TR on a second principal surface P2 of a silicon carbide layer 101. Each trench TR has a first sidewall part SW1 on which a second layer 82 and a third layer 83 are exposed and a bottom part BT which continues to the first sidewall part SW1 and lies in the second layer 82. The silicon carbide semiconductor device further comprises: a gate insulation film 91 which covers the first sidewall part SW1 and the bottom part BT; and a gate electrode 92 provided on the gate insulation film 91.

Description

  The present invention relates to a silicon carbide semiconductor device.

  Silicon carbide semiconductor devices have many advantages such as low power loss and high-temperature operation compared to silicon semiconductor devices that are currently mainstream, and are expected as next-generation power semiconductor devices. Yes. At present, various approaches have been made in view of the structure of the device in order to further improve the performance of the silicon carbide semiconductor device (see, for example, Patent Document 1).

International Publication No. 2002/029900

  The planar structure is one of the most basic structures and is widely used. In the planar structure, the channel region is formed in parallel to the semiconductor substrate. Although this structure is suitable for increasing the breakdown voltage, there is a parasitic resistance called a JFET (Junction Field Effect Transistor) resistance, which makes it difficult to reduce the on-resistance.

  On the other hand, since the trench gate structure does not include a JFET resistance component, it is suitable for low on-resistance. However, in the trench gate structure, dielectric breakdown of the gate insulating film is likely to occur at the bottom of the trench, and it is difficult to increase the breakdown voltage.

  In addition, since a power semiconductor device handles a large current, it is required to be a normally-off type having a high threshold voltage and capable of interrupting a current without applying a gate voltage from the viewpoint of reducing power loss. However, a high threshold voltage and a low on-resistance are generally in a trade-off relationship, and it is not easy to achieve both of them.

  Various techniques have been proposed to deal with such problems. For example, in International Publication No. 2002/029900 (Patent Document 1), in a silicon carbide semiconductor device having a planar structure, by providing an n-type storage channel, a channel resistance component is reduced and a low on-resistance is achieved. ing.

  Since the semiconductor device disclosed in Patent Document 1 has a planar structure, it can have a relatively high breakdown voltage. However, the n-type storage channel used in Patent Document 1 has a problem that the threshold voltage is lower than when a p-type semiconductor is used as the channel. In the planar structure, it is also difficult to adjust the threshold voltage by controlling the channel length due to restrictions on the device size in the planar direction. On the other hand, in this structure, if the channel length is shortened in order to reduce the on-resistance, the threshold voltage is drastically lowered due to the short channel effect, and in some cases, there is a problem that punch-through is caused. That is, with this structure, it is extremely difficult to achieve both a high threshold voltage and a low on-resistance while having a high breakdown voltage.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a silicon carbide semiconductor device that has a high breakdown voltage and has both a high threshold voltage and a low on-resistance. is there.

  A silicon carbide semiconductor device of the present invention includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface.

  Here, the silicon carbide layer has a first layer that constitutes the first main surface and has the first conductivity type, and a second conductivity type that is provided in the first layer and is different from the first conductivity type. And a third layer provided in at least the second layer and constituting a part of the second main surface and having the first conductivity type.

  The second main surface of the silicon carbide layer is provided with a trench, and the trench is connected to the first side wall and the first side wall where the second layer and the third layer are exposed. The silicon carbide semiconductor device further comprising: a gate insulating film covering each of the first side wall and the bottom; a gate electrode provided on the gate insulating film; Is provided.

  The silicon carbide semiconductor device of the present invention has a high breakdown voltage and can achieve both a high threshold voltage and a low on-resistance.

FIG. 1 schematically shows an example of a configuration of a silicon carbide semiconductor device in an embodiment of the present invention, and is a partial cross-sectional view taken along line II in FIG. FIG. 2 is a partial plan view schematically showing a shape of a silicon carbide layer included in the silicon carbide semiconductor device of FIG. 1. It is a flowchart which shows the outline of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in embodiment of this invention. It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in embodiment of this invention. It is a figure which shows one modification of the cross-sectional shape of the trench in embodiment of this invention. It is a figure which shows the other modification of the cross-sectional shape of the trench in embodiment of this invention. FIG. 4 is a partial cross sectional view schematically showing a third step (step 3) in the manufacturing process of the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a fourth step (step 4) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. FIG. 7 is a partial cross sectional view schematically showing a fifth step (step 5) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. FIG. 8 is a partial cross sectional view schematically showing a sixth step (step 6) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. It is a fragmentary sectional view showing roughly the fine structure of the surface of a silicon carbide layer which a silicon carbide semiconductor device has. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line XVIII-XVIII of FIG. It is a figure which shows the crystal structure in the surface vicinity of the composite surface of FIG. It is the figure which looked at the compound surface of Drawing 11 from the (01-10) plane. FIG. 5 is a graph showing an example of the relationship between the angle between the channel plane and the (000-1) plane viewed macroscopically and the channel mobility when thermal etching is performed and when it is not performed. It is. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG. It is a graph which shows an example of the relationship between channel length, a threshold voltage, and characteristic ON resistance. It is a graph which shows another example of the relationship between channel length, a threshold voltage, and characteristic ON resistance.

  Hereinafter, embodiments according to the present invention will be described in more detail. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane {}. In addition, a negative crystallographic index is usually expressed by adding “-” (bar) above a number, but in this specification, a negative sign is added before the number. It shall be expressed by

[Description of Embodiment of Present Invention]
First, an outline of an embodiment of the present invention (hereinafter also referred to as “the present embodiment”) will be described in the following (1) to (7).

  The present inventor conducted intensive studies to solve the above-mentioned problems, and found a novel device structure that combines the advantages of the planar structure and the trench gate structure. That is, the silicon carbide semiconductor device according to the present embodiment has the following configuration.

  (1) Silicon carbide semiconductor device 201 of the present embodiment includes a silicon carbide layer 101 having a first main surface P1 and a second main surface P2 opposite to the first main surface P1.

  Here, the silicon carbide layer 101 includes a first layer 81 constituting the first main surface P1 and having the first conductivity type, and a second layer provided in the first layer 81 and different from the first conductivity type. A second layer 82 having the first conductivity type, and a third layer 83 provided in at least the second layer 82 and constituting a part of the second main surface P2 and having the first conductivity type. .

  The second main surface P2 of the silicon carbide layer 101 is provided with a trench TR, and the trench TR has a first side wall portion SW1 where the second layer 82 and the third layer 83 are exposed, and the second side surface SW1. A silicon nitride semiconductor device 201 having a bottom portion BT connected to one side wall portion SW1 and positioned in the second layer 82, and a silicon carbide semiconductor device 201 covering each of the first side wall portion SW1 and the bottom portion BT; A gate electrode 92 provided on the gate insulating film 91.

  According to silicon carbide semiconductor device 201, since bottom BT of trench TR is located in second layer 82, a strong electric field is not applied to gate insulating film 91, and a high breakdown voltage can be exhibited. Similarly to the semiconductor device having the trench gate structure, the channel region CH is formed along the side wall of the trench TR. Therefore, the device can be easily miniaturized and the on-resistance can be reduced. Further, since the influence of the channel length on the device size is small as compared with a normal planar structure, a sufficient channel length can be ensured. Therefore, it can have a high threshold voltage. Thus, according to silicon carbide semiconductor device 201, it is possible to realize a silicon carbide semiconductor device having a high breakdown voltage and having both a high threshold voltage and a low on-resistance.

  (2) It is preferable that the surface including the first surface S1 having the plane orientation {0-33-8} is provided in a portion where the second layer 82 is exposed in the first sidewall portion SW1. .

  In order to further increase the threshold voltage, it is conceivable to increase the impurity concentration in the second layer 82 constituting the channel region CH. However, usually, when the impurity concentration in the second layer 82 is increased, the scattering of impurities due to the increase in dopant becomes significant, so that the channel mobility is greatly reduced and the on-resistance is increased. However, the portion of the first sidewall portion SW1 where the second layer 82 is exposed includes the first surface S1 having the plane orientation {0-33-8}, so that the impurity concentration in the second layer 82 is increased. Even if the channel height is increased, the channel mobility is not greatly decreased. Therefore, by adopting such a configuration, it is possible to achieve both high threshold voltage and low on-resistance at a high level.

  (3) The cross-sectional shape of the trench TR is preferably V-shaped. Conventionally, when the cross-sectional shape of the trench TR is V-shaped, the gate insulating film 91 protrudes greatly at the bottom portion BT, so that the electric field is easily concentrated on the portion, and the withstand voltage is reduced. However, according to silicon carbide semiconductor device 201, bottom portion BT is located in second layer 82, and the electric field does not concentrate, so that the withstand voltage does not decrease even when the shape is V-shaped. Then, by adopting the V shape, the first surface S1 having the aforementioned plane orientation {0-33-8} can be easily included in the first sidewall portion SW1 of the trench TR. That is, high threshold voltage and low on-resistance can be achieved at a high level.

  (4) The trench TR has a second side wall part SW2 that is disposed opposite to the first side wall part SW1 and that is continuous with the bottom part BT. In the second side wall part SW2, the second layer 82 and the third side wall part SW2 are arranged. It is preferable that the layer 83 is exposed.

  In this configuration, the channel region CH is formed along the first sidewall portion SW1, the bottom portion BT, and the second sidewall portion SW2. As a result, the channel length is determined substantially depending on the cross-sectional shape of the trench TR, so that the control of the channel length is facilitated and the variation in the channel length is remarkably reduced.

  (5) When a voltage is applied to the gate electrode 92, the region including the second layer 82 and the bottom portion BT exposed at least in the first side wall portion SW1 of the trench TR becomes the channel region CH, and the channel of the channel region CH The length is preferably 0.6 μm or more.

  By setting the channel length to 0.6 μm or more, the threshold voltage can be further shifted to the positive side, and silicon carbide semiconductor device 201 can be made a stable normally-off type.

(6) The impurity concentration in the second layer 82 is preferably 5 × 10 ¹⁶ cm ⁻³ or more. As described above, in the present embodiment, the first sidewall portion SW1 can include the first surface S1 having the plane orientation {0-33-8}, so that the impurity concentration in the second layer 82 is ^Can be made as high as 5 × 10 ¹⁶ cm ⁻³ or more. Thereby, the threshold voltage can be further increased.

  (7) It is preferable that the first conductivity type is n-type and the second conductivity type is p-type. Thereby, since the channel region CH formed in the second layer 82 can be a p-type semiconductor, the threshold voltage can be further increased.

[Details of the embodiment of the present invention]
Hereinafter, although the silicon carbide semiconductor device which concerns on this Embodiment is demonstrated in detail, this invention is not limited to these.

<Silicon carbide semiconductor device>
A silicon carbide semiconductor device 201 according to the embodiment shown in FIG. 1 is configured as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 201 includes single crystal substrate 80, silicon carbide layer 101 (epitaxial layer), gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring layer 95, drain And an electrode 98. Single crystal substrate 80 is made of silicon carbide and has an n-type (first conductivity type). Silicon carbide layer 101 is provided on single crystal substrate 80.

  Silicon carbide layer 101 is a silicon carbide layer epitaxially grown on single crystal substrate 80. Silicon carbide layer 101 has a polytype 4H hexagonal crystal structure. By adopting such a crystal structure, the on-resistance of silicon carbide semiconductor device 201 can be lowered. Silicon carbide layer 101 has a lower surface P1 (first main surface) facing single crystal substrate 80 and an upper surface P2 (second main surface) opposite to lower surface P1. Silicon carbide layer 101 has n drift layer 81 (first layer), p body layer 82 (second layer), n + layer 83 (third layer), and p contact region 84.

N drift layer 81 has n type. N drift layer 81 constitutes lower surface P <b> 1 of silicon carbide layer 101. The impurity concentration of n drift layer 81 is preferably lower than the impurity concentration of single crystal substrate 80. Here, the impurity concentration of the n drift layer 81 is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less.

P body layer 82 has p type (second conductivity type different from the first conductivity type). P body layer 82 is provided in n drift layer 81. The impurity concentration of p body layer 82 is preferably 5 × 10 ¹⁶ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less.

  N + layer 83 has n-type. N + layer 83 is provided in n drift layer 81 and p body layer 82, and constitutes upper surface P <b> 2 of silicon carbide layer 101 together with p contact region 84. That is, n + layer 83 is formed so as to extend from within p body layer 82 to n drift layer 81, and constitutes a part of the upper surface of silicon carbide layer 101.

  Trench TR is provided on upper surface P2 of silicon carbide layer 101. Trench TR is formed in a hexagonal shape so as to surround part of p contact region 84 and n + layer 83 in plan view (FIG. 2). Trench TR has a first side wall part SW1, a bottom part BT continuous with first side wall part SW1, and a second side wall part SW2 arranged opposite to first side wall part SW1 and continuous with bottom part BT. ing. A p body layer 82 and an n + layer 83 are exposed on the first sidewall portion SW1 and the second sidewall portion SW2, respectively. Further, bottom portion BT is located in p body layer 82. In the present specification, the first side wall portion SW1 and the second side wall portion SW2 may be collectively referred to simply as “side wall portion SW”. That is, the “side wall part SW” indicates at least one of the first side wall part SW1 and the second side wall part SW2.

  Gate insulating film 91 is formed on trench TR and covers each of first sidewall portion SW1, bottom portion BT, and second sidewall portion SW2 of trench TR. The gate insulating film 91 is preferably a silicon oxide film. A gate electrode 92 is provided on the gate insulating film 91. The interlayer insulating film 93 is provided on the gate electrode 92 and insulates between the gate electrode 92 and the source electrode 94. The source wiring layer 95 is in contact with the interlayer insulating film 93 and the source electrode 94. Source wiring layer 95 is, for example, an aluminum layer. Drain electrode 98 is provided on lower surface P <b> 1 of silicon carbide layer 101 via single crystal substrate 80.

  In silicon carbide semiconductor device 201 having the above configuration, bottom portion BT of trench TR is located in p body layer 82. Therefore, a strong electric field is not applied to the gate insulating film 91 and an extremely high breakdown voltage can be realized.

  Silicon carbide semiconductor device 201 has JFET region 85 sandwiched between a pair of p body layers 82 in n drift layer 81. JFET region 85 is a part of n drift layer 81 and has n type conductivity. In the present embodiment, JFET region 85 preferably has a higher impurity concentration than n drift layer 81. The impurity concentration of JFET region 85 can be made higher than the portion of n drift layer 81 excluding JFET region 85 by ion-implanting n-type impurities into n drift layer 81, for example. More preferably, JFET region 85 has a lower impurity concentration than n + layer 83.

  In a normal planar structure, the impurity concentration in the JFET region is set low in order to ensure the breakdown voltage of the device. Therefore, the on-resistance of the device must be high. On the other hand, in silicon carbide semiconductor device 201, since bottom BT of trench TR is located in p body layer 82, a sufficient breakdown voltage is ensured, so that the impurity concentration of JFET region 85 can be increased. Further, the on-resistance of the semiconductor device can be further reduced.

  That is, silicon carbide semiconductor device 201 of the present embodiment includes a JFET region 85 having a first conductivity type sandwiched between a pair of second layers 82 in first layer 81, The impurity concentration is preferably higher than that of the first layer 81.

  Further, the region including the portion of the p body layer 82 exposed on the first side wall portion SW1, the portion of the p body layer 82 exposed on the second side wall portion SW2, and the bottom portion BT has a gate voltage applied to the gate electrode 92. Is applied, the channel region CH is formed. That is, the channel region CH is formed so as to reach the second side wall portion SW2 from the first side wall portion SW1 of the trench TR through the bottom portion BT. That is, the channel region CH is formed so that the n + layer 83 and the n drift layer 81 connected to the first sidewall portion SW1 can be electrically connected. Thus, in this embodiment, since the channel region CH is formed in the vertical direction of the device, the device can be easily miniaturized and the on-resistance can be reduced. In this structure, the channel length can be easily controlled mainly by the depth of the trench TR and the inclination angle of the side wall portion SW. Therefore, a high threshold voltage can be obtained by controlling the channel length.

  As shown in FIG. 1, in silicon carbide semiconductor device 201, trench TR has a V-shaped cross section. The V shape is preferable because the manufacturing process can be simplified. Here, the cross-sectional shape of trench TR is not limited to the V shape, and may be, for example, a trapezoidal shape as shown in FIG. 5 or a rectangular shape as shown in FIG. However, it is preferable that first sidewall portion SW1 and second sidewall portion SW2 of trench TR are inclined with respect to upper surface P2 of silicon carbide layer 101. By tilting the side wall of the trench TR, when the channel length is reduced, the short channel effect appears moderately, and a low on-resistance can be achieved while maintaining a high threshold voltage.

  Here, the short channel effect is manifested mainly when a depletion layer due to a pn junction extends to the channel region CH. In general, to suppress the short channel effect, it is effective to increase the impurity concentration of the channel region CH to suppress the spread of the depletion layer. Therefore, when the p-type semiconductor layer is used for the channel region CH, the number of acceptors (Np) in the p-type semiconductor layer is increased with respect to the number of donors (Nn) in the n-type semiconductor layer (that is, Np / Nn is increased). It is effective. In silicon carbide semiconductor device 201, a part of n + layer 83 and p body layer 82 is removed to form trench TR that opens in a tapered shape toward upper surface P2. Therefore, a larger volume is removed from n + layer 83 than p body layer 82 by forming trench TR. As a result, the value obtained by dividing Np by Nn (Np / Nn) can be increased as compared to before formation of the trench TR. Therefore, the short channel effect can be suppressed by providing a trench in which side wall part SW is inclined like silicon carbide semiconductor device 201.

Here, the inclination of the side wall SW in the trench TR is preferably in the following manner. In other words, the plane orientation of the side wall SW is preferably inclined by 50 ° or more and 65 ° or less with respect to the {0001} plane, and is inclined by 50 ° or more and 65 ° or less with respect to the (000-1) plane. It is preferable. By forming the channel region CH in the sidewall portion SW having such an inclination, the channel mobility does not decrease even if the impurity concentration in the p body layer 82 constituting the channel region CH is increased. Therefore, the impurity concentration of p body layer 82 can be increased, and thus a high threshold voltage can be obtained. Here, the impurity concentration in the p body layer 82 is preferably 5 × 10 ¹⁶ cm ⁻³ or more. When the impurity concentration is 5 × 10 ¹⁶ cm ⁻³ or more, the semiconductor device can be brought close to a normally-off type. From the viewpoint of a more stable normally-off type, the impurity concentration in the p body layer 82 is more preferably 1 × 10 ¹⁷ cm ⁻³ or more, and particularly preferably 5 × 10 ¹⁷ cm ⁻³ or more. More preferably, it is 1 × 10 ¹⁸ cm ⁻³ or more.

≪Special surface≫
When sidewall portion SW is inclined with respect to upper surface P2, sidewall portion SW preferably has a predetermined crystal plane (hereinafter referred to as “special plane”), particularly in a portion on p body layer 82. . The p body layer 82 exposed on the side wall portion SW constituting the channel region CH has a special surface, so that the channel resistance component of the on-resistance of the semiconductor device is reduced. That is, the on-resistance of the semiconductor device can be reduced.

  As shown in FIG. 11, the side wall part SW provided with the special surface includes a surface S1 (first surface) having a surface orientation {0-33-8}. In other words, the p body layer 82 of the sidewall portion SW of the trench TR is provided with a surface including the surface S1. The plane S1 preferably has a plane orientation (0-33-8).

  More preferably, the side wall part SW microscopically includes a surface S1, and the side wall part SW microscopically includes a surface S2 (second surface) having a surface orientation {0-11-1}. . Here, “microscopic” means “detailed to such an extent that at least a dimension of about twice the atomic spacing is taken into consideration”. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used. The plane S2 preferably has a plane orientation (0-11-1).

  Further, preferably, the surface S1 and the surface S2 in the side wall portion SW constitute a composite surface SR having a surface orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. Thus, as a macroscopic off angle measurement method, for example, a method using general X-ray diffraction can be cited. Moreover, it is preferable that the composite surface SR has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the (000-1) plane.

  Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface (that is, the thickness direction of the MOSFET (vertical direction in FIG. 1 and the like)) is along the direction in which the above-described periodic repetition is performed. . Next, the detailed structure of the composite surface SR will be described.

  Generally, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 12, Si atoms (or C atoms) are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 13, in the (11-20) plane (cross section taken along line XVIII-XVIII in FIG. 12), the atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 13, the (0-11-2) plane is shown so as to pass through the position of the atoms in the B layer. In this case, the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 14, the composite surface SR is alternately provided with a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface.

  As shown in FIG. 15, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 15) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 15) It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

  Next, the relationship between the crystal plane of the sidewall portion SW and the mobility MB of the channel surface will be described with reference to FIG. In the graph of FIG. 16, the horizontal axis indicates the angle D1 (°) between the macroscopic plane orientation of the side wall portion SW having the channel surface and the (000-1) plane, and the vertical axis indicates the mobility MB. The plot group CM corresponds to the case where the side wall SW is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed. A manufacturing method such as thermal etching will be described later.

  The mobility MB in the plot group MC was maximized when the macroscopic plane orientation of the surface of the channel surface was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the microscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) when considering even the atomic level is stochastically increased.

  On the other hand, the mobility MB in the plot group CM is maximized when the macroscopic surface orientation of the channel surface is (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 14 and 15, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is fine. This is probably because the ratio of the visual plane orientation (0-33-8) is increased.

  The mobility MB has orientation dependency on the composite surface SR. In the graph shown in FIG. 17, the horizontal axis indicates the angle D2 (°) between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 (°) of the channel direction CD (FIG. 11) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. It turned out to be preferable.

  As shown in FIG. 18, the sidewall portion SW may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the sidewall portion SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. In this case, the off angle of the side wall portion SW with respect to the {000-1} plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle with respect to the (000-1) plane of the side wall portion SW deviates from 62 ° that is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane. Such a periodic structure can be observed, for example, by TEM or AFM.

  For the reason described above, the surface including the surface S1 (FIG. 11) having the plane orientation {0-33-8} is provided on the p body layer 82 on the first sidewall portion SW1 (FIG. 1) of the trench TR. It is preferable. More preferably, p body layer 82 is provided with a surface including surface S1 (FIG. 11) having a plane orientation {0-33-8} on first sidewall portion SW1 and second sidewall portion SW2. It is suitable. Thereby, of the on-resistance of silicon carbide semiconductor device 201, the resistance of the channel portion formed by p body layer 82 can be reduced. Therefore, even if resistance of n drift layer 81 is larger, it is permissible. Therefore, the impurity concentration of n drift layer 81 can be further reduced. Thereby, it is possible to further increase the breakdown voltage of the silicon carbide semiconductor device.

  This surface may include the surface S1 microscopically, and the surface may further include the surface S2 (FIG. 11) having the surface orientation {0-11-1} microscopically. The surface surfaces S1 and S2 preferably constitute a composite surface SR (FIG. 11) having a surface orientation {0-11-2}. More preferably, this surface has an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane. As a result, the resistance of the channel portion can be further reduced.

≪Channel length≫
The channel length is preferably 0.6 μm or more. Thereby, a silicon carbide semiconductor device can be made into a normally-off type. FIG. 19 shows the threshold voltage and the characteristic on in the weak inversion region when the impurity concentration in the p body layer is fixed to 3 × 10 ¹⁷ cm ⁻³ and the channel length (L _ch ) is changed in the silicon carbide semiconductor device. It is a figure which shows the relationship with resistance (ON resistance x area of a device active region). In FIG. 19, the vertical axis represents the characteristic on-resistance (unit: mΩ · cm ² ), and the horizontal axis represents the threshold voltage (unit: V) in the weak inversion region.

Here, the channel length (L _ch ) in FIG. 19 and FIG. 20 described later is a value obtained from the mask dimension at the time of impurity implantation. The actual channel length (effective channel length) in the semiconductor device is a value obtained by adding 0.2 μm to this L _ch . Thus, the fact that the actual channel length is 0.2 μm longer than the channel length obtained from the mask dimension is confirmed by, for example, observing the carrier distribution near the interface of the pn junction by the SCM (Scanning Capacitance Microscopy) method. be able to.

As shown in FIG. 19, the threshold voltage and the characteristic on-resistance gradually increase as the channel length (L _ch ) increases. When the channel length (L _ch ) is 0.6 μm, the threshold voltage is completely positive. That is, it is a normally-off type. When the channel length (L _ch ) further increases to 0.8 μm and 1.2 μm, the characteristic on-resistance increases rapidly. Therefore, from the viewpoint of achieving both a high threshold voltage and a low on-resistance, the channel length is preferably 1.2 μm or less, and more preferably 0.8 μm or less. That is, the actual channel length in the semiconductor device is preferably 0.8 μm or more and 1.4 μm or less, and more preferably 0.8 μm or more and 1.0 μm or less.

FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 × 10 ¹⁶ cm ⁻³ and the channel length (L _ch ) is changed. FIG. As shown in FIG. 20, also in this case, as the channel length (L _ch ) increases, the threshold voltage and the characteristic on-resistance gradually increase, from the vicinity where the channel length (L _ch ) becomes 0.6 μm. The threshold voltage turns to the positive side, and thereafter the characteristic on-resistance increases rapidly. Therefore, also in this case, in order to make the silicon carbide semiconductor device normally-off type, the channel length (L _ch ) is preferably 0.6 μm or more. From the viewpoint of achieving both a high threshold voltage and a low on-resistance, the channel length is preferably 1.2 μm or less, and more preferably 0.8 μm or less. That is, the actual channel length in the semiconductor device is preferably 0.8 μm or more and 1.4 μm or less, and more preferably 0.8 μm or more and 1.0 μm or less.

Further, comparing FIG. 19 and FIG. 20, when the impurity concentration is low (FIG. 20), the threshold voltage at which the characteristic on-resistance starts to increase more rapidly when the channel length (L _ch ) is increased. Is low. Therefore, in order to achieve both a low on-resistance and a high threshold voltage, the p body layer 82 preferably has a high impurity concentration. However, when the impurity concentration of the p body layer 82 increases, the impurity scattering usually becomes remarkable, the channel mobility decreases, and the on-resistance increases. As described above, in this embodiment, since at least the first sidewall portion SW1 includes a special surface, even if the impurity concentration is increased, the channel mobility does not decrease. Therefore, a high threshold voltage and a low on-resistance are obtained. It is possible to achieve both.

<Method for Manufacturing Silicon Carbide Semiconductor Device>
Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described. FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment. As shown in FIG. 3, the silicon carbide semiconductor device of the present embodiment can be manufactured by executing Step 1 (S1) to Step 7 (S7).

<< Step 1 (S1) >>
In step 1 (S1), a silicon carbide single crystal substrate 80 is prepared.

<< Step 2 (S2) >>
In step 2 (S2), n drift layer 81 is formed by epitaxial growth on single crystal substrate 80 prepared as described above. This epitaxial growth is performed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. be able to. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.

<< Step 3 (S3) >>
In step 3 (S3), p body layer 82, n + layer 83, and p contact region 84 are formed in n drift layer 81 by ion implantation, as shown in FIG. These can be formed by ion implantation into the n drift layer 81, for example. In ion implantation for forming p body layer 82 and p contact region 84, an impurity for imparting p-type, such as aluminum (Al), can be used. In the ion implantation for forming the n + layer 83, an impurity for imparting n-type, such as phosphorus (P), can be used. The depth of the p body layer 82 formed by ion implantation can be about 0.7 to 0.8 μm, for example. At this time, an n-type impurity is implanted into the JFET region 85 sandwiched between the pair of p body layers 82, and the impurity concentration of the JFET region 85 is changed from the portion of the n drift layer 81 excluding the JFET region 85. Can also be higher.

  Further, instead of ion implantation, epitaxial growth may be performed with addition of impurities.

  Next, heat treatment is performed to activate the impurities. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.

<< Step 4 (S4) >>
In step 4 (S4), as shown in FIG. 8, trench TR is formed in upper surface P2. The trench TR having a V-shaped cross section as shown in FIG. 8 can be formed by, for example, heating in an atmosphere containing a reactive gas having at least one halogen atom, that is, thermal etching. .

  The etching location is specified by a mask layer. As the mask layer, for example, a silicon oxide film can be used. The silicon oxide film is preferable because it can be easily formed by thermally oxidizing the upper surface P2.

Here, it is preferable that at least one or more halogen atoms include at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . Further, for example, a mixed gas of chlorine gas and oxygen gas can be used as a reaction gas, and the heat treatment temperature can be set to 700 ° C. or higher and 1000 ° C. or lower.

Further, the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of silicon carbide is about 70 μm / hour, for example. Further, in this case, the mask layer made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide. Thus, a special surface is self-formed on the first sidewall portion SW1 and the second sidewall portion SW2, particularly on the p body layer 82. Note that the mask layer used here can be removed by an arbitrary method such as etching. Moreover, it is preferable to adjust the depth of trench TR so that the channel length of silicon carbide semiconductor device 201 is substantially 0.6 μm or more. The depth of trench TR can be adjusted by, for example, etching time.

Also, as shown in FIG. 6, in order to make the cross-sectional shape of the trench TR rectangular (that is, to form a vertical trench), for example, reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE. Can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used.

  Further, as shown in FIG. 5, in order to make the cross-sectional shape of the trench TR trapezoidal, the above-described thermal etching can be performed once a vertical trench having a rectangular cross-sectional shape is formed. By thermal etching, side wall portion SW of trench TR is selectively etched, and trench TR having a special surface is formed on first side wall portion SW1 and second side wall portion SW2, particularly on p body layer 82.

<< Step 5 (S5) >>
In step 5 (S5), as shown in FIG. 9, gate insulating film 91 is formed so as to cover each of first side wall portion SW1, second side wall portion SW2 and bottom portion BT of trench TR. The gate insulating film 91 can be formed by thermal oxidation, for example.

  After the gate insulating film 91 is formed, NO annealing using nitrogen monoxide (NO) gas as an atmospheric gas may be performed. For example, the temperature profile can be set to a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. As a result, nitrogen atoms are introduced into the interface region between gate insulating film 91 and p body layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. If such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas.

  Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate insulating film 91. The time during which this heating temperature is maintained can be set to about 1 hour, for example. Thereby, the formation of interface states in the interface region between gate insulating film 91 and p body layer 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

<< Step 6 (S6) >>
In step 6 (S6), a gate electrode 92 is formed on the gate insulating film 91 as shown in FIG. Specifically, gate electrode 92 is formed on gate insulating film 91 so as to fill the region inside trench TR with gate insulating film 91 interposed therebetween. The gate electrode 92 can be formed by, for example, forming a conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing) or RIE.

<< Step 7 (S7) >>
In step 7 (S7), a post-process for forming source electrode 94, drain electrode 98, and the like is performed, and silicon carbide semiconductor device 201 shown in FIG. 1 is manufactured. Specifically, an interlayer insulating film 93 is formed on the gate electrode 92 and the gate insulating film 91 so as to cover the exposed surface of the gate electrode 92, and then an opening is formed in the interlayer insulating film 93 and the gate insulating film 91. Etching is performed as shown. As a result, each of n + layer 83 and p contact region 84 is exposed on upper surface P2 from the opening. Next, source electrode 94 in contact with each of n + layer 83 and n contact region 84 is formed on upper surface P2. Then, drain electrode 98 is formed on lower surface P <b> 1 made of n drift layer 81 through single crystal substrate 80.

<Modification>
Next, a modification of the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGS. 4A and 4B.

  Silicon carbide semiconductor device 301 shown in FIG. 4A is different from silicon carbide semiconductor device 201 shown in FIG. 1 in that n + layer 83 is not exposed at second sidewall portion SW2 of trench TR.

  In this configuration, similarly to silicon carbide semiconductor device 201 shown in FIG. 1, channel region CH is formed along side wall portion SW of trench TR, so that the occurrence of the short channel effect is suppressed, and a high threshold voltage and a low threshold voltage are achieved. Both on-resistance and resistance can be achieved. Further, since bottom portion BT of trench TR is located in p body layer 82, the electric field does not concentrate on the portion of gate insulating film 91 covering bottom portion BT of trench TR. Furthermore, since there is no restriction that the second sidewall portion SW2 of the trench TR is formed in the p body layer 82, the p body layer 82 can be made small. That is, the semiconductor device can be further miniaturized while avoiding electric field concentration at the bottom BT of the trench TR.

  In silicon carbide semiconductor device 301 shown in FIG. 4A, n + layer 83 is not exposed at second sidewall portion SW2. In this structure, for example, as in silicon carbide semiconductor device 401 shown in FIG. 4B, the channel length changes when the position where trench TR is formed (the position of bottom portion BT) is shifted in the plane direction of FIG. 4B. In contrast, in silicon carbide semiconductor device 201 shown in FIG. 1, trench TR is formed such that n + layer 83 is exposed on both first sidewall portion SW1 and second sidewall portion SW2. Therefore, the channel length is not affected by the position of trench TR in the planar direction. Therefore, silicon carbide semiconductor device 201 shown in FIG. 1 can be a silicon carbide semiconductor device having extremely small variations in channel length and stable performance.

  Although the embodiments of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the respective embodiments described above.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

80 single crystal substrate 81 n drift layer (first layer)
82 p body layer (second layer)
83 n + layer (third layer)
84 p contact layer 85 JFET region 91 gate insulating film 92 gate electrode 93 interlayer insulating film 94 source electrode 95 source wiring layer 98 drain electrode 101 silicon carbide layers 201, 301, 401 silicon carbide semiconductor device TR trench BT bottom SW side wall SW1 first 1 side wall portion SW2 second side wall portion CD channel direction CH channel region P1 lower surface (first main surface)
P2 upper surface (second main surface)
S1 First surface S2 Second surface SQ, SR Composite surface

Claims (7)

A silicon carbide layer having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide layer includes a first layer constituting the first main surface and having a first conductivity type;
A second layer provided in the first layer and having a second conductivity type different from the first conductivity type;
A third layer provided in at least the second layer and constituting a part of the second main surface and having the first conductivity type,
A trench is provided in the second main surface of the silicon carbide layer,
The trench has a first side wall portion where the second layer and the third layer are exposed, and a bottom portion which is connected to the first side wall portion and located in the second layer, and
A gate insulating film covering each of the first side wall and the bottom;
A silicon carbide semiconductor device comprising: a gate electrode provided on the gate insulating film.   The surface including the 1st surface which has a plane orientation {0-33-8} is provided in the portion which the 2nd layer expresses in the 1st side wall part according to claim 1. Silicon carbide semiconductor device.   The silicon carbide semiconductor device according to claim 1, wherein a cross-sectional shape of the trench is V-shaped. The trench has a second side wall portion arranged opposite to the first side wall portion and continuous with the bottom portion,
4. The silicon carbide semiconductor device according to claim 1, wherein at the second side wall portion, the second layer and the third layer are exposed. 5. When a voltage is applied to the gate electrode, a region including at least the second layer and the bottom portion exposed on the first side wall portion of the trench is a channel region,
The silicon carbide semiconductor device according to claim 1, wherein a channel length of the channel region is 0.6 μm or more. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration in the second layer is 5 × 10 ¹⁶ cm ⁻³ or more.   The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.

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