JP2019207906A - Semiconductor device and manufacturing method therefor, power conversion device, three-phase motor system, vehicle, and railway vehicle - Google Patents

Abstract

To provide a power semiconductor device having high performance and high reliability.SOLUTION: A semiconductor device includes: a first conductivity type semiconductor substrate; a drain electrode formed on the rear surface side of the semiconductor substrate; a first conductivity type drift layer formed on the semiconductor substrate; a second conductivity type body layer; a first conductivity type JFET region interposed between body layers; a first conductivity type source region that is connected to a source electrode and is formed in the body layer; a first conductivity type first current diffusion layer that is connected to the source region and has a concentration lower than that of the source region; a second conductivity type first electric field relaxation layer formed on the first current diffusion layer; a first conductivity type second current diffusion layer that is connected to the JFET region and has a concentration equal to that of the first current diffusion layer; a second conductivity type second electric field relaxation layer formed on the second current diffusion layer; a trench that extends to the first current diffusion layer, the first electric field relaxation layer, the body layer, the second current diffusion layer, and the second electric field relaxation layer, is located at a position shallower than that of the body layer, and has a bottom surface in contact with the body layer; a gate insulation film formed on an inner wall of the trench; and a gate electrode formed on the gate insulation film.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power semiconductor device including a plurality of power semiconductor devices and a manufacturing method thereof, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle.

  Conventionally, a power metal insulating film semiconductor field effect transistor (MISFET), which is one of power semiconductor devices, is a power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET). Was the mainstream.

  However, a power MISFET (hereinafter referred to as a SiC power MISFET) using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) can have a higher breakdown voltage and a lower loss than a Si power MISFET. . For this reason, particular attention has been paid in the field of power-saving or environment-friendly inverter technology.

  The SiC power MISFET can reduce the on-resistance at the same breakdown voltage as compared with the Si power MISFET. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength that is about seven times larger than that of silicon (Si), and the epitaxial layer serving as a drift layer can be thinned. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and further reduction of the on-resistance is desired from the viewpoint of efficient use of energy. ing.

  In the SiC power MISFET, a DMOS (Double Diffused Metal Oxide Semiconductor) structure using a substrate surface of a 4H-SiC substrate as a channel is generally used (Patent Document 1). In general, the channel mobility of the Si (0001) plane used as the channel plane in SiC DMOS is extremely low, about 1/5, compared with Si MISFET. Therefore, the channel parasitic resistance is large, which is a big problem. As an effective means for reducing this channel parasitic resistance, the use of the (11-20) plane or the (1-100) plane capable of obtaining a high channel mobility has been studied. In order to use a surface with high channel mobility such as the (11-20) plane or the (1-100) plane, it is necessary to form a MOS having a trench structure on the (0001) plane substrate.

According to Patent Document 2, a structure is proposed in which a trench is formed up to a drift layer so as to penetrate a p ⁺ type body layer that supports a breakdown voltage, and a channel current flows in a vertical direction with respect to the substrate. However, the dielectric breakdown strength of SiC is about seven times that of Si, and the electric field applied to the gate insulating film formed under the trench is seven times that of Si during blocking. As a result, the breakdown voltage of the gate insulating film is exceeded, leading to dielectric breakdown. In order to avoid the breakdown of the gate insulating film at the time of blocking, Patent Document 2 proposes a structure that relaxes the electric field of the gate insulating film. However, since the structure as in Patent Document 2 narrows the drain current path, the parasitic resistance increases, and sufficient performance cannot be obtained.

Therefore, Patent Document 3 discloses a structure in which a trench is formed inside without being exposed from a p ⁺ type body layer. In this case, the channel current flows parallel to the substrate. However, because it is formed as the same layer from the body layer of the p ⁺ -type until p ⁺ -type body layers outside the JFET region of the across the high-concentration source diffusion layer trench n ⁺⁺ type connected to the source electrode, high electrostatic The potential reaches the side surface of the trench through the n ⁺⁺ type high concentration source diffusion layer on the JFET region side exposed from the p ⁺ type body layer. As a result, a high electric field exceeding the dielectric breakdown is applied to the gate insulating film on the trench side during blocking, leading to breakdown.

Patent Document 4 discloses a structure in which a trench is formed inside a p ⁺ -type body layer without being exposed from the p ⁺ type body layer, as in Patent Document 3. However, apart from the n ⁺⁺ type high concentration source diffusion layer connected to the source electrode, the high concentration source diffusion layer extends from the p ⁺ type body layer to the n type JFET region outside the p ⁺ type body layer across the trench. An n ⁺ -type current diffusion layer having a lighter concentration than that is formed. Further, a p ⁺ type electric field relaxation layer for relaxing the electric field is formed on the n ⁺ type current diffusion layer so as to connect the p ⁺ type body layer. With this p ⁺ type electric field relaxation layer, it is possible to increase the concentration so that the n ⁺ type current diffusion layer does not become a parasitic resistance. In other words, the p ⁺ type electric field relaxation layer suppresses the penetration of the electrostatic potential into the n ⁺ type current diffusion layer, and reduces the gate insulating film electric field applied to the gate insulating film on the trench side during blocking. be able to. As a result, both low on-resistance and high reliability can be achieved.

In Patent Document 4, a p ⁺ type electric field relaxation layer is provided on the n ⁺ type current diffusion layer at the drain end. On the other hand, in Patent Document 5, a p-type layer is provided on an n-type source diffusion layer at the source end. However, in Patent Document 5, the trench is formed up to the drift layer so as to penetrate the p-type body layer that supports the withstand voltage. As in Patent Documents 3 and 4, the trench is covered with the p-type body layer. However, a high electric field exceeding the dielectric breakdown is applied to the gate insulating film at the end of the trench on the drain side during blocking, leading to breakdown.

Japanese Patent No. 6168732 JP 2009-260253 A JP2015-32813A International Publication No. 2016/116998 International Publication No. 2016/129068

However, in the technique disclosed in Patent Document 4, the channel length is determined by the position of the n ⁺⁺ type high concentration source diffusion layer and the n ⁺ -type current spreading layer, the channel length due to misalignment of two layers at the time of exposure Variations are a problem. The variation in channel length is a variation in threshold voltage and on-resistance between chips, and a variation in performance between chips installed in the power module. When the performance varies between chips in the power module, a high load is generated in the chip with inferior performance, and local heat generation occurs in the power module, thereby impairing the reliability of the power module.

Further, since the channel length is determined by the combination of the two layers at the time of exposure, it is necessary to give a large margin to the channel length. As a result, it becomes difficult to reduce the channel resistance by shortening the channel.
Furthermore, since the electric field concentrates on the trench upper edge portion on the source side when the transistor is on, the threshold voltage is lowered, resulting in an off-leak problem.
In order to solve the above problems, the inventors of the present application have studied an n ⁺ type current diffusion layer and a p ⁺ type electric field relaxation layer, and further a peripheral structure thereof.

  An object of the present invention is to provide a power semiconductor device that can be expected to have high performance and high reliability, and a method for manufacturing the same, by suppressing the variation in channel length and making the channel short. As a result, a compact, high-performance, highly reliable power converter using the semiconductor device, and a three-phase motor system using the power converter are provided. Furthermore, the present invention provides light weight, high performance, and high reliability of automobiles and railway vehicles using the three-phase motor system.

In a preferred example of the semiconductor device of the present invention, a first conductivity type semiconductor substrate having a first impurity concentration, a back electrode formed on the back surface side of the semiconductor substrate, and the semiconductor substrate formed on the semiconductor substrate. The first conductivity type first region having a second impurity concentration lower than the first impurity concentration, and the first conductivity type first region formed in the first conductivity type first region and on the semiconductor substrate surface side. Between the second region of the second conductivity type opposite to the conductivity type and the plurality of adjacent second regions, the third region of the first conductivity type and the second region of the second conductivity type The formed first region of the first conductivity type is adjacent to and electrically connected to the fourth region of the first conductivity type, and the first region having a lower concentration than the fourth region of the first conductivity type. A fifth region of conductivity type, electrically connected to the third region, and a fifth region of first conductivity type; Extending to the first conductivity type sixth region, the fifth region, the second region, and the sixth region having a high concentration, shallower than the second region, and having a bottom surface in the first region. It has a trench in contact with two regions, a gate insulating film formed on the inner wall of the trench, and a gate electrode formed on the gate insulating film.
Here, the equal concentration means that the difference is within ± 10%. The concentration of the first current diffusion layer and the concentration of the second current diffusion layer is equal to the center of the cross section of the first current diffusion layer. The difference between the concentration at the center and the concentration at the center position in the cross section of the second current diffusion layer is within ± 10%.

  In a preferred example of the method for manufacturing a semiconductor device of the present invention, the first conductivity type silicon carbide semiconductor substrate on which a first conductivity type epitaxial layer is formed is prepared, and the first conductivity type is provided in the epitaxial layer. Forming a second conductivity type body layer opposite to the mold, forming the first conductivity type JFET region sandwiched between a plurality of adjacent body layers, and forming the first conductivity type body layer in the second conductivity type body layer; A first conductivity type source region is formed, adjacent to and electrically connected to the first conductivity type source region, and the first conductivity type first current is lower in concentration than the first conductivity type source region. Forming a diffusion layer, electrically connecting to the JFET region, forming a first current diffusion layer of the first conductivity type and a second current diffusion layer of the first conductivity type using one photomask; Shallower than the body layer, the bottom surface is in contact with the body layer, A trench extending in contact with the first current diffusion layer, the body layer, and the second current diffusion layer is formed, an insulating film is formed on an inner wall of the trench, and a gate electrode is formed on the insulating film. It has each process to form, It is characterized by the above-mentioned.

  That is, the manufacturing method is characterized in that the first conductive type first current diffusion layer and the first conductive type second current diffusion layer are formed by a resist mask formed by simultaneously exposing with the same photomask. The first conductivity type impurity is ion-implanted through the step and formed simultaneously.

  According to the present invention, a high-performance and highly reliable power semiconductor device can be provided. As a result, high performance of the power conversion device, the three-phase motor system, the automobile, and the railway vehicle can be realized.

It is a principal part top view of the semiconductor chip with which the silicon carbide semiconductor device comprised by several SiC power MISFET by Embodiment 1 of this invention was mounted. It is a principal part bird's-eye view of SiC power MISFET by Embodiment 1 of this invention. FIG. 6 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is principal part sectional drawing of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device by Embodiment 1 of this invention. FIG. 5 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 4. FIG. 6 is a main-portion cross-sectional view of the same portion of the silicon carbide semiconductor device as shown in FIG. 4 in the manufacturing process of the silicon carbide semiconductor device continued from FIG. 5; FIG. 7 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 6. FIG. 8 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 7. FIG. 9 is a main part top view in the manufacturing process of the silicon carbide semiconductor device, following FIG. 8; FIG. 9 is a main-portion cross-sectional view taken along the cutting line AA 'of FIG. 9 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 8; FIG. 9 is a main-portion cross-sectional view taken along the cutting line BB 'in FIG. 9 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 8; FIG. 9 is a main-portion cross-sectional view of the same portion of the silicon carbide semiconductor device as shown in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device, following FIGS. 9 (a) to 9 (c). FIG. 11 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 10. FIG. 12 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 11. FIG. 13 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 12. FIG. 14 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 13. FIG. 15 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for producing the silicon carbide semiconductor device continued from FIG. 14. FIG. 16 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for producing the silicon carbide semiconductor device continued from FIG. 15. FIG. 17 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 16. It is a principal part bird's-eye view of SiC power MISFET by Embodiment 2 of this invention. It is principal part sectional drawing of SiC power MISFET by Embodiment 2 of this invention. It is principal part sectional drawing of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device by Embodiment 2 of this invention. It is a principal part bird's-eye view of SiC power MISFET by Embodiment 3 of this invention. FIG. 22 is a top view of a principal portion in the manufacturing process of the silicon carbide semiconductor device, following FIG. 21. FIG. 22 is a main-portion cross-sectional view taken along the cutting line AA ′ of FIG. 22 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 21. FIG. 22 is a main-portion cross-sectional view taken along the cutting line BB ′ in FIG. 22 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 21. FIG. 23 is a main-portion cross-sectional view of the silicon carbide semiconductor device, illustrating a manufacturing step of the silicon carbide semiconductor device at the position along the cutting line AA ′ in FIG. 22 (a) according to Embodiment 3 of the present invention. FIG. 23 is a main-portion cross-sectional view of the silicon carbide semiconductor device, for explaining the manufacturing process of the silicon carbide semiconductor device at the position of the cutting line BB 'in FIG. 22 (a) according to Embodiment 3 of the present invention. It is a circuit diagram of the power converter device (inverter) carrying any one of Embodiment 1-3 by Embodiment 4 of this invention. It is a circuit diagram of the power converter device (inverter) carrying any one of Embodiment 1-3 by Embodiment 5 of this invention. It is a block diagram of the electric vehicle carrying any one of Embodiment 4, 5 by Embodiment 6 of this invention. It is a circuit diagram of the boost converter carrying any one of Embodiment 4 and 5 by Embodiment 6 of this invention. It is a block diagram of the rail vehicle carrying any one of Embodiment 4, 5 by Embodiment 7 of this invention.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

≪Silicon carbide semiconductor device≫
The structure of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a top view of a main part of a semiconductor chip on which a silicon carbide semiconductor device composed of a plurality of SiC power MISFETs is mounted, and FIG. 2 is a bird's eye view of the main parts of the SiC power MISFET. The SiC power MISFET constitutes the silicon carbide semiconductor device.

As shown in FIG. 1, a semiconductor chip 1 on which a silicon carbide semiconductor device is mounted includes an active region (formation of SiC power MISFET formation) located below a source wiring electrode 2 in which a plurality of n-channel SiC power MISFETs are connected in parallel. Region, element formation region) and a peripheral formation region surrounding the active region in plan view. The peripheral formation region includes a plurality of p-type floating field limited rings (FLRs) 3 formed so as to surround the active region in plan view, and the plurality of the plurality of p-type floating field limited rings (FLR) in plan view. An n ⁺⁺ type guard ring 4 is formed so as to surround the p type floating field limiting ring 3.

On the surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as an SiC epitaxial substrate), a gate electrode of an SiC power MISFET, an n ⁺⁺ type source region, an n ⁺ type first current diffusion layer , A p ⁺ -type first electric field relaxation layer, an n ⁺ -type second current diffusion layer, a p ⁺ -type second electric field relaxation layer, a p ⁺ -type body layer, a trench, and a channel region on the side surface of the trench. The n ⁺ -type drain region of the SiC power MISFET is formed on the back side of the SiC epitaxial substrate.

By forming a plurality of p-type floating field limiting rings 3 around the active region, the maximum electric field portion sequentially moves to the outer p-type floating field limiting ring 3 when off. Since breakdown occurs at the outermost p-type floating field limiting ring 3, the silicon carbide semiconductor device can have a high breakdown voltage. Although FIG. 1 illustrates an example in which three p-type floating field limiting rings 3 are formed, the present invention is not limited to this. The n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

  The plurality of SiC power MISFETs 6 formed in the active region have a stripe pattern in plan view, and the gate electrodes of all the SiC power MISFETs are gated by lead wires (gate bus lines) connected to the respective stripe patterns. The wiring electrode 8 is electrically connected.

The plurality of SiC power MISFETs are covered with the source wiring electrode 2, and the source and body potential fixing layers of the respective SiC power MISFETs are connected to the source wiring electrode 2. The source wiring electrode 2 is connected to an external wiring through a source opening 7 provided in the insulating film. The gate wiring electrode 8 is formed separately from the source wiring electrode 2 and is connected to the gate electrode of each SiC power MISFET. The gate wiring electrode 8 is connected to an external wiring through the gate opening 5. Further, the n ⁺ -type drain region formed on the back side of the n-type SiC epitaxial substrate is electrically connected to a drain wiring electrode (not shown) formed on the entire back surface of the n-type SiC epitaxial substrate. doing.

Next, the structure of the SiC power MISFET according to the first embodiment will be described with reference to FIG.
Although not shown, it consists of a top surface (first main surface) of the ^{n +} -type SiC substrate 107 made of silicon carbide (SiC), ^{n +} -type SiC substrate low carbide impurity concentration than (SiC) An n ⁻ type epitaxial layer 101 is formed. The n ⁻ type epitaxial layer 101 functions as a drift layer. The thickness of the n ⁻ type epitaxial layer 101 is, for example, about 5 to 50 μm.

A p ⁺ type body layer (well region) 102 is formed in the epitaxial layer 101 with a predetermined depth from the surface of the epitaxial layer 101. An n ⁻ type JFET region 124 is formed between adjacent p ⁺ type body layers 102.
Although not shown, a p ⁺⁺ type body layer potential fixing region 109 is formed.
Further, an n ⁺⁺ type source region 103 having a predetermined depth from the surface of the epitaxial layer 101 and having nitrogen as an impurity is formed in the p ⁺ type body layer 102.

The p ⁺ -type body layer 102 includes an n ⁺ -type first current diffusion layer 122 and an n ⁺ -type second current diffusion layer 105 having the same depth as the n ⁺ -type first current diffusion layer 122. Is formed. The first current spreading layer 122 of n ⁺ -type is adjacent to the ^{n ++} -type source region 103, a portion of the second current spreading layer 105 of ^{n +} -type n adjacent to the body layer 102 of ^{p +} -type ^- type It extends to the JFET region 124.

n ⁺ -type on the first current spreading layer 122, the first electric field relaxation layer 123 of ^{p +} -type is formed on the second current spreading layer 105 of ^{n +} type, ^{p +} -type second electric field relaxation of Layer 119 is formed. The p ⁺ -type first electric field relaxation layer 123 and the p ⁺ -type second electric field relaxation layer 119 have the same depth.

A trench 106 is formed extending from the n ⁺ -type first current diffusion layer 122 across the p ⁺ -type body layer 102 to reach the n ⁺ -type second current diffusion layer 105. The bottom surface of the trench 106 is in contact with the p ⁺ type body layer 102. A gate insulating film 110 (not shown in FIG. 2) is formed on the surface of the trench 106. A gate electrode 111 (not shown in FIG. 2) is formed on the gate insulating film 110.

The depth (first depth) of the p ⁺ type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. Further, the depth (third depth) of the n ⁺⁺ type source region 103 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1 μm. The depth (fourth depth) of the n ⁺ -type first current diffusion layer 122 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1 μm. n ⁺ -type depth from the surface of the epitaxial layer 101 of the second current spreading layer 105 is identical to the first current spreading layer 122 of ^{n +} -type (fourth depth). The depth (fifth depth) from the surface of the epitaxial layer 101 of the p ⁺ -type first electric field relaxation layer 123 is, for example, about 0.01 to 0.5 μm. depth from the surface of the epitaxial layer 101 of the second electric field relaxation layer 119 of p ⁺ -type is identical to the first electric field relaxation layer 123 of ^{p +} -type (Fifth depth).

The depth of the trench 106 from the surface of the epitaxial layer 101 (sixth depth) is shallower than the depth of the p ⁺ -type body layer 102 from the surface of the epitaxial layer 101 (first depth). It is about 1 to 1.5 μm. The length in the direction parallel to the channel length of the trench (trench length) is, for example, about 1 to 3 μm. The length (trench width) in the direction parallel to the channel width in the direction parallel to the substrate of the trench is, for example, about 0.1 to 2 μm. The trench interval in the direction parallel to the channel width is, for example, about 0.1 to 2 μm. Although not shown, the depth (second depth) of the p ⁺⁺ type body layer potential fixing region 109 (see FIG. 8) from the surface of the epitaxial layer 101 is, for example, about 0.1 to 0.5 μm.

Note that “ ⁻ ” and “ ⁺ ” are signs representing the relative impurity concentration of the n-type or p-type conductivity, for example, “n ⁻ ”, “n”, “n ⁺ ”, “n ⁺⁺ ”. The impurity concentration of the n-type impurity increases in this order.

Although not shown, a preferable range of the impurity concentration of the n ⁺ -type SiC substrate 107 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . A preferred range of the impurity concentration of the n ⁻ type epitaxial layer 101 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . A preferable range of the impurity concentration of the p ⁺ -type body layer 102 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁺⁺ type source region 103 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . The preferred range of the impurity concentration of the n ⁺ -type first current spreading layer 122 and the ^{n +} -type second current spreading layer 105 is, for example, ^{5 × 10 16 ~5 × 10 18} cm -3. The preferred range of the impurity concentration of the p ⁺ -type 1 field relaxation layer 123 and the ^{p +} -type second electric field relaxation layer 119 is, for example, ^{1 × 10 17 ~1 × 10 19} cm -3. A preferable range of the impurity concentration of the n ⁻ type JFET region 124 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . Although not shown, a preferable range of the impurity concentration of the p ⁺⁺ type body layer potential fixing region 109 is, for example, a range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . The channel region is the surface of the trench 106 and the surface of the p ⁺ type body layer 102 sandwiched between the trenches 106. The n ⁻ type JFET region 124 is a region sandwiched between each pair of the n ⁺ type second current diffusion region 105 and the p type body layer 102.

  Although not shown, a gate insulating film 110 is formed on the channel region, and a gate electrode 111 is formed on the gate insulating film 110.

Next, features of the configuration of the SiC power MISFET according to the first embodiment will be described with reference to FIG.
As shown in FIG. 2 described above, since the side surface of the trench 106 becomes a channel region, a higher channel mobility can be expected as compared with the channel region on the surface of the SiC epitaxial layer 101. Furthermore, to determine the first current spreading layer 122 and the n ⁺ -type second current spreading layer 105 of n ⁺ -type formed using the same mask, the channel length, as in Patent Document 4, the n ⁺⁺ type Compared to the structure determined by the alignment of the high-concentration source diffusion layer and the n ⁺ -type current diffusion layer having a lower concentration than the high-concentration source diffusion layer, the variation in channel length is small. As a result, variations in threshold voltage and on-resistance between chips can be reduced. Furthermore, since the channel length is determined by one layer, it is not necessary to give a large margin to the channel length as compared with the case where it is determined by two layers. As a result, the channel resistance can be reduced by shortening the channel. In addition, since the p ⁺ -type first electric field relaxation layer 123 exists not only on the n ⁺ -type second current diffusion layer 105 but also on the n ⁺ -type first current diffusion layer 122, The edge is covered with a p ⁺ -type first electric field relaxation layer 123. Therefore, even if the electric field is concentrated on the upper edge portion of the trench at the time of turning on, the threshold voltage does not decrease and off leakage can be suppressed.

As described above, the n ⁺ -type first current diffusion layer 122 and the n ⁺ -type second current diffusion layer 105 are formed so as to define the channel length with the same mask, and the p ⁺ -type first electric field relaxation layer 123 is formed. By forming the p ⁺ -type second electric field relaxation layer 119, variation in channel length can be reduced and the channel can be shortened. Further, even if the electric field is concentrated on the upper edge portion of the trench at the time of turning on, the threshold voltage does not decrease and the off-leak problem does not occur. Therefore, compared with the structure disclosed in Patent Document 4, performance variation between chips in the power module does not occur, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, there is no problem of erroneous firing that occurs during switching.

≪Method for manufacturing silicon carbide semiconductor device≫
A method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. FIG. 3 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 4 to 8 and FIGS. 9B to 17 are cross-sectional views of main parts showing an enlarged part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device. FIG. 9A is a top view of a principal part of a semiconductor chip on which a silicon carbide semiconductor device constituted by a SiC power MISFET is mounted.

<Process P1>
First, as shown in FIG. 4, an n ⁺ type 4H—SiC substrate 107 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 107. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The n ⁺ type SiC substrate 107 has both a Si surface and a C surface, but the surface of the n ⁺ type SiC substrate 107 may be either an Si surface or a C surface.

Next, an n ⁻ type epitaxial layer 101 of silicon carbide (SiC) is formed on the surface (first main surface) of the n ⁺ type SiC substrate 107 by an epitaxial growth method. In the n ⁻ type epitaxial layer 101, an n type impurity lower than the impurity concentration of the n ⁺ type SiC substrate 107 is introduced. Although the impurity concentration of the n ⁻ -type epitaxial layer 101 depends on the element rating of the SiC power MISFET, it is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ type epitaxial layer 101 is, for example, 5 to 50 μm. Through the above steps, SiC epitaxial substrate 104 including n ⁺ -type SiC substrate 107 and n ⁻ -type epitaxial layer 101 is formed.

<Process P2>
Next, the n ⁺ -type drain region has a predetermined depth (seventh depth) from the back surface (second main surface) of the n ⁺ -type SiC substrate 107 and is formed on the back surface of the n ⁺ -type SiC substrate 107. 108 is formed. The impurity concentration of the n ⁺ -type drain region 108 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 5, a mask M <b> 11 is formed on the surface of the n ⁻ type epitaxial layer 101. The thickness of the mask M11 is, for example, about 1.0 to 3.0 μm. The width of the mask M1 in the element formation region is, for example, about 1.0 to 5.0 μm. As the mask material, an inorganic material SiO ₂ film, Si film, SiN film, organic material resist film, or polyimide film can be used.

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted into the n ⁻ -type epitaxial layer 101 through the mask M11. Thus, the p ⁺ type body layer 102 is formed in the element formation region of the n ⁻ type epitaxial layer 101. Further, a JFET region 124 is formed between adjacent p ⁺ -type body layers 102 by shielding ion implantation with a mask M11. Although not shown, a p ⁺ type floating field limiting ring 3 is simultaneously formed around the element formation region. The structure of the terminal portion is not limited to this, and may be, for example, a junction termination extension (JTE) structure.

The depth (first depth) of the p ⁺ type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. Further, the impurity concentration of the p ⁺ -type body layer 102 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The maximum impurity concentration of the p ⁺ type body layer 102 is, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 6, after removing the mask M11, a mask M12 is formed. For example, the mask M12 is formed of a resist film. In particular, the mask M12 is formed by drawing on a resist film by simultaneously exposing each pattern with the same photomask. The thickness of the mask M12 is, for example, about 1.0 to 3.0 μm. The channel length is determined by the length of the mask M12 and is, for example, about 0.1 to 2 μm.

Next, n-type impurities, for example, nitrogen atoms (N) are ion-implanted into the n ⁻ -type epitaxial layer 101 and the p ⁺ -type body layer 102 through the mask M12. As a result, the n ⁺ -type first current diffusion layer 122 and the n ⁺ -type second current diffusion layer 105 are formed in the element formation region of the n ⁻ -type epitaxial layer 101 and the p ⁺ -type body layer 102.

n ⁺ -type first current spreading layer 122 and the ^{n +} -type depth from the second current surface diffusion layer 105 of the (fourth depth), for example, about 0.1 to 1.0 [mu] m. The impurity concentration of the first current spreading layer 122 and the ^{n +} -type second current spreading layer 105 of ^{n +} type, for example, in the range of ^{5 × 10 16 ~5 × 10 18} cm -3.

Subsequently, the mask M12 over, p-type impurities on the surface of the ^{n +} -type first current spreading layer 122 and the ^{n +} -type second current spreading layer 105 of, for example, the Al atoms are ion-implanted. Thus, the p ⁺ -type first electric field relaxation layer 123 and the p ⁺ -type second electric field relaxation layer 119 are formed on the surfaces of the n ⁺ -type first current diffusion layer 122 and the n ⁺ -type second current diffusion layer 105. .

p ⁺ -type first electric field relaxation layer 123 and the ^{p +} -type depth from the surface of the second electric field relaxation layer 119 of the (fifth depth), for example, about 0.01 to 0.5 [mu] m. The impurity concentration of the ^{p +} -type 1 field relaxation layer 123 and the ^{p +} -type second electric field relaxation layer 119 is, for example, in a range ^{1 × 10 17 ~1 × 10 19} cm -3.

Next, as shown in FIG. 7, after removing the mask M12, a mask M13 is formed. For example, the mask M13 is formed of a resist film. The thickness of the mask M13 is, for example, about 1 to 4 μm. Mask M13 is open the ^{n ++} -type source region 103 formed portion adjacent to the first current spreading layer 122 of ^{n +} -type. Although not shown, the mask M13 is provided with an opening in a region where the guard ring 4 is formed on the outer periphery of the floating field limiting ring 3. An n ⁺ type source region 103 is formed by implanting ions of an n type impurity such as nitrogen atoms (N) or phosphorus atoms (P) into the p ⁺ type body layer 102 through the mask M13, which is not shown. However, the n ⁺⁺ type guard ring 4 is formed in the peripheral formation region.

The depth (third depth) from the surface of the n ⁺⁺ type source region 103 is, for example, about 0.1 to 1 μm. The impurity concentration of the n ⁺⁺ type source region 103 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 8, the mask M13 is removed and a mask 14 is formed. For example, the mask M14 is formed of a resist film. The thickness of the mask M14 is, for example, about 0.5 to 3 μm. The mask M14 is opened only in the portion where the potential fixing region 109 of the p ⁺⁺ type body layer is formed. A p-type impurity is ion-implanted into the p-type body layer 102 through the mask M14 to form a potential fixing region 109 of the p ^++- type body layer. The depth (second depth) of the p ⁺⁺ type body layer potential fixing region 109 from the surface of the p ⁺ type body layer 102 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the potential fixing region 109 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

<Process P3>
Next, after removing the mask M14, although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 104 by, for example, plasma CVD. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of SiC epitaxial substrate 104 with this carbon (C) film, heat treatment is performed on SiC epitaxial substrate 104 at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. Thereby, each impurity ion-implanted into SiC epitaxial substrate 104 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

<Process P4>
Next, as shown in FIGS. 9A to 9C, a trench processing hard mask and a mask 125A also used as a field oxide film are formed. The mask 125A is formed of, for example, a silicon dioxide (SiO ₂ ) film.

  9A is a top view of the main part, FIG. 9B is a cross-sectional view of the main part at the position of the cutting line AA ′ in FIG. 9A, and FIG. 9C is the cutting line BB ′ in FIG. 9A. It is principal part sectional drawing of a position. The thickness of the mask 125A is, for example, about 0.5 to 3 μm. The mask 125A has an opening in a region where the trench 106 is formed in a later process.

Next, as shown in FIG. 9C, using a dry etching process, the n ⁺ -type first current diffusion layer 122, the p ⁺ -type first electric field relaxation layer 123, the p ⁺ -type body layer 102, , Trenches 106 extending to the n ⁺ -type second current diffusion layer 105 and the p ⁺ -type second electric field relaxation layer 119 are formed.
The depth of the trench to be formed is shallower than the depth of the p ⁺ -type body layer 102. The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length X (see FIG. 9A) in the direction parallel to the channel length direction of the trench is, for example, about 1 to 3 μm. The width Y1 which is the length in the direction orthogonal to the channel length direction of the trench is, for example, about 0.1 to 2 μm. The interval Y2 between the trenches in the direction orthogonal to the channel length direction is, for example, about 0.1 to 2 μm.

<Process P5>
Next, as shown in FIG. 10, the gate insulating film 110 is formed on the surface of the epitaxial layer 101 and the surface of the trench 106 while leaving the field oxide film 125. The gate insulating film 110 is made of, for example, a SiO ₂ film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 11, an n-type or p-type polycrystalline silicon (Si) film 111 </ b> A is formed on the gate insulating film 110. The n-type or p-type polycrystalline silicon (Si) film 111A has a thickness of about 0.01 to 4 μm, for example.

  Next, as shown in FIG. 12, using the mask M17 (photoresist film), the polycrystalline silicon (Si) film 111A is processed by a dry etching method to form the gate electrode 111. Next, as shown in FIG.

<Process P6>
Next, as illustrated in FIG. 13, an interlayer insulating film 112 is formed on the surface of the n ⁻ -type epitaxial layer 101 by, for example, a plasma CVD method so as to cover the gate electrode 111 and the gate insulating film 110.

Next, as shown in FIG. 14, using the mask M18 (photoresist film), the interlayer insulating film 112 and the gate insulating film 110 are processed by the dry etching method, and a part of the n ⁺⁺ type source region 103 and the p Opening CNT_S reaching ⁺⁺ type body layer potential fixing region 109 is formed.

Next, as shown in FIG. 15, after removing the mask M18, a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109 exposed on the bottom surface of the opening CNT_S, respectively. A metal silicide layer 113 is formed on the surface.

First, although not shown in the drawing, for example, nickel (Ni) is used as the first metal film by sputtering, for example, so as to cover the inside (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT_S on the surface of the epitaxial layer 101. ). The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicidation heat treatment at 600 to 1000 ° C., the first metal film and the epitaxial layer 101 are reacted at the bottom surface of the opening CNT_S, and a nickel silicide (NiSi) layer, for example, is formed as the metal silicide layer 113. A portion of the n ⁺⁺ type source region 103 exposed on the bottom surface of the opening CNT_S and the surface of the p ⁺⁺ type body layer potential fixing region 109 are formed. Subsequently, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, sulfuric acid / hydrogen peroxide is used.

  Next, although not shown, the interlayer insulating film 112 is processed using a mask (photoresist film) to form an opening CNT_G reaching the gate electrode 111.

Next, as shown in FIG. 16, an opening CNT_S reaching the metal silicide layer 113 formed on the surface of a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109, and A third metal film 114, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film is formed on the interlayer insulating film 112 including the inside of the opening CNT_G (not shown) reaching the gate electrode 111. A laminated film is deposited. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the third metal film 114, it is electrically connected to a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109 via the metal silicide layer 113 in the CNT_S. The source wiring electrode 2 to be formed and the gate wiring electrode 8 electrically connected to the gate electrode 111 through the opening CNT_G are formed.

Next, although not shown, an SiO ₂ film or a polyimide film is deposited as a passivation film so as to cover the gate wiring electrode 8 and the source wiring electrode 2.

  Next, although illustration is omitted, the passivation film is processed to form a passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited on the n ⁺ -type drain region 108 by, for example, sputtering. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 17, by applying a laser silicidation heat treatment, it is reacted with a second metal film and the n ⁺ -type drain region 108, a metal silicide layer covering the n ⁺ -type drain region 108 115 is formed. Subsequently, a drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. The drain wiring electrode 116 is formed by depositing a laminated film of a Ti film, a Ni film, and a gold (Au) film by 0.5 to 1 μm.

  Thereafter, external wirings are electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively.

Thus, according to the first embodiment, as shown in FIG. 6, the channel length between the first current spreading layer 122 and the n ⁺ -type second current spreading layer 105 of the formed n ⁺ -type mask M12 Is stipulated. Therefore, the channel length variation can be reduced and the channel length can be reduced as compared with the structure disclosed in Patent Document 4. In addition, as shown in FIG. 6, the p ⁺ type first electric field relaxation layer 123 and the p ⁺ type of the n ⁺ type first current diffusion layer 122 and the n ⁺ type second current diffusion layer 105 on the surface of the mask M12. A second electric field relaxation layer 119 is formed. Therefore, since the source-side trench upper edge becomes the p ⁺ -type first electric field relaxation layer 123, even if an electric field is concentrated on the trench upper edge portion at the time of turning on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, performance variation between chips in the power module does not occur, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, there is no problem of erroneous firing that occurs during switching.

The difference between the second embodiment and the first embodiment described above is that, as shown in the bird's-eye view of the main part of the SiC power MISFET of FIG. 18, the n-type JFET region 224 is highly concentrated, and the p ⁺ -type second The p ⁺ type second electric field relaxation layer 219 is formed by extending the electric field relaxation layer to the upper portion of the JFET region 224. By increasing the concentration of the n-type JFET region 224, the JFET resistance that becomes a parasitic resistance can be lowered. However, when the concentration of the JFET region 224 is increased, the electric field above the JFET increases. Therefore, by forming the second electric field relaxation layer 219 of ^{p +} -type, which extended to the top of the second electric field relaxation layer of ^{p +} -type JFET region 224, to protect the JFET region 224 top of the oxide film. As a result, high reliability can be obtained while reducing the on-resistance.

≪Method for manufacturing silicon carbide semiconductor device≫
A method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described with reference to FIGS. 19 and 20 show an enlarged part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device of the present embodiment.

The process up to the first embodiment described above is the same up to the formation process of the p ⁺⁺ type body layer potential fixing region 209. FIG. 19 shows a process of forming the p ⁺ -type second electric field relaxation layer 219 in which the n-type JFET region 224 and the p ⁺ -type second electric field relaxation layer extend to the upper part of the JFET region 224. As shown in FIG. 19, a mask M20 is formed. For example, the mask M20 is formed of a resist film. The thickness of the mask M20 is, for example, about 1 to 4 μm. The mask M20 opens an n-type JFET region forming part. An n-type JFET region 224 is formed by ion-implanting an n-type impurity, such as a nitrogen atom (N) or a phosphorus atom (P), into the n ⁻ -type epitaxial layer 201 through the mask M20.

The depth from the surface of the n-type JFET region 224 (seventh depth) is, for example, about 0.5 to 2.0 μm. The impurity concentration of the n-type JFET region 224 is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

Next, p-type impurities, for example, Al atoms are ion-implanted into the surface of the n-type JFET region 224 through the mask M20. Thus, forming the second electric field relaxation layer 219 and the second electric field relaxation layer of ^{p +} -type n-type JFET region 224 surface of the extended allowed the ^{p +} -type to the top of the JFET region 224.

The depth (seventh depth) from the surface of the p ⁺ -type second electric field relaxation layer 219 is, for example, about 0.01 to 0.5 μm. The impurity concentration of the p ⁺ -type second electric field relaxation layer 219 is, for example, in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

  The remaining steps are the same as those in the first embodiment described above. By performing the remaining steps, the second embodiment shown in the cross-sectional view of the main part in FIG. 20 is completed.

As described above, according to the second embodiment, as in the first embodiment, it is possible to reduce channel length variation and shorten the channel as compared with the structure disclosed in Patent Document 4. Further, since the source-side trench upper edge becomes the p ⁺ -type first electric field relaxation layer 223, even if an electric field is concentrated on the trench upper edge portion at the time of turning on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, performance variation between chips in the power module does not occur, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, there is no problem of erroneous firing that occurs during switching. In addition, since the n-type JFET region 224 has a high concentration, the JFET resistance, which is a parasitic resistance, can be reduced. Further, since there is the p ⁺ -type second electric field relaxation layer 219 in which the p ⁺ -type second electric field relaxation layer extends to the upper part of the JFET region 224, even if the n-type JFET region 224 has a high concentration, During blocking, a high electric field that causes dielectric breakdown is not applied to the field oxide film 225 above the JFET. Therefore, a silicon carbide semiconductor device with higher performance and higher reliability can be provided.

The difference between the third embodiment and the first embodiment described above is that, as shown in the bird's-eye view of the main part of the SiC power MISFET of FIG. 21, the trench 306 has an n ⁺ -type first current diffusion layer 322 and a p ⁺ -type. The first electric field relaxation layer 323 passes through the n ^{+ +} type high concentration source region 303. Since the trench 306 reaches the n ^{+ +} type high concentration source region 303, when the SiC power MISFET is in the on state, the surface of the n ⁺ type first current diffusion layer 322 becomes an accumulation layer, and The parasitic resistance of the low concentration n ⁺ -type first current diffusion layer 322 becomes so small that it can be ignored. Therefore, the on-resistance can be further reduced.

≪Method for manufacturing silicon carbide semiconductor device≫
A method for manufacturing the silicon carbide semiconductor device according to the third embodiment will be described with reference to FIGS. 22 (a) to 23 (b). 22 and 23 are enlarged views of a part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device of the present embodiment.

The steps up to the first embodiment described above are the same up to the impurity activation step P3. Next, as shown in FIGS. 22A to 22C, a mask 325A serving as both a trench processing hard mask and a field oxide film is formed. The mask 325A is formed of, for example, a silicon dioxide (SiO ₂ ) film.

22A is a top view of the main part, FIG. 22B is a cross-sectional view of the main part at the position of the cutting line AA ′ in FIG. 22A, and FIG. 22C is the cutting line BB ′ in FIG. It is principal part sectional drawing of a position. The thickness of the mask 325A is, for example, about 0.5 to 3 μm. The mask 325A has an opening in a region where the trench 306 is formed in a later step. Differences from the first embodiment, as shown in FIG. 22 (c), an opening portion through the first current spreading layer 322 and the ^{p +} -type first electric field relaxation layer 323 of ^{n +} -type ^{n ++} type This is that it reaches the high concentration source region 303.

Next, using a dry etching process, the trench 306 extends through the n ⁺ -type first current diffusion layer 322 and the p ⁺ -type first electric field relaxation layer 323 to the n ^{+ +} -type high concentration source region 303, Further, it extends to the p ⁺ type body layer 302, the n ⁺ type second current diffusion layer 305, and the p ⁺ type second electric field relaxation layer 319.

The depth of the trench to be formed is shallower than the depth of the p ⁺ type body layer 302. The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length X (trench length) in the direction parallel to the channel length direction of the trench is, for example, about 1 to 4 μm. The length Y1 (trench width) in the direction parallel to the channel width direction parallel to the substrate of the trench is, for example, about 0.1 to 2 μm. The trench interval Y2 in the direction parallel to the channel width direction parallel to the substrate is, for example, about 0.1 to 2 μm.

  The remaining steps are the same as those in the first embodiment described above. By performing the remaining steps, FIG. 23A and FIG. 22A corresponding to the position of the cutting line AA ′ in FIG. The third embodiment shown in the cross-sectional view of the relevant part in FIG. 23B corresponding to the position of the cutting line BB ′ is completed.

Thus, according to the third embodiment, as in the first embodiment, the channel length variation can be reduced and the channel length can be reduced as compared with the structure disclosed in Patent Document 4. In addition, since the source-side trench upper edge becomes the p ⁺ -type first electric field relaxation layer 323, even when an electric field is concentrated on the trench upper edge portion at the time of turning on, the threshold voltage does not decrease and the problem of off-leakage occurs. Does not occur. Therefore, performance variation between chips in the power module does not occur, and local heat generation does not occur in the power module. Furthermore, since the threshold voltage can be increased, there is no problem of erroneous firing that occurs during switching. In addition, as shown in FIG. 23B, when the SiC power MISFET is in the ON state, the trench 306 reaches the n ⁺⁺ type high concentration source region 303, so that the concentration is lower than that of the high concentration source region 303. The surface of the n ⁺ -type first current diffusion layer 322 becomes an accumulation layer, and the parasitic resistance of the n ⁺ -type first current diffusion layer 322 becomes so small that it can be ignored. Therefore, a higher performance silicon carbide semiconductor device can be provided.

  The semiconductor device having the SiC power MISFET described in the first to third embodiments can be used for a power conversion device. A power conversion apparatus according to Embodiment 4 will be described with reference to FIG. FIG. 24 is a circuit diagram showing an example of a power converter (inverter) in the fourth embodiment.

  As shown in FIG. 24, the inverter 802 includes a SiC power MISFET 804 that is a switching element and a diode 805. In each single phase, a SiC power MISFET 804 and a diode 805 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of a load (for example, a motor) 801 (upper arm). The SiC power MISFET element 804 and the diode 805 are also connected in antiparallel with the ground potential (GND) (lower arm). That is, the load 801 is provided with two SiC power MISFETs 804 and two diodes 805 for each single phase, and is provided with six switching elements 804 and six diodes 805 for three phases. A control circuit 803 is connected to the gate electrode of each SiC power MISFET 804, and the SiC power MISFET 804 is controlled by the control circuit 803. Therefore, the load 801 can be driven by controlling the current flowing through the SiC power MISFET 804 constituting the inverter 802 by the control circuit 803.

  The function of the SiC power MISFET 804 constituting the inverter 802 will be described below. In order to control and drive the load 801, for example, a motor, it is necessary to input a sine wave of a desired voltage to the load 801. The control circuit 803 controls the SiC power MISFET 804 and performs a pulse width modulation operation for dynamically changing the pulse width of the rectangular wave. The outputted rectangular wave passes through the inductor and is smoothed to become a pseudo desired sine wave. The SiC power MISFET 804 has a function of generating a rectangular wave for performing this pulse width modulation operation.

  As described above, according to the fourth embodiment, by using the semiconductor device described in the first to third embodiments for the SiC power MISFET 804, for example, the inverter has a higher performance than the SiC power MISFET 804. Thus, it is possible to improve the performance of the power conversion device. In addition, since SiC power MISFET 804 has long-term reliability, it is possible to extend the service life of a power converter such as an inverter.

  The power conversion device can use a three-phase motor system. The load 801 shown in FIG. 24 is a three-phase motor, and the inverter 802 uses the power conversion device provided with the semiconductor device described in the first to third embodiments, thereby providing a three-phase motor. It is possible to improve the performance of the system and prolong the service life.

  The semiconductor device having the SiC power MISFET described in the first to third embodiments can be used for a power conversion device. A power conversion apparatus according to Embodiment 5 will be described with reference to FIG. FIG. 25 is a circuit diagram showing an example of a power converter (inverter) in the fifth embodiment.

  As shown in FIG. 25, the inverter 902 includes a SiC power MISFET 904 that is a switching element. In each single phase, the SiC power MISFET 904 is connected between the power supply voltage (Vcc) and the input potential of the load (eg, motor) 901 (upper arm), and the input potential of the load 901 and the ground potential (GND) An SiC power MISFET element 904 is also connected between them (lower arm). That is, in the load 901, two SiC power MISFETs 904 are provided in each single phase, and six switching elements 904 are provided in three phases. A control circuit 903 is connected to the gate electrode of each SiC power MISFET 904, and the SiC power MISFET 904 is controlled by the control circuit 903. Therefore, the load 901 can be driven by controlling the current flowing through the SiC power MISFET 904 constituting the inverter 902 by the control circuit 903.

  The function of the SiC power MISFET 904 constituting the inverter 902 will be described below. Also in this embodiment, as one of the functions of the SiC power MISFET, it has a function of generating a rectangular wave for performing a pulse width modulation operation as in the fourth embodiment. Further, in the present embodiment, the SiC power MISFET also serves as the diode 805 of the fourth embodiment. In the inverter 902, when the load 901 includes an inductance like a motor, for example, when the SiC power MISFET 904 is turned off, the energy stored in the inductance must be released (reflux current). In the fourth embodiment, the diode 805 plays this role. On the other hand, in the fifth embodiment, the SiC power MISFET 904 plays this role. That is, synchronous rectification driving is used. Here, the synchronous rectification driving is a method in which the gate of the SiC power MISFET 904 is turned on at the time of reflux to reversely conduct the SiC power MISFET 904.

  Therefore, the conduction loss during reflux is determined not by the characteristics of the diode but by the characteristics of the SiC power MISFET 904. Further, when performing synchronous rectification driving, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required during which both the upper and lower SiC power MISFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiC power MISFET 904 is driven. However, SiC has a shorter carrier travel distance than Si and has a small loss during non-operation time. For example, this is equivalent to the case where the diode 805 of the fourth embodiment is a SiC Schottky barrier diode.

  As described above, according to the fifth embodiment, by using the semiconductor device described in the first to third embodiments for the SiC power MISFET 904, for example, the SiC power MISFET 904 has a high performance and is returned. Loss of time can be reduced. In addition, since no diode is used, a power converter such as an inverter can be downsized. Furthermore, since the SiC power MISFET 904 has long-term reliability, it is possible to extend the service life of a power converter such as an inverter.

  The power converter can be used for a three-phase motor system. The load 901 shown in FIG. 25 is a three-phase motor, and a three-phase motor is used by using the power conversion device including the semiconductor device described in the first to third embodiments for the inverter 902. It is possible to improve the performance of the system and prolong the service life.

  The three-phase motor system described in the fourth embodiment or the fifth embodiment can be used for vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles. An automobile using the three-phase motor system in the sixth embodiment will be described with reference to FIGS. FIG. 26 is a schematic diagram showing an example of the configuration of the electric vehicle in the sixth embodiment, and FIG. 27 is a circuit diagram showing an example of the boost converter in the sixth embodiment.

  As shown in FIG. 26, the electric vehicle includes a three-phase motor 1003 that can input / output power to / from a drive shaft 1002 to which the drive wheel 1001a and the drive wheel 1001b are connected, and an inverter 1004 for driving the three-phase motor 1003. And a battery 1005. The electric vehicle further includes a boost converter 1008, a relay 1009, and an electronic control unit 1010. The boost converter 1008 includes a power line 1006 to which an inverter 1004 is connected and a power line 1007 to which a battery 1005 is connected. And connected to.

  The three-phase motor 1003 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 1004, the inverter described in Embodiment 4 or Embodiment 5 described above can be used.

  As shown in FIG. 27, boost converter 1008 has a configuration in which a reactor 1011 and a smoothing capacitor 1012 are connected to inverter 1013. For example, the inverter 1013 is the same as the inverter described in the fifth embodiment, and the element configuration in the inverter is also the same. In the sixth embodiment, for example, as in the fifth embodiment, a diagram including a SiC power MISFET 1014 is shown.

  The electronic control unit 1010 shown in FIG. 26 includes a microprocessor, a storage device, and an input / output port. Receive. Then, a signal for controlling inverter 1004, boost converter 1008, and relay 1009 is output.

  Thus, according to the sixth embodiment, the power conversion device described in the above-described fourth embodiment and the above-described fifth embodiment can be used for inverter 1004 and boost converter 1008 that are power conversion devices. Further, the three-phase motor system described in the above-described fourth embodiment or the above-described fifth embodiment can be used for a three-phase motor system including the three-phase motor 1003 and the inverter 1004. Thereby, energy saving, size reduction, weight reduction, and space saving of an electric vehicle can be achieved.

  Although the electric vehicle has been described in the sixth embodiment, the three-phase motor system of each of the above-described embodiments is similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 1005 is a fuel cell stack. Can be applied.

  The three-phase motor system described in the fourth embodiment and the fifth embodiment can be used for a railway vehicle. A railway vehicle using the three-phase motor system in the seventh embodiment will be described with reference to FIG. FIG. 28 is a circuit diagram showing an example of a converter and an inverter provided in the railway vehicle in the seventh embodiment.

  As shown in FIG. 28, electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 1109 and converted from alternating current to direct current by the converter 1107. Furthermore, it is converted from direct current to alternating current by an inverter 1102 via a capacitor 1108 to drive a three-phase motor as a load 1101. The element configuration in converter 1107 may be a SiC power MISFET and a diode used together as in the fourth embodiment described above, or a SiC power MISFET alone as described in the fifth embodiment. In the seventh embodiment, for example, a diagram including a SiC power MISFET 1104 as in the fifth embodiment is shown. In FIG. 28, the control circuit described in the fourth embodiment or the fifth embodiment is omitted. Moreover, in the figure, symbol RT indicates a track, and symbol WH indicates a wheel.

  As described above, according to the seventh embodiment, the converter 1107 can use the power conversion device described in the fourth embodiment or the fifth embodiment. In addition, the three-phase motor system described in the fourth embodiment or the fifth embodiment described above can be used for the three-phase motor system including the load 1101, the inverter 1102, and the control circuit. As a result, it is possible to save energy in the railway vehicle and to reduce the size and weight of the underfloor parts.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the material, conductivity type, manufacturing conditions, etc. of each part are not limited to those described in the above-described embodiments, and it goes without saying that many modifications can be made. Here, for convenience of explanation, the description has been made with the conductivity types of the semiconductor substrate and the semiconductor film being fixed, but it is not limited to the conductivity types described in the above embodiments.

1: Semiconductor chip, 2: Source wiring electrode (SiC power MISFET forming region, element forming region), 3: p-type floating field limiting ring, 4: n ⁺⁺ type guard ring, 5: gate opening Part: 6: SiC power MISFET, 7: source opening, 8: gate wiring electrode, 101, 201, 301: n ⁻ type epitaxial layer, 102, 202, 302: p ⁺ type body layer, 103, 203 , 303: n ⁺⁺ type source region, 122, 222, 322: n ⁺ type first current diffusion layer, 123, 223, 323: p ⁺ type first electric field relaxation layer, 119, 219, 319: p ^+. the second electric field relaxation layer type, 105, 205, 305: ^{n +} -type second current diffusion layer, 124,224,324: n ^- -type JFET region, 106, 206, 06: trench, 107, 207, 307: ^{n +} -type SiC substrate, 108, 208, 308: ^{n +} -type drain region, ^{109,209,309: p ++} type body layer potential fixing region, 110 and 210, 310: gate insulating film, 111, 211, 311: gate electrode, 112, 212, 312: interlayer insulating film, 113, 213, 313: metal silicide layer, 114, 214, 314: third metal film, 115, 215 315: metal silicide layer, 116, 216, 316: drain wiring electrode, 801: load, 802: inverter, 803: control circuit, 804: SiCMISFET, 805: diode, 901: load, 902: inverter, 903: control circuit 904: SiCMISFET 905: 1001a, 1001b: driving wheel, 10 2: drive shaft, 1003: three-phase motor, 1004: inverter, 1005: battery, 1006: power line, 1007: power line, 1008: boost converter, 1009: relay, 1010: electronic control unit, 1011: reactor, 1012: Smoothing capacitor, 1013: inverter, 1014: SiCIMSFET, 1101: load, 1102: inverter, 1104: SiCIMSFET, 1107: converter, 1108: capacitor, 1109: transformer, OW: overhead line OW, RT: track, WH: wheel, Vcc : Power supply voltage, GND: Ground potential.

Claims (16)

A first conductivity type semiconductor substrate having a first impurity concentration;
A back electrode formed on the back side of the semiconductor substrate;
A first region of the first conductivity type having a second impurity concentration lower than the first impurity concentration formed on the semiconductor substrate;
A second region of a second conductivity type formed in the first region of the first conductivity type and opposite to the first conductivity type formed on the semiconductor substrate surface side;
Sandwiched between a plurality of adjacent second regions, the third region of the first conductivity type,
A fourth region of the first conductivity type formed in the second region of the second conductivity type;
A fifth region of the first conductivity type adjacent to and electrically connected to the fourth region of the first conductivity type and having a lower concentration than the fourth region of the first conductivity type;
A sixth region of the first conductivity type electrically connected to the third region and having a concentration equal to that of the fifth region of the first conductivity type;
A trench extending to the fifth region, the second region, and the sixth region, shallower than the second region and having a bottom surface in contact with the second region;
A gate insulating film formed on the inner wall of the trench;
And a gate electrode formed on the gate insulating film. The semiconductor device according to claim 1,
A seventh region of the second conductivity type formed on the fifth region of the first conductivity type and electrically connected to the second region of the second conductivity type;
An eighth region of the second conductivity type formed on the sixth region of the first conductivity type, electrically connected to the second region of the second conductivity type, and having the same concentration as the seventh region; A semiconductor device, further comprising: The semiconductor device according to claim 1,
The impurity concentration of the fourth region of the first conductivity type is in the range of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ;
The impurity concentration of the fifth region of the first conductivity type and the sixth region of the first conductivity type are equal, and the impurity concentration is in the range of 5 × 10 ¹⁶ cm ⁻³ to 5 × 10 ¹⁸ cm ^−3. A featured semiconductor device. The semiconductor device according to claim 2,
The impurity concentration of the seventh region of the second conductivity type and the eighth region of the second conductivity type are equal, and the impurity concentration is in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. A semiconductor device characterized by the above. Preparing the first conductivity type silicon carbide semiconductor substrate on which the first conductivity type epitaxial layer is formed;
Forming a body layer of a second conductivity type opposite to the first conductivity type in the epitaxial layer;
Forming the first conductivity type JFET region sandwiched between a plurality of adjacent body layers;
Forming a source region of the first conductivity type in the body layer of the second conductivity type;
Forming a first current diffusion layer of the first conductivity type adjacent to and electrically connected to the source region of the first conductivity type and having a lower concentration than the source region of the first conductivity type;
Electrically connecting to the JFET region, forming a first current diffusion layer of the first conductivity type and a second current diffusion layer of the first conductivity type using a mask;
Forming a trench that is shallower than the body layer, has a bottom surface in contact with the body layer, and a side surface extending in contact with the first current diffusion layer, the body layer, and the second current diffusion layer;
Forming an insulating film on the inner wall of the trench;
A method of manufacturing a semiconductor device, comprising forming a gate electrode on the insulating film. In the manufacturing method of the semiconductor device according to claim 5,
The step of forming the first current diffusion layer of the first conductivity type and the second current diffusion layer of the first conductivity type includes the step of exposing the first conductivity type impurity through a resist mask formed by simultaneous exposure with the same photomask. A method of manufacturing a semiconductor device, characterized by being a step of forming ions simultaneously. In the manufacturing method of the semiconductor device according to claim 5,
Forming a first electric field relaxation layer of the second conductivity type on the first current diffusion layer of the first conductivity type so as to be electrically connected to the body layer of the second conductivity type;
The second conductivity type second electric field relaxation layer is electrically connected to the second conductivity type body layer on the first conductivity type second current diffusion layer and has the same concentration as the first electric field relaxation layer. A method of manufacturing a semiconductor device, further comprising forming a layer. In the manufacturing method of the semiconductor device according to claim 7,
The step of forming the second electric conductivity type first electric field relaxation layer and the second electric conductivity type second electric field relaxation layer includes the steps of exposing the first electric conductivity type impurity through a resist mask formed by simultaneous exposure with the same photomask. After ion implantation and simultaneously forming the first current diffusion layer and the second current diffusion layer, a second conductivity type impurity is ion-implanted through the resist mask and simultaneously the first electric field relaxation layer and the A method for manufacturing a semiconductor device, comprising forming a second electric field relaxation layer. The semiconductor device according to claim 2,
The third region of the first conductivity type is a ninth region of the first conductivity type formed at a higher concentration than the impurity concentration of the first region of the first conductivity type;
The eighth region of the second conductivity type is formed to extend from the sixth region of the first conductivity type to the third region of the first conductivity type, and is electrically connected to the second region of the second conductivity type. A semiconductor device characterized in that it is the tenth region of the second conductivity type that is connected electrically. The semiconductor device according to claim 1,
The trench extends to the fourth region in addition to the fifth region, the second region, and the sixth region, is shallower than the second region, and has a bottom surface that is the second region. A semiconductor device characterized by being a trench in contact with the semiconductor device. The semiconductor device according to claim 10.
A seventh region of the second conductivity type formed on the fifth region of the first conductivity type and electrically connected to the second region of the second conductivity type;
An eighth region of the second conductivity type formed on the sixth region of the first conductivity type, electrically connected to the second region of the second conductivity type, and having the same concentration as the seventh region; A semiconductor device, further comprising: The semiconductor device according to claim 1,
The semiconductor device is characterized in that a material of the semiconductor substrate is silicon carbide.   A power converter having the semiconductor device according to claim 1 as a switching element.   A three-phase motor system for converting DC power to AC power by the power conversion device according to claim 13 and driving a three-phase motor.   The motor vehicle which drives a wheel with the three-phase motor system of Claim 14.   The railway vehicle which drives a wheel with the three-phase motor system of Claim 14.

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