JP6843561B2 - Semiconductor devices and power converters - Google Patents

Description

The present invention relates to a semiconductor device composed of a power semiconductor device, a method for manufacturing the same, and a power conversion device.

As background technologies in this technical field, there are International Patent Publication WO 2010/11246 (Patent Document 1), Japanese Patent Application Laid-Open No. 2015-15464 (Patent Document 2), and International Patent Publication WO 2015/177914 (Patent Document 3). ..

In International Patent Publication WO 2010/11246 (Patent Document 1), a trench is formed in the semiconductor layer by digging from the surface thereof, and a trench straddling between two source regions adjacent to each other is formed. A semiconductor device having an inner surface coated and a gate electrode having a surface facing portion facing the surface of the semiconductor layer and a buried portion embedded in a trench is described.

Japanese Unexamined Patent Publication No. 2015-15464 (Patent Document 2) describes a semiconductor device including a silicon carbide (SiC) drift layer arranged on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface containing a plurality of repeating shapes oriented parallel to the channel length of the semiconductor device, and the channel region is arranged in a specific crystal plane of the SiC drift layer.

According to International Patent Publication WO 2015/177914 (Patent Document 3), a trench extending to the source region, the body layer, and the current diffusion layer, shallower than the body layer, and having the bottom surface in contact with the body layer, and a trench. A semiconductor device having a gate insulating film formed on an inner wall and a gate electrode formed on the gate insulating film is described.

International Patent Publication WO 2010/11246 Japanese Unexamined Patent Publication No. 2015-15464 International Patent Publication WO 2015/177914

In a semiconductor device composed of a power semiconductor device, it is necessary to reduce the channel parasitic resistance while suppressing the short channel effect. As an effective means for this, there is a method in which a trench is formed in a part of the body layer and a new current diffusion layer is formed in the upper part of the JFET region (see, for example, Patent Document 3). There were problems such as distortion, and further improvements in power semiconductor devices were needed.

In order to solve the above problems, a semiconductor device of the present invention, n ^- from the upper surface of the mold of the epitaxial layer n ^- -type and a first body layer p-type formed in the epitaxial layer, the n ^- -type epitaxial layer of ^{It has an n ++} type source region formed in the p-type first body layer from the upper surface. Moreover, apart from the n ⁺⁺ -type source region, and, n ^- across the interface between the type epitaxial layer and the p-type first body layer of the n ^- -type first body layer of p-type from the upper surface of the epitaxial layer ^{It has an n +} type current diffusion layer formed shallower than the n + type current diffusion layer and a p type second body layer formed shallower than the p type first body layer immediately below ^{the n + type current diffusion layer.} In addition, it has an n ⁺⁺ type source region, a p-type first body layer and a trench extending over the ^{n + type current diffusion layer.} The depth of the trench is shallower than the depth of the p-type first body layer, and the gate electrode provided inside the trench via the gate insulating film is the p-type first body layer and p in a plan view. It is provided inside the region consisting of the second body layer of the mold.

According to the present invention, it is possible to provide a semiconductor device having high performance and high reliability. Further, it is possible to realize high performance of the power conversion device.

Issues, configurations and effects other than those described above will be clarified by the following description of embodiments.

FIG. 5 is a top view of a semiconductor chip on which a semiconductor device configured by the SiC power MISFET according to the first embodiment is mounted. It is a top view of the SiC power MISFET according to the first embodiment. It is a bird's-eye view of the SiC power MISFET according to the first embodiment. FIG. 5 is a cross-sectional view (cross-sectional view taken along the line AA of FIG. 2) in a direction parallel to the channel length of the SiC power MISFET according to the first embodiment. FIG. 5 is a cross-sectional view (cross-sectional view taken along line BB of FIG. 2) in a direction parallel to the channel width of the SiC power MISFET according to the first embodiment. It is a process drawing explaining the manufacturing method of the semiconductor device according to Example 1. FIG. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device according to Example 1. FIG. FIG. 7 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 8 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 9 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 10 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 11 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 12 is a plan view during the manufacturing process of the semiconductor device following FIG. FIG. 3 is a cross-sectional view taken along the line CC of FIG. It is sectional drawing along the DD line of FIG. It is sectional drawing in the manufacturing process of the semiconductor device which follows | FIG. FIG. 16 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 17 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. It is sectional drawing in the manufacturing process of the semiconductor device following FIG. It is sectional drawing in the manufacturing process of the semiconductor device following FIG. FIG. 20 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 21 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. FIG. 22 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. It is sectional drawing of the direction parallel to the channel length of the SiC power MISFET according to Example 2. FIG. It is a top view of the SiC power MISFET for explaining the manufacturing process of the semiconductor device according to Example 2. FIG. FIG. 5 is a cross-sectional view taken along the line EE of FIG. 25. FIG. 5 is a cross-sectional view taken along the line FF of FIG. 25. 25 is a cross-sectional view during the manufacturing process of the semiconductor device following FIGS. 25 to 27. It is a bird's-eye view of the SiC power MISFET according to the third embodiment. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device by Example 3. FIG. FIG. 30 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. It is a bird's-eye view of the SiC power MISFET according to the fourth embodiment. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device by Example 4. FIG. FIG. 33 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. 33. It is a bird's-eye view of the SiC power MISFET according to the fifth embodiment. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device according to Example 5. FIG. 36 is a cross-sectional view during the manufacturing process of the semiconductor device following FIG. It is a bird's-eye view of the SiC power MISFET according to the 1st modification of Example 5. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device by 1st modification of Example 5. It is a bird's-eye view of the SiC power MISFET according to the 2nd modification of Example 5. It is sectional drawing of the SiC power MISFET explaining the manufacturing process of the semiconductor device by the 2nd modification of Example 5. It is a circuit diagram which shows an example of the power conversion apparatus (inverter) by Example 6. It is a circuit diagram which shows an example of the power conversion apparatus (inverter) by Example 7. It is the schematic which shows an example of the structure of the electric vehicle according to Example 8. It is a circuit diagram which shows an example of the boost converter according to Example 8. It is a circuit diagram which shows an example of the converter and the inverter provided in the railroad vehicle by Example 9. FIG.

In addition, in all the drawings for explaining the following embodiments, those having the same function are, in principle, given the same reference numerals, and the repeated description thereof will be omitted. Further, in the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. Further, even when the cross-sectional view and the plan view correspond to each other, a specific portion may be displayed in a relatively large size in order to make the drawing easy to understand. Further, even if it is a cross-sectional view, hatching may be omitted to make the drawing easier to see, and even if it is a plan view, hatching may be added to make the drawing easier to see.

First, since it is considered that the structure of the semiconductor device according to the present embodiment will be clarified, the problems that occur in the semiconductor device found by the present inventors will be described in detail below.

In the power metal insulating film semiconductor field effect transistor (MISFET), which is one of the power semiconductor devices, conventionally, a power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET) has been used. It was mainstream.

However, a power MISFET using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) (hereinafter referred to as a SiC power MISFET) can have a higher withstand voltage and a lower loss than a Si power MISFET. .. For this reason, particular attention has been paid to the field of power saving or environment-friendly inverter technology.

Compared with the Si power MISFET, the SiC power MISFET can reduce the on-resistance with the same withstand voltage. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength of about 7 times as large as that of silicon (Si), and the epitaxial layer serving as a drift layer can be made thinner. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and further reduction of on-resistance is desired from the viewpoint of highly efficient use of energy. ing.

One of the problems to be solved regarding the on-resistance of the SiC power MISFET having a DMOS (Double diffused Metal Oxide Semiconductor) structure is the channel parasitic resistance. Shortening the channel length is effective in reducing the channel parasitic resistance. However, as the channel shortening progresses, the drain current with respect to the drain voltage is not sufficiently saturated due to the short channel effect. Therefore, for example, when the anti-arm is turned off or short-circuited due to an erroneous pulse, a high saturation current flows through the SiC power MISFET, causing a problem that the SiC power MISFET is destroyed.

Therefore, it is necessary to reduce the channel parasitic resistance while suppressing the short channel effect. As an effective means, for example, high channel mobility can be mentioned. However, the channel mobility of the Si (0001) plane, which is the channel plane of the SiC power MISFET having a DMOS structure, is extremely low, about 1/5 of that of the Si power MISFET.

In order to solve this problem, Patent Documents 1 and 2 describe a method of forming a trench in a part of the body layer and the outside of the body layer in the SiC power MISFET having a DMOS structure to widen the effective channel width. It is disclosed. Further, in order to reduce the channel parasitic resistance, the use of the (11-20) plane or the (1-100) plane where high channel mobility can be obtained is being studied. In order to utilize a surface having high channel mobility such as the (11-20) surface or the (1-100) surface, it is necessary to form a trench-type MISFET on the (0001) surface SiC substrate. However, since the trench is formed not only in the body layer in which the gate insulating film and a part of the gate electrode support the withstand voltage but also in the drift layer through the body layer, an electric field exceeding the dielectric breakdown is applied to the gate insulating film. As a result, the gate insulating film may suffer dielectric breakdown.

Patent Document 3 discloses a method of lowering the electric field applied to the gate insulating film at the time of off by forming a trench inside the body layer and newly forming a current diffusion layer in the upper part of the JFET region. .. Further, since a part of the current diffusion layer having a higher impurity concentration than the JFET region directly faces the drain electrode formed on the back surface of the SiC substrate, it is horizontal along the main surface of the SiC substrate at the lower part of the body layer when it is off. The gently changing equipotential line is greatly distorted in the JFET region, and the electric field applied to the gate insulating film can be reduced from the SiC power MISFET disclosed in Patent Documents 1 and 2. However, the reduction of the electric field is not sufficient. Further, since the current diffusion layer having a higher impurity concentration than the JFET region is carelessly wide, the depletion layer is difficult to grow when it is off, which may cause a decrease in switching speed or an erroneous arc.

Therefore, in order to solve the above problems, the present inventors have examined the current diffusion layer and its peripheral structure. An object of the present invention is a semiconductor device having high performance and high reliability by using a trench structure that can be expected to have high channel mobility in a SiC power MISFET having a DMOS structure and further suppressing distortion of equipotential lines in the JFET region. And its manufacturing method. Further, a compact, high-performance and highly reliable power conversion device using the semiconductor device, and a three-phase motor system using the power conversion device are provided. Furthermore, a lightweight, high-performance and highly reliable automobile and railroad vehicle using the three-phase motor system will be provided.

≪Semiconductor device≫
The semiconductor chip on which the semiconductor device configured by the SiC power MISFET according to the first embodiment is mounted will be described with reference to FIG. FIG. 1 is a plan view of a semiconductor chip on which a semiconductor device configured by a SiC power MISFET according to the first embodiment is mounted.

As shown in FIG. 1, the semiconductor chip 1 on which the semiconductor device is mounted has an active region (SiC power MISFET forming region, which is located below the source wiring electrode 2 in which a plurality of n-channel type SiC power MISFETs are connected in parallel. It is composed of an element forming region) and a peripheral forming region surrounding the active region in a plan view. The peripheral forming region includes a plurality of p-shaped floating field limiting ring (FLR) 3 formed so as to surround the active region in a plan view, and a plurality of the above-mentioned plurality in a plan view. ^{An n ++} type guard ring 4 formed so as to surround the p-type floating field limiting ring 3 is formed.

^{A gate electrode of a SiC power MISFET, an n ++} type source region, a channel region, and the like are formed on the surface side of an active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as a SiC epitaxial substrate), and SiC epitaxial. ^{An n +} type drain region of the SiC power MISFET is formed on the back surface side of the substrate.

By forming a plurality of p-type floating field limiting rings 3 around the active region, the maximum electric field portion sequentially shifts to the outer p-type floating field limiting ring 3 when off. Since the yield is achieved by the p-type floating field limiting ring 3 on the outermost circumference, the semiconductor device can have a high withstand voltage. FIG. 1 illustrates an example in which three p-shaped floating field limiting rings 3 are formed, but the present invention is not limited to this. Further, the n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

The plurality of SiC power MISFETs formed in the active region have a stripe pattern in a plan view, and the gate electrodes of all the SiC power MISFETs are gated by the lead wiring (gate bus line) connected to each stripe pattern. It is electrically connected to the wiring electrode 8.

Further, the plurality of SiC power MISFETs are covered with the source wiring electrodes 2, and the n ⁺⁺ type source region and the body layer potential fixing region of the respective SiC power MISFETs are connected to the source wiring electrodes 2. The source wiring electrode 2 is connected to the external wiring through a source opening 7 provided in the insulating film. The gate wiring electrode 8 is formed so as to be separated from the source wiring electrode 2, and is connected to the gate electrode of each SiC power MISFET. The gate wiring electrode 8 is connected to the external wiring through a gate opening 5 provided in the insulating film. ^{Further, the n +} type drain region formed on the back surface side of the SiC epitaxial substrate is electrically connected to the drain wiring electrode (not shown) formed on the entire back surface of the SiC epitaxial substrate.

Next, the structure of the SiC power MISFET according to the first embodiment will be described with reference to FIGS. 2 to 5. FIG. 2 is a plan view of the SiC power MISFET according to the first embodiment. FIG. 3 is a bird's-eye view of the SiC power MOSFET according to the first embodiment. FIG. 4 is a cross-sectional view (cross-sectional view taken along the line AA of FIG. 2) in the direction parallel to the channel length of the SiC power MISFET according to the first embodiment. FIG. 5 is a cross-sectional view (cross-sectional view taken along line BB of FIG. 2) in a direction parallel to the channel width of the SiC power MISFET according to the first embodiment.

An ^n- type epitaxial made of silicon carbide (SiC) having a lower impurity concentration than the ^{n +} type SiC substrate 107 on the surface (first main surface) of the n ^{+ type SiC substrate 107 made of silicon carbide (SiC).} A layer 101 is formed, and the SiC epitaxial substrate 100 is composed of ^{an n +} type SiC substrate 107 and an n ^{− -type epitaxial layer 101.} The n ^- type epitaxial layer 101 functions as a drift layer. n ^- -type thickness of the epitaxial layer 101 is, for example, about 5 to 50 [mu] m.

the n ^- has the epitaxial layer from the top surface of a predetermined depth 101 of the mold, n ^- -type epitaxial layer 101, extend in the y direction (parallel to the channel width direction, the direction along the channel width) A p-shaped first body layer (well region) 102 is formed.

Further, the p-type first body layer 102 ^{has a predetermined depth from the upper surface of the n −} -type epitaxial layer 101, and is separated from the end of the p-type first body layer 102 in the y direction. ^{An n ++} type source region 103 extending to the surface is formed.

Further, the p-type first body layer 102 ^{has a predetermined depth from the upper surface of the n − -type epitaxial layer 101, and is of a p ++} type that fixes the potential of the p-type first body layer 102. The body layer potential fixing region 109 is formed.

Further, the n ⁺⁺ type source region 103 is separated from the n ++ type source region 103 in the x direction (direction parallel to the channel length, direction along the channel length), ^{and straddles the n −} type epitaxial layer 101 and the p type first body layer 102. Further, ^{an n +} type current diffusion layer 105 ^{having a predetermined depth from the upper surface of the n −} type epitaxial layer 101 and extending in the y direction is formed. Further, a p-type second body layer 104 extending in the y direction is formed directly below ^{the n + type current diffusion layer 105.} The depth of the n ⁺ type current diffusion layer 105 ^{from the upper surface of the n-} type epitaxial layer 101 and the depth of the p-type second body layer 103 ^{from the upper surface of the n-} type epitaxial layer 101 are p-type. It is shallower than the depth from the upper surface of ^{the n-} type epitaxial layer 101 of the first body layer 102.

The distance between the p-type first body layers 102 facing each other in the x direction ^{is larger than the distance between the n +} type current diffusion layers 105 facing each other in the x direction and the distance between the p-type second body layers 104, and in a plan view. There is a region where the n ⁺ type current diffusion layer 105 does not overlap with the p-type first body layer 102 and a region where the p-type second body layer 104 does not overlap with the p-type first body layer 102.

Further, ^{a trench 106 extending from the n ++} type source region 103 to the p-type first body layer 102 and extending in the x direction so as to extend ^{over the n + type current diffusion layer 105 is formed.} The bottom surface of the trench 106 is in contact with the p-shaped first body layer 102. A gate insulating film 110 is formed on the inner walls (side surfaces and bottom surface) of the trench 106, and a gate electrode 111 is formed on the gate insulating film 110. However, the gate electrode 111, n sandwiched n ⁺ -type current spreading layer 105 facing each other in the x-direction ^- not formed above the type epitaxial layer 101, in the x direction of the gate electrode 111 end Is located above the n ⁺ type current diffusion layer 105 or the p type second body layer 104. That is, the gate electrode 111 is formed inside a region composed of a p-type first body layer 102 and a p-type second body layer 104 in a plan view.

The depth of the p-type first body layer 102 ^{from the upper surface of the n-} type epitaxial layer 101 is, for example, about 0.5 to 2 μm. The depth of the n ⁺⁺ type source region 103 ^{from the upper surface of the n −} type epitaxial layer 101 is, for example, about 0.1 to 1 μm. The depth of the p ⁺⁺ type body layer potential fixing region 109 ^{from the upper surface of the n −} type epitaxial layer 101 is, for example, about 0.1 to 0.5 μm.

The depth of the n ⁺ type current diffusion layer 105 ^{from the upper surface of the n −} type epitaxial layer 101 is, for example, about 0.1 to 1 μm. The depth of the p-type second body layer 104 ^{from the upper surface of the n-} type epitaxial layer 101 is, for example, about 0.1 to 1.5 μm. The width W1 of the region where the p-type second body layer 104 does not overlap with the p-type first body layer 102 is, for example, about 0.1 to 2 μm.

N trench 106 ^- depth from the upper surface of the mold of the epitaxial layer 101, n of the p-type first body layer 102 of the ^- smaller than the depth from the upper surface of the type epitaxial layer 101, for example, 0.1 to 1. It is about 5 μm. The length of the trench 106 in the x direction is, for example, about 1 to 3 μm. The length of the trench 106 in the y direction is, for example, about 0.1 to 2 μm, and the interval of the trench 106 in the y direction is, for example, about 0.1 to 2 μm.

Incidentally, ^"-" and ^"+" is a code conductivity type expressed relative impurity concentrations of the n-type or p-type, for example, "n ^-", "n", "n ^+", "n ⁺⁺ the impurity concentration of the n-type impurity in this order "is increased, similarly," p ^- "," p "," p ⁺ ", the impurity concentration of the p-type impurity in the order of" p ⁺⁺ "increases.

The preferable range of the impurity concentration of the n ⁺ type SiC substrate 107 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^-3 . The preferable range of the impurity concentration of the n ^- type epitaxial layer 101 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 . The preferred range of the impurity concentration of the p-type first body layer 102 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^-3 , and the preferable range of the maximum impurity concentration of the p-type first body layer 102 is, for example. It is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 .

The preferable range of the impurity concentration in the n ⁺⁺ type source region 103 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 . The preferable range of the impurity concentration of the n ⁺ type current diffusion layer 105 is, for example, 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 . The preferred range of the impurity concentration of the p-type second body layer 104 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^-3 , and the preferable range of the maximum impurity concentration of the p-type second body layer 104 is, for example. It is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 . The preferable range of the impurity concentration in the p ⁺⁺ type body layer potential fixing region 109 is, for example, the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^-3 .

The channel region is the surface of the p-shaped first body layer 102 exposed on the side and bottom surfaces of the trench 106 along the x direction. ^{Further, the JFET region 10 is sandwiched between an n-} type epitaxial layer 101 sandwiched between p-type second body layers 104 facing each other in the x direction and n-type first body layer 102 sandwiched between p-type first body layers 102 facing each other in the x direction. ⁻ Type epitaxial layer 101.

A gate insulating film 110 is formed on the channel region, and a gate electrode 111 is formed on the gate insulating film 110. However, as described above, the gate electrode 111, n sandwiched ^{n +} -type current spreading layer 105 facing each other in the x-direction ^- not formed in the above type of epitaxial layer 101, JFET region of the gate electrode 111 The end on the 10 side is on the n ⁺ type current diffusion layer 105 via the gate insulating film 110. In addition, reference numeral 108 shown in FIG. 4 and FIG. These are electrodes, which will be described later in the method for manufacturing a semiconductor device.

Next, the features of the configuration of the SiC power MISFET according to the first embodiment will be described with reference to FIG.

As shown in FIG. 3, in the SiC power MISFET according to the first embodiment, the surface of the p-shaped first body layer 102 exposed on the side surface and the bottom surface of the trench 106 along the x direction is the channel region. Thereby, for example, when a substrate having a 4 ° off Si (0001) plane is used, the (11-2) plane or the (1-100) plane can be used as the channel plane. Therefore, in the SiC power MISFET according to the first embodiment, higher channel mobility can be expected as compared with the SiC power MISFET whose channel surface is the upper surface of ^{the n-type epitaxial layer 101, that is, the (0001) plane.}

Further, in the SiC power MISFET according to the first embodiment, by forming the trench 106, the channel width becomes larger and a higher current density can be expected as compared with the SiC power MISFET that does not form the trench 106. Further, the trench 106 is formed within a range shallower than the depth of the p-type first body layer 102, and the bottom surface of the trench 106 is surrounded by the p-type first body layer 102. Therefore, in the SiC power MISFET according to the first embodiment, as compared with the trench type SiC power MISFET having a trench portion exposed from the p-type first body layer 102, the gate formed on the inner wall of the trench 106 when the withstand voltage is maintained. The electric field applied to the insulating film 110 can be relaxed.

Further, in the SiC power MISFET according to the first embodiment, the impurity concentration of the n ⁺ type current diffusion layer 105 is higher than the impurity concentration of the JFET region 10 composed ^{of the n − type epitaxial layer 101.} However, since the p-type second body layer 104 is formed directly under ^{the n + type current diffusion layer 105, the equipotential lines are not affected by the n +} type current diffusion layer 105 and p when off. From the lower part of the first body layer 102 of the mold to the lower part of the second body layer 104 of the p-type, the current changes horizontally and gently along the main surface of ^{the n + type SiC substrate 107.} Therefore, the electric field applied to the gate insulating film 110 can be sufficiently reduced. Further, the n ⁺ type current diffusion layer 105 has a high impurity concentration in which the depletion layer does not easily grow when it is off, but it is formed only directly above the p-type second body layer 104, and its area is kept to the minimum necessary. Therefore, the feedback capacity can be reduced. Therefore, the switching speed can be improved and an erroneous arc can be prevented.

As described above, the SiC power MISFET according to the first embodiment has a high channel mobility and a wide channel width, so that a high current density can be obtained and a high reliability of the gate insulating film 110 can be obtained. Further, ^{by suppressing the area of the n +} type current diffusion layer 105 to the minimum necessary, the Miller effect generated during switching can be reduced, and the switching loss can be reduced. In addition, it is possible to prevent an erroneous arc. From these facts, it is possible to provide a semiconductor device composed of a SiC power MISFET having high performance and high reliability.

≪Manufacturing method of semiconductor devices≫
The method for manufacturing a semiconductor device according to the first embodiment will be described in order of steps with reference to FIGS. 6 to 23. FIG. 6 is a process diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment. 7 to 12 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the first embodiment. FIG. 13 is a plan view of the SiC power MISFET in the manufacturing process of the semiconductor device according to the first embodiment. 14 to 23 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 14 is a cross-sectional view taken along the line CC of FIG. , FIG. 15 is a cross-sectional view taken along the line DD of FIG.

<Process P1>
First, as shown in FIG. 7, an n ⁺ type 4H-SiC substrate 107 is prepared. An n-type impurity is introduced into the ^{n + -type SiC substrate 107.} The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, in the range of ^{1 × 10 18} to 1 × 10 ²¹ cm ^-3. Further, the n ⁺ type SiC substrate 107 has both Si and C surfaces, but ^{the surface of the n +} type SiC substrate 107 may be either the Si surface or the C surface.

Next, ^{an n-} type epitaxial layer 101 of ^{silicon carbide (SiC) is formed on the surface (first main surface) of the n +} type SiC substrate 107 by an epitaxial growth method. the n ^- -type epitaxial layer 101, ^{n +} -type low n-type impurity than the impurity concentration of the SiC substrate 107 has been introduced. The impurity concentration of the n ^- type epitaxial layer 101 depends on the element rating of the SiC power MISFET, and is in the range of ^{, for example, 1 × 10 14} to 1 × 10 ¹⁷ cm ^-3. Further, n ^- -type epitaxial layer thickness 101 is, for example, 5 to 50 [mu] m. Through the above steps, a ^{SiC epitaxial substrate 100 composed of an n +} type SiC substrate 107 and an n ⁻ -type epitaxial layer 101 is formed.

<Process P2>
Next, an n ⁺ type drain region 108 is formed on the back surface of the n ⁺ type SiC substrate 107 having a predetermined depth from the back surface (second main surface) of the n ^{+ type SiC substrate 107.} The impurity concentration of the n ⁺ type drain region 108 is, for example, in the range of ^{1 × 10 19} to 1 × 10 ²¹ cm ^-3.

Next, as shown in FIG. 8, a mask M11 is formed on the surface of the SiC epitaxial substrate 100. The thickness of the mask M11 is, for example, about 1 to 3 μm. The width of the mask M11 in the element forming region is, for example, about 1 to 5 μm. As the mask material, an inorganic material silicon oxide (SiO ₂ ) film, silicon (Si) film or silicon nitride (SiN) film, or an organic material resist film or polyimide film can be used.

Next, a p-type impurity, for example, an aluminum (Al) atom, is ion-implanted into the ^n- type epitaxial layer 101 through the mask M11. As a result, the p-type first body layer 102 is formed in the element forming region ^{of the n-type epitaxial layer 101.} At the same time, a p-type floating field limiting ring (not shown) is formed in the peripheral formation region. The structure of the terminal portion is not limited to this, and may be, for example, a Junction Termination Extension (JTE) structure.

The depth of the p-type first body layer 102 ^{from the upper surface of the n-} type epitaxial layer 101 is, for example, about 0.5 to 2 μm. The impurity concentration of the p-type first body layer 102 is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3. The maximum impurity concentration of the p-type first body layer 102 is, for example, in the range of ^{1 × 10 17} to 1 × 10 ¹⁹ cm ^-3.

Next, as shown in FIG. 9, after removing the mask M11, the mask M12 is formed on the surface of the SiC epitaxial substrate 100. The mask M12 is formed of, for example, a silicon oxide (SiO ₂ ) film. The thickness of the mask M12 is, for example, about 0.5 to 3 μm. The channel length is determined by the dimensions of the mask M12, and the width of the mask M12 in the direction of the channel length is, for example, about 0.1 to 2 μm.

Next, as shown in FIG. 10, the mask M13 is formed on the surface of the SiC epitaxial substrate 100 while leaving the mask M12. The mask M13 is formed of, for example, a resist film. The thickness of the mask M13 is, for example, about 1 to 4 μm. The opening portion of the mask M13 is provided in the n ⁺⁺ type source region 103 forming portion and a part of the mask M12. The mask M13 is also provided with an opening portion on the outer circumference of the p-type floating field limiting ring and ^{in the region where the n ++ type guard ring is formed.}

Next, n-type impurities such as nitrogen (N) atoms or phosphorus (P) atoms are ion-implanted into the p-type first body layer 102 through the masks M12 and M13. Thus, the ^{n ++} -type source region 103 is formed in the p-type first body layer 102, ^{n ++} type guard ring surrounding formation region (not shown) is formed.

Next, as shown in FIG. 11, after removing the mask M13, the mask M14 is formed on the surface of the SiC epitaxial substrate 100 while leaving the mask M12. The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, about 1 to 4 μm. The opening portion of the mask M14 is provided in the n ⁺ type current diffusion layer 105 forming portion, the p-type second body layer 104 forming portion, and a part of the mask M12.

^{Next, p-type impurities are ion-implanted into the n-} type epitaxial layer 101 and the p-type first body layer 102 through the mask M12 and the mask M14 to form the p-type second body layer 104. Subsequently, an n-type impurity is ion-implanted to form an n ⁺ -type current diffusion layer 105.

Next, as shown in FIG. 12, the mask M12 and the mask M14 are removed. Subsequently, the mask M15 is formed on the surface of the SiC epitaxial substrate 100. The mask M15 is formed of, for example, a resist film. The thickness of the mask M15 is, for example, about 0.5 to 3 μm. The opening portion of the mask M15 is provided in the p ⁺⁺ type body layer potential fixing region 109 forming portion.

Next, p-type impurities are ionically injected into the p-type first body layer 102 through the mask M15 to form a p ⁺⁺ type body layer potential fixing region 109. The depth of the p ⁺⁺ type body layer potential fixing region 109 ^{from the upper surface of the n −} type epitaxial layer 101 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the p ⁺⁺ type body layer potential fixing region 109 is, for example, in the range of ^{1 × 10 19} to 1 × 10 ²¹ cm ^-3.

<Process P3>
Next, after removing the mask M15, although not shown, a carbon (C) film is deposited on the front surface and the back surface of the SiC epitaxial substrate 100 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front surface and the back surface of the SiC epitaxial substrate 100 with this carbon (C) film, the SiC epitaxial substrate 100 is heat-treated at a temperature of, for example, 1500 ° C. or higher for about 2 to 3 minutes. As a result, each impurity ion-implanted into the SiC epitaxial substrate 100 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

<Process P4>
Next, as shown in FIGS. 13, 14 and 15, a mask M16 is formed on the surface of the SiC epitaxial substrate 100. The mask M16 is formed of, for example, a resist film. FIG. 14 is a cross-sectional view taken along the line CC of FIG. 13, and FIG. 15 is a cross-sectional view taken along the line DD of FIG. The thickness of the mask M16 is, for example, about 0.5 to 3 μm. The opening portion of the mask M16 is provided in the trench 106 forming portion.

Next, the n ⁻ type epitaxial layer 101 is processed by a ^{dry etching method, and the n +} type current diffusion layer 105 is applied ^{from the n ++} type source region 103 to the p type first body layer 102. The trench 106 is formed so as to extend. The trench 106 is formed shallower than the depth of the p-shaped first body layer 102. The depth of the trench 106 is, for example, about 0.1 to 1.5 μm. The length in the direction parallel to the channel length of the trench 106 is, for example, about 1 to 3 μm. The length of the trench 106 in the direction parallel to the channel width is, for example, about 0.1 to 2 μm. The distance in the direction parallel to the channel width of the trench 106 is, for example, about 0.1 to 2 μm.

<Process P5>
Next, as shown in FIG. 16, after removing the mask M16, n ^- to form the gate insulating film 110 on the inner wall of the upper surface and the trench 106 of the type epitaxial layer 101 (side surface and bottom surface). The gate insulating film 110 is formed by, for example, a thermal CVD method, and is made of, for example, a silicon oxide (SiO ₂ ) film. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

Next, as shown in FIG. 17, an n-type polycrystalline silicon (Si) film 111A is formed on the gate insulating film 110. The thickness of the n-type polycrystalline silicon (Si) film 111A is, for example, about 0.01 to 4 μm.

Next, as shown in FIG. 18, a mask M17 is formed on the surface of the SiC epitaxial substrate 100. The mask M17 is formed of, for example, a resist film. The opening portion of the mask M17 is provided in a region other than the gate electrode 111 forming portion. Next, the polycrystalline silicon (Si) film 111A is processed by a dry etching method to form a gate electrode 111. At this time, the polycrystalline silicon (Si) film 111A above the JFET region sandwiched between the p-type first body layers 102 facing each other is removed.

Next, after removing the mask M17, a dry oxidation heat treatment is performed at a temperature of, for example, 900 ° C. for about 30 minutes to light-oxidize the gate electrode 111.

<Process P6>
Next, as shown in FIG. 19, so as to cover the gate electrode 111 and the gate insulating film 110, n ^- the upper surface of the type epitaxial layer 101, an interlayer insulating film 112 by, for example, a plasma CVD method.

Next, as shown in FIG. 20, a mask M18 is formed on the surface of the SiC epitaxial substrate 100. The mask M18 is formed of, for example, a resist film. The opening portion of the mask M18 is provided in a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential fixing region 109. Next, the interlayer insulating film 112 and the gate insulating film 110 are processed by a dry etching method to ^{form a part of the n ++} type source region 103 and the ^{opening CNT reaching the p ++} type body layer potential fixing region 109. ..

Next, as shown in FIG. 21, after removing the mask M18, a part of the n ⁺⁺ type source region 103 ^{exposed on the bottom surface of the opening CNT and the p ++} type body layer potential fixing region 109, respectively. A metal silicide layer 113 is formed on the surface of the above.

The metal silicide layer 113 can be formed, for example, by the following procedure. First, so as to cover the inner wall (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT, n ^- the upper surface of the type epitaxial layer 101, for example, depositing a first metal film by sputtering. The first metal film is, for example, nickel (Ni). The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing the silicidation heat treatment at about 600 to 1000 ° C., the first metal film and the n at the bottom of the opening CNT ^- reacting the epitaxial layer 101 of the mold, it is exposed to the bottom surface of the opening CNT A metal silicide layer 113 is formed on a ^{part of the n ++} type source region 103 and ^{on each surface of the p ++ type body layer potential fixing region 109.} The metal silicide layer 113 is, for example, a nickel silicide (NiSi) layer. Subsequently, the unreacted first metal film is removed by a wet etching method. For the wet etching method, for example, sulfuric acid hydrogen peroxide is used.

Next, the interlayer insulating film 112 is processed by a dry etching method using a mask to form an opening (not shown) that reaches the gate electrode 111.

Next, as shown in FIG. 22, an ^{opening CNT reaching a part of the n ++} type source region 103 and ^{the surface of each of the p ++} type body layer potential fixing region 109 and the metal silicide film 113 formed, and A second metal film is deposited on the interlayer insulating film 112 including the inside of the opening (not shown) that reaches the gate electrode 111. The second metal film is, for example, a laminated film composed of a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example.

Next, the second metal film is processed by a tri-etching method using a mask, and a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer potential are formed through the metal VDD layer 113 in the opening CNT. A source wiring electrode 114 that is electrically connected to the fixed region 109, and a gate wiring electrode (not shown) that is electrically connected to the gate electrode 111 through an opening (not shown) are formed.

Next, a passivation film (not shown) is formed so as to cover the source wiring electrode 114 and the gate wiring electrode. The passivation film is made of, for example, a silicon oxide (SiO ₂ ) film or a polyimide film.

Next, the passivation film is processed to form a source opening (not shown) that exposes the upper surface of the source wiring electrode 114 and a gate opening (not shown) that exposes the upper surface of the gate wiring electrode (not shown). (See FIG. 1).

Next, a third metal film is deposited on the back surface (n ⁺ type drain region 108) of the SiC epitaxial substrate 100 by, for example, a sputtering method. The thickness of the third metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 23, a laser silicidizing heat treatment is performed to ^{react the third metal film with the n +} type drain region 108 so as to cover the ^{n + type drain region 108.} Form 115. Subsequently, the drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. The drain wiring electrode 116 is made of, for example, a laminated film composed of a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film, and its thickness is, for example, about 0.5 to 1 μm.

After that, external wiring is electrically connected to the source wiring electrode 114, the gate wiring electrode, and the drain wiring electrode 116, respectively.

As described above, according to the first embodiment, a high current density can be obtained in the SiC power MISFET, and a high reliability of the gate insulating film can be obtained. Further, the Miller effect generated during switching can be reduced, and the switching loss can be reduced. In addition, it is possible to prevent an erroneous arc. From these facts, it is possible to provide a semiconductor device composed of a plurality of SiC power MISFETs having high performance and high reliability.

The difference between the second embodiment and the first embodiment is that the hard mask used when forming the trench 106 is left as a field oxide film.

≪Semiconductor device≫
The structure of the SiC power MISFET according to the second embodiment will be described with reference to FIG. 24. FIG. 24 is a cross-sectional view in a direction parallel to the channel length of the SiC power MISFET according to the second embodiment.

As shown in FIG. 24, by leaving the hard mask used when forming the trench 106 as the field oxide film 117, it is ^{located above the n +} type current diffusion layer 105 and the n ⁺ type current diffusion layer 105. Since the field oxide film 117 and the gate insulating film 110 are sandwiched between the gate electrode 111 and the gate electrode 111, a structure having high insulation between the two can be obtained. As a result, the SiC power MISFET according to the second embodiment can reduce the electric field applied to the gate insulating film 110 when it is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

≪Manufacturing method of semiconductor devices≫
The method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 25 to 28. FIG. 25 is a plan view of the SiC power MISFET in the manufacturing process of the semiconductor device according to the second embodiment. 26 to 28 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the second embodiment, and FIG. 26 is a cross-sectional view taken along the line EE of FIG. 27 is a cross-sectional view taken along the line FF of FIG. 25.

Since the step of forming the trench 106 (the manufacturing process described with reference to FIGS. 7 to 12) is the same as that of the first embodiment, the description thereof will be omitted.

As shown in FIGS. 25 to 27, a field oxide film 117 that doubles as a hard mask for forming the trench 106 and a field oxide film is formed. For the field oxide film 117, for example, a silicon oxide (SiO ₂ ) film is used. The thickness of the field oxide film 117 is, for example, about 0.1 to 1 μm. The field oxide film 117 is provided with an opening in the region where the trench 106 is formed in a later step.

Next, the n ⁻ type epitaxial layer 101 is processed by a ^{dry etching method, and the n +} type current diffusion layer 105 is applied ^{from the n ++} type source region 103 to the p type first body layer 102. The trench 106 is formed so as to extend. The trench 106 is formed shallower than the depth of the p-shaped first body layer 102. The depth of the trench 106 is, for example, about 0.1 to 1.5 μm. The length in the direction parallel to the channel length of the trench 106 is, for example, about 1 to 3 μm. The length of the trench 106 in the direction parallel to the channel width is, for example, about 0.1 to 2 μm. The trench spacing in the direction parallel to the channel width of the trench 106 is, for example, about 0.1 to 2 μm.

Next, as shown in FIG. 28, the gate insulating film 110 is formed on the upper surface of the field oxide film 117 and the inner wall (side surface and bottom surface) of the trench 106 without removing the field oxide film 117. The gate insulating film 110 is made of, for example, a silicon oxide (SiO ₂ ) film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

After that, the SiC power MISFET according to the second embodiment shown in FIG. 24 is substantially completed by the same manufacturing process as the first embodiment described above.

As described above, the SiC power MISFET according to the second embodiment has a structure in which a relatively thick insulating film is sandwiched between the upper corner portion of the trench 106 and the gate electrode 111. Compared to the indicated SiC power MOSFET, it is possible to reduce the electric field applied to the gate insulating film 110 when it is off. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

The difference between the third embodiment and the first embodiment is that a p-type electric field relaxation layer is formed on the ^{n + type current diffusion layer 105.}

≪Semiconductor device≫
The structure of the SiC power MISFET according to the third embodiment will be described with reference to FIG. 29. FIG. 29 is a bird's-eye view of the SiC power MOSFET according to the third embodiment.

As shown in FIG. 29, a p-type electric field relaxation layer 118 is provided ^{above the n + type current diffusion layer 105.} By forming the p-type electric field relaxation layer 118, it is possible to reduce the electric field applied to the gate insulating film 110 when it is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

≪Manufacturing method of semiconductor devices≫
The method of manufacturing the semiconductor device according to the third embodiment will be described with reference to FIGS. 30 and 31. 30 and 31 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the third embodiment.

The steps (manufacturing process described with reference to FIGS. 7 to 11) until the n ⁺ type current diffusion layer 105 and the p-type second body layer 104 are formed are the same as those in the above-described first embodiment. Therefore, the description thereof will be omitted.

As shown in FIG. 30, the mask M14 is formed while leaving the mask M12 in the same manner as in the first embodiment. The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, about 1 to 4 μm. The opening portion of the mask M14 is provided in a p-type electric field relaxation layer 118 forming portion, an n ⁺ type current diffusion layer 105 forming portion, a p-type second body layer 104 forming portion, and a part of the mask M12.

^{Next, p-type impurities are ion-implanted into the n-} type epitaxial layer 101 and the p-type first body layer 102 through the mask M12 and the mask M14 to form the p-type second body layer 104. Subsequently, an n-type impurity is ion-implanted to form an n ⁺ -type current diffusion layer 105. Subsequently, p-type impurities are ion-implanted to form the p-type electric field relaxation layer 118. The impurity concentration of the p-type electric field relaxation layer 118 is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3. The distance between the p-type electric field relaxation layer 118 sandwiching the n ⁺ type current diffusion layer 105 and the p-type second body layer 104 is about 0.1 to 1 μm.

After that, the SiC power MISFET according to the third embodiment shown in FIG. 31 is substantially completed by the same manufacturing process as the first embodiment described above.

As described above, the SiC power MISFET according to the third embodiment has the p-type electric field relaxation layer 118 electrically connected to the p-type first body layer 102 above the n ⁺ type current diffusion layer 105. Therefore, it is possible to reduce the electric field applied to the gate insulating film 110 when it is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

The difference between this Example 4 and the above-mentioned Example 1 is that ^{the upper part of the n +} type current diffusion layer 105 and the upper part ^{of the n −} type epitaxial layer 101 ^{between the n +} type current diffusion layers 105 facing each other. This is a point where a p-type electric field relaxation layer is formed.

≪Semiconductor device≫
The structure of the SiC power MISFET according to the fourth embodiment will be described with reference to FIG. FIG. 32 is a bird's-eye view of the SiC power MISFET according to the fourth embodiment.

As shown in FIG. 32, n between the ^{n +} -type current spreading layer top and facing each other ^{n +} -type current spreading layer 105 of 105 ^- p-type electric field relaxation layer 119 is provided above the type epitaxial layer 101 Has been done. By forming the p-type electric field relaxation layer 119, it is possible to reduce the electric field applied to the gate insulating film 110 when it is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

≪Manufacturing method of semiconductor devices≫
The method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS. 33 and 34. 33 and 34 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the fourth embodiment.

The steps (manufacturing process described with reference to FIGS. 7 to 11) until the n ⁺ type current diffusion layer 105 and the p-type second body layer 104 are formed are the same as those in the above-described first embodiment. Therefore, the description thereof will be omitted.

First, in the same manner as in Example 1 described above, the mask M14 is formed while leaving the mask M12 (see FIG. 11). The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, about 1 to 4 μm. The opening portion of the mask M14 is provided in a p-type electric field relaxation layer 118 forming portion, an n ⁺ type current diffusion layer 105 forming portion, a p-type second body layer 104 forming portion, and a part of the mask M12.

^{Next, p-type impurities are ion-implanted into the n-} type epitaxial layer 101 and the p-type first body layer 102 through the mask M12 and the mask M14 to form the p-type second body layer 104. Subsequently, an n-type impurity is ion-implanted to form an n ⁺ -type current diffusion layer 105. Subsequently, p-type impurities are ion-implanted to form a ^{p-type electric field relaxation layer 118 on the n +} type current diffusion layer 105 (see FIG. 30). The impurity concentration of the p-type electric field relaxation layer 118 is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3.

Next, as shown in FIG. 33, the mask M12 and the mask M14 are removed. Subsequently, the mask M19 is formed on the surface of the SiC epitaxial substrate 100. The mask M19 is formed of, for example, a resist film. The thickness of the mask M19 is, for example, about 1 to 4 μm. The opening portion of the mask M19 is provided above the JFET region located between the p-shaped first body layers 102 facing each other.

Next, a p-type impurity is ion-implanted into the upper part of ^{the n − -type epitaxial layer 101 between the n +} -type current diffusion layers 105 facing each other through the mask M19 to form the p-type electric field relaxation layer 118A. .. The impurity concentration of the p-type electric field relaxation layer 118A is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3. Thus, the electric field relaxation layer 118 of p-type formed in an upper portion of the n ⁺ -type current spreading layer 105, n between the opposed n ⁺ -type current spreading layer 105 to each other ^- forming on top of the type epitaxial layer 101 The p-type electric field relaxation layer 118A and the p-type electric field relaxation layer 119 are formed.

After that, the SiC power MISFET according to the fourth embodiment shown in FIG. 34 is substantially completed by the same manufacturing process as the first embodiment described above.

As described above, in the SiC power MISFET according to the fourth embodiment, the p-type electric field relaxation layer 119 electrically connected to the p-type first body layer 102 ^{faces the upper part of the n +} type current diffusion layer 105 and each other. ^{It is provided above the n-} type epitaxial layer 101 (above the JFET region) between the n ⁺ type current diffusion layers 105. This makes it possible to reduce the electric field applied to the gate insulating film 110 when the gate insulating film 110 is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

The difference between the fifth embodiment and the first embodiment is that ^{the upper part of the n +} type current diffusion layer 105 and the upper part ^{of the n −} type epitaxial layer 101 ^{between the n +} type current diffusion layers 105 facing each other. This is a point where a p-type electric field relaxation layer is formed. Further, in addition to this, between the p-type first body layers 102 facing each other, between the p-type second body layers 104 facing each other, and between the n ⁺ -type current diffusion layers 105 facing each other, the p-type field relaxation layer n is not formed ^- -type epitaxial layer 101, a point which forms a high-concentration region of the n-type.

≪Semiconductor device≫
The structure of the SiC power MISFET according to the fifth embodiment will be described with reference to FIG. 35. FIG. 35 is a bird's-eye view of the SiC power MOSFET according to the fifth embodiment.

As shown in FIG. 35, n between the ^{n +} -type current spreading layer top and facing each other ^{n +} -type current spreading layer 105 of 105 ^- p-type electric field relaxation layer 119 is provided above the type epitaxial layer 101 Has been done. By forming the p-type electric field relaxation layer 119, it is possible to reduce the electric field applied to the gate insulating film 110 when it is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented.

Further, between the p-type first body layers 102 facing each other, between the p-type second body layers 104 facing each other, and between the n ⁺ -type current diffusion layers 105 facing each other, the p-type electric field relaxation layer 119. but n is not formed ^- -type epitaxial layer 101, the high concentration region 120 of the n-type is provided. The impurity concentration in the n ^- type high concentration region 120 is higher than the impurity concentration in the n-type epitaxial layer 101, and is in the range of, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. Further, is the depth of the n-type high concentration region 120 ^{from the upper surface of the n-} type epitaxial layer 101 the same as the depth of the p-type first body layer 102 from the upper surface of ^{the n-type epitaxial layer 101?} Or deeper than that.

By forming the n-type high concentration region 120, it is possible to reduce the JFET resistance, which is one of the parasitic resistances. Generally, when the impurity concentration in the n-type high concentration region 120 is high, the electric field applied to the gate insulating film 110 tends to be high. However, in the fifth embodiment, since the p-type electric field relaxation layer 119 is formed above the p-type second body layer 104 and the n-type high concentration region 120, the electric field applied to the gate insulating film 110 is applied. It can be reduced.

≪Manufacturing method of semiconductor devices≫
The method of manufacturing the semiconductor device according to the fifth embodiment will be described with reference to FIGS. 36 and 37. 36 and 37 are cross-sectional views in a direction parallel to the channel length of the SiC power MISFET in the manufacturing process of the semiconductor device according to the fifth embodiment.

Since ^{the steps (FIGS. 7 to 11) until the n +} type current diffusion layer 105 and the p-type second body layer 104 are formed are the same as those in the first embodiment, the description thereof will be omitted. ..

First, in the same manner as in Example 1 described above, the mask M14 is formed while leaving the mask M12 (see FIG. 11). The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, about 1 to 4 μm. The opening portion of the mask M14 is provided in a p-type electric field relaxation layer 118 forming portion, an n ⁺ type current diffusion layer 105 forming portion, a p-type second body layer 104 forming portion, and a part of the mask M12.

^{Next, p-type impurities are ion-implanted into the n-} type epitaxial layer 101 and the p-type first body layer 102 through the mask M12 and the mask M14 to form the p-type second body layer 104. Subsequently, an n-type impurity is ion-implanted to form an n ⁺ -type current diffusion layer 105. Subsequently, p-type impurities are ion-implanted to form a ^{p-type electric field relaxation layer 118 on the n +} type current diffusion layer 105 (see FIG. 30). The impurity concentration of the p-type electric field relaxation layer 118 is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3.

Next, as shown in FIG. 36, the mask M12 and the mask M14 are removed. Subsequently, the mask M20 is formed on the surface of the SiC epitaxial substrate 100. The mask M20 is formed of, for example, a resist film. The thickness of the mask M20 is, for example, about 1 to 4 μm. The opening portion of the mask M20 is provided above the JFET region located between the p-shaped first body layers 102 facing each other.

Next, the mask M20 over, n ^- and ion-implanting an n-type impurity into the -type epitaxial layer 101, to form a high concentration region 120 of the n-type. The impurity concentration in the n-type high concentration region 120 is, for example, in the range of ^{1 × 10 15} to 1 × 10 ¹⁸ cm ^-3. Further, n in n-type heavily doped region 120 ^- the depth from the upper surface of the type epitaxial layer 101, n of the p-type first body layer 102 of the ^- deeper than the depth from the upper surface of the type epitaxial layer 101.

^{Subsequently, p-type impurities are ion-implanted into the upper part of the n- type epitaxial layer 101 between the n +} type current diffusion layers 105 facing each other to form the p-type electric field relaxation layer 118A (see FIG. 33). .. The impurity concentration of the p-type boundary relaxation layer 118A is, for example, in the range of ^{1 × 10 16} to 1 × 10 ¹⁹ cm ^-3. Thus, the electric field relaxation layer 118 of p-type formed in an upper portion of the n ⁺ -type current spreading layer 105, n between the opposed n ⁺ -type current spreading layer 105 to each other ^- forming on top of the type epitaxial layer 101 The p-type electric field relaxation layer 118A and the p-type electric field relaxation layer 119 are formed.

After that, the SiC power MISFET according to the fifth embodiment shown in FIG. 37 is substantially completed by the same manufacturing process as the first embodiment described above.

As described above, in the SiC power MISFET according to the fifth embodiment, the p-type electric field relaxation layer 119 electrically connected to the p-type first body layer 102 ^{faces the upper part of the n +} type current diffusion layer 105 and each other. ^{It is provided above the n-} type epitaxial layer 101 (above the JFET region) between the n ⁺ type current diffusion layers 105. This makes it possible to reduce the electric field applied to the gate insulating film 110 when the gate insulating film 110 is off, as compared with the SiC power MISFET shown in the first embodiment. Further, since the electric capacitance between the gate electrode 111 and the n ⁺ type current diffusion layer 105 is reduced, switching loss can be reduced and erroneous arc can be prevented. In addition, n ^- by forming a high concentration region 120 of high n-type impurity concentration than the epitaxial layer 101 of the mold, it is possible to reduce the JFET resistance which is one of the parasitic resistance.

(First modification of Example 5)
The SiC power MISFET according to the first modification of the fifth embodiment will be described with reference to FIGS. 38 and 39. FIG. 38 is a bird's-eye view of the SiC power MISFET according to the first modification of the fifth embodiment. FIG. 39 is a cross-sectional view in a direction parallel to the channel length of the SiC power MISFET according to the first modification of the fifth embodiment.

As shown in FIGS. 38 and 39, in the SiC power MISFET according to the first modification of the fifth embodiment, the depth from the upper surface of ^{the n-type epitaxial layer 101 of the n-type high concentration region 120A is p-type.} Is shallower than the depth from the upper surface of ^{the n-} type epitaxial layer 101 of the first body layer 102, and is the same as the depth from the upper surface of ^{the n-type epitaxial layer 101 of the p-type second body layer 104.} Or deeper than that. For high-voltage element, n ^- type low impurity concentration of the epitaxial layer 101, the first body layer 102 of p-type is likely to be deeply formed. Therefore, by making the depth of the n-type high concentration region 120A shallower than the depth of the p-type first body layer 102, the process can be facilitated and the manufacturing price can be lowered.

(Second modification of Example 5)
The SiC power MISFET according to the second modification of the fifth embodiment will be described with reference to FIGS. 40 and 41. FIG. 40 is a bird's-eye view of the SiC power MISFET according to the second modification of the fifth embodiment. FIG. 41 is a cross-sectional view in a direction parallel to the channel length of the SiC power MISFET according to the second modification of the fifth embodiment.

As shown in FIGS. 40 and 41, in the SiC power MISFET according to the second modification of the fifth embodiment, the depth from the upper surface of ^{the n-type epitaxial layer 101 of the n-type high concentration region 120B is p-type.} It is shallower than the depth from the upper surface of ^{the n-} type epitaxial layer 101 of the second body layer 104. For high-voltage element, n ^- type low impurity concentration of the epitaxial layer 101, the first body layer 102 of p-type is likely to be deeply formed. Therefore, by making the depth of the n-type high concentration region 120B shallower than the depth of the p-type second body layer 104, the process can be facilitated and the manufacturing price can be lowered.

The semiconductor device composed of the plurality of SiC power MISFETs described in Examples 1 to 5 described above can be used as a power conversion device.

The power conversion device according to the sixth embodiment will be described with reference to FIG. 42. FIG. 42 is a circuit diagram showing an example of the power conversion device (inverter) according to the sixth embodiment.

As shown in FIG. 42, the inverter 802 has a SiC power MISFET 804 and a diode 805, which are switching elements. In each single phase, the SiC power MISFET 804 and the diode 805 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of the load (for example, motor) 801 (upper arm), and the input potential of the load 801 is connected. The SiC power MOSFET element 804 and the diode 805 are also connected in antiparallel between the ground potential (GND) and the ground potential (GND) (lower arm).

That is, in the load 801, two SiC power MISFETs 804 and two diodes 805 are provided in each single phase, and six SiC power MISFETs 804 and six diodes 805 are provided in three phases. A control circuit 803 is connected to the gate electrode of each SiC power MISFET 804, and the SiC power MISFET 804 is controlled by the control circuit 803. Therefore, the load 801 can be driven by controlling the current flowing through the SiC power MISFET 804 constituting the inverter 802 with the control circuit 803.

The functions of the SiC power MISFET 804 constituting the inverter 802 will be described below.

In order to control and drive the load 801 such as the motor, it is necessary to input a sine wave of a desired voltage to the load 801. The control circuit 803 controls the SiC power MISFET 804 and performs a pulse width modulation operation that dynamically changes the pulse width of the square wave. The output square wave is smoothed by passing through the inductor to become a pseudo desired sine wave. The SiC power MISFET 804 has a function of creating a rectangular wave for performing this pulse width modulation operation.

As described above, according to the sixth embodiment, by using the semiconductor device described in the first to fifth embodiments described above for the SiC power MISFET 804, the SiC power MISFET 804 has a higher performance, for example, the inverter 802 or the like. The performance of the power converter can be improved. Further, since the SiC power MISFET 804 has long-term reliability, the years of use of the power conversion device such as the inverter 802 can be extended.

Further, the power conversion device can be used for a three-phase motor system. The load 801 shown in FIG. 42 is a three-phase motor, and by using the power conversion device including the semiconductor device described in the first to fifth embodiments described above for the inverter 802, the performance of the three-phase motor system is high. It is possible to realize a long-term use and a long period of use.

The semiconductor device composed of the plurality of SiC power MISFETs described in Examples 1 to 5 described above can be used as a power conversion device.

The power conversion device according to the seventh embodiment will be described with reference to FIG. 43. FIG. 43 is a circuit diagram showing an example of the power conversion device (inverter) according to the seventh embodiment.

As shown in FIG. 43, the inverter 902 has a SiC power MISFET 904 which is a switching element. In each single phase, a SiC power MOSFET 904 is connected between the power supply voltage (Vcc) and the input potential of the load (for example, motor) 901 (upper arm), and the input potential of the load 901 and the ground potential (GND). A SiC power MISFET element 904 is also connected between them (lower arm).

That is, in the load 901, two SiC power MISFETs 904 are provided in each single phase, and six SiC power MISFETs 904 are provided in three phases. A control circuit 903 is connected to the gate electrode of each SiC power MISFET 904, and the SiC power MISFET 904 is controlled by the control circuit 903. Therefore, the load 901 can be driven by controlling the current flowing through the SiC power MISFET 904 constituting the inverter 902 with the control circuit 903.

The functions of the SiC power MISFET 904 constituting the inverter 902 will be described below.

Also in the seventh embodiment, as one of the functions of the SiC power MISFET 904, as in the sixth embodiment described above, there is a function of creating a rectangular wave for performing the pulse width modulation operation. Further, in the seventh embodiment, the SiC power MISFET 904 also plays the role of the diode 805 described in the sixth embodiment. In the inverter 902, when the load 901 includes an inductance, for example, a motor, when the SiC power MISFET 904 is turned off, the energy stored in the inductance must be released (reflux current). In the sixth embodiment described above, the diode 805 plays this role. On the other hand, in the seventh embodiment, the SiC power MISFET 904 plays this role. That is, synchronous rectification drive is used. Here, the synchronous rectification drive is a method of turning on the gate of the SiC power MISFET 904 at the time of reflux to reverse-conduct the SiC power MISFET 904.

Therefore, the conduction loss at reflux is determined not by the characteristics of the diode but by the characteristics of the SiC power MISFET 904. Further, when the synchronous rectification drive is performed, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiC power MISFETs 904 are turned off. During this non-operation time, the built-in PN diode formed by the drift layer of the SiC power MISFET 904 and the p-type body layer is driven. However, the mileage of the silicon carbide (SiC) carrier is shorter than the mileage of the silicon (Si) carrier, and the loss during the non-operation time is small. For example, it is equivalent to the case where the diode 805 of the above-mentioned Example 6 is used as a SiC Schottky barrier diode.

As described above, according to the seventh embodiment, by using the semiconductor device described in the above-mentioned Examples 1 to 5 for the SiC power MISFET 904, the SiC power MISFET 904 has a high performance, for example, a loss at reflux. Can also be made smaller. Further, since a diode is not used, the power conversion device such as the inverter 902 can be miniaturized. Further, since the SiC power MISFET 904 has long-term reliability, the years of use of the power conversion device such as the inverter 902 can be extended.

Further, the power conversion device can be used for a three-phase motor system. The load 901 shown in FIG. 43 is a three-phase motor, and by using the power conversion device including the semiconductor device described in the first to fifth embodiments described above for the inverter 902, the performance of the three-phase motor system is high. It is possible to realize a long-term use and a long period of use.

The power conversion device (three-phase motor system) described in the sixth or seventh embodiment can be used in an automobile such as a hybrid automobile, an electric vehicle, or a fuel cell vehicle.

The automobile according to the eighth embodiment will be described with reference to FIGS. 44 and 45. FIG. 44 is a schematic view showing an example of the configuration of the electric vehicle according to the eighth embodiment. FIG. 45 is a circuit diagram showing an example of a boost converter according to the eighth embodiment.

As shown in FIG. 44, the electric vehicle has a three-phase motor 1003 capable of inputting and outputting power to a drive shaft 1002 to which the drive wheels 1001a and the drive wheels 1001b are connected, and an inverter 1004 for driving the three-phase motor 1003. And a battery 1005. Further, this electric vehicle includes a boost converter 1008, a relay 1009, and an electronic control unit 1010, and the boost converter 1008 includes a power line 1006 to which the inverter 1004 is connected and a power line 1007 to which the battery 1005 is connected. And are connected to.

The three-phase motor 1003 is a synchronous generator motor including a rotor in which a permanent magnet is embedded and a stator in which a three-phase coil is wound. As the inverter 1004, the inverter described in the above-mentioned Example 6 or Example 7 can be used.

As shown in FIG. 45, the boost converter 1008 has a configuration in which a reactor 1011 and a smoothing capacitor 1012 are connected to an inverter 1013. The inverter 1013 is, for example, the same as the inverter described in the above-mentioned Example 7, and the element configuration in the inverter 1013 is also the same. FIG. 45 shows a circuit diagram configured by the SiC power MISFET 1014 as in the above-mentioned Example 7, for example.

The electronic control unit 1010 shown in FIG. 44 includes a microprocessor, a storage device, and an input / output port, and is a signal from a sensor that detects the rotor position of the three-phase motor 1003, or charging / discharging of the battery 1005. Receive values etc. Then, a signal for controlling the inverter 1004, the boost converter 1008, and the relay 1009 is output.

As described above, according to the eighth embodiment, the three-phase motor system described in the sixth or seventh embodiment can be used for the inverter 1004 and the boost converter 1008. Further, the three-phase motor system described in the sixth or seventh embodiment can be used for the three-phase motor system including the three-phase motor 1003 and the inverter 1004. As a result, it is possible to save energy, size, weight and space of the electric vehicle.

Although the electric vehicle has been described in the eighth embodiment, the hybrid vehicle that also uses the engine and the fuel cell vehicle in which the battery 1005 is a fuel cell stack have also been described in the above-described 6 or 7 embodiment. A phase motor system can be applied.

The power conversion device (three-phase motor system) described in the sixth or seventh embodiment can be used for a railway vehicle.

The railway vehicle according to the ninth embodiment will be described with reference to FIG. FIG. 46 is a circuit diagram showing an example of a converter and an inverter provided in a railway vehicle according to the ninth embodiment.

As shown in FIG. 46, electric power is supplied to the railroad vehicle from the overhead wire OW (for example, 25 kV) via the pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 1109 and converted from alternating current to direct current by the converter 1107. Further, it is converted from direct current to alternating current by the inverter 1102 via the capacitor 1108 to drive the three-phase motor which is the load 1101.

The element configuration in the converter 1107 may be a combination of a SiC power MISFET and a diode as in the above-mentioned Example 6, or a single SiC-power MISFET as in the above-mentioned Example 7. FIG. 46 shows a circuit diagram composed of the SiC power MISFET 1104 alone, for example, as in the above-mentioned Example 7. Further, in FIG. 46, the control circuit described in the above-described 6th or 7th embodiment is omitted. Further, in FIG. 46, reference numeral RT indicates a railroad track, and reference numeral WH indicates a wheel.

As described above, according to the ninth embodiment, the three-phase motor system described in the sixth or seventh embodiment can be used for the converter 1107. Further, the three-phase motor system described in the sixth or seventh embodiment can be used for the three-phase motor system including the load 1101, the inverter 1102, and the control circuit. As a result, it is possible to save energy in railway vehicles and to reduce the size and weight of underfloor parts.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

For example, the material, conductive type, manufacturing conditions, etc. of each part are not limited to the description of the above-described embodiment, and it goes without saying that many modifications can be made. Here, for convenience of explanation, the conductive type of the semiconductor substrate and the semiconductor film has been fixed and described, but the present invention is not limited to the conductive type described in the above-described embodiment.

1 Semiconductor chip 2 Source wiring electrode 3 Floating field limiting ring 4 Guard ring 5 Gate opening 7 Source opening 8 Gate wiring electrode 10 JFET region 100 SiC epitaxial substrate 101 epitaxial layer 102 first body layer 103 source Region 104 Second body layer 105 Current diffusion layer 106 Trench 107 SiC substrate 108 Drain area 109 Body layer Potential fixed region 110 Gate insulating film 111 Gate electrode 111A Polycrystalline silicon film 112 Interlayer insulating film 113 Metal VDD layer 114 Source wiring electrode 115 Metal VDD layer 116 Drain wiring electrode 117 Field oxide film 118, 118A, 119 Electric potential relaxation layer 120, 120A, 120B High concentration region 801 Load 802 Inverter 803 Control circuit 804 SiC power MISFET
805 Diode 901 Load 902 Inverter 903 Control Circuit 904 SiC Power MISFET
1001a, 1001b Drive wheels 1002 Drive shaft 1003 Three-phase motor 1004 Inverter 1005 Battery 1006, 1007 Power line 1008 Boost converter 1009 Relay 1010 Electronic control unit 1011 Reactor 1012 Smoothing capacitor 1013 Inverter 1014 SiC power MISFET
1101 load 1102 inverter 1104 SiC power MISFET
1107 Converter 1108 Capacitor 1109 Transformer CNT Opening M11-M20 Mask OW Overhead PG Pantograph RT Line WH Wheel

Claims (11)

A first conductive type substrate having a first main surface and a second main surface opposite to the first main surface,
The first conductive type epitaxial layer formed on the first main surface and
Extending from the upper surface of the epitaxial layer to the epitaxial layer in a second direction orthogonal to the first direction along the first main surface, formed so as to be separated from each other in the first direction along the first main surface. A plurality of first body layers of the second conductive type different from the existing first conductive type, and
A source region of the first conductive type extending in the second direction formed in the first body layer from the upper surface of the epitaxial layer and separated from the end portion of the first body layer.
It extends in the second direction, which is separated from the source region and is formed shallower than the first body layer from the upper surface of the epitaxial layer across the interface between the epitaxial layer and the first body layer. The first conductive type current diffusion layer and
The second conductive type second body layer extending in the second direction, which is formed shallower than the first body layer immediately below the current diffusion layer,
A plurality of trenches extending in the first direction over the source region, the first body layer and the current diffusion layer, and formed apart from each other in the second direction.
The gate insulating film formed on the inner wall of the trench and
The gate electrode formed on the gate insulating film and
The first conductive type drain region formed in the substrate from the second main surface, and
Have,
The depth of the trench from the upper surface of the epitaxial layer is shallower than the first depth of the first body layer from the upper surface of the epitaxial layer.
The gate electrode is provided inside a region composed of the first body layer and the second body layer in a plan view.
A semiconductor device having the second conductive type electric field relaxation layer on the upper part of the current diffusion layer and the upper part of the epitaxial layer between the current diffusion layers facing each other. In the semiconductor device according to claim 1,
A semiconductor device having a width of a portion of the second body layer that does not overlap with the first body layer in a plan view in the first direction of 0.1 μm or more and 2 μm or less. In the semiconductor device according to claim 1,
A semiconductor device having a maximum impurity concentration of the second body layer of 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^{-3 or less.} In the semiconductor device according to claim 1,
In the third direction orthogonal to the horizontal plane composed of the first direction and the second direction, the distance between the electric field relaxation layer sandwiching the current diffusion layer and the second body layer is 0.1 μm or more and 1 μm or less. There is a semiconductor device. In the semiconductor device according to claim 1,
The first conductive type semiconductor region formed in the epitaxial layer between the current diffusion layers which are in contact with the electric field relaxation layer and the current diffusion layer and face each other.
Have,
A semiconductor device in which the impurity concentration in the semiconductor region is higher than the impurity concentration in the epitaxial layer and lower than the impurity concentration in the source region. In the semiconductor device according to claim 5,
A semiconductor device having an impurity concentration in the semiconductor region of 1 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less. In the semiconductor device according to claim 5,
A semiconductor device in which the depth of the semiconductor region from the upper surface of the epitaxial layer is the same as or deeper than the first depth of the first body layer. In the semiconductor device according to claim 5,
Is the depth of the semiconductor region from the upper surface of the epitaxial layer shallower than the first depth of the first body layer and the same as the second depth of the second body layer from the upper surface of the epitaxial layer? , Or a semiconductor device deeper than the second depth. In the semiconductor device according to claim 5,
A semiconductor device in which the depth of the semiconductor region from the upper surface of the epitaxial layer is shallower than the depth of the second body layer from the upper surface of the epitaxial layer. In the semiconductor device according to claim 1,
The substrate is a semiconductor device made of silicon carbide. A power conversion device including the semiconductor device according to claim 1 as a switching element.

Images