JP6626807B2 - Semiconductor device, power module and power converter - Google Patents

Description

  The present invention relates to a semiconductor device, a power module, and a power converter, and more particularly, to a structure of a power device using silicon carbide.

  Semiconductor power devices are required to have high withstand voltage, low on-resistance, and low switching loss, but silicon (Si) power devices, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a breakdown electric field strength about one order of magnitude higher than that of Si. Therefore, the element resistance can be reduced by making the drift layer holding the breakdown voltage about 1/10 thinner and increasing the impurity concentration about 100 times. Theoretically, it can be reduced by three digits or more. Further, since the band gap is about three times larger than that of Si, high-temperature operation is possible, and the performance of the SiC power device is expected to exceed that of the Si power device.

  As described above, SiC has characteristics such as a larger band gap and a higher breakdown electric field strength than Si, but SiC is applied to devices such as MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). In such a case, an electric field applied to the insulating film constituting the element becomes a problem.

  For example, Patent Document 1 discloses a SiC-MOSFET in which an n-type semiconductor substrate is made of SiC. This SiC-MOSFET has the largest cross-sectional area among a plurality of p-type well layers provided in the n-type drift layer, and has an upper surface of an outermost p-type well layer located immediately below a gate electrode pad portion. A p-type semiconductor layer is entirely or partially provided thereon.

  Patent Document 2 discloses a silicon carbide power semiconductor device in which a low-resistance, n-type low-resistance region is provided in a surface layer of a well region below a gate electrode pad. It is disclosed that such a configuration suppresses the occurrence of dielectric breakdown of the gate insulating film.

International Publication No. WO2010 / 098249 Japanese Patent No. 5539355

  The present inventor is engaged in research and development on MOSFETs using SiC. In this situation, there has been encountered an event that deterioration of an insulating film (field oxide film) having a relatively large thickness among the insulating films constituting the MOSFET becomes a problem.

  Then, the cause of the above-mentioned problem was searched for, and a configuration of a semiconductor device having good characteristics was found.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a typical embodiment among the embodiments disclosed in the present application will be briefly described as follows.

  A semiconductor device according to an embodiment disclosed in the present application is formed on a top surface of a substrate, a first conductivity type semiconductor layer containing silicon carbide, and an upper portion of the semiconductor layer at an outer peripheral portion of an element formation region. A first well region of a second conductivity type opposite to the first conductivity type and formed in the first well region; and a first semiconductor region of the second conductivity type formed in the first well region. . Further, a second well region of the second conductivity type formed in the element formation region and formed on the semiconductor layer, and a gate electrode formed on the second well region with a gate insulating film interposed therebetween. And a gate pad connected to the gate electrode. The first well region extends to the gate pad formation region, and the gate electrode is disposed on the first well region via the first insulating film in the gate pad formation region. I have. The semiconductor device further includes a second semiconductor region of the second conductivity type formed in the first well region in a formation region of the gate pad.

  According to the semiconductor device shown in the typical embodiment disclosed in the present application, characteristics of the semiconductor device can be improved. In addition, the performance of a power module and a power converter using the semiconductor device can be improved.

FIG. 2 is a plan view showing a configuration of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view illustrating a configuration of the semiconductor device according to the first embodiment; FIG. 2 is a plan view showing a configuration of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 4 is a plan view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 4 is a plan view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 4 is a plan view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment. FIG. 3 is a plan view showing a configuration of a semiconductor device of a comparative example of the first embodiment. FIG. 2 is a cross-sectional view illustrating a configuration of a semiconductor device according to a comparative example of the first embodiment. FIG. 3 is a plan view showing a configuration of a semiconductor device of a comparative example of the first embodiment. It is an inverter circuit diagram. FIG. 4 is a diagram illustrating an example of a current / voltage waveform at the time of switching of a MOSFET constituting an inverter. FIG. 11 is a cross-sectional view schematically illustrating a configuration near a gate pad portion of a semiconductor device of a comparative example. FIG. 3 is a cross-sectional view schematically illustrating a configuration near a gate pad unit according to the first embodiment. FIG. 4 is a diagram illustrating a waveform of an applied pulse. It is a figure showing a simulation result using TCAD. It is a top view showing the composition of the semiconductor device of a study example. FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device of a study example. It is a top view showing the composition of the semiconductor device of a study example. FIG. 4 is a diagram for explaining a measurement result of a stress applied to a crystal. FIG. 4 is a diagram for explaining a measurement result of a stress applied to a crystal. FIG. 4 is a diagram for explaining a measurement result of a stress applied to a crystal. FIG. 9 is a circuit diagram of a power conversion device (inverter) according to a second embodiment. FIG. 10 is a schematic diagram illustrating a configuration of an electric vehicle according to a third embodiment. FIG. 10 is a circuit diagram of a boost converter according to a third embodiment. FIG. 14 is a circuit diagram including a converter and an inverter of a railway vehicle according to a fourth embodiment. FIG. 39 is a plan view showing a configuration of a semiconductor device of Application Example 1 of the fifth embodiment. FIG. 39 is a cross-sectional view illustrating a configuration of a semiconductor device of Application Example 1 of the fifth embodiment. FIG. 39 is a plan view showing a configuration of a semiconductor device of Application Example 2 of the fifth embodiment. FIG. 39 is a plan view showing a configuration of a semiconductor device of Application Example 2 of the fifth embodiment. FIG. 39 is a cross-sectional view showing a configuration of a semiconductor device of Application Example 2 of the fifth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. In the embodiments, the same or similar portions will not be described in principle unless otherwise necessary. Further, in the drawings for describing the embodiments, hatching is used even in a plan view or a perspective view in order to make the configuration easy to understand. Further, in the drawings for describing the embodiments, hatching may be omitted in cross-sectional views in order to make the configuration easy to understand. In the cross-sectional view and plan view, the size of each part does not correspond to the size of the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. Further, even when the cross-sectional view and the plan view correspond to each other, a specific portion may be displayed relatively large in order to make the drawing easy to understand.

The sign ^"-" and ^"+", the conductive type represents the relative concentration of the n-type or p-type impurities, if for example, the n-type impurity, "n ^-", "n", " The impurity concentration increases in the order of “n ⁺ ”.

(Embodiment 1)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

[Structure description]
1 to 3 are sectional views or plan views showing the configuration of the semiconductor device of the present embodiment. 1 and 3 are plan views, and FIG. 2 is a cross-sectional view. In the cross-sectional views, (A), (B), and (C) correspond to the AA cross section, the BB cross section, and the CC cross section in the plan view, respectively.

  The semiconductor device of the present embodiment is a semiconductor device (semiconductor chip) having a SiC (silicon carbide) MOSFET.

  The MOSFET (semiconductor element) is formed in a cell region, and the cell region is surrounded by a peripheral region. That is, the inside of the semiconductor device (semiconductor chip) is a cell region, and the outer peripheral portion is a peripheral region.

In the cell region, the MOSFET shown in FIG. 2C, the gate pad GP and the source electrode SE shown in FIG. 2B are formed. In the peripheral region, a p-type semiconductor region (termination region) TM and an n ⁺ -type semiconductor region NR on the outer periphery thereof are formed.

FIG. 1 shows various semiconductor regions provided on the main surface of an n-type n ⁻ -type semiconductor layer (epitaxial layer) ND made of SiC on an n ⁺ -type SiC substrate NS. The n ⁻ type semiconductor layer ND mainly becomes a drift layer. That is, FIG. 1 shows the top surface of the n ⁻ type semiconductor layer ND, and illustrates a gate insulating film, a gate electrode, an interlayer insulating film, a gate pad, a source electrode, and the like on the n ⁻ type semiconductor layer ND. Omitted.

Specifically, FIG. 1 shows a p-type semiconductor region (termination region) TM and an n ⁺ -type semiconductor region NR in the peripheral region. In addition, a p ⁺ -type semiconductor region GRa, GRb, and PRG and a p ⁺ -type semiconductor region GRa, GRb, and a p-type body region PB that includes the p ⁺ -type semiconductor region are shown in the cell region. Further, a source region SR forming a MOSFET, ap ⁺ type semiconductor region PR adjacent to the source region, a source region SR, and ap type body region PB containing the p ⁺ type semiconductor region PR are shown. I have. Here, the cell region means inside the p-type semiconductor region (termination region) TM.

Here, in the present embodiment, as shown in FIG. 1, in a region GPA where a gate pad (GP) is arranged (region surrounded by a broken line in FIG. 1), <11-20> of SiC substrate NS A substantially rectangular p ⁺ type semiconductor region PRG having a long side is provided in a direction perpendicular to the direction. Such approximately rectangular p ⁺ -type semiconductor regions PRG are arranged side by side at predetermined intervals in the <11-20> direction.

As described above, since the p ⁺ -type semiconductor region PRG having a higher concentration than this layer is provided in the p-type body region PB below the gate pad GP, generation of a surge voltage can be suppressed. Further, since the p ⁺ type semiconductor region PRG is arranged not in the entire region corresponding to the formation region (GPA) of the gate pad GP but in a part of the region, the influence of crystal defects can be suppressed. Further, the arrangement of the p ⁺ -type semiconductor region PRG in a direction parallel to the <11-20> direction in which crystal defects easily occur is minimized, and the p ⁺ -type semiconductor region PRG extends in a direction perpendicular to the <11-20> direction. ^{Since the +} type semiconductor region PRG is arranged in a rectangular shape, the influence of crystal defects can be effectively suppressed. Details will be described later.

  Next, the configuration of the semiconductor device of the present embodiment will be described below with reference to FIGS.

A plurality of MOSFETs each having a cell structure are formed in a cell region arranged at the center of the semiconductor device. This MOSFET is a planar type MOSFET having a double diffused metal oxide semiconductor (DMOS) structure. As shown in FIG. 2C, the MOSFET includes an n ⁺ -type source region SR, a p-type body region PB serving as a channel region, and a gate electrode GE disposed on the channel region via a gate insulating film GI. And Note that the n ⁺ -type SiC substrate NS functions as a drain region.

An n ⁺ type source region SR is arranged so as to be surrounded by p type body region PB, and ap ⁺ type semiconductor region PR is arranged inside n ⁺ type source region SR. The p ⁺ type semiconductor region PR becomes a contact region for extracting the source region SR. The p-type body region PB and an n ⁻ type semiconductor layer (drift layer) ND below the p-type body region PB constitute a diode (that is, a body diode).

  As described above, by incorporating a body diode in a semiconductor device, it is not necessary to prepare a chip on which a diode is separately mounted, so that the device can be reduced in size and weight.

In FIG. 1, a source region SR having a square planar shape is arranged inside a p-type body region PB having a square planar shape, and a planar shape is located inside a source region SR having a square planar shape. A square p ⁺ type semiconductor region PR is arranged. The unit regions having such a configuration are arranged in an array. For example, a gate electrode GE is arranged between unit regions (between adjacent p ⁺ -type semiconductor regions PR) via a gate insulating film GI (FIG. 2). The gate electrode GE is covered with an insulating film (interlayer insulating film) IL2, and the p ⁺ type semiconductor region PR is connected to the source electrode SE via a plug in the contact hole C1S. Further, the gate electrode GE is connected to the gate pad GP via a plug in the contact hole C1GE. Note that the gate pad GP has a cross-shaped gate finger GF that partitions the cell region into a sub-cell region (see FIG. 3).

Here, under the gate pad GP and in the peripheral region, an insulating film (field oxide film) IL1 is disposed above the semiconductor layer. The insulating film (field oxide film) IL1 may be damaged by the influence of the surge voltage, but in the present embodiment, by providing the p ⁺ type semiconductor region PRG, as described later. In addition, generation of a surge voltage can be suppressed, and destruction of the insulating film (field oxide film) IL1 can be suppressed.

[Production method explanation]
Next, the manufacturing process of the semiconductor device of the present embodiment will be described, and the structure of the semiconductor device of the present embodiment will be clarified. 4 to 16 are cross-sectional views or plan views showing the manufacturing steps of the semiconductor device according to the present embodiment.

First, as shown in FIG. 4, an n ⁺ -type SiC substrate NS is prepared. An n-type impurity is introduced into the SiC substrate NS at a relatively high concentration. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . The main surface of the SiC substrate NS is, for example, a {0001} surface.

Next, an n ⁻ type semiconductor layer ND is formed on the main surface of the SiC substrate NS. For example, an SiC n ^- type semiconductor layer (epitaxial layer) is formed on the main surface of the SiC substrate NS by an epitaxial growth method. An n-type impurity lower than the impurity concentration of the SiC substrate NS is introduced into the n ⁻ -type semiconductor layer ND. The impurity concentration of the n ⁻ type semiconductor layer ND depends on the rated withstand voltage of the element and is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ type semiconductor layer ND is, for example, 30 μm. The thickness of the n ⁻ type semiconductor layer ND can be adjusted within a range of, for example, 3 to 80 μm according to the withstand voltage of the element.

Next, as shown in FIG. 5, a p-type semiconductor region TM is formed in a peripheral region surrounding the element region (element formation region, active region). For example, a mask film (not shown, for example, a silicon oxide film) having an opening is formed in the formation region of the p-type semiconductor region TM, and p-type impurities (for example, aluminum (Al)) are ion-implanted. Thus, a rectangular annular p-type semiconductor region TM can be formed in the n ⁻ -type semiconductor layer ND in the peripheral region surrounding the element region (see FIG. 1). The depth of the p-type semiconductor region TM is, for example, about 0.5 to 2.0 μm from the surface of the n ⁻ -type semiconductor layer ND. The impurity concentration of the p-type semiconductor region TM is, for example, 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³ .

Next, after removing the mask, a p-type body region (also referred to as a p-type well region) PB, which is a p-type semiconductor region, is formed in an array in the element region (see FIG. 1). At this time, the p-type body region PB is also formed in the region including the formation region of the p ⁺ -type semiconductor regions GRa, GRb, and PRG shown in FIG.

For example, a mask film (not shown, for example, a silicon oxide film) having an opening is formed in the formation region of the p-type body region PB, and p-type impurities (for example, aluminum (Al)) are ion-implanted. Thus, a p-type body region PB is formed on the outer periphery of the element region. The depth of p-type body region PB is, for example, about 0.5 to 2.0 μm from the surface of n ⁻ type semiconductor layer ND. Further, the impurity concentration of the p-type body region PB is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . Thereby, a plurality of square p-type body regions PB are formed in the element region in an array. A rectangular annular p-type body region PB is formed inside the p-type semiconductor region TM. A cross-shaped p-type body region PB is formed so as to divide the inside of the rectangular annular p-type body region PB into four parts. Further, a p-type body region PB is formed in a region (a region surrounded by a broken line in FIG. 1) GPA where the gate pad (GP) is arranged (see FIG. 8). The length in the vertical direction (length in the direction perpendicular to the <11-20> direction) of the region GPA is, for example, about 500 to 1000 μm, and the length in the horizontal direction (length in the <11-20> direction). ) Is, for example, about 500 to 2000 μm.

Next, after removing the mask film, a source region SR is formed in the p-type body region PB in the element region as shown in FIG. At this time, an n ⁺ type semiconductor region NR is formed on the outer periphery of the p type semiconductor region TM.

For example, n ⁺ -type by mask film having an opening in the formation region of the source region SR and the n ⁺ -type semiconductor region NR (not shown) as a mask, the n-type impurity (e.g., nitrogen (N)) is ion-implanted Is formed. The source region SR is formed in, for example, an array in the element region. The source region SR is formed at the center of the substantially square p-type body region PB in plan view (see FIG. 9). The depth from the upper surface of the n ⁻ type semiconductor layer ND such as the source region SR is, for example, about 0.05 to 1.0 μm. The impurity concentration of the source region SR and the like is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

Next, after removing the mask film, as shown in FIGS. 7 and 8, ap ⁺ type semiconductor region PR is formed inside the source region SR in the element region. The p ⁺ type semiconductor region PR becomes a contact region between the source electrode SE and the source region SR. For example, using a mask film (not shown) having an opening in the formation region of the p ⁺ -type semiconductor region PR as a mask, ions of a p-type impurity (for example, aluminum (Al)) are implanted into the p ⁺ -type semiconductor region PR. To form Further, in the ion implantation step, an annular p ⁺ -type semiconductor region GRa is formed in the p-type body region PB on the outer periphery of the element region, and a cross-shaped p-type body region PB in the element region is formed. The p ⁺ type semiconductor region GRb is formed.

Further, in the ion implantation step, ap ⁺ -type semiconductor region PRG is formed in the p-type body region PB of a region (a region surrounded by a broken line in FIG. 8) GPA in which a gate pad (GP) described later is arranged. I do. The p ⁺ type semiconductor region PRG is a substantially rectangular pattern having long sides in a direction perpendicular to the <11-20> direction of the SiC substrate NS. Such substantially rectangular patterns (p ⁺ type semiconductor regions PRG) are arranged side by side in the <11-20> direction at a predetermined interval. Here, five p ⁺ -type semiconductor regions PRG are provided in the region GPA, and the p ⁺ -type semiconductor region PRG located at the center is connected to the p ⁺ -type semiconductor region GRb. The five p ⁺ -type semiconductor regions PRG are connected to the ring-shaped p ⁺ -type semiconductor regions GRa. Specifically, in the annular p ⁺ -type semiconductor region GRa, a portion extending in the <11-20> direction (the horizontal direction in FIG. 8) and one end of the five p ⁺ -type semiconductor regions PRG It is connected.

The depth of the p ⁺ -type semiconductor regions PR, GRa, GRb, and PRG from the upper surface of the n ⁻ -type semiconductor layer ND is, for example, about 1 μm. The impurity concentration of the p ⁺ -type semiconductor regions PR, GRa, GRb, and PRG is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . As described above, the p ⁺ -type semiconductor regions PR, GRa, GRb, and PRG are formed in the same layer, that is, in the same ion implantation step, and have the same impurity concentration. Note that these may be formed in separate steps, and the impurity concentration may be changed as necessary. However, when the mask is formed in the same layer, the number of mask masters can be reduced, and a semiconductor device can be manufactured in a short process.

Next, an n-type impurity (for example, nitrogen (N)) is ion-implanted into the back surface of the SiC substrate NS to form a drain region (not shown). The depth of the drain region from the back surface of the SiC substrate NS is, for example, about 0.05 to 2.0 μm. The impurity concentration of the drain region is 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, a carbon (C) film is formed on the upper surface of the n ⁻ type semiconductor layer ND and the back surface of the SiC substrate NS, and is subjected to heat treatment, so that ions are formed on the upper portion of the n ⁻ type semiconductor layer ND and the back surface of the SiC substrate NS. The implanted impurities are activated. For example, a carbon (C) film is deposited by using a plasma CVD (Chemical Vapor Deposition) method. The thickness of the carbon (C) film is, for example, about 0.03 to 0.05 μm. After covering the upper surface of the n ⁻ type semiconductor layer ND and the back surface of the SiC substrate NS with the carbon (C) film as described above, heat treatment is performed at a temperature of 1500 ° C. or more for about 2 to 3 minutes. Thereafter, the carbon (C) film is removed by, for example, a plasma treatment.

Next, as shown in FIG. 9, an insulating film (field insulating film) IL1 is formed on the upper surface of the n ⁻ type semiconductor layer ND. For example, a silicon oxide film is formed by a CVD method as the insulating film (field insulating film) IL1. The thickness of the insulating film (field insulating film) IL1 is, for example, about 0.3 to 2 μm. Next, the insulating film (field insulating film) IL1 is etched using the mask film in which the subcell region is opened as a mask (FIGS. 10 and 11). That is, the insulating film (field insulating film) IL1 is formed on the peripheral region, the region where the gate pad (GP) is arranged (the region GPA surrounded by a broken line in FIG. 8), and the cross-shaped p ⁺ type semiconductor region GRb. Will remain. Here, the sub-cell region means an element region that is not covered with the insulating film (field insulating film) IL1.

Next, as shown in FIG. 12, a gate electrode GE is formed on the p-type body region PB adjacent above between the source regions SR via the gate insulating film GI. Here, the gate electrode GE is formed between the source regions SR via the gate insulating film GI. Note that a connection portion buried in a contact hole C1S described later is arranged near the source region SR. Therefore, the gate electrode GE is formed so as to have an opening OA1 in a region including a formation region of the connection portion. Process. The gate electrode GE remains on the cross-shaped p ⁺ -type semiconductor region GRb, and is not arranged on the annular p ⁺ -type semiconductor region GRa. Note that the gate electrode GE may also be arranged over the annular p ⁺ -type semiconductor region GRa. The gate electrode GE on the cross-shaped p ⁺ type semiconductor region GRb is called a finger electrode.

For example, a gate insulating film is formed on an n ⁻ type semiconductor layer (drift layer, p type body region PB, p ⁺ type semiconductor region PR, GR, PRG, source region SR) ND and an insulating film (field insulating film) IL1. An insulating film to be the GI and a conductive film to be the gate electrode GE are sequentially deposited. Here, a silicon oxide film is deposited as a gate insulating film GI by a CVD method, and then a polycrystalline silicon film is deposited as a gate electrode GE by a CVD method. Next, a mask film is formed to cover the region where the gate electrode GE remains, and the polycrystalline silicon film is etched using this film as a mask (FIGS. 12 and 13). The thickness of the gate insulating film GI is, for example, about 0.05 to 0.15 μm. The thickness of the gate electrode GE is, for example, about 0.2 to 0.5 μm.

  Next, after removing the mask film, an insulating film (interlayer insulating film) IL2 is formed as shown in FIG. For example, a silicon oxide film is formed over the gate electrode GE, the gate insulating film GI, and the insulating film (field insulating film) IL1 by a plasma CVD method.

  Next, as shown in FIG. 15, contact holes (C1S, C1GR, C1GE) are formed in the insulating film (interlayer insulating film) IL2. For example, on the insulating film (interlayer insulating film) IL2, a mask film (not shown) having an opening in a formation region of the contact hole C1 (C1S, C1GR, C1GE) is formed, and using this film as a mask, (Interlayer insulating film) IL2 is etched.

Thereby, the contact hole C1S is formed on the source region SR, and the contact hole C1GR is formed on the annular p ⁺ -type semiconductor region GRa. In addition, a contact hole C1GE is formed on the gate electrode GE by the above etching process (see FIGS. 15 and 3). The contact holes C1S have a substantially square shape and are arranged in an array in the cell region. The contact hole C1GR is annularly arranged on the annular p ⁺ type semiconductor region GRa. The contact hole C1GE is arranged on the gate electrode GE in a region (GPA) where the gate pad (GP) is arranged. The contact hole C1GE may be formed also on the cross-shaped gate electrode (finger electrode) GE. The shape (planar shape) of the contact hole may be a substantially square shape or a line shape along the electrode.

Next, after removing the mask film (not shown), a source electrode SE, a gate pad GP, and a gate finger GF are formed as shown in FIG. First, a conductive film to be the source electrode SE and the gate pad GP is formed on the insulating film (interlayer insulating film) IL2 including the inside of the contact hole C1 (C1S, C1GR, C1GE). For example, a stacked film of Ti / TiN / Al / TiN / Al is formed as the conductive film. For example, these films are sequentially deposited using a sputtering method or the like. Next, the conductive film is etched using a mask film (not shown) covering a region where the source electrode SE, the gate pad GP, and the gate finger GF are formed as a mask, thereby forming the source electrode SE, the gate pad GP, and the gate finger GF. Is formed (see FIGS. 16 and 3). The source electrode SE is arranged so as to cover the sub cell region and the annular p ⁺ type semiconductor region (GRa). The gate pad GP is arranged in a substantially rectangular shape at the end of the cell region. Further, the gate fingers GF are arranged in a cross shape between the sub-cell regions.

As a result, the source electrode SE and the source region SR are connected by the plug made of the conductive film embedded in the contact hole C1S, and the source electrode SE and the annular p ⁺ -type semiconductor region GRa are located in the contact hole C1GR. The connection is made by a plug made of a buried conductive film. In addition, the gate pad GP and the gate electrode GE are connected by a plug made of a conductive film embedded in the contact hole C1GE, and the gate finger GF and the gate electrode GE are connected by a conductive film embedded in the contact hole C1GE. Connected by a plug. Note that a metal silicide film may be formed below the plug in order to reduce the connection resistance between these plugs and the lower layer region.

  Next, the mask film (not shown) is removed, a protective film (not shown) is formed on the source electrode SE, the gate pad GP, and the gate finger GF, and the source electrode is formed by etching the protective film. An opening is provided on the SE and the gate pad GP. This opening serves as a pad (external connection).

For example, a SiO ₂ film or a polyimide film is formed as a protective film (passivation film) on the source electrode SE gate pad GP and the gate finger GF, and a part of the protective film is removed by using an etching technique or the like. Then, a pad portion is formed.

  Next, a drain electrode DE is formed on the back surface of the SiC substrate NS. For example, a stacked film of Ti / Ni / Au (total thickness: 0.5 to 1 μm) is sequentially deposited on the back surface of the SiC substrate NS by a sputtering method or the like to form a drain electrode DE. Note that a metal silicide film may be formed between the SiC substrate NS and the drain electrode DE.

  Thereafter, the SiC substrate NS is cut into individual pieces by cutting in a dicing process, whereby a plurality of semiconductor chips can be obtained.

  Through the above steps, the semiconductor device of this embodiment can be formed. Note that the above process is an example, and the semiconductor device of the present embodiment may be manufactured by a process other than the above process. Further, the planar shape and the formation position of each region may be appropriately changed. For example, the gate pad GP may be provided at the center of the cell region.

According to the semiconductor device of the present embodiment, the p ⁺ -type semiconductor region PRG formed in the p-type body region PB below the gate pad GP and applied with a source potential (for example, 0 V) is provided. The surface resistance of p-type body region PB can be reduced. Further, since the p ⁺ type semiconductor region PRG is arranged not in the entire region corresponding to the formation region of the gate pad GP but in a part of the region, the influence of crystal defects can be suppressed. Further, the arrangement of the p ⁺ -type semiconductor region PRG in a direction parallel to the <11-20> direction in which crystal defects easily occur is minimized, and the p ⁺ -type semiconductor region PRG extends in a direction perpendicular to the <11-20> direction. ^{Since the +} type semiconductor region PRG is arranged in a rectangular shape, the influence of crystal defects can be effectively suppressed.

  Hereinafter, 1) the effect of suppressing the surge voltage and 2) the effect of suppressing the influence of the crystal defect will be described.

1) Surge Voltage Suppressing Effect FIGS. 17 to 19 are sectional views or plan views showing a configuration of a semiconductor device of a comparative example of the present embodiment. As shown in FIGS. 17 to 19, in the semiconductor device of the comparative example, the p ⁺ -type semiconductor region PRG is not provided in the p-type body region PB below the gate pad GP. Note that the other configuration is the same as the configuration of the present embodiment (FIGS. 1 to 3), and a description thereof will be omitted.

As described above, in the semiconductor device of the comparative example, since the p ⁺ -type semiconductor region PRG is not formed below the gate pad GP, a stack of the gate pad GP and the gate electrode GE is formed below the gate pad GP. The portion is arranged on p-type body region PB via a relatively thick insulating film (field insulating film) IL1 (FIG. 18B). Although the insulating film (field insulating film) IL1 is relatively thick (for example, 0.3 μm) and has a high withstand voltage, according to the study of the present inventors, it has been confirmed that a dielectric breakdown has occurred below the gate pad GP. Was.

  The following investigation was conducted to determine the cause. FIG. 20 is an inverter circuit diagram. This circuit is an inverter circuit that converts DC into AC. Note that the inverter circuit will also be described in the second embodiment.

  This circuit includes two MOSFETs (GD1, GD2) connected in series between a first node and a second node, and two MOSFETs connected in series between the first node and a second node. MOSFETs (GD3, GD4) are provided, and an L load is connected between these connection parts. A power supply Vcc is connected between the first node and the second node, and a capacitor is connected between the first node and the second node.

  When an ON signal is input to GD1 and GD4 and an OFF signal is input to GD2 and GD3 among the four MOSFETs (GD1 to GD4), a current in the (1) direction flows through the L load. Conversely, when an off signal is supplied to GD1 and GD4 and an on signal is supplied to GD2 and GD3, a current in the (2) direction flows through the L load. By repeating the switching of the input of the ON / OFF signal, DC (direct current) can be converted from several Hz to AC (alternating current) of several kHz.

  FIG. 21 is a diagram showing an example of a current / voltage waveform at the time of switching of the MOSFET constituting the inverter. Here, a waveform when the MOSFET is switched from on to off is shown. The left vertical axis shows the drain voltage (Vds, [V]), the right vertical axis shows the drain current (Id, [A]), and the horizontal axis shows time (Time, [s]).

  As shown in FIG. 21, when the MOSFET switches from ON to OFF, the drain current of the MOSFET rapidly changes from 400 A to zero, and at the same time, the drain voltage changes from zero to 1800 V. At this time, the voltage change speed (dVds / dt) reaches about 4 kV / μs.

  A surge voltage can occur in the semiconductor region due to such a rapid voltage change. As shown in FIG. 21, the drain voltage which has only to be raised to 1800 V rises to about 2150 V in the transition period. Such a surge voltage destroys the relatively thick insulating film (field insulating film) IL1 below the gate pad GP. For example, the insulation withstand voltage of the insulation film (field insulation film) IL1 is designed to be about 300 V, but it is considered that the insulation film (field insulation film) may be destroyed by the surge voltage. In FIG. 18B, a region that is easily broken by the present inventors is indicated by a broken-line circle.

On the other hand, according to the semiconductor device of the present embodiment, the p ⁺ -type semiconductor region PRG having a higher concentration than this layer is provided in the p-type body region PB below the gate pad GP. Generation can be suppressed.

  FIG. 22 is a cross-sectional view schematically showing the configuration near the gate pad portion of the semiconductor device of the comparative example, and FIG. 23 is a cross-sectional view schematically showing the configuration near the gate pad portion of the present embodiment. . FIG. 24 shows a waveform of an applied pulse, and FIG. 25 shows a simulation result using TCAD. 24, the vertical axis indicates the drain voltage (Vds, [V]), the horizontal axis indicates the time (Time, [μs]. In FIG. 25, the vertical axis indicates the surface potential [V]. The horizontal axis indicates the X coordinate [μm].

Specifically, for example, the source electrode SE is fixed to 0 V, and the drain electrode DE has a pulse shown in FIG. 24 (a pulse having a waveform that rises to 2000 V in 1 μs, maintains for 100 μs, and then drops in 2 μs). Was applied, and the surface potential [V] was examined using TCAD at a length of 500 μm from the source electrode SE arranged on the outer periphery of the gate pad in the x direction (along the line AA in FIG. 17). As a result, as shown in FIG. 25, in the case of the comparative example (dashed line graph, FIG. 22), the surface potential of the p-type body region PB is shifted from the source electrode SE in the x direction (the cross section along the line AA in FIG. 17). It can be seen that the voltage increases as the distance increases, and a high voltage of 400 V or more is at a position separated by about 400 to 500 μm. This is because, as the reverse bias between the p-type body regions PB / n ⁻ -type semiconductor layers ND increases, carriers (holes) generated in the inter-band transition are generated, and the generated carriers are transferred to the sheet of the p-type body region PB. It is considered that, because of the high resistance, the movement of carriers cannot keep up with the potential fluctuation, and an excessive electric field is applied to the pn junction. That is, the generated holes flow into the p-type body region PB, but the holes are immediately absorbed in the vicinity of the plug in the contact hole C1GR, whereas the holes accumulate at the far end, and the hole distribution in this plane is reduced. It is considered that the bias has caused the surface potential distribution. Therefore, the surface potential of p-type body region PB becomes high.

On the other hand, in the case of the present embodiment in which the p ⁺ type semiconductor region is provided (solid line graph, FIG. 23), the surface potential of the p ⁺ type semiconductor region PRG is shifted from the source electrode SE in the x direction (FIG. 1). (A-A cross-sectional direction) is about 40 V even at a position about 400 to 500 μm apart. As described above, by providing the p ⁺ -type semiconductor region PRG having a higher concentration than this layer in the p-type body region PB below the gate pad GP, the surface potential thereof is reduced by about 1 / It can be reduced to 10. That is, in this embodiment, since the p ⁺ -type semiconductor region PRG is provided in the p-type body region PB, the sheet resistance is reduced, so that the distribution of the holes can be made uniform, and the local potential of the surface potential can be reduced. Can be suppressed. As a result, breakdown of the insulating film (field insulating film) IL1 below the gate pad GP can be prevented. Note that in the above simulation, the simulation was performed with the gate potential set to 0 V in order to simplify the analysis.

Thus, it can be seen that the surge voltage can be suppressed by providing the p ⁺ -type semiconductor region PRG having a higher concentration than this layer in the p-type body region PB below the gate pad GP.

2) Effect of Suppressing the Effect of Crystal Defects FIGS. 26 to 28 are cross-sectional views or plan views showing the configuration of a semiconductor device of a study example by the present inventors. From the above simulation results, an example in which ap ⁺ type semiconductor region PRG is provided in the entire region overlapping with the gate pad GP can be considered. As shown in FIGS. 26 to 28, in the semiconductor device of the study example, in the p-type body region PB below the gate pad GP and in the entire region overlapping with the gate pad GP, the p ⁺ -type semiconductor region PRG Is provided. Note that the other configuration is the same as the configuration of the present embodiment (FIGS. 1 to 3), and a description thereof will be omitted.

As described above, the p ⁺ -type semiconductor region PRG may be provided in the entire region overlapping with the gate pad GP, but in this case, the region is easily affected by crystal defects. In particular, in a semiconductor device having a body diode as in this embodiment, a forward current flows through the body diode, so that defects easily grow (growth phenomenon of basal plane dislocation).

FIGS. 29 to 31 are diagrams for explaining the measurement results of the stress applied to the crystal. As shown in FIG. 29, for the p-type SiC layer (p ⁺ ), a direction parallel to <11-20> (referred to as <11-20> parallel direction) and a direction perpendicular to <11-20>(<11-20> perpendicular direction), the crystal stress was measured by Raman spectroscopy. The results are shown in FIGS. The horizontal axis of each graph indicates the measurement position (μm), and the vertical axis indicates the Raman shift amount (Δν). The Raman shift amount is a parameter proportional to the residual stress. On the vertical axis, the + direction is the compressive stress and the-direction is the tensile stress.

When a p-type impurity is ion-implanted into the SiC layer, the SiC layer in the implantation region becomes amorphous. Thereafter, the activation anneal of the implanted p-type impurity causes recrystallization of the SiC layer. At this time, stress is generated at the edge of the pattern of the p-type SiC layer (p ⁺ ).

  How to apply this stress depends on the crystal orientation. Therefore, it can be seen that the stress at the edge part is smaller when scanning in the <11-20> parallel direction (FIG. 30) than when scanning in the <11-20> vertical direction (FIG. 31). That is, in FIG. 29, the stress of the edge extending in the horizontal direction is larger than that of the edge extending in the vertical direction. Therefore, crystal defects increase at the edge extending in the lateral direction.

For this reason, in the present embodiment, the p ⁺ type semiconductor region PRG is formed in a substantially rectangular shape having a long side in a direction perpendicular to the <11-20> direction of the SiC substrate NS, and such a substantially rectangular shape is formed. By arranging the p ⁺ -type semiconductor regions PRG in the <11-20> direction at predetermined intervals, crystal defects due to activation annealing can be significantly reduced. As a result, for example, even if a forward current flows through a body diode (semiconductor element) including the p-type body region PB and the n ⁻ -type semiconductor layer (drift layer) ND during the regenerative operation of the inverter, The growth phenomenon of plane dislocation can be suppressed. In other words, conduction deterioration of the body diode can be prevented. Thus, stable inverter operation can be guaranteed for a long period of time.

The length (width) of the short side of the substantially rectangular p ⁺ -type semiconductor region PRG is not less than the resolution limit (for example, about 0.5 μm), and is 100 μm or less, more preferably 50 μm or less, and further more preferably. Can be 30 μm or less. For example, when a plurality of substantially rectangular patterns (p ⁺ -type semiconductor regions PRG) are arranged in the area GPA, when the arrangement area is about 50% of the area GPA, the line width / line space = about 20 μm / 20 μm It is preferable to dispose them.

(Embodiment 2)
In the present embodiment, a power converter including the semiconductor device (SiC power element) of the first embodiment will be described. FIG. 32 is a circuit diagram of the power converter (inverter) of the present embodiment. As shown in FIG. 32, the inverter of this embodiment includes a plurality of SiC power MOSFETs (also referred to as MISFETs (Metal Insulator Semiconductor FETs)) 404 as switching elements in a power module 402. In each single phase, the SiC power MOSFET 404 is connected between the power supply voltage Vcc and the input potential of the load (for example, the motor) 401 via the terminals 405 to 409, and the SiC power MOSFET 404 forms an upper arm. . The SiC power MOSFET 404 is also connected between the input potential of the load 401 and the ground potential GND, and the SiC power MOSFET 404 forms a lower arm. That is, in the load 401, two SiC power MOSFETs 404 are provided for each single phase, and six switching elements (SiC power MOSFETs 404) are provided for three phases.

  The power supply voltage Vcc is connected to the drain electrode of each single-layer SiC power MOSFET 404 via a terminal 405, and the ground potential GND is connected to the source electrode of each single-layer SiC power MOSFET 404 via a terminal 409. Have been. The load 401 is connected to the source electrode of the single-layer SiC power MOSFET 404 in the upper arm of each single layer via each of the terminals 406 to 408, and is connected to each single layer via each of the terminals 406 to 408. The lower arm is connected to the drain electrode of each single-layer SiC power MOSFET 404.

  A control circuit 403 is connected to the gate electrodes of the individual SiC power MOSFETs 404 via terminals 410 and 411, and the control circuit 403 controls the SiC power MOSFET 404. Therefore, the inverter of this embodiment can drive the load 401 by controlling the current flowing through the SiC power MOSFET 404 included in the power module 402 with the control circuit 403.

  As the SiC power MOSFET 404, the MOSFET formed on the semiconductor chip (see FIG. 1) described in the first embodiment is used. As shown in FIG. 32, the power converter has the MOSFET described in the first embodiment and a body diode (built-in pn diode).

  That is, the anode of the body diode is connected to the source electrode of the MOSFET, and the cathode is connected to the drain electrode of the MOSFET. Therefore, in each single layer shown in FIG. 32, the body diode is connected in antiparallel to the MOSFET. The function of the body diode at this time will be described below.

  When the load 401 is a pure resistor that does not include an inductance, the body diode is unnecessary because there is no energy to return. However, when a circuit including an inductance such as a motor (electric motor) is connected to the load 401, there is a mode in which a load current flows in a direction opposite to that of a MOSFET which is an ON switching element. At this time, since the MOSFET alone does not have a function of allowing the load current flowing in the reverse direction to flow, it is necessary to connect a body diode in antiparallel to the MOSFET.

  That is, in the power module 402, when the load 401 includes an inductance like a motor, for example, when the MOSFET is turned off, the energy stored in the inductance must be released. However, the MOSFET alone cannot flow a reverse current for releasing the energy stored in the inductance. Therefore, in order to circulate the electric energy stored in the inductance, a body diode is connected to the MOSFET in the reverse direction. That is, the body diode has a function of flowing a reverse current in order to release electric energy stored in the inductance.

  When the power module 402 is configured by MOSFETs and diodes, a semiconductor chip provided with a diode may be connected to a semiconductor chip provided with a MOSFET. However, in this case, it is necessary to provide a semiconductor chip including a diode in addition to the semiconductor chip including the MOSFET, and thus there is a problem that the power module 402 and the inverter are increased in size. Even when a semiconductor chip including a diode is not separately prepared, but a Schottky barrier diode or the like connected to a MOSFET is mixedly mounted on a semiconductor chip on which the MOSFET is formed, the problem of an increase in the size of the power module 402 and the inverter occurs. Occurs. Also, preparing the diode as described above without performing diodeless operation causes an increase in the manufacturing cost of the semiconductor device.

  On the other hand, in the present embodiment, the power module 402 uses the MOSFET and the body diode described in the first embodiment. That is, the MOSFET shown in FIG. 2 and the body diode connected in antiparallel to the MOSFET are provided on one semiconductor chip. In a semiconductor chip including a basal plane dislocation, there is a problem that conduction degradation occurs when a pn current flows through a body diode. However, the semiconductor device described in the first embodiment has a problem in that a pn current flows through a built-in diode and a peripheral region. In addition, deterioration due to energization can be suppressed. This makes it possible to reduce the size, weight, and cost of the power conversion device including the inverter including the power module 402, while preventing the power supply from deteriorating.

  Further, the power converter can be used for a three-phase motor system. The load 401 shown in FIG. 32 is a three-phase motor. By using the power converter including the semiconductor device described in Embodiment 1 for the inverter, the size of the three-phase motor system can be reduced. .

(Embodiment 3)
The three-phase motor system described in the second embodiment can be used for automobiles such as hybrid automobiles, electric automobiles, and fuel cell automobiles. In this embodiment, an automobile equipped with a three-phase motor system will be described with reference to FIGS. FIG. 33 is a schematic diagram showing a configuration of the electric vehicle according to the present embodiment. FIG. 34 is a circuit diagram of the boost converter of the present embodiment.

  As shown in FIG. 33, the electric vehicle of the present embodiment includes a three-phase motor 503 that can input and output power to and from a drive shaft 502 to which drive wheels (wheels) 501a and drive wheels (wheels) 501b are connected. An inverter 504 for driving the three-phase motor 503 and a battery 505 are provided. Further, the electric vehicle of the present embodiment includes boost converter 508, relay 509, and electronic control unit 510, and boost converter 508 is connected to power line 506 to which inverter 504 is connected, and battery 505. It is connected to a power line 507. The three-phase motor 503 is a synchronous generator motor including a rotor in which permanent magnets are embedded and a stator in which three-phase coils are wound. As the inverter 504, the inverter described in Embodiment 2 is used.

  Boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 512 are connected to an inverter 513, as shown in FIG. Inverter 513 is, for example, similar to the inverter described in the second embodiment, and has the same element configuration in the inverter. Also in this case, the switching element is the SiC power MOSFET 514 and is driven by synchronous rectification. In the electric vehicle according to the present embodiment, the output is supplied to the three-phase motor 503 using the inverter 504 as the power conversion device and the boost converter 508 as the power conversion device, so that the three-phase motor 503 drives the wheels (wheels). Drive 501a and 501b.

  The electronic control unit 510 in FIG. 33 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor for detecting the rotor position of the three-phase motor 503, a charge / discharge value of the battery 505, and the like. Receive. Electronic control unit 510 outputs a signal for controlling inverter 504, boost converter 508, and relay 509.

  According to the present embodiment, the power converter of Embodiment 2 can be used for inverter 504 and boost converter 508 that are power converters. Further, the three-phase motor system according to the second embodiment can be used for a three-phase motor system including the three-phase motor 503, the inverter 504, and the like. As a result, it is possible to reduce the size of the drive system occupied in the electric vehicle while preventing the inverter 504 and the step-up converter 508 of the electric vehicle from being energized and to reduce the size, weight, and cost of the electric vehicle. .

  In this embodiment, an electric vehicle has been described. However, the above-described three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which a battery 505 is a fuel cell stack. .

(Embodiment 4)
The three-phase motor system according to Embodiment 2 can be used for railway vehicles. In the present embodiment, a railway vehicle using a three-phase motor system will be described. FIG. 35 is a circuit diagram including a converter and an inverter of the railway vehicle of the present embodiment.

  As shown in FIG. 35, for example, power of 25 kV is supplied to the railway vehicle from the overhead line OW via the pantograph PG. The voltage is reduced to 1.5 kV via the transformer 609, and converted from AC to DC by the converter 607. Further, the direct current is converted into alternating current by the inverter 602 via the capacitor 608, and the three-phase motor as the load 601 is driven. In the present embodiment, the switching element is synchronously rectified and driven as the SiC power MOSFET 604. The overhead wire OW is electrically connected to the line RT via the pantograph PG, the transformer 609, and the wheels WH.

  According to the present embodiment, the converter 607 can use the power converter of the second embodiment. That is, by supplying power from the power converter to the load 601, the wheels WH of the railway vehicle can be driven. Further, the three-phase motor system according to the second embodiment can be used for a three-phase motor system including a load 601, an inverter 602, and a control circuit. This makes it possible to reduce the size, weight, and cost of the railway vehicle while preventing the deterioration of the power supply to the inverter 602 and the converter 607 of the railway vehicle.

(Embodiment 5)
In the present embodiment, an application example of the first embodiment will be described.

(Application Example 1)
In the semiconductor device according to the first embodiment (FIGS. 1 to 3), as described above, the area around the gate pad (GP) (the area surrounded by the broken line in FIG. 1) GPA is a cell area. , And a MOSFET having a cell structure is arranged (for example, see FIG. 2B). That is, an n ⁺ -type source region SR, a p-type body region PB serving as a channel region, and a gate electrode GE arranged on the channel region via a gate insulating film GI, which constitute the MOSFET, are formed around the GPA. Placed in The n ⁺ -type source region SR is arranged inside the p-type body region PB, and the p ⁺ -type semiconductor region PR is arranged inside the n ⁺ -type source region SR (see FIG. 1). .

In this application example, the p-type body region PB arranged around the region GPA where the gate pad (GP) is arranged, the n ⁺ -type source region SR inside the p-type body region PB, and n ⁺ The p-type body region PB of the p ⁺ -type semiconductor region PR inside the n ⁺ -type source region SR is disposed so as to be in contact with the p-type body region PB of the region GPA, and the n ⁺ -type source region SR Is omitted. FIG. 36 is a plan view illustrating a configuration of a semiconductor device of Application Example 1 of the present embodiment, and FIG. 37 is a cross-sectional view illustrating a configuration of a semiconductor device of Application Example 1 of the present embodiment. FIG. 37 corresponds to a section taken along line DD of FIG.

As shown in FIGS. 36 and 37, in this application example, the substantially square p-type body region PB of the cell region is in contact with the p-type body region PB of the region GPA, and is located inside the substantially square p-type body region PB. Has only ap ⁺ type semiconductor region PR formed therein. The substantially square p-type body region PB and the p ⁺ -type semiconductor region PR inside the p-type body region PB are connected to the source electrode SE via a plug in the contact hole C1S (see FIG. 37).

  As described above, the source potential is supplied to the p-type body region PB of the region GPA by connecting the p-type body region PB of the region GPA and the source electrode SE via the substantially square p-type body region PB of the cell region. Easier to do.

(Application 2)
In the above-described application example 1, although the approximately square p-type body region PB of the cell region is used to supply the source potential better to the p-type body region PB of the region GPA, The p-type body region PB may be formed to be slightly larger than the gate pad (GP), and the source potential may be supplied using such a region.

  38 and 39 are plan views showing a configuration of a semiconductor device of Application Example 2 of the present embodiment, and FIG. 40 is a cross-sectional view showing a configuration of a semiconductor device of Application Example 2 of the present embodiment. . FIG. 40 corresponds to a section taken along line DD of FIG.

As shown in FIGS. 38 to 40, in this application example, the left and right p-type body regions PB of the region GPA are formed to be slightly larger than the gate pad (GP). This area is called an enlarged area PBw. The source electrode SE extends over the enlarged region PBw (see FIG. 40). Therefore, PBw includes an overlapping region between source electrode SE and p-type body regions PB on the left and right of region GPA. That is, the enlarged region PBw is provided in the p-type body region PB of the region GPA, and the enlarged region PBw and the source electrode SE are connected via the plug in the contact hole C1S. It is preferable to provide the p ⁺ -type semiconductor region PRG also in the enlarged region PBw.

  In this manner, by connecting the p-type body region PB of the region GPA and the source electrode SE via the enlarged region PBw, it becomes easier to supply the source potential to the left and right p-type body regions PBw of the region GPA.

  In the semiconductor device according to the present embodiment, the power conversion device described in the second embodiment, the three-phase motor system of the vehicle described in the third embodiment, and the inverter or converter of the railway vehicle described in the fourth embodiment And so on.

  As described above, the invention made by the present inventors has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof. is there.

401 load 402 power module 403 control circuit 404 power MOSFET
405-411 Terminal 501a Drive wheel (wheel)
501b Drive wheel (wheel)
502 Drive shaft 503 Three-phase motor 504 Inverter 505 Battery 506 Power line 507 Power line 508 Boost converter 509 Relay 510 Electronic control unit 511 Reactor 512 Smoothing capacitor 513 Inverter 514 Power MOSFET
601 Load 602 Inverter 604 Power MISFET
607 Converter 608 Capacitor 609 Transformer C1GE Contact hole C1GR Contact hole C1S Contact hole DE Drain electrodes GD1 to GD4 MOSFET
GE Gate electrode GF Gate finger GI Gate insulating film GND Ground potential GP Gate pad GPA region (region where gate pad is arranged)
GRa p ⁺ type semiconductor region GRb p ⁺ type semiconductor region IL1 Insulating film (field insulating film)
IL2 insulating film (interlayer insulating film)
ND n ⁻ type semiconductor layer NR n ⁺ type semiconductor region NS SiC substrate OA1 opening OW overhead wire PB p type body region PG pantograph PR p ⁺ type semiconductor region PRG p ⁺ type semiconductor region RT line SE source electrode SR source Region TM p-type semiconductor region Vcc Power supply voltage WH Wheel

Claims (11)

A first conductivity type semiconductor layer formed on the upper surface of the substrate and including silicon carbide;
A first well region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, formed on the semiconductor layer at an outer peripheral portion of the element formation region;
A first semiconductor region of the second conductivity type formed in the first well region;
A second well region of the second conductivity type formed in the element formation region and formed on the semiconductor layer;
A semiconductor device having a gate electrode formed on the second well region via a gate insulating film;
A gate pad connected to the gate electrode;
Has,
The first well region extends to a region where the gate pad is formed,
The gate electrode is disposed on the first well region via a first insulating film in a region where the gate pad is formed;
A second semiconductor region of the second conductivity type formed in the first well region in a formation region of the gate pad;
The impurity concentration of the second conductivity type of the second semiconductor region is much larger than the impurity concentration of said second conductivity type of said first well region,
The first semiconductor region is annularly arranged at an outer peripheral portion of the element formation region,
The second semiconductor region is connected to the first semiconductor region;
The second semiconductor region includes a plurality of rectangular patterns having long sides in a first direction,
The semiconductor device , wherein the first direction is a direction perpendicular to a <11-20> direction . The semiconductor device according to claim 1 ,
The semiconductor device, wherein a length of the rectangular pattern in a second direction orthogonal to the first direction is 100 μm or less. The semiconductor device according to claim 1,
The semiconductor element comprises:
An n-type source region formed on an upper surface of the semiconductor layer in the element formation region;
The gate electrode formed on the channel region in contact with the source region via the gate insulating film;
A third semiconductor region of the second conductivity type in contact with the source region;
Has,
The semiconductor device, wherein the source region and the third semiconductor region are arranged in a second well region of the second conductivity type that forms the channel region. The semiconductor device according to claim 3 ,
A semiconductor device, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region have substantially the same concentration of the second conductivity type. The semiconductor device according to claim 3 ,
A source electrode connected to the source region, the third semiconductor region, and the first semiconductor region;
And a drain electrode formed on the back surface of the substrate. The semiconductor device according to claim 3 ,
A semiconductor device having a diode composed of the second well region and the semiconductor layer. The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.   A power module comprising the semiconductor device according to claim 1. The power module according to claim 8 ,
A power module comprising an inverter constituted by a MOSFET as the semiconductor element according to claim 1. A power module having the semiconductor device according to claim 1,
A control circuit for controlling the semiconductor device in the power module;
A power conversion device comprising: The power converter according to claim 10 ,
A power converter, wherein the power module includes an inverter configured by a MOSFET that is the semiconductor element according to claim 1.