JP6309656B2 - Semiconductor device and manufacturing method thereof, power conversion device, three-phase motor system, automobile and railway vehicle - Google Patents

Description

  The present invention relates to a power semiconductor device including a plurality of power semiconductor devices and a manufacturing method thereof, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle.

  Conventionally, a power metal insulating film semiconductor field effect transistor (MISFET), which is one of power semiconductor devices, is a power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET). Was the mainstream.

  However, a power MISFET (hereinafter referred to as a SiC power MISFET) using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) can have a higher breakdown voltage and a lower loss than a Si power MISFET. . For this reason, particular attention is focused in the field of power-saving or environment-friendly inverter technology.

  The SiC power MISFET can reduce the on-resistance at the same breakdown voltage as compared with the Si power MISFET. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength that is about seven times larger than that of silicon (Si), and the epitaxial layer serving as a drift layer can be thinned. However, considering the original characteristics that should be obtained from SiC, it cannot be said that sufficient characteristics have been obtained yet, and further reduction of the on-resistance is desired from the viewpoint of highly efficient use of energy.

  One of the problems to be solved with respect to the on-resistance of a SiC power MISFET having a DMOS (Double diffused Metal Oxide Semiconductor) structure is a channel parasitic resistance. In a low withstand voltage 600V withstand voltage DMOS, the channel parasitic resistance is the main cause of the parasitic resistance, and in a high withstand voltage 3300V withstand voltage DMOS, it is next to the drift resistance. Therefore, this reduction in channel parasitic resistance is necessary for the SiC power MISFET.

  The cause of the high channel parasitic resistance is the low channel mobility of the Si (0001) plane, which is the DMOS channel plane. In order to solve this problem, Patent Document 1 discloses that a trench is formed so as to dig a part of a DMOS p-type body layer and the outside of the body layer, thereby widening an effective channel width. A method is disclosed. In order to reduce the channel parasitic resistance, the use of the (11-20) plane or (1-100) plane from which high channel mobility can be obtained has been studied. In order to use a surface with high channel mobility such as the (11-20) plane or the (1-100) plane, it is necessary to form a MOS having a trench structure on the (0001) plane substrate. However, since the trench MOS is formed not only in the lower part of the p-type body layer that supports the breakdown voltage but also in the gate insulating film and a part of the gate, an electric field exceeding the breakdown voltage is applied to the gate insulating film, It leads to dielectric breakdown. Therefore, attempts have been made to relax the electric field applied to the gate insulating film while having a trench structure. Patent Document 2 discloses a method of relaxing an electric field applied to a gate insulating film by forming a part of a p-type body layer at a position lower than a gate insulating film formed under a trench.

  Patent Document 3 proposes a structure in which a p-type electric field relaxation region is provided below a trench as one of trench-type MOSs.

International Publication No. 2010/110246 JP 2009-260253 A JP 2012-43955 A

  However, in the techniques disclosed in Patent Document 1 and Patent Document 2, since both of the trench structures are exposed to the outside of the p-type body layer, the electric field applied to the gate insulating film is a normal DMOS. High compared to the structure. Therefore, even if the initial withstand voltage is equal to or higher than the desired withstand voltage, the oxide film is destroyed over time. In the technique disclosed in Patent Document 3, since the current path is limited due to the presence of the electric field relaxation region, the resistance of the element is increased.

  The object of the present invention is to use a trench structure that can be expected to have a high channel mobility, and to suppress the electric field applied to the gate insulating film below the trench to a level equivalent to or lower than that of a DMOS, thereby achieving high performance and high reliability. A semiconductor device and a manufacturing method thereof are provided. As a result, a compact, high-performance, and highly reliable power converter using the semiconductor device and a three-phase motor system using the power converter are provided. Furthermore, the present invention provides light weight, high performance, and high reliability of automobiles and railway vehicles using the three-phase motor system.

  In the present invention, a first conductivity type semiconductor substrate, a drain electrode formed on the back side of the semiconductor substrate, a first conductivity type drift layer formed on the surface side of the semiconductor substrate, and the first conductivity type A source region of the first conductivity type, a current diffusion layer of the first conductivity type, a body layer of a second conductivity type opposite to the first conductivity type in contact with the source region and the current diffusion layer, a source region, a body layer, And a trench extending to the current spreading layer, shallower than the body layer and having a bottom surface in contact with the body layer, and deeper than the boundary between the current spreading layer and the body layer. A high-concentration JFET layer of a first conductivity type having an impurity concentration higher than that of the drift layer, a gate insulating film formed on the inner wall of the trench, and a gate electrode formed on the gate insulating film; The above-mentioned problem Resolve.

  According to the present invention, a high-performance and highly reliable power semiconductor device can be provided. As a result, high performance of the power conversion device, the three-phase motor system, the automobile, and the railway vehicle can be realized.

It is a principal part top view of the semiconductor chip with which the silicon carbide semiconductor device comprised by several SiC power MISFET by Embodiment 1 of this invention was mounted. It is a principal part bird's-eye view of SiC power MISFET by Embodiment 1 of this invention. FIG. 6 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is principal part sectional drawing of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device by Embodiment 1 of this invention. FIG. 5 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 4. FIG. 6 is a main-portion cross-sectional view of the same portion of the silicon carbide semiconductor device as shown in FIG. 4 in the manufacturing process of the silicon carbide semiconductor device continued from FIG. 5; FIG. 7 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 6. FIG. 8 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 7. FIG. 9 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 8. FIG. 10 is a main part top view in the manufacturing process of the silicon carbide semiconductor device, following FIG. 9; FIG. 10 is a main-portion cross-sectional view of the segment AA 'in FIG. 10 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 9; FIG. 10 is a main-portion cross-sectional view of the segment BB 'in FIG. 10 (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 9; FIG. 10 is a main-portion cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 during the manufacturing process of the silicon carbide semiconductor device, following FIGS. FIG. 12 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 11. FIG. 13 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 12. FIG. 14 is a principal part cross-sectional view of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 13. FIG. 15 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for producing the silicon carbide semiconductor device continued from FIG. 14. FIG. 16 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for producing the silicon carbide semiconductor device continued from FIG. 15. FIG. 17 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for manufacturing the silicon carbide semiconductor device continued from FIG. 16. FIG. 18 is a cross-sectional view of a principal portion of the silicon carbide semiconductor device in the same place as in FIG. 4 in the process for producing the silicon carbide semiconductor device continued from FIG. 17. It is a principal part bird's-eye view of SiC power MISFET by Embodiment 2 of this invention. It is principal part sectional drawing of the silicon carbide semiconductor device explaining the manufacturing process of the silicon carbide semiconductor device by Embodiment 2 of this invention. FIG. 21 is a main-portion cross-sectional view of the silicon carbide semiconductor device, following FIG. 20; FIG. 22 is a main part cross-sectional view of the silicon carbide semiconductor device, following FIG. 21. FIG. 23 is a main-portion top view of the silicon carbide semiconductor device in the manufacturing process, following FIG. 22; FIG. 23 is a main-portion cross-sectional view of the segment AA ′ in FIG. 23- (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 22; FIG. 23 is a main-portion cross-sectional view of the segment BB ′ in FIG. 23- (a) during the manufacturing process of the silicon carbide semiconductor device, following FIG. 22; FIG. 24 is a main part top view in the manufacturing process of the silicon carbide semiconductor device, following FIGS. 23 (a) to 23 (c). FIG. 25 is an essential part top view of the silicon carbide semiconductor device in the manufacturing process, following FIG. 24; FIG. 26 is a top view of essential parts in the process of manufacturing the silicon carbide semiconductor device, following FIG. 25. FIG. 27 is a top view of a principal portion in the manufacturing process of the silicon carbide semiconductor device, following FIG. 26. FIG. 28 is a top view of a principal portion in the manufacturing process of the silicon carbide semiconductor device, following FIG. 27. FIG. 29 is a top view of essential parts in the process of manufacturing the silicon carbide semiconductor device, following FIG. 28. FIG. 30 is a main part top view in the manufacturing process of the silicon carbide semiconductor device, following FIG. 29; FIG. 31 is an essential part top view of the silicon carbide semiconductor device in the manufacturing process, following FIG. 30; It is a circuit diagram of the power converter device (inverter) carrying Embodiment 1 or Embodiment 2 by Embodiment 3 of this invention. It is a circuit diagram of the power converter device (inverter) carrying Embodiment 1 or Embodiment 2 by Embodiment 4 of this invention. It is a circuit diagram of the power converter device (inverter) which mounts Embodiment 1 or Embodiment 2 by Embodiment 5 of this invention. It is a block diagram of the electric vehicle carrying Embodiment 1 or Embodiment 2 by Embodiment 6 of this invention. It is a circuit diagram of the boost converter which mounts Embodiment 1 or Embodiment 2 by Embodiment 7 of this invention. It is a block diagram of the railway vehicle carrying Embodiment 1 or Embodiment 2 by Embodiment 8 of this invention.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

≪Silicon carbide semiconductor device≫
The structure of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a top view of a main part of a semiconductor chip on which a silicon carbide semiconductor device composed of a plurality of SiC power MISFETs is mounted, and FIG. 2 is a bird's-eye view of the main parts of the SiC power MISFET. The SiC power MISFET constitutes the silicon carbide semiconductor device.

  As shown in FIG. 1, a semiconductor chip 1 on which a silicon carbide semiconductor device is mounted includes an active region (formation of SiC power MISFET formation) located below a source wiring electrode 2 in which a plurality of n-channel SiC power MISFETs are connected in parallel. Region, element formation region) and a peripheral formation region surrounding the active region in plan view. The peripheral formation region includes a plurality of p-type floating field limited rings (FLRs) 3 formed so as to surround the active region in plan view, and the plurality of the plurality of p-type floating field limited rings (FLR) in plan view. An n-type guard ring 4 is formed so as to surround the p-type floating field limiting ring 3.

On the surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as SiC epitaxial substrate), a gate electrode of an SiC power MISFET, an n ⁺⁺ type source region, a channel region, and the like are formed. An n ⁺ type drain region of the SiC power MISFET is formed on the back surface side of the epitaxial substrate.

By forming a plurality of p-type floating field limiting rings 3 around the active region, the maximum electric field portion sequentially moves to the outer p-type floating field limiting ring 3 when off. Since breakdown occurs at the outermost p-type floating field limiting ring 3, the silicon carbide semiconductor device can have a high breakdown voltage. Although FIG. 1 illustrates an example in which three p-type floating field limiting rings 3 are formed, the present invention is not limited to this. The n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

  The plurality of SiC power MISFETs 6 formed in the active region have a stripe pattern in plan view, and the gate electrodes of all the SiC power MISFETs are gated by lead wires (gate bus lines) connected to the respective stripe patterns. The wiring electrode 8 is electrically connected.

The plurality of SiC power MISFETs are covered with the source wiring electrode 2, and the source and body potential fixing layers of the respective SiC power MISFETs are connected to the source wiring electrode 2. The source wiring electrode 2 is connected to an external wiring through a source opening 7 provided in the insulating film. The gate wiring electrode 8 is formed away from the source wiring electrode 2 and is connected to the gate electrode of each SiC power MISFET. The gate wiring electrode 8 is connected to an external wiring through the gate opening 5. Further, the n ⁺ -type drain region formed on the back side of the n-type SiC epitaxial substrate is electrically connected to a drain wiring electrode (not shown) formed on the entire back surface of the n-type SiC epitaxial substrate. doing.

  Next, the structure of the SiC power MISFET according to the first embodiment will be described with reference to FIG.

Made of silicon carbide (SiC) ^{n +} -type SiC substrate (substrate) 101 surface of the (first main surface) side consisting, ^{n +} -type low silicon carbide impurity concentration than SiC substrate 101 (SiC) n ^- A type epitaxial layer 102 is formed, and an SiC epitaxial substrate 104 is constituted by the n ⁺ type SiC substrate 101 and the n ⁻ type epitaxial layer 102. The n ⁻ type epitaxial layer 102 functions as a drift layer. The thickness of the n ⁻ type epitaxial layer 102 is, for example, about 5 to 50 μm.

  A p-type body layer (well region) 105 is formed in the epitaxial layer 102 with a predetermined depth from the surface of the epitaxial layer 102.

Although not shown, a p ⁺⁺ type body layer potential fixing region 106 is formed.

Further, an n ⁺ type source region 107 having nitrogen as an impurity is formed in the p type body layer 105 with a predetermined depth from the surface of the epitaxial layer 102.

In the epitaxial layer 102 sandwiched between the p-type body layer 105 and the p-type body layer 105, an n-type current diffusion layer 108-A having a predetermined depth from the surface of the epitaxial layer 102 is formed. ing. The epitaxial layer 102 sandwiched between the p-type body layer 105 and the p-type body layer 105 has a predetermined depth from the surface of the epitaxial layer 102 and has a p ⁺ -type gate insulating film protective layer 108. -B is formed.

The epitaxial layer 102 sandwiched between the p-type body layer 105 and the p-type body layer 105 has a predetermined depth from the surface of the epitaxial layer 102 to a predetermined depth, and is an n ⁻ -type epitaxial layer. An n-type high-concentration JFET layer 117 having an impurity concentration higher than the impurity concentration of 102 is formed.

A trench 109 extending from the n ⁺ type source region 107 across the p type body layer 105 to the n type current diffusion layer 108 -A and the p type gate insulating film protective layer 108 -B is formed. Is formed. The bottom surface of the trench 109 is in contact with the p-type body layer 105. Gate insulation is provided between the surface of the trench 109, the surface of the p-type body layer 105, the p-type gate insulating film protection layer 108 -B, and the surface of the epitaxial layer 102 sandwiched between the p-type body layers 105. A film 110 (not shown in FIG. 2) is formed. A gate electrode 111 is formed on the gate insulating film 110 except for the epitaxial layer 102 sandwiched between the p-type body layers 105.

The depth (first depth) of the p-type body layer 105 from the surface of the epitaxial layer 102 is, for example, about 0.5 to 2.0 μm. Further, the depth (third depth) of the n ⁺⁺ type source region 107 from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.6 μm. On the other hand, the depth (fourth depth) of the n ⁺ -type current diffusion layer region 108 -A from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.7 μm. The depth (fifth depth) of the p ⁺ -type gate insulating film protective layer 108-B from the surface of the epitaxial layer 102 is, for example, about 0.05 to 0.3 μm. The depth (sixth depth) of the upper surface of the n-type high-concentration JFET layer 117 from the surface of the epitaxial layer 102 is the depth of the n ⁺ -type current diffusion layer region 108 -A from the surface of the epitaxial layer 102 ( 4th depth), for example, about 0.1 to 0.7 μm. The depth (seventh depth) of the lower surface of the n-type high-concentration JFET layer 117 from the surface of the epitaxial layer 102 is the depth of the n ⁺ -type current diffusion layer region 108 -A from the surface of the epitaxial layer 102 ( Deeper than the fourth depth), that is, deeper than the boundary between the n ⁺ -type current diffusion layer region 108 -A and the p-type body layer 105, for example, about 0.5 to 2.0 μm. The depth of the trench 109 from the surface of the epitaxial layer 102 (eighth depth) is shallower than the depth of the p-type body layer 105 from the surface of the epitaxial layer 102 (first depth). ˜1.5 μm. The length in the direction parallel to the channel length of the trench is, for example, about 1 to 3 μm. The length in the direction parallel to the channel width of the trench is, for example, about 0.1 to 2 μm. The trench interval in the direction parallel to the channel width is, for example, about 0.1 to 2 μm.

Although not shown, the depth (second depth) of the p ⁺⁺ type body layer potential fixing region 106 from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.3 μm.

Note that “ ⁻ ” and “ ⁺ ” are signs representing the relative impurity concentration of the n-type or p-type conductivity, for example, “n ⁻ ”, “n”, “n ⁺ ”, “n ⁺⁺ ”. The impurity concentration of the n-type impurity increases in this order.

A preferable range of the impurity concentration of the n ⁺ -type SiC substrate 101 is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁻ type epitaxial layer 102 is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . A preferable range of the impurity concentration of the p-type body layer 105 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁺⁺ type source region 107 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . A preferable range of the impurity concentration of the n-type current diffusion region 108-A is, for example, 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ . A preferable range of the impurity concentration of the p ⁺ -type gate insulating film protective layer 108-B is, for example, 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ . A preferable range of the impurity concentration of the n-type high concentration JFET region 117 is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ . Although not shown, a preferable range of the impurity concentration of the p ⁺⁺ type body layer potential fixing region 106 is, for example, a range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . The impurity concentration of the n-type current diffusion region 108-A is likely to contribute to resistance because the n-type current diffusion region 108-A is directly connected to the channel, so that the n-type high-concentration JFET region 117 Make it higher than the impurity concentration.

  The channel region is the surface of the trench 109 and the surface of the p-type body layer 105 sandwiched between the trenches 109.

A gate insulating film 110 is formed on the channel region, and a gate electrode 111 is formed on the gate insulating film 110. The end portion of the gate electrode 111 on the JFET region side is formed so as to extend from the body layer 105 in the longitudinal direction of the trench 109, that is, in the channel direction of the trench 109, up to above the n-type high-concentration JFET region 117. Over the p ⁺ -type gate insulating film protective layer 108 -B.

  Next, features of the configuration of the SiC power MISFET according to the first embodiment will be described with reference to FIG.

As shown in FIG. 2 described above, since the side surface of the trench 109 becomes a channel region, a higher channel mobility can be expected as compared with the channel region on the surface of the SiC epitaxial substrate 104. Further, by forming the trench 109, the channel width is increased as compared with a normal DMOS structure in which no trench is formed, and a low channel resistance can be expected. Further, the n-type impurity layer is formed to a position deeper than the boundary between the current diffusion layer 108-A and the body layer 105, and electrically connects the drift layer and the current diffusion layer 108-A. Since the high concentration JFET region 117 is provided, a low JFET resistance can be expected. Since the trench is formed only in the p-type body layer 105, the gate insulating film formed on the trench surface when the withstand voltage is maintained, as compared with a normal trench type MOS structure having a portion exposed from the p-type body layer. The electric field applied to can be greatly relaxed. In this embodiment, a p ⁺ -type gate insulating film protective layer 108 -B is provided between the n-type high-concentration JFET region 117 and the gate insulating film 110 in a region sandwiched between adjacent channel regions. ing. Thereby, the oxide film electric field above the n-type high concentration JFET region 117 can be greatly reduced. Further, in this embodiment, the end portion of the gate electrode 111 is formed above the p ⁺ type gate insulating film protective layer 108-B. Therefore, it is possible to further relax the oxide film electric field on the JFET region at the time of holding the withstand voltage as compared with the normal DMOS structure.

As described above, by having high channel mobility and a wide channel width, it is possible to realize a low channel resistance comparable to that of a normal trench type MOS structure, and also to realize a low JFET resistance. Therefore, a high current density can be realized. Furthermore, since high insulation film reliability can be obtained, it is possible to provide a SiC power MOSFET that is more reliable than a normal DMOS structure. Further, since the gate electrode 111 is not formed on the JFET region, the area having an electric capacity with the n ⁻ type epitaxial layer 102 is small. Therefore, it is possible to reduce the mirror effect generated at the time of switching and to reduce the switching loss. Thus, it is possible to provide lower conduction loss and switching loss than the normal DMOS structure.

≪Method for manufacturing silicon carbide semiconductor device≫
A method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. FIG. 3 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 4 to 9 and FIGS. 10B to 18 are cross-sectional views of main parts showing an enlarged part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device. FIG. 10A is a top view of a principal part of a semiconductor chip on which a silicon carbide semiconductor device constituted by a SiC power MISFET is mounted.

<Process P1>
First, as shown in FIG. 4, an n ⁺ -type 4H—SiC substrate 101 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 101. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The n ⁺ -type SiC substrate 101 has both a Si surface and a C surface, but the surface of the n ⁺ -type SiC substrate 101 may be either an Si surface or a C surface.

Next, an n ⁻ type epitaxial layer 102 of silicon carbide (SiC) is formed on the surface (first main surface) of the n ⁺ type SiC substrate 101 by an epitaxial growth method. In the n ⁻ type epitaxial layer 102, an n type impurity lower than the impurity concentration of the n ⁺ type SiC substrate 101 is introduced. The impurity concentration of the n ⁻ -type epitaxial layer 102 depends on the element rating of the SiC power MISFET, but is, for example, in a range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ type epitaxial layer 102 is, for example, 5 to 50 μm. Through the above steps, SiC epitaxial substrate 104 including n ⁺ type SiC substrate 101 and n ⁻ type epitaxial layer 102 is formed.

<Process P2>
Next, the n ⁺ -type drain region has a predetermined depth (seventh depth) from the back surface (second main surface) of the n ⁺ -type SiC substrate 101 and is formed on the back surface of the n ⁺ -type SiC substrate 101. 103 is formed. The impurity concentration of the n ⁺ -type drain region 103 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 5, a mask M <b> 1 is formed on the surface of the n ⁻ type epitaxial layer 102. The thickness of the mask M1 is, for example, about 1.0 to 3.0 μm. The width of the mask M1 in the element formation region is, for example, about 1.0 to 5.0 μm. As the mask material, an inorganic material SiO ₂ film, Si film, SiN film, organic material resist film, or polyimide film can be used.

Next, p-type impurities, for example, aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 102 through the mask M1. Thereby, the p-type body layer 105 is formed in the element formation region of the n ⁻ -type epitaxial layer 102. Although not shown, a p-type floating field limiting ring 3 is formed around the element formation region at the same time. The structure of the terminal portion is not limited to this, and may be, for example, a junction termination extension (JTE) structure.

The depth (first depth) of the p-type body layer 105 from the surface of the epitaxial layer 102 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the p-type body layer 105 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 6, after removing the mask M1, the mask M2 is formed of, for example, a resist film. The thickness of the mask M2 is, for example, about 0.5 to 3 μm. The mask M2 is provided with an opening only in a region where the potential fixing region 106 of the p ⁺⁺ type body layer that fixes the potential of the p type body layer 105 in a later step is formed.

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted into the n ⁻ -type epitaxial layer 102 through the mask M2, thereby forming a potential fixing region 106 of the p ^++- type body layer. The depth (second depth) of the potential fixing region 106 of the p ⁺⁺ type body layer from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.3 μm. The impurity concentration of the potential fixing region 106 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 7, after removing the mask M2, the mask M3 is formed of, for example, a resist film. The thickness of the mask M3 is, for example, about 0.5 to 3 μm. In the mask M3, an opening is provided in a region where the n ⁺⁺ type source region 107 is formed in a later step. Although not shown, the mask M3 is also provided with an opening in a region where the guard ring 4 is formed on the outer periphery of the floating field limiting ring 3.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through the mask M3 to form an n ⁺⁺ type source region 107 in the element formation region. An n ⁺⁺ type guard ring 4 is formed in the formation region. The depth (third depth) from the surface of the epitaxial layer 102 of the n ⁺⁺ type source region 107 and the n ⁺⁺ type guard ring 4 is, for example, about 0.1 to 0.6 μm. The impurity concentration of the n ⁺⁺ type source region 107 and the n ⁺⁺ type guard ring 4 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 8, after removing the mask M3, the mask M4 is formed of, for example, a resist film. The thickness of the mask M4 is, for example, about 0.5 to 3 μm. The mask M4 has an opening in a region where the n ⁺ -type current diffusion region 108-A is formed in a later step.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through the mask M4, and an n ⁺ -type is formed in the element formation region partially including the region 105 formed using the mask M3. A current diffusion region 108-A is formed. The depth (fourth depth) of the n ⁺ -type current diffusion region 108 -A from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.7 μm. The impurity concentration of the n ⁺ -type current diffusion region 108 -A is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, aluminum atoms (Al) are ion-implanted as a p-type impurity into the epitaxial layer 102 through the mask M4 to form a p ⁺ -type gate insulating film protection region 108-B in the element formation region. The depth (fifth depth) of the p ⁺ -type gate insulating film protection region 108 -B from the surface of the epitaxial layer 102 is, for example, about 0.05 to 0.3 μm. The impurity concentration of the p ⁺ -type gate insulating film protection region 108-B is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

  Next, as shown in FIG. 9, after removing the mask M4, the mask M5 is formed of, for example, a resist film. The thickness of the mask M5 is, for example, about 0.5 to 3 μm. The mask M5 is provided with an opening in a region where an n-type high concentration JFET region 117 is formed in a later step. The opening portion of the mask M5 overlaps with the opening portion of the mask M4.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through the mask M5 to form an n-type high concentration JFET region 117 in the element formation region. The upper depth (sixth depth) of the n-type high-concentration JFET region 117 is shallower than the fourth depth, for example, about 0.1 to 0.7 μm. The lower depth (seventh depth) of the n-type high-concentration JFET region 117 is approximately the same as the depth (first depth) of the p-type body layer 105, for example, 0.5 to 2.0 μm. Degree. As a result, the n-type high-concentration JFET region 117 is formed up to a region deeper than the n ⁺ -type current diffusion region 108-A. Further, since the opening portion of the mask M5 overlaps with the opening portion of the mask M4, the n-type high-concentration JFET region 117 is in contact with and electrically connected to the n ⁺ -type current diffusion region 108-A. . The impurity concentration of the n-type high-concentration JFET region 117 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

<Process P3>
Next, after removing the mask M5, although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 104 by, for example, a plasma CVD method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of SiC epitaxial substrate 104 with this carbon (C) film, heat treatment is performed on SiC epitaxial substrate 104 at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. Thereby, each impurity ion-implanted into SiC epitaxial substrate 104 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

<Process P4>
Next, as shown in FIGS. 10A to 10C, a mask M6 is formed of, for example, a resist film. 10A is a top view of the main part, FIG. 10B is a cross-sectional view of the main part of the line segment AA ′ in FIG. 10A, and FIG. 10C is the line BB ′ in FIG. It is principal part sectional drawing. The thickness of the mask M6 is, for example, about 0.5 to 3 μm. The mask M6 has an opening in a region where the trench 109 is formed in a later process.

Next, using a dry etching process, an n ⁺⁺ type source region 107, a p type body layer 105, an n ⁺ type current diffusion region 108-A, and a p ⁺ type gate insulating film protection region 108-B , Trenches 109 are formed. The depth of the trench to be formed is shallower than the depth of the p-type body layer 105 and deeper than the depth of the p ⁺ -type gate insulating film protection region 108 -B. The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length in the direction parallel to the channel length of the trench is, for example, about 1 to 3 μm. The length in the direction parallel to the channel width of the trench is, for example, about 0.1 to 1 μm. The trench interval in the direction parallel to the channel width is, for example, about 0.1 to 1 μm.

<Process P5>
Next, as shown in FIG. 11, after removing the mask M <b> 6, a gate insulating film 110 is formed on the surface of the epitaxial layer 102 and the surface of the trench 109. The gate insulating film 110 is made of, for example, a SiO ₂ film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 12, an n-type polycrystalline silicon (Si) film 111 </ b> A is formed on the gate insulating film 110. The thickness of the n-type polycrystalline silicon (Si) film 111A is, for example, about 0.01 to 4 μm.

  Next, as shown in FIG. 13, using the mask M7 (photoresist film), the polycrystalline silicon (Si) film 111A is processed by a dry etching method to form the gate electrode 111. Next, as shown in FIG. At this time, the polycrystalline silicon (Si) film 111A on the JFET region sandwiched between the p-type body layers 105 is removed.

  Next, although illustration is omitted, after removing the mask M7, the gate electrode 111 is light-oxidized. For example, dry oxidation is performed at 900 ° C. for about 30 minutes.

<Process P6>
Next, as shown in FIG. 14, an interlayer insulating film 112 is formed on the surface of the epitaxial layer 102 so as to cover the gate electrode 111 and the gate insulating film 110 by, for example, a plasma CVD method.

Next, as shown in FIG. 15, using the mask M8 (photoresist film), the interlayer insulating film 112 and the gate insulating film 110 are processed by a dry etching method, and a part of the n ⁺⁺ type source region 107 and p Opening CNT_S reaching ⁺⁺ type body layer potential fixing region 106 is formed.

Next, as shown in FIG. 16, after removing the mask M8, a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106 exposed on the bottom surface of the opening CNT_S, respectively. A metal silicide layer 113 is formed on the surface.

First, although not shown in the drawing, for example, nickel (Ni) is used as the first metal film by, for example, sputtering so as to cover the inside (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT_S on the surface of the epitaxial layer 102. ). The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicidation heat treatment at 600 to 1000 ° C., the first metal film and the epitaxial layer 102 are reacted at the bottom surface of the opening CNT_S, and, for example, a nickel silicide (NiSi) layer is formed as the metal silicide layer 113. A portion of the n ⁺⁺ type source region 107 exposed on the bottom surface of the opening CNT_S and the surface of the p ⁺⁺ type body layer potential fixing region 106 are formed. Subsequently, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, sulfuric acid / hydrogen peroxide is used.

  Next, although not shown, the interlayer insulating film 112 is processed using a mask (photoresist film) to form an opening CNT_G reaching the gate electrode 111.

Next, as shown in FIG. 17, an opening CNT_S reaching the metal silicide film 113 formed on the surface of a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106, and A third metal film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film is formed on the interlayer insulating film 112 including the inside of the opening CNT_G (not shown) reaching the gate electrode 111. A laminated film is deposited. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the third metal film, a part of the n ⁺⁺ type source region 107 and the p ⁺⁺ type body layer potential fixing region 106 are electrically connected via the metal silicide layer 113 in the opening CNT_S. The source wiring electrode 2 to be connected and the gate wiring electrode 8 to be electrically connected through the gate electrode 111 and the opening CNT_G are formed.

Next, although not shown, an SiO ₂ film or a polyimide film is deposited as a passivation film so as to cover the gate wiring electrode 8 and the source wiring electrode 2.

  Next, although illustration is omitted, the passivation film is processed to form a passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited on the back surface of the n ⁺ -type SiC substrate 101 by, for example, sputtering. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 18, by applying the laser silicidation heat treatment, by reacting an SiC substrate 101 of the second metal film and the ^{n +} -type is formed on the back surface side of the SiC substrate 101 of ^{n +} -type A metal silicide layer 115 is formed so as to cover the n ⁺ -type drain region 103. Subsequently, a drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. The drain wiring electrode 116 is formed by depositing a laminated film of a Ti film, a Ni film, and a gold (Au) film by 0.5 to 1 μm.

  Thereafter, external wirings are electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively.

  As described above, according to the first embodiment, since the side surface of the trench 109 becomes a channel region, for example, when a 4 ° off Si (0001) plane substrate is used, the (11-20) plane or (1-100) ) Surface can be used as a channel surface. Therefore, high channel mobility can be expected as compared with the channel region on the surface of the SiC substrate (substrate) 101. Further, by forming the trench 109, the channel width is increased as compared with a normal DMOS structure in which no trench is formed, and a low channel resistance can be expected. Further, since the high concentration JFET region 117 is continuously connected to the current diffusion region 108-A, a low JFET resistance can be expected.

Further, the trench 109 is formed in a range shallower than the depth of the p-type body layer 105, and the bottom of the bottom of the trench 109 is surrounded by the p-type body layer 105. Therefore, in the present embodiment, the electric field applied to the gate insulating film formed on the trench surface at the time of holding the withstand voltage is greatly reduced as compared with a normal trench type MOS structure having a portion exposed from the p-type body layer. be able to. In this embodiment, a p ⁺ type gate insulating film protective layer 108 -B is provided between the n type high concentration JFET region 117 and the gate electrode 111. Thereby, the oxide film electric field above the n-type high concentration JFET region 117 can be greatly reduced. Further, in this embodiment, the end portion of the gate electrode 111 is formed above the p ⁺ type gate insulating film protective layer 108-B. Therefore, the electric field of the gate insulating film applied at the off time can be further greatly reduced as compared with the normal DMOS structure. In the present embodiment, the electric capacity between the gate electrode 111 and the n ⁻ -type epitaxial layer 102 can be reduced, and not only the conduction loss but also the switching loss can be reduced. is there. As described above, it is possible to provide a silicon carbide semiconductor device having a lower loss and higher reliability than a normal DMOS structure and a method for manufacturing the same.

  The difference between the second embodiment and the first embodiment described above is that the entire JFET region above the high-concentration JFET region 117 as shown in the bird's-eye view of the main part of the SiC power MISFET in FIG. The gate insulating film protection region 108 -B and the gate electrode 111 are covered. Since the gate electrode 111 has a structure covering the entire JFET region, the area of the gate electrode 111 on the chip is widened, and the gate resistance can be reduced. Furthermore, since the gate insulating film protection region 108-B covers the entire JFET region, it is possible to reduce the gate insulating film electric field applied at the time of OFF.

Further, since the gate insulating film protection region 108-B is present, gate electrode 111 and n in the JFET region ^- without -type epitaxial layer 102 is opposed, the gate electrode 111 and between the n ^- -type epitaxial layer 102 It is possible to reduce the electrical capacity of the switch, and no new switching loss occurs. Therefore, the second embodiment can reduce the gate resistance while maintaining the loss and the reliability as compared with the first embodiment, and enables further high-speed switching.

≪Method for manufacturing silicon carbide semiconductor device≫
A method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described in the order of steps with reference to FIGS. 20 to 31 are enlarged views of a part of the SiC power MISFET formation region (element formation region) of the silicon carbide semiconductor device of the present embodiment.

In the same manner as in the first embodiment, an n ⁻ type epitaxial layer 102 is formed on the surface (first main surface) of an n ⁺ type SiC substrate (substrate) 101 as shown in FIG. A SiC epitaxial substrate 104 having an n ⁺ type SiC substrate 101 and an n ⁻ type epitaxial layer 102 is formed. The impurity concentration of the n ⁺ -type SiC substrate 101 is, for example, in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the n ⁻ -type epitaxial layer 102 is 1 × 10 ¹⁴ to 1 × 10 6. It is in the range of ¹⁷ cm ⁻³ . Subsequently, an n ⁺ -type drain region 103 is formed on the back surface (second main surface) of the n ⁺ -type SiC substrate 101. The impurity concentration of the n ⁺ -type drain region 103 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted into the n ⁻ -type epitaxial layer 102 through the mask (not shown). Thereby, the p-type body layer 105 is formed in the element formation region of the epitaxial layer 102. Although not shown, a p-type floating field limiting ring is formed around the element formation region at the same time. The impurity concentration of the p-type body layer 105 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, a p-type impurity, for example, aluminum atoms (Al) is ion-implanted into the epitaxial layer 102 through a mask (not shown). As a result, the potential fixing region 106 of the p ⁺⁺ type body layer is formed in the p type body layer 105. The impurity concentration of the potential fixing region 106 of the p ⁺⁺ type body layer is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through a mask to form an n ⁺⁺ type source region 107 in the element formation region (not shown). The impurity concentration of the n ⁺⁺ type source region 107 is, for example, in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . Thereafter, the mask is removed.

Next, as shown in FIG. 21, a mask M4 ′ is formed of, for example, a resist film. The thickness of the mask M4 ′ is, for example, about 0.5 to 3 μm. The mask M4 ′ has an opening in a region where the n ⁺ -type current diffusion region 108-A is formed in a later step.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through the mask M4 ′ to form an n ⁺ -type current diffusion region 108-A in the element formation region. The depth (fourth depth) of the n ⁺ -type current diffusion region 108 -A from the surface of the epitaxial layer 102 is, for example, about 0.1 to 0.7 μm. The impurity concentration of the n ⁺ -type current diffusion region 108 -A is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ . The difference from the first embodiment is that an n ⁺ -type current diffusion region 108 -A is formed on the entire surface of the JFET region.

Next, aluminum atoms (Al) are ion-implanted as a p-type impurity into the epitaxial layer 102 through the mask M4 ′ to form a p ⁺ -type gate insulating film protection region 108-B in the element formation region. The depth (fifth depth) of the p ⁺ -type gate insulating film protection region 108 -B from the surface of the epitaxial layer 102 is, for example, about 0.05 to 0.3 μm. The impurity concentration of the p ⁺ -type gate insulating film protection region 108-B is, for example, in the range of 5 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ . The difference from the first embodiment is that a p ⁺ -type gate insulating film protection region 108-B is formed on the entire surface of the JFET region.

  Next, after removing the mask M4 ', the mask M5' is formed of a resist film, for example. The thickness of the mask M5 ′ is, for example, about 0.5 to 3 μm. The mask M5 'has an opening in a region where an n-type high concentration JFET region 117 is formed in a later step. The opening portion of the mask M5 'overlaps with the opening portion of the mask M4'.

Next, nitrogen atoms (N) are ion-implanted as an n-type impurity into the epitaxial layer 102 through the mask M5 ′ to form an n-type high-concentration JFET region 117 in the element formation region. The upper depth (sixth depth) of the n-type high-concentration JFET region 117 is shallower than the fourth depth, for example, about 0.1 to 0.7 μm. The lower depth (seventh depth) of the n-type high-concentration JFET region 117 is approximately the same as the depth (first depth) of the p-type body layer 105, for example, 0.5 to 2.0 μm. Degree. As a result, the n-type high-concentration JFET region 117 is formed up to a region deeper than the n ⁺ -type current diffusion region 108-A. Further, since the opening portion of the mask M5 ′ overlaps with the opening portion of the mask M4 ′, the n-type high-concentration JFET region 117 is in contact with and electrically connected to the n ⁺ -type current diffusion region 108-A. Is done. The impurity concentration of the n-type high-concentration JFET region 117 is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

  Next, after removing the mask M5 ', although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 104 by, for example, plasma CVD. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of SiC epitaxial substrate 104 with this carbon (C) film, heat treatment is performed on SiC epitaxial substrate 104 at a temperature of 1500 ° C. or higher for about 2 to 3 minutes. Thereby, each impurity ion-implanted into SiC epitaxial substrate 104 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

  Next, as shown in FIGS. 23B and 23C, a mask M6 'is formed of, for example, a resist film. 23A is a top view of the main part, FIG. 23B is a cross-sectional view of the main part of the line segment AA ′ in FIG. 23A, and FIG. 23C is the line BB ′ in FIG. It is principal part sectional drawing. The thickness of the mask M6 ′ is, for example, about 0.5 to 3 μm. The mask M6 'has an opening in a region where the trench 109 is formed in a later step.

  Next, a trench 109 is formed in the p-type body layer 105 using a dry etching process. The trench depth is, for example, about 0.1 to 1.5 μm. The length in the direction parallel to the channel length of the trench is, for example, about 1 to 3 μm. The length in the direction parallel to the channel width of the trench is, for example, about 0.1 to 1 μm. The trench interval in the direction parallel to the channel width is, for example, about 0.1 to 1 μm.

Next, as shown in FIG. 24, after removing the mask M 6 ′, a gate insulating film 110 is formed on the surface of the epitaxial layer 102 and the surface of the trench 109. The gate insulating film 110 is made of, for example, a SiO ₂ film formed by a thermal CVD method. The thickness of the gate insulating film 110 is, for example, about 0.005 to 0.15 μm.

  Next, as shown in FIG. 25, an n-type polycrystalline silicon (Si) film 111 </ b> A is formed on the gate insulating film 110. The thickness of the n-type polycrystalline silicon (Si) film 111A is, for example, about 0.01 to 4 μm.

  Next, as shown in FIG. 26, the polycrystalline silicon (Si) film 111A is processed by a dry etching method using a mask M7 '(photoresist film) to form the gate electrode 111. Next, although illustration is omitted, after removing the mask M7 ', the gate electrode 111 is light-oxidized. For example, dry oxidation is performed at 900 ° C. for about 30 minutes.

  Next, as shown in FIG. 27, an interlayer insulating film 112 is formed on the surface of the epitaxial layer 102 so as to cover the gate electrode 111 and the gate insulating film 110 by, for example, a plasma CVD method.

Next, as shown in FIG. 28, using the mask M8 ′ (photoresist film), the interlayer insulating film 112 and the gate insulating film 110 are processed by a dry etching method, and a part of the n ⁺⁺ type source region 107 and An opening CNT_S reaching the potential fixing region 106 of the p ⁺⁺ type body layer is formed.

Next, as shown in FIG. 29, after removing the mask M8 ′, a part of the n ⁺⁺ type source region 107 exposed on the bottom surface of the opening CNT_S and the potential fixing region 106 of the p ⁺⁺ type body layer. A metal silicide layer 113 is formed on each surface. First, although not shown, a first metal film, for example, nickel (Ni) is formed by sputtering, for example, so as to cover the inner surface (side surface and bottom surface) of the interlayer insulating film 112 and the opening CNT_S on the surface of the epitaxial layer 102. accumulate. The thickness of the first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicidation heat treatment at 600 to 1000 ° C., the first metal film and the epitaxial layer 102 are reacted at the bottom surface of the opening CNT_S, and for example, a nickel silicide (NiSi) layer is formed as the metal silicide layer 113. A portion of the n ⁺⁺ type source region 107 exposed on the bottom surface of the opening CNT_S and the surface of the potential fixing region 106 of the p ⁺⁺ type body layer are formed. Subsequently, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, sulfuric acid / hydrogen peroxide is used.

  Next, although not shown, the interlayer insulating film 112 is processed using a mask (photoresist film) to form an opening CNT_G reaching the gate electrode 111.

Next, as shown in FIG. 30, an opening CNT_S reaching the metal silicide film 113 formed on the surface of a part of the n ⁺⁺ type source region 107 and the potential fixing region 106 of the p ⁺⁺ type body layer, As a third metal film on the interlayer insulating film 112 including the inside of the opening CNT_G (not shown) reaching the gate electrode 111, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film are formed. A laminated film made of is deposited. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the third metal film, a part of the n ⁺⁺ type source region 107 and the potential fixing region 106 of the p ⁺⁺ type body layer are electrically connected to each other through the metal silicide layer 113 in the opening CNT_S. Next, the source wiring electrode 2 connected to the gate electrode 111 and the gate wiring electrode 8 electrically connected through the opening CNT_G are formed. Next, although not shown, a SiO ₂ film or a polyimide film is passivated. A film is deposited so as to cover the gate wiring electrode 8 and the source wiring electrode 2 as a film. Next, although illustration is omitted, the passivation film is processed to form a passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited on the back surface of the n ⁺ -type SiC substrate 101 by, for example, sputtering. The thickness of the second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 31, a laser silicidation heat treatment is performed to cause the second metal film and n ⁺ type SiC substrate 101 to react with each other to form the n ⁺ type SiC substrate 101 on the back surface side. A metal silicide layer 115 is formed so as to cover the n ⁺ -type drain region 103. Subsequently, a drain wiring electrode 116 is formed so as to cover the metal silicide layer 115. The drain wiring electrode 116 is formed by depositing a laminated film of a Ti film, a Ni film, and a gold (Au) film by 0.5 to 1 μm.

  Thereafter, external wirings are electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively.

  Thus, according to the second embodiment, as in the first embodiment, the gate on the chip is realized while realizing a silicon carbide semiconductor device having a lower loss and higher reliability than a normal DMOS structure and a manufacturing method thereof. Since the area of the electrode 111 is larger than that of the first embodiment, the gate resistance can be reduced. Therefore, further high-speed switching is possible.

  The semiconductor device having the SiCIMS FET described in the first embodiment and the semiconductor device having the SiCIMS FET described in the second embodiment can be used for a power conversion device. A power conversion apparatus according to Embodiment 3 will be described with reference to FIG. FIG. 32 is a circuit diagram showing an example of a power converter (inverter) in the third embodiment.

  As shown in FIG. 32, the inverter module 302 includes a SiCMISFET 304 that is a switching element and a diode 305. In each single phase, the SiCIMS FET 304 and the diode 305 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of the load (eg, motor) 301 (upper arm), and the input potential of the load 301 and the ground potential The SiCIMS FET element 304 and the diode 305 are also connected in reverse parallel to (GND) (lower arm). In other words, the load 301 is provided with two SiCMISFETs 304 and two diodes 305 for each single phase, and is provided with six switching elements 304 and six diodes 305 for three phases. A control circuit 303 is connected to the gate electrode of each SiCIMS FET 304, and the SiCIMS FET 304 is controlled by the control circuit 303. Therefore, the load 301 can be driven by controlling the current flowing through the SiCIMS FET 304 constituting the inverter module 302 by the control circuit 303.

  The function of the SiCIMS FET 304 constituting the inverter module 302 will be described below. In order to control and drive the load 301, for example, a motor, it is necessary to input a sine wave of a desired voltage to the load 301. The control circuit 303 controls the SiCIMS FET 304 and performs a pulse width modulation operation for dynamically changing the pulse width of the rectangular wave. The output rectangular wave is smoothed by passing through the inductor, and becomes a pseudo desired sine wave. The SiCIMS FET 304 has a function of creating a rectangular wave for performing this pulse width modulation operation.

  As described above, according to the third embodiment, by using the semiconductor device described in the first embodiment or the second embodiment described above as the SiCIMSFET 304, for example, the high performance of the SiCIMSFET 304, the inverter, etc. The power converter can be improved in performance. Moreover, since the SiCMISFET 304 has long-term reliability, it is possible to extend the service life of a power conversion device such as an inverter.

  Moreover, the power converter device of this Embodiment can be used for a three-phase motor system. The above-described load 301 shown in FIG. 32 is a three-phase motor. By providing the inverter module 302 with the semiconductor device described in the first embodiment or the second embodiment, a high-level three-phase motor system is provided. It is possible to achieve higher performance and longer service life.

  The semiconductor device having the SiCIMS FET described in the first embodiment and the semiconductor device having the SiCIMS FET described in the second embodiment can be used for a power conversion device. A power conversion device according to Embodiment 4 will be described with reference to FIG. FIG. 33 is a circuit diagram showing an example of a power converter (inverter) in the fourth embodiment.

  As shown in FIG. 33, the inverter module 302 includes a SiCMISFET 304 that is a switching element and a diode 305. In each single phase, the SiCIMS FET 304 and the diode 305 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of the load (eg, motor) 301 (upper arm), and the input potential of the load 301 and the ground potential The SiCIMS FET element 304 and the diode 305 are also connected in reverse parallel to (GND) (lower arm). In other words, the load 301 is provided with two SiCMISFETs 304 and two diodes 305 for each single phase, and is provided with six switching elements 304 and six diodes 305 for three phases. A control circuit 303 is connected to the gate electrode of each SiCIMS FET 304, and the SiCIMS FET 304 is controlled by the control circuit 303. Therefore, the load 301 can be driven by controlling the current flowing through the SiCIMS FET 304 constituting the inverter module 302 by the control circuit 303.

  The function of the SiCIMS FET 304 constituting the inverter module 302 will be described below. The SiCMISFET 304 described in the first embodiment and the second embodiment can obtain a higher current density than a normal DMOS. Therefore, a sufficiently high current can be obtained even if the difference (gate overdrive amount) between the applied gate voltage and the threshold voltage is small. Therefore, the amount of gate overdrive required for driving can be reduced, and the gate driving circuit 303 can be a single power source. That is, the DC voltage converter is unnecessary, and the fourth embodiment in which the gate drive circuit 303 is downsized and directly connected to the inverter module 302 can be provided. By using the fourth embodiment, an electromechanically integrated small system can be provided.

  The semiconductor device having the SiCIMS FET described in the first embodiment and the semiconductor device having the SiCIMS FET described in the second embodiment can be used for a power conversion device. A power conversion device according to Embodiment 5 will be described with reference to FIG. FIG. 34 is a circuit diagram showing an example of a power converter (inverter) in the fifth embodiment.

  As shown in FIG. 34, the inverter module 402 includes a SiCMISFET 404 that is a switching element. In each single phase, a SiCMISFET 404 is connected between the power supply voltage (Vcc) and the input potential of the load (eg, motor) 401 (upper arm), and between the input potential of the load 401 and the ground potential (GND). Also, the SiCMISFET element 404 is connected (lower arm). That is, in the load 401, two SiCISFETs 404 are provided for each single phase, and six switching elements 404 are provided for three phases. A control circuit 403 is connected to the gate electrode of each SiCIMS FET 404, and the SiCIMS FET 404 is controlled by the control circuit 403. Therefore, the load 401 can be driven by controlling the current flowing through the SiCIMS FET 404 constituting the inverter module 402 by the control circuit 403.

  The function of the SiCIMS FET 404 constituting the inverter module 402 will be described below. As one of the functions of the SiCMISFET 404, there is a function of creating a rectangular wave for performing a pulse width modulation operation as in the third embodiment. Further, the SiCIMS FET 404 plays a role of the diode 305 of the third embodiment. In the inverter module 402, when an inductance is included in the load 401 like a motor, for example, when the SiCIMS FET 404 is turned off, the energy stored in the inductance must be released (reflux current). In the third embodiment, the diode 305 plays this role. On the other hand, in the fifth embodiment, the SiCIMS FET 404 plays this role. That is, synchronous rectification driving is used in the fifth embodiment. Here, the synchronous rectification driving is a method in which the gate of the SiCMISFET 404 is turned on at the time of recirculation and the SiCMISFET 404 is reversely conducted.

  Therefore, the conduction loss during reflux is determined not by the characteristics of the diode but by the characteristics of the SiCIMS FET 404. Further, when performing synchronous rectification driving, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiCMISFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiCIMS FET 404 is driven. However, SiC has a shorter carrier travel distance than Si and has a small loss during non-operation time. For example, this is equivalent to the case where the diode 305 of the third embodiment is a SiC Schottky barrier diode.

  As described above, according to the fifth embodiment, by using the semiconductor device described in the first embodiment or the second embodiment described above as the SiCMISFET 404, for example, when the SiCIMS FET 404 has high performance, Loss can be reduced. In addition, since no diode is used, a power converter such as an inverter can be downsized. Furthermore, since the SiCMISFET 404 has long-term reliability, it is possible to extend the service life of a power conversion device such as an inverter.

  Moreover, the power converter of Embodiment 5 can be used for a three-phase motor system. The load 401 shown in FIG. 34 described above is a three-phase motor, and the inverter module 402 includes the semiconductor device described in the first embodiment or the second embodiment described above, thereby increasing the height of the three-phase motor system. It is possible to achieve higher performance and longer service life.

  In the fifth embodiment, the gate driving circuit 403 can be directly connected to the inverter module 402 as in the fourth embodiment. Therefore, the fifth embodiment is also suitable for an electromechanically integrated small system.

  The three-phase motor system described in the third embodiment, the fourth embodiment, or the fifth embodiment described above can be used for a vehicle such as a hybrid vehicle, an electric vehicle, and a fuel cell vehicle. An automobile using the three-phase motor system in the sixth embodiment will be described with reference to FIGS. 35 and 36. FIG. FIG. 35 is a schematic diagram showing an example of the configuration of the electric vehicle in the sixth embodiment, and FIG. 36 is a circuit diagram showing an example of the boost converter in the sixth embodiment.

  As shown in FIG. 35, the electric vehicle includes a three-phase motor 503 that can input / output power to / from a drive shaft 502 to which drive wheels 501a and 501b are connected, and an inverter 504 for driving the three-phase motor 503. And a battery 505. The electric vehicle further includes a boost converter 508, a relay 509, and an electronic control unit 510. The boost converter 508 includes a power line 506 to which an inverter 504 is connected and a power line 507 to which a battery 505 is connected. And connected to.

  The three-phase motor 503 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 504, the inverter described in the third embodiment, the fourth embodiment, or the fifth embodiment can be used.

  As shown in FIG. 36, boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 512 are connected to inverter 513. For example, the inverter 513 is the same as the inverter described in the fifth embodiment, and the element configuration in the inverter is also the same. In the sixth embodiment, for example, similarly to the fifth embodiment, a diagram including the SiCIMS FET 514 is shown.

  The electronic control unit 510 shown in FIG. 35 includes a microprocessor, a storage device, and an input / output port. A signal from a sensor that detects the rotor position of the three-phase motor 503, a charge / discharge value of the battery 505, and the like. Receive. Electronic control unit 510 outputs a signal for controlling inverter 504, boost converter 508, and relay 509.

  As described above, according to the sixth embodiment, the inverter 504 and the boost converter 508 which are power converters are connected to the power conversion described in the above-described third embodiment, the above-described fourth embodiment, and the above-described fifth embodiment. An apparatus can be used. In addition, the three-phase motor system described in the above-described third embodiment, the above-described fourth embodiment, or the above-described fifth embodiment is used for a three-phase motor system including the three-phase motor 503 and the inverter 504. Can do. Thereby, energy saving, size reduction, weight reduction, and space saving of an electric vehicle can be achieved.

  Although the electric vehicle has been described in the sixth embodiment, the three-phase motor system of each of the above-described embodiments is similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 505 is a fuel cell stack. Can be applied.

  The three-phase motor system described in the third embodiment, the fourth embodiment, and the fifth embodiment described above can be used for a railway vehicle. A railway vehicle using the three-phase motor system in the seventh embodiment will be described with reference to FIG. FIG. 37 is a circuit diagram showing an example of a converter and an inverter provided in the railway vehicle in the seventh embodiment.

  As shown in FIG. 37, electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 609 and converted from alternating current to direct current by the converter 607. Furthermore, it is converted from direct current to alternating current by an inverter 602 through a capacitor 608 to drive a three-phase motor as a load 601. The element configuration in converter 607 may be a combination of a SiCMISFET and a diode as in the third embodiment described above, or a single SiCIMSFET as in the aforementioned fifth embodiment. In the seventh embodiment, for example, a diagram including the SiCIMS FET 604 as in the fifth embodiment is shown. In FIG. 37, the control circuit described in the third embodiment, the fourth embodiment, or the fifth embodiment is omitted. Moreover, in the figure, symbol RT indicates a track, and symbol WH indicates a wheel.

  As described above, according to the seventh embodiment, the converter 607 can use the power conversion device described in the third embodiment, the fourth embodiment, or the fifth embodiment. In addition, the three-phase motor system described in the above-described third embodiment, the above-described fourth embodiment, or the above-described fifth embodiment is used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. Can do. As a result, it is possible to save energy in the railway vehicle and to reduce the size and weight of the underfloor parts.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the material, conductivity type, manufacturing conditions, etc. of each part are not limited to those described in the above-described embodiments, and it goes without saying that many modifications can be made. Here, for convenience of explanation, the description has been made with the conductivity types of the semiconductor substrate and the semiconductor film being fixed. However, the conductivity types are not limited to those described in the above-described embodiments.

1: Semiconductor chip, 2: Source wiring electrode (SiC power MISFET forming region, element forming region), 3: p-type floating field limiting ring, 4: n ⁺⁺ type guard ring, 5: gate opening Part: 6: SiC power MISFET, 7: source opening, 8: gate wiring electrode, 101: n ⁺ type SiC substrate (substrate), 102: n ⁻ type epitaxial layer, 103: n ⁺ type drain region 104: SiC epitaxial substrate, 105: p-type body layer (well region), 106: p ^++- type body layer potential fixing region, 107: n ^++- type source region, 108-A: n ⁺ -type current diffusion region, 108-B: ^{p +} -type gate insulating film protected area, 109: trench, 110: gate insulating film, 111: gate electrode, 117: n-type Concentration JFET layer.

Claims (15)

A first conductivity type semiconductor substrate having a first impurity concentration;
A back electrode formed on the back side of the semiconductor substrate;
A first region of the first conductivity type having a second impurity concentration lower than the first impurity concentration formed on the surface side of the semiconductor substrate;
A second region of the first conductivity type;
A third region of the first conductivity type having a second impurity concentration higher than the first impurity concentration;
On the first region, formed below the second region and the third region, in contact with the second region and the third region, opposite to the first conductivity type A fourth region of the second conductivity type;
The second region, the fourth region, and the third region extend, are shallower than the fourth region, have a bottom surface in contact with the fourth region, and a first side surface in contact with the second region. A trench in which a second side surface disposed opposite to the first side surface is in contact with the third region ;
The first conductivity having a higher impurity concentration than the first region, which is formed to a position deeper than a boundary between the second region and the fourth region, and electrically connects the first region and the second region. a fifth region of the mold,
An insulating film formed on the inner wall of the trench;
A gate electrode formed on the insulating film;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device, wherein a sixth region of the second conductivity type is formed between the fifth region and the insulating film. The semiconductor device according to claim 2,
The semiconductor device, wherein the sixth region is formed extending from the fourth region. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an impurity concentration of the second region is higher than an impurity concentration of the fifth region. The semiconductor device according to claim 1,
A semiconductor device characterized in that the semiconductor substrate is made of silicon carbide.   A power converter having the semiconductor device according to claim 1 as a switching element.   A three-phase motor system for converting DC power to AC power by the power conversion device according to claim 6 and driving a three-phase motor.   The motor vehicle which drives a wheel with the three-phase motor system of Claim 7.   A railway vehicle that drives wheels with the three-phase motor system according to claim 7. A first conductivity type semiconductor substrate;
A drain electrode formed on the back side of the semiconductor substrate;
The first conductivity type drift layer formed on the surface side of the semiconductor substrate;
A source region of the first conductivity type;
A current diffusion layer of the first conductivity type;
Second conductivity opposite to the first conductivity type, which is formed on the drift layer, below the source region and the current diffusion layer, and in contact with the source region and the current diffusion layer. The body layer of the mold,
And said source region, said body layer, extends, and the current diffusion layer, shallower than the body layer, the bottom is tangent to the body layer, a first side surface is in contact with said source region, said first a trench second side is disposed sides facing is contact with the current diffusion layer,
The first conductivity type high impurity layer having a higher impurity concentration than the drift layer is formed to a position deeper than a boundary between the current diffusion layer and the body layer, and electrically connects the drift layer and the current diffusion layer. A concentration JFET layer;
A gate insulating film formed on the inner wall of the trench;
And a gate electrode formed on the gate insulating film. The semiconductor device according to claim 10.
A semiconductor device, wherein the second conductive type gate insulating film protective layer is formed between the high-concentration JFET region and the gate insulating film. The semiconductor device according to claim 11,
The semiconductor device, wherein the gate insulating film protective layer is formed extending from the body layer. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein an impurity concentration of the current diffusion layer is higher than an impurity concentration of the high-concentration JFET layer. The semiconductor device according to claim 10.
A semiconductor device characterized in that the semiconductor substrate is made of silicon carbide. Preparing a semiconductor substrate on which an epitaxial layer of a first conductivity type having a first impurity concentration is formed;
Forming a first region of a second conductivity type opposite to the first conductivity type in the epitaxial layer;
Forming a second region of the first conductivity type in the first region;
Forming a third region of the first conductivity type with a first mask spaced apart from the second region in the epitaxial layer;
The second mask having an overlap with the first mask has a second impurity concentration higher than the first impurity concentration in the epitaxial layer to a region deeper than the formation depth of the third region. Forming a fourth region of the first conductivity type;
Said second region, said first region and extending in a third region, said shallower than the first region, the bottom surface is in contact with the first region, the first side is in contact with the second region Forming a trench in which the second side surface disposed opposite to the first side surface is in contact with the third region ;
Forming an insulating film on the inner wall of the trench;
A method of manufacturing a semiconductor device, comprising forming a gate electrode on the insulating film.

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