WO2015019731A1 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

Info

Publication number
WO2015019731A1
WO2015019731A1 PCT/JP2014/066818 JP2014066818W WO2015019731A1 WO 2015019731 A1 WO2015019731 A1 WO 2015019731A1 JP 2014066818 W JP2014066818 W JP 2014066818W WO 2015019731 A1 WO2015019731 A1 WO 2015019731A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon carbide
semiconductor device
side wall
trench
Prior art date
Application number
PCT/JP2014/066818
Other languages
French (fr)
Japanese (ja)
Inventor
増田　健良
透 日吉
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2015019731A1 publication Critical patent/WO2015019731A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a silicon carbide semiconductor device.
  • Silicon carbide semiconductor devices have many advantages such as low power loss and high-temperature operation compared to silicon semiconductor devices that are currently mainstream, and are expected as next-generation power semiconductor devices. Yes. At present, various approaches are being taken from the structural aspect of the device to pursue higher performance of the silicon carbide semiconductor device [see, for example, International Publication No. 2002/029900 (Patent Document 1). ].
  • the planar structure is one of the most basic structures and is widely used.
  • the channel region is formed in parallel to the semiconductor substrate.
  • this structure is suitable for increasing the breakdown voltage, there is a parasitic resistance called a JFET (Junction-Field-Effect-Transistor) resistance, and it is difficult to reduce the on-resistance.
  • JFET Joint-Field-Effect-Transistor
  • the trench gate structure does not include a JFET resistance component, it is suitable for low on-resistance.
  • dielectric breakdown of the gate insulating film tends to occur at the bottom of the trench, and it is difficult to increase the breakdown voltage.
  • the power semiconductor device handles a large current, it is required to be a normally-off type that has a high threshold voltage and can cut off the current without applying a gate voltage from the viewpoint of reducing power loss.
  • a high threshold voltage and a low on-resistance are generally in a trade-off relationship, and it is not easy to achieve both of them.
  • Patent Document 1 in a silicon carbide semiconductor device having a planar structure, an n-type accumulation channel is provided to reduce a channel resistance component and to reduce the on-resistance.
  • the semiconductor device disclosed in Patent Document 1 has a planar structure, it can have a relatively high breakdown voltage.
  • the n-type storage channel used in Patent Document 1 has a problem that the threshold voltage is lower than when a p-type semiconductor is used as the channel.
  • the threshold voltage is drastically lowered due to the short channel effect, and in some cases, there is a problem that punch-through is caused. That is, with this structure, it is extremely difficult to achieve both a high threshold voltage and a low on-resistance while having a high breakdown voltage.
  • an object is to provide a silicon carbide semiconductor device which has a high breakdown voltage and has both a high threshold voltage and a low on-resistance.
  • a silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface.
  • the silicon carbide layer has a first layer that constitutes the first main surface and has the first conductivity type, and a second conductivity type that is provided in the first layer and is different from the first conductivity type. And a third layer provided in at least the second layer and constituting a part of the second main surface and having the first conductivity type.
  • the second main surface of the silicon carbide layer is provided with a trench, and the trench is connected to the first side wall and the first side wall where the second layer and the third layer are exposed.
  • the silicon carbide semiconductor device further comprising: a gate insulating film covering each of the first side wall and the bottom; a gate electrode provided on the gate insulating film; Is provided.
  • the above silicon carbide semiconductor device has a high breakdown voltage, and can achieve both a high threshold voltage and a low on-resistance.
  • FIG. 4 schematically shows an exemplary configuration of a silicon carbide semiconductor device in one embodiment of the present invention, and is a partial cross sectional view taken along line II in FIG. 2.
  • FIG. 2 is a partial plan view schematically showing a shape of a silicon carbide layer included in the silicon carbide semiconductor device of FIG. 1. It is a flowchart which shows the outline of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in one embodiment of this invention. It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in one embodiment of this invention. It is a figure which shows one modification of the cross-sectional shape of the trench in one embodiment of this invention.
  • FIG. 4 is a partial cross sectional view schematically showing a third step (step 3) in the manufacturing process of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a fourth step (step 4) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 7 is a partial cross sectional view schematically showing a fifth step (step 5) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a sixth step (step 6) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal.
  • FIG. 13 is a view showing a crystal structure of a (11-20) plane along line XIII-XIII in FIG.
  • FIG. 21 is a view showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 11 in the (11-20) plane.
  • FIG. 12 is a view of the composite surface of FIG. 11 as viewed from the (01-10) plane.
  • FIG. 5 is a graph showing an example of a relationship between a channel surface and a (000-1) plane viewed macroscopically and channel mobility when a thermal etching is performed and when it is not performed. It is. It is a graph which shows an example of the relationship between the angle between a channel direction and the ⁇ 0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG. It is a graph which shows an example of the relationship between channel length, a threshold voltage, and characteristic ON resistance. It is a graph which shows another example of the relationship between channel length, a threshold voltage, and characteristic ON resistance.
  • the silicon carbide semiconductor device according to the present embodiment has the following configuration.
  • Silicon carbide semiconductor device 201 of the present embodiment includes a silicon carbide layer 101 having a first main surface P1 and a second main surface P2 opposite to the first main surface P1.
  • the silicon carbide layer 101 includes a first layer 81 constituting the first main surface P1 and having the first conductivity type, and a second layer provided in the first layer 81 and different from the first conductivity type.
  • the second main surface P2 of the silicon carbide layer 101 is provided with a trench TR, and the trench TR has a first side wall portion SW1 where the second layer 82 and the third layer 83 are exposed, and the second side surface SW1.
  • a silicon nitride semiconductor device 201 having a bottom portion BT connected to one side wall portion SW1 and positioned in the second layer 82, and a silicon carbide semiconductor device 201 covering each of the first side wall portion SW1 and the bottom portion BT;
  • a gate electrode 92 provided on the gate insulating film 91.
  • silicon carbide semiconductor device 201 since bottom portion BT of trench TR is located in second layer 82, a strong electric field is not applied to gate insulating film 91, and a high breakdown voltage can be exhibited. Similarly to the semiconductor device having the trench gate structure, the channel region CH is formed along the side wall of the trench TR. Therefore, the device can be easily miniaturized and the on-resistance can be reduced. Further, since the influence of the channel length on the device size is small as compared with a normal planar structure, a sufficient channel length can be ensured. Therefore, it can have a high threshold voltage. Thus, according to silicon carbide semiconductor device 201, it is possible to realize a silicon carbide semiconductor device having a high breakdown voltage and having both a high threshold voltage and a low on-resistance.
  • the impurity concentration in the second layer 82 constituting the channel region CH In order to further increase the threshold voltage, it is conceivable to increase the impurity concentration in the second layer 82 constituting the channel region CH. However, usually, when the impurity concentration in the second layer 82 is increased, the scattering of impurities due to the increase in dopant becomes significant, so that the channel mobility is greatly reduced and the on-resistance is increased. However, the portion of the first sidewall portion SW1 where the second layer 82 is exposed includes the first surface S1 having the plane orientation ⁇ 0-33-8 ⁇ , so that the impurity concentration in the second layer 82 is increased. Even if the channel height is increased, the channel mobility is not greatly decreased. Therefore, by adopting such a configuration, it is possible to achieve both high threshold voltage and low on-resistance at a high level.
  • the cross-sectional shape of the trench TR is preferably V-shaped.
  • the gate insulating film 91 protrudes greatly at the bottom portion BT, so that the electric field is easily concentrated on the portion, and the withstand voltage is reduced.
  • bottom portion BT is located in second layer 82, and the electric field does not concentrate, so that the withstand voltage does not decrease even when the shape is V-shaped.
  • the first surface S1 having the aforementioned plane orientation ⁇ 0-33-8 ⁇ can be easily included in the first side wall portion SW1 of the trench TR. That is, high threshold voltage and low on-resistance can be achieved at a high level.
  • the trench TR has a second side wall part SW2 that is disposed opposite to the first side wall part SW1 and that is continuous with the bottom part BT.
  • the second side wall part SW2 In the second side wall part SW2, the second layer 82 and the third side wall part SW2 are arranged. It is preferable that the layer 83 is exposed.
  • the channel region CH is formed along the first side wall part SW1, the bottom part BT, and the second side wall part SW2.
  • the channel length is determined substantially depending on the cross-sectional shape of the trench TR, so that the control of the channel length is facilitated and the variation in the channel length is remarkably reduced.
  • the region including the second layer 82 and the bottom portion BT exposed at least in the first side wall portion SW1 of the trench TR becomes the channel region CH, and the channel of the channel region CH
  • the length is preferably 0.6 ⁇ m or more.
  • the threshold voltage is further shifted to the positive side, and the silicon carbide semiconductor device 201 can be made a stable normally-off type.
  • the impurity concentration in the second layer 82 is preferably 5 ⁇ 10 16 cm ⁇ 3 or more.
  • the impurity concentration in the second layer 82 can be made as high as 5 ⁇ 10 16 cm ⁇ 3 or more. Thereby, the threshold voltage can be further increased.
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the threshold voltage can be further increased.
  • a silicon carbide semiconductor device 201 according to the embodiment shown in FIG. 1 is configured as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • Silicon carbide semiconductor device 201 includes single crystal substrate 80, silicon carbide layer 101 (epitaxial layer), gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring layer 95, drain And an electrode 98.
  • Single crystal substrate 80 is made of silicon carbide and has an n-type (first conductivity type). Silicon carbide layer 101 is provided on single crystal substrate 80.
  • Silicon carbide layer 101 is a silicon carbide layer epitaxially grown on single crystal substrate 80. Silicon carbide layer 101 has a polytype 4H hexagonal crystal structure. By adopting such a crystal structure, the on-resistance of silicon carbide semiconductor device 201 can be lowered. Silicon carbide layer 101 has a lower surface P1 (first main surface) facing single crystal substrate 80 and an upper surface P2 (second main surface) opposite to lower surface P1. Silicon carbide layer 101 has n drift layer 81 (first layer), p body layer 82 (second layer), n + layer 83 (third layer), and p contact region 84.
  • N drift layer 81 has n type.
  • N drift layer 81 constitutes lower surface P ⁇ b> 1 of silicon carbide layer 101.
  • the impurity concentration of n drift layer 81 is preferably lower than the impurity concentration of single crystal substrate 80.
  • the impurity concentration of the n drift layer 81 is preferably 1 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less.
  • P body layer 82 has p type (second conductivity type different from the first conductivity type). P body layer 82 is provided in n drift layer 81.
  • the impurity concentration of p body layer 82 is preferably 5 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less.
  • n + layer 83 has an n type.
  • N + layer 83 is provided in n drift layer 81 and p body layer 82, and constitutes upper surface P ⁇ b> 2 of silicon carbide layer 101 together with p contact region 84. That is, n + layer 83 is formed so as to extend from within p body layer 82 to n drift layer 81, and constitutes a part of the upper surface of silicon carbide layer 101.
  • a trench TR is provided on the upper surface P2 of the silicon carbide layer 101.
  • Trench TR is formed in a hexagonal shape so as to surround part of p contact region 84 and n + layer 83 in plan view (FIG. 2).
  • Trench TR has a first side wall part SW1, a bottom part BT continuous with first side wall part SW1, and a second side wall part SW2 arranged opposite to first side wall part SW1 and continuous with bottom part BT. ing.
  • a p body layer 82 and an n + layer 83 are exposed on the first sidewall portion SW1 and the second sidewall portion SW2, respectively. Further, bottom portion BT is located in p body layer 82.
  • first side wall portion SW1 and the second side wall portion SW2 may be collectively referred to simply as “side wall portion SW”. That is, the “side wall part SW” indicates at least one of the first side wall part SW1 and the second side wall part SW2.
  • the gate insulating film 91 is formed on the trench TR and covers each of the first sidewall portion SW1, the bottom portion BT, and the second sidewall portion SW2 of the trench TR.
  • the gate insulating film 91 is preferably a silicon oxide film.
  • a gate electrode 92 is provided on the gate insulating film 91.
  • the interlayer insulating film 93 is provided on the gate electrode 92 and insulates between the gate electrode 92 and the source electrode 94.
  • the source wiring layer 95 is in contact with the interlayer insulating film 93 and the source electrode 94.
  • Source wiring layer 95 is, for example, an aluminum layer.
  • Drain electrode 98 is provided on lower surface P ⁇ b> 1 of silicon carbide layer 101 via single crystal substrate 80.
  • bottom portion BT of trench TR is located in p body layer 82. Therefore, a strong electric field is not applied to the gate insulating film 91 and an extremely high breakdown voltage can be realized.
  • silicon carbide semiconductor device 201 has JFET region 85 sandwiched between a pair of p body layers 82 in n drift layer 81.
  • JFET region 85 is a part of n drift layer 81 and has n type conductivity.
  • JFET region 85 preferably has a higher impurity concentration than n drift layer 81.
  • the impurity concentration of JFET region 85 can be made higher than the portion of n drift layer 81 excluding JFET region 85 by ion-implanting n-type impurities into n drift layer 81, for example. More preferably, JFET region 85 has a lower impurity concentration than n + layer 83.
  • the impurity concentration in the JFET region is set low in order to ensure the breakdown voltage of the device. Therefore, the on-resistance of the device must be high.
  • silicon carbide semiconductor device 201 since bottom BT of trench TR is located in p body layer 82, a sufficient breakdown voltage is ensured, so that the impurity concentration of JFET region 85 can be increased. Further, the on-resistance of the semiconductor device can be further reduced.
  • silicon carbide semiconductor device 201 of the present embodiment includes a JFET region 85 having a first conductivity type sandwiched between a pair of second layers 82 in first layer 81, and JFET region 85 is The impurity concentration is preferably higher than that of the first layer 81.
  • the region including the portion of the p body layer 82 exposed on the first side wall portion SW1, the portion of the p body layer 82 exposed on the second side wall portion SW2, and the bottom portion BT has a gate voltage applied to the gate electrode 92. Is applied, the channel region CH is formed. That is, the channel region CH is formed so as to reach the second side wall portion SW2 from the first side wall portion SW1 of the trench TR through the bottom portion BT. That is, the channel region CH is formed so that the n + layer 83 and the n drift layer 81 connected to the first sidewall portion SW1 can be electrically connected.
  • the channel region CH is formed in the vertical direction of the device, the device can be easily miniaturized and the on-resistance can be reduced.
  • the channel length can be easily controlled mainly by the depth of the trench TR and the inclination angle of the side wall portion SW. Therefore, a high threshold voltage can be obtained by controlling the channel length.
  • the cross-sectional shape of trench TR has a V shape.
  • the V shape is preferable because the manufacturing process can be simplified.
  • the cross-sectional shape of trench TR is not limited to the V shape, and may be, for example, a trapezoidal shape as shown in FIG. 5 or a rectangular shape as shown in FIG.
  • first sidewall portion SW1 and second sidewall portion SW2 of trench TR are inclined with respect to upper surface P2 of silicon carbide layer 101.
  • the short channel effect is manifested mainly when the depletion layer due to the pn junction extends to the channel region CH.
  • it is effective to increase the impurity concentration of the channel region CH to suppress the spread of the depletion layer. Therefore, when the p-type semiconductor layer is used for the channel region CH, the number of acceptors (Np) in the p-type semiconductor layer is increased with respect to the number of donors (Nn) in the n-type semiconductor layer (that is, Np / Nn is increased). Is effective.
  • n + layer 83 and p body layer 82 is removed to form trench TR that opens in a tapered shape toward upper surface P2.
  • the inclination of the side wall SW in the trench TR is preferably in the following manner. That is, the plane orientation of the side wall SW is preferably tilted from 50 ° to 65 ° with respect to the ⁇ 0001 ⁇ plane, and tilted from 50 ° to 65 ° with respect to the (000-1) plane. It is preferable.
  • the channel mobility does not decrease even if the impurity concentration in the p body layer 82 constituting the channel region CH is increased. Therefore, the impurity concentration of p body layer 82 can be increased, and thus a high threshold voltage can be obtained.
  • the impurity concentration in the p body layer 82 is preferably 5 ⁇ 10 16 cm ⁇ 3 or more.
  • the impurity concentration in the p body layer 82 is more preferably 1 ⁇ 10 17 cm ⁇ 3 or more, and particularly preferably 5 ⁇ 10 17 cm ⁇ 3 or more. More preferably, it is 1 ⁇ 10 18 cm ⁇ 3 or more.
  • sidewall portion SW When sidewall portion SW is inclined with respect to upper surface P2, sidewall portion SW preferably has a predetermined crystal plane (hereinafter referred to as “special plane”), particularly in a portion on p body layer 82.
  • the p body layer 82 exposed on the side wall portion SW constituting the channel region CH has a special surface, so that the channel resistance component of the on-resistance of the semiconductor device is reduced. That is, the on-resistance of the semiconductor device can be reduced.
  • the side wall portion SW provided with the special surface includes a surface S1 (first surface) having a surface orientation ⁇ 0-33-8 ⁇ .
  • the p body layer 82 of the sidewall portion SW of the trench TR is provided with a surface including the surface S1.
  • the plane S1 preferably has a plane orientation (0-33-8).
  • the side wall portion SW microscopically includes the surface S1
  • the side wall portion SW microscopically includes the surface S2 (second surface) having the surface orientation ⁇ 0-11-1 ⁇ .
  • “microscopic” means “detailed to such an extent that at least a dimension about twice the atomic spacing is taken into consideration”.
  • TEM Transmission Electron Microscope
  • the plane S2 preferably has a plane orientation (0-11-1).
  • the surface S1 and the surface S2 in the side wall portion SW constitute a composite surface SR having a surface orientation ⁇ 0-11-2 ⁇ . That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane.
  • “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. Thus, as a macroscopic off angle measurement method, for example, a method using general X-ray diffraction can be cited.
  • the composite surface SR preferably has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the (000-1) plane.
  • the channel direction CD which is the direction in which carriers flow on the channel surface [that is, the thickness direction of the MOSFET (the vertical direction in FIG. 1 and the like)], is along the direction in which the above-described periodic repetition is performed.
  • the detailed structure of the composite surface SR will be described.
  • Si atoms are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.
  • the atoms in each of the four layers ABCB constituting one period described above are (0-11-2) It is not arranged to be completely along the plane.
  • the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer.
  • the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), this surface is microscopically Can take various structures.
  • a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being.
  • the length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms).
  • the surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface.
  • the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (surface S1 portion) equivalent to a cubic crystal when viewed partially.
  • a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in.
  • polytypes other than 4H may constitute the surface according to S2).
  • the polytype may be 6H or 15R, for example.
  • the horizontal axis indicates the angle D1 (°) between the macroscopic plane orientation of the side wall portion SW having the channel surface and the (000-1) plane
  • the vertical axis indicates the mobility MB.
  • the plot group CM corresponds to the case where the side wall SW is finished as a special surface by thermal etching
  • the plot group MC corresponds to the case where such thermal etching is not performed. A manufacturing method such as thermal etching will be described later.
  • the mobility MB in the plot group MC was maximized when the macroscopic surface orientation of the channel surface was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the general plane orientation (0-33-8), that is, the plane orientation (0-33-8) considering the atomic level has stochastically increased.
  • the mobility MB in the plot group CM was maximized when the macroscopic surface orientation of the channel surface was (0-11-2) (arrow EX).
  • the reason for this is that, as shown in FIGS. 14 and 15, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is minute. This is probably because the proportion of the visual plane orientation (0-33-8) has increased.
  • the mobility MB has an orientation dependency on the composite surface SR.
  • the horizontal axis indicates the angle D2 (°) between the channel direction and the ⁇ 0-11-2> direction
  • the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface.
  • a broken line is added to make the graph easier to see.
  • the angle D2 (°) of the channel direction CD is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. It turned out to be preferable.
  • the sidewall SW may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the sidewall portion SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR.
  • the off angle of the side wall portion SW with respect to the ⁇ 000-1 ⁇ plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ⁇ 10 °.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a ⁇ 0-33-8 ⁇ plane.
  • the off angle with respect to the (000-1) plane of the side wall portion SW deviates from 62 ° which is the ideal off angle of the composite surface SR.
  • This deviation is preferably small and preferably within a range of ⁇ 10 °.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.
  • Such a periodic structure can be observed, for example, by TEM or AFM.
  • the surface including the surface S1 (FIG. 11) having the plane orientation ⁇ 0-33-8 ⁇ is provided on the p body layer 82 on the first sidewall portion SW1 (FIG. 1) of the trench TR. It is preferable. More preferably, p body layer 82 is provided with a surface including surface S1 (FIG. 11) having a plane orientation ⁇ 0-33-8 ⁇ on first sidewall portion SW1 and second sidewall portion SW2. It is suitable. Thereby, of the on-resistance of silicon carbide semiconductor device 201, the resistance of the channel portion formed by p body layer 82 can be reduced. Therefore, even if resistance of n drift layer 81 is larger, it is permissible. Therefore, the impurity concentration of n drift layer 81 can be further reduced. Thereby, it is possible to further increase the breakdown voltage of the silicon carbide semiconductor device.
  • this surface may microscopically include the surface S1, and the surface may further microscopically include a surface S2 (FIG. 11) having a plane orientation ⁇ 0-11-1 ⁇ .
  • the surface planes S1 and S2 preferably constitute a composite plane SR (FIG. 11) having a plane orientation ⁇ 0-11-2 ⁇ . It is more preferable that this surface has an off angle of 62 ° ⁇ 10 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane. As a result, the resistance of the channel portion can be further reduced.
  • FIG. 19 shows the threshold voltage and the characteristic on in the weak inversion region when the impurity concentration in the p body layer is fixed to 3 ⁇ 10 17 cm ⁇ 3 and the channel length (L ch ) is changed in the silicon carbide semiconductor device. It is a figure which shows the relationship with resistance (ON resistance x area of a device active region).
  • the vertical axis represents the characteristic on-resistance (unit: m ⁇ ⁇ cm 2 )
  • the horizontal axis represents the threshold voltage (unit: V) in the weak inversion region.
  • the channel length (L ch ) in FIG. 19 and FIG. 20 described later is a value obtained from the mask dimension at the time of impurity implantation.
  • the actual channel length (effective channel length) in the semiconductor device is a value obtained by adding 0.2 ⁇ m to this L ch .
  • the fact that the actual channel length is 0.2 ⁇ m longer than the channel length obtained from the mask dimensions as described above is confirmed by, for example, observing the carrier distribution near the interface of the pn junction by the SCM (Scanning Capacitance Microscopy) method. Can do.
  • the threshold voltage and the characteristic on-resistance gradually increase as the channel length (L ch ) increases.
  • the threshold voltage is completely positive. That is, it is a normally-off type.
  • the channel length (L ch ) further increases to 0.8 ⁇ m and 1.2 ⁇ m, the characteristic on-resistance increases rapidly. Therefore, from the viewpoint of achieving both a high threshold voltage and a low on-resistance, the channel length is preferably 1.2 ⁇ m or less, and more preferably 0.8 ⁇ m or less. That is, the actual channel length in the semiconductor device is preferably 0.8 ⁇ m or more and 1.4 ⁇ m or less, and more preferably 0.8 ⁇ m or more and 1.0 ⁇ m or less.
  • FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 ⁇ 10 16 cm ⁇ 3 and the channel length (L ch ) is changed.
  • FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 ⁇ 10 16 cm ⁇ 3 and the channel length (L ch ) is changed.
  • FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 ⁇ 10 16 cm ⁇ 3 and the channel length (L ch ) is changed.
  • FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 ⁇ 10 16 cm ⁇ 3 and the channel length (L ch ) is changed.
  • the channel length is preferably 1.2 ⁇ m or less, and more preferably 0.8 ⁇ m or less. That is, the actual channel length in the semiconductor device is preferably 0.8 ⁇ m or more and 1.4 ⁇ m or less, and more preferably 0.8 ⁇ m or more and 1.0 ⁇ m or less.
  • the p body layer 82 when the impurity concentration is low (FIG. 20), the threshold voltage at which the characteristic on-resistance starts to increase more rapidly when the channel length (L ch ) is increased. Is low. Therefore, in order to achieve both a low on-resistance and a high threshold voltage, the p body layer 82 preferably has a high impurity concentration. However, when the impurity concentration of the p body layer 82 increases, the impurity scattering usually becomes remarkable, the channel mobility decreases, and the on-resistance increases. As described above, in this embodiment, since at least the first sidewall portion SW1 includes a special surface, even if the impurity concentration is increased, the channel mobility does not decrease. Therefore, a high threshold voltage and a low on-resistance are obtained. It is possible to achieve both.
  • FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment.
  • the silicon carbide semiconductor device of the present embodiment can be manufactured by executing Step 1 (S101) to Step 7 (S107).
  • Step 1 (S101) a silicon carbide single crystal substrate 80 is prepared.
  • n drift layer 81 is formed by epitaxial growth on single crystal substrate 80 prepared as described above.
  • This epitaxial growth is performed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a source gas and using, for example, hydrogen gas (H 2 ) as a carrier gas.
  • CVD Chemical Vapor Deposition
  • H 2 hydrogen gas
  • Step 3 (S103) p body layer 82, n + layer 83, and p contact region 84 are formed in n drift layer 81 by ion implantation, as shown in FIG. These can be formed by ion implantation into the n drift layer 81, for example.
  • an impurity for imparting p-type such as aluminum (Al)
  • Al aluminum
  • an impurity for imparting an n-type such as phosphorus (P) can be used.
  • the depth of the p body layer 82 formed by ion implantation can be about 0.7 to 0.8 ⁇ m, for example.
  • an n-type impurity is implanted into the JFET region 85 sandwiched between the pair of p body layers 82, and the impurity concentration of the JFET region 85 is set to be higher than that of the portion of the n drift layer 81 excluding the JFET region 85. It can also be raised.
  • epitaxial growth may be performed with addition of impurities.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
  • Step 4 (S104) trench TR is formed in upper surface P2.
  • the trench TR having a V-shaped cross section as shown in FIG. 8 can be formed by, for example, heating in an atmosphere containing a reactive gas having at least one halogen atom, that is, thermal etching. .
  • the etching location is specified by the mask layer.
  • a silicon oxide film can be used as the mask layer.
  • the silicon oxide film is preferable because it can be easily formed by thermally oxidizing the upper surface P2.
  • At least one or more halogen atoms include at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCl 3 , SF 6 or CF 4 .
  • a heat treatment temperature can be set to 700 ° C. or higher and 1000 ° C. or lower by using a mixed gas of chlorine gas and oxygen gas as a reaction gas.
  • the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above.
  • a carrier gas for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used.
  • N 2 nitrogen
  • argon gas argon gas
  • helium gas helium gas or the like
  • the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above
  • the etching rate of silicon carbide is about 70 ⁇ m / hour, for example.
  • the mask layer made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide. Thereby, a special surface is self-formed on the first sidewall portion SW1 and the second sidewall portion SW2, particularly on the p body layer 82.
  • the mask layer used here can be removed by an arbitrary method such as etching. Moreover, it is preferable to adjust the depth of trench TR so that the channel length of silicon carbide semiconductor device 201 is substantially 0.6 ⁇ m or more.
  • the depth of trench TR can be adjusted by, for example, etching time.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • the above-described thermal etching can be performed once a vertical trench having a rectangular cross-sectional shape is formed.
  • side wall portion SW of trench TR is selectively etched, and trench TR having a special surface is formed on first side wall portion SW1 and second side wall portion SW2, particularly on p body layer 82.
  • Step 5 (S105) As shown in FIG. 9, gate insulating film 91 is formed so as to cover each of first side wall portion SW1, second side wall portion SW2 and bottom portion BT of trench TR.
  • the gate insulating film 91 can be formed by thermal oxidation, for example.
  • NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed.
  • the temperature profile can be set to a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour.
  • nitrogen atoms are introduced into the interface region between gate insulating film 91 and p body layer 82.
  • a gas other than NO gas may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed.
  • the heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate insulating film 91.
  • the time during which this heating temperature is maintained can be set to about 1 hour, for example. Thereby, the formation of interface states in the interface region between gate insulating film 91 and p body layer 82 is further suppressed.
  • other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
  • Step 6 (S106) a gate electrode 92 is formed on the gate insulating film 91 as shown in FIG. Specifically, gate electrode 92 is formed on gate insulating film 91 so as to fill the region inside trench TR with gate insulating film 91 interposed therebetween.
  • the gate electrode 92 can be formed by, for example, forming a conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing) or RIE.
  • Step 7 (S107) a post-process for forming source electrode 94, drain electrode 98, and the like is performed, and silicon carbide semiconductor device 201 shown in FIG. 1 is manufactured. Specifically, an interlayer insulating film 93 is formed on the gate electrode 92 and the gate insulating film 91 so as to cover the exposed surface of the gate electrode 92, and then an opening is formed in the interlayer insulating film 93 and the gate insulating film 91. Etching is performed as shown. As a result, each of n + layer 83 and p contact region 84 is exposed on upper surface P2 from the opening. Next, source electrode 94 in contact with each of n + layer 83 and n contact region 84 is formed on upper surface P2. Then, drain electrode 98 is formed on lower surface P ⁇ b> 1 made of n drift layer 81 through single crystal substrate 80.
  • n + layer 83 is not exposed on second side wall portion SW2 of trench TR.
  • channel region CH is formed along side wall portion SW of trench TR, so that the occurrence of the short channel effect is suppressed, and a high threshold voltage and a low threshold voltage are achieved. Both on-resistance and resistance can be achieved.
  • bottom portion BT of trench TR is located in p body layer 82, the electric field does not concentrate on the portion of gate insulating film 91 covering bottom portion BT of trench TR.
  • the p body layer 82 can be made small. That is, the semiconductor device can be further miniaturized while avoiding electric field concentration at the bottom BT of the trench TR.
  • silicon carbide semiconductor device 301 shown in FIG. 4A the n + layer 83 is not exposed on the second side wall portion SW2.
  • the channel length changes when the position where trench TR is formed (the position of bottom portion BT) is shifted in the plane direction of FIG. 4B.
  • trench TR is formed such that n + layer 83 is exposed on both first sidewall portion SW1 and second sidewall portion SW2. Therefore, the channel length is not affected by the position of trench TR in the planar direction. Therefore, silicon carbide semiconductor device 201 shown in FIG. 1 can be a silicon carbide semiconductor device having extremely small variations in channel length and stable performance.
  • 80 single crystal substrate 81 n drift layer (first layer), 82 p body layer (second layer), 83 n + layer (third layer), 84 p contact layer, 85 JFET region, 91 gate insulating film , 92 gate electrode, 93 interlayer insulation film, 94 source electrode, 95 source wiring layer, 98 drain electrode, 101 silicon carbide layer, 201, 301, 401 silicon carbide semiconductor device, TR trench, BT bottom, SW side wall, SW1 No. 1 side wall portion, SW2 second side wall portion, CD channel direction, CH channel region, P1 lower surface (first main surface), P2 upper surface (second main surface), S1 first surface, S2 second Surface, SQ, SR composite surface.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A silicon carbide semiconductor device provided with a silicon carbide layer (101) comprising a first main surface (P1) and a second main surface (P2), wherein the silicon carbide layer (101) contains: a first layer (81) of a first conductivity type, forming the first main surface (P1); a second layer (82) of a second conductivity type different from the first conductivity type, disposed within the first layer (81); and a third layer (83) of the first conductivity type, disposed within at least the second layer (82) and forming a portion of the second main surface (P2). On the second main surface (P2) of the silicon carbide layer (101), trenches (TR) are disposed, and the trenches (TR) comprise a first sidewall portion (SW1) which exposes the second layer (82) and the third layer (83), and a bottom portion (BT) which continues from the first sidewall portion (SW1) and is positioned within the second layer (82), said trenches additionally being provided with: a gate insulator film (91) covering each of the first sidewall portion (SW1) and the bottom portion (BT); and gate electrodes (92) disposed upon the gate insulator film (91).

Description

炭化珪素半導体装置Silicon carbide semiconductor device
　本発明は、炭化珪素半導体装置に関する。 The present invention relates to a silicon carbide semiconductor device.
　炭化珪素半導体装置は、現在主流である珪素半導体装置に比べて、電力損失が少なく、高温動作が可能である等の多くの利点を有しており、次世代の電力用半導体装置として期待されている。現在、炭化珪素半導体装置のさらなる高性能化を追求すべく、装置の構造面から様々なアプローチが行なわれている〔たとえば、国際公開第２００２／０２９９００号（特許文献１）参照。〕。 Silicon carbide semiconductor devices have many advantages such as low power loss and high-temperature operation compared to silicon semiconductor devices that are currently mainstream, and are expected as next-generation power semiconductor devices. Yes. At present, various approaches are being taken from the structural aspect of the device to pursue higher performance of the silicon carbide semiconductor device [see, for example, International Publication No. 2002/029900 (Patent Document 1). ].
国際公開第２００２／０２９９００号International Publication No. 2002/029900
　プレーナ構造は、最も基本的な構造の一つであり、広く利用されている。プレーナ構造では、チャネル領域が半導体基板に対して平行に形成される。この構造は、高耐圧化に適した構造ではあるが、ＪＦＥＴ（Junction Field Effect Transistor）抵抗と呼ばれる寄生抵抗が存在するため、低オン抵抗化が困難である。 The planar structure is one of the most basic structures and is widely used. In the planar structure, the channel region is formed in parallel to the semiconductor substrate. Although this structure is suitable for increasing the breakdown voltage, there is a parasitic resistance called a JFET (Junction-Field-Effect-Transistor) resistance, and it is difficult to reduce the on-resistance.
　これに対して、トレンチゲート構造は、ＪＦＥＴ抵抗成分を含まない構造であるため、低オン抵抗化に適している。しかしながらトレンチゲート構造では、トレンチの底部でゲート絶縁膜の絶縁破壊が発生しやすく、高耐圧化が困難である。 On the other hand, since the trench gate structure does not include a JFET resistance component, it is suitable for low on-resistance. However, in the trench gate structure, dielectric breakdown of the gate insulating film tends to occur at the bottom of the trench, and it is difficult to increase the breakdown voltage.
　また電力用半導体装置は大電流を扱うため、電力損失を低減するとの観点から、閾値電圧が高く、ゲート電圧を印加しない状態で電流を遮断できるノーマリーオフ型であることが求められる。ところが、高い閾値電圧と低オン抵抗とは、一般にトレードオフの関係にあり、これらの両立は容易ではない。 Further, since the power semiconductor device handles a large current, it is required to be a normally-off type that has a high threshold voltage and can cut off the current without applying a gate voltage from the viewpoint of reducing power loss. However, a high threshold voltage and a low on-resistance are generally in a trade-off relationship, and it is not easy to achieve both of them.
　このような課題に対応するため、様々な技術が提案されている。たとえば、特許文献１では、プレーナ構造を有する炭化珪素半導体装置において、ｎ型の蓄積型チャネルを設けることにより、チャネル抵抗成分を低減し、低オン抵抗化を図っている。 Various technologies have been proposed to deal with such issues. For example, in Patent Document 1, in a silicon carbide semiconductor device having a planar structure, an n-type accumulation channel is provided to reduce a channel resistance component and to reduce the on-resistance.
　特許文献１に開示される半導体装置は、プレーナ構造であるため、比較的高い耐圧を有することができる。しかしながら、特許文献１で用いられているｎ型の蓄積型チャネルは、ｐ型半導体をチャネルとして用いる場合に比べて、閾値電圧が低いという問題がある。また、プレーナ構造では平面方向の装置サイズの制約から、チャネル長を制御することによって、閾値電圧を調整することも困難である。他方、この構造において、オン抵抗を低減するためにチャネル長を短くすると、短チャネル効果により、閾値電圧が急激に低下し、場合によってはパンチスルーに至るという問題がある。すなわち、この構造では、高耐圧でありながら、高い閾値電圧と低オン抵抗とを両立することは極めて困難である。 Since the semiconductor device disclosed in Patent Document 1 has a planar structure, it can have a relatively high breakdown voltage. However, the n-type storage channel used in Patent Document 1 has a problem that the threshold voltage is lower than when a p-type semiconductor is used as the channel. In the planar structure, it is also difficult to adjust the threshold voltage by controlling the channel length due to restrictions on the device size in the planar direction. On the other hand, in this structure, if the channel length is shortened in order to reduce the on-resistance, the threshold voltage is drastically lowered due to the short channel effect, and in some cases, there is a problem that punch-through is caused. That is, with this structure, it is extremely difficult to achieve both a high threshold voltage and a low on-resistance while having a high breakdown voltage.
　そこで上記のような課題に鑑み、高耐圧であり、高い閾値電圧と低オン抵抗とを両立した炭化珪素半導体装置を提供することを目的とする。 Therefore, in view of the problems as described above, an object is to provide a silicon carbide semiconductor device which has a high breakdown voltage and has both a high threshold voltage and a low on-resistance.
　本発明の一態様に係る炭化珪素半導体装置は、第１の主面と、第１の主面と反対の第２の主面とを有する炭化珪素層を備える。 A silicon carbide semiconductor device according to one embodiment of the present invention includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface.
　ここで、炭化珪素層は、第１の主面を構成し第１の導電型を有する第１の層と、第１の層内に設けられ第１の導電型と異なる第２の導電型を有する第２の層と、少なくとも第２の層内に設けられ第２の主面の一部を構成しかつ第１の導電型を有する第３の層とを含む。 Here, the silicon carbide layer has a first layer that constitutes the first main surface and has the first conductivity type, and a second conductivity type that is provided in the first layer and is different from the first conductivity type. And a third layer provided in at least the second layer and constituting a part of the second main surface and having the first conductivity type.
　そして、炭化珪素層の第２の主面にはトレンチが設けられており、当該トレンチは第２の層と第３の層とが表出する第１の側壁部と第１の側壁部に連なり第２の層内に位置する底部とを有し、さらに上記炭化珪素半導体装置は、第１の側壁部および底部の各々を覆うゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、を備える。 The second main surface of the silicon carbide layer is provided with a trench, and the trench is connected to the first side wall and the first side wall where the second layer and the third layer are exposed. The silicon carbide semiconductor device further comprising: a gate insulating film covering each of the first side wall and the bottom; a gate electrode provided on the gate insulating film; Is provided.
　上記の炭化珪素半導体装置は、高耐圧であり、高い閾値電圧と低オン抵抗とを両立することができる。 The above silicon carbide semiconductor device has a high breakdown voltage, and can achieve both a high threshold voltage and a low on-resistance.
本発明の一実施の形態における炭化珪素半導体装置の構成の一例を概略的に示す図であり、図２の線Ｉ－Ｉに沿う部分断面図である。FIG. 4 schematically shows an exemplary configuration of a silicon carbide semiconductor device in one embodiment of the present invention, and is a partial cross sectional view taken along line II in FIG. 2. 図１の炭化珪素半導体装置が有する炭化珪素層の形状を概略的に示す部分平面図である。FIG. 2 is a partial plan view schematically showing a shape of a silicon carbide layer included in the silicon carbide semiconductor device of FIG. 1. 本発明の一実施の形態における炭化珪素半導体装置の製造方法の概略を示すフローチャートである。It is a flowchart which shows the outline of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. 本発明の一実施の形態における炭化珪素半導体装置の構成の他の一例を概略的に示す図である。It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in one embodiment of this invention. 本発明の一実施の形態における炭化珪素半導体装置の構成の他の一例を概略的に示す図である。It is a figure which shows schematically another example of a structure of the silicon carbide semiconductor device in one embodiment of this invention. 本発明の一実施の形態におけるトレンチの断面形状の一変形例を示す図である。It is a figure which shows one modification of the cross-sectional shape of the trench in one embodiment of this invention. 本発明の一実施の形態におけるトレンチの断面形状の他の変形例を示す図である。It is a figure which shows the other modification of the cross-sectional shape of the trench in one embodiment of this invention. 図１の炭化珪素半導体装置の製造過程の第３段階（ステップ３）を概略的に示す部分断面図である。FIG. 4 is a partial cross sectional view schematically showing a third step (step 3) in the manufacturing process of the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造過程の第４段階（ステップ４）を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a fourth step (step 4) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造過程の第５段階（ステップ５）を概略的に示す部分断面図である。FIG. 7 is a partial cross sectional view schematically showing a fifth step (step 5) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. 図１の炭化珪素半導体装置の製造過程の第６段階（ステップ６）を概略的に示す部分断面図である。FIG. 8 is a partial cross sectional view schematically showing a sixth step (step 6) of the manufacturing process of the silicon carbide semiconductor device of FIG. 1. 炭化珪素半導体装置が有する炭化珪素層の表面の微細構造を概略的に示す部分断面図である。It is a fragmentary sectional view showing roughly the fine structure of the surface of a silicon carbide layer which a silicon carbide semiconductor device has. ポリタイプ４Ｈの六方晶における（０００－１）面の結晶構造を示す図である。FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal. 図１２の線ＸＩＩＩ－ＸＩＩＩに沿う（１１－２０）面の結晶構造を示す図である。FIG. 13 is a view showing a crystal structure of a (11-20) plane along line XIII-XIII in FIG. 図１１の複合面の表面近傍における結晶構造を（１１－２０）面内において示す図である。FIG. 21 is a view showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 11 in the (11-20) plane. 図１１の複合面を（０１－１０）面から見た図である。FIG. 12 is a view of the composite surface of FIG. 11 as viewed from the (01-10) plane. 巨視的に見たチャネル面および（０００－１）面の間の角度と、チャネル移動度との関係の一例を、熱エッチングが行われた場合と行われなかった場合との各々について示すグラフ図である。FIG. 5 is a graph showing an example of a relationship between a channel surface and a (000-1) plane viewed macroscopically and channel mobility when a thermal etching is performed and when it is not performed. It is. チャネル方向および＜０－１１－２＞方向の間の角度と、チャネル移動度との関係の一例を示すグラフ図である。It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. 図１２の変形例を示す図である。It is a figure which shows the modification of FIG. チャネル長と、閾値電圧および特性オン抵抗との関係の一例を示すグラフ図である。It is a graph which shows an example of the relationship between channel length, a threshold voltage, and characteristic ON resistance. チャネル長と、閾値電圧および特性オン抵抗との関係の他の一例を示すグラフ図である。It is a graph which shows another example of the relationship between channel length, a threshold voltage, and characteristic ON resistance.
　以下、本発明に係わる一実施の形態についてさらに詳細に説明する。なお、以下の図面において同一または相当する部分には同一の参照符号を付し、その説明は繰り返さない。また、本明細書中の結晶学的な記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面{}で、それぞれ示すものとする。なおまた、結晶学上の指数が負であることは、通常、”－”（バー）を数字の上に付すことによって表現されるが、本明細書中では数字の前に負の符号を付すことで表現するものとする。 Hereinafter, an embodiment according to the present invention will be described in more detail. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane {}. Furthermore, a negative crystallographic index is usually expressed by adding “-” (bar) above a number, but in this specification, a negative sign is added before the number. It shall be expressed by
　[本願発明の実施形態の説明]
　まず、本願発明の実施の形態（以下、「本実施の形態」とも記す）の概要を以下の（１）～（７）に列記して説明する。 [Description of Embodiment of Present Invention]
First, an outline of an embodiment of the present invention (hereinafter also referred to as “this embodiment”) will be described in the following (1) to (7).
　本発明者は、上記課題を解決するため鋭意研究を行なったところ、プレーナ構造の利点とトレンチゲート構造の利点とを併せ持つ、新規な装置構造を見出した。すなわち、本実施の形態に係る炭化珪素半導体装置は、以下の構成を備える。 The present inventor conducted intensive research to solve the above problems, and found a novel device structure that combines the advantages of the planar structure and the trench gate structure. That is, the silicon carbide semiconductor device according to the present embodiment has the following configuration.
　（１）本実施の形態の炭化珪素半導体装置２０１は、第１の主面Ｐ１と、第１の主面Ｐ１と反対の第２の主面Ｐ２とを有する炭化珪素層１０１を備える。 (1) Silicon carbide semiconductor device 201 of the present embodiment includes a silicon carbide layer 101 having a first main surface P1 and a second main surface P2 opposite to the first main surface P1.
　ここで、炭化珪素層１０１は、第１の主面Ｐ１を構成し第１の導電型を有する第１の層８１と、第１の層８１内に設けられ第１の導電型と異なる第２の導電型を有する第２の層８２と、少なくとも第２の層８２内に設けられ第２の主面Ｐ２の一部を構成しかつ第１の導電型を有する第３の層８３とを含む。 Here, the silicon carbide layer 101 includes a first layer 81 constituting the first main surface P1 and having the first conductivity type, and a second layer provided in the first layer 81 and different from the first conductivity type. A second layer 82 having the first conductivity type, and a third layer 83 provided in at least the second layer 82 and constituting a part of the second main surface P2 and having the first conductivity type. .
　そして、炭化珪素層１０１の第２の主面Ｐ２にはトレンチＴＲが設けられており、トレンチＴＲは第２の層８２と第３の層８３とが表出する第１の側壁部ＳＷ１と第１の側壁部ＳＷ１に連なり第２の層８２内に位置する底部ＢＴとを有し、さらに炭化珪素半導体装置２０１は、第１の側壁部ＳＷ１および底部ＢＴの各々を覆うゲート絶縁膜９１と、ゲート絶縁膜９１上に設けられたゲート電極９２と、を備える。 The second main surface P2 of the silicon carbide layer 101 is provided with a trench TR, and the trench TR has a first side wall portion SW1 where the second layer 82 and the third layer 83 are exposed, and the second side surface SW1. A silicon nitride semiconductor device 201 having a bottom portion BT connected to one side wall portion SW1 and positioned in the second layer 82, and a silicon carbide semiconductor device 201 covering each of the first side wall portion SW1 and the bottom portion BT; A gate electrode 92 provided on the gate insulating film 91.
　この炭化珪素半導体装置２０１によれば、トレンチＴＲの底部ＢＴが第２の層８２内に位置するため、ゲート絶縁膜９１に強電界が印加されることがなく、高耐圧を示すことができる。また、トレンチゲート構造の半導体装置と同様に、トレンチＴＲの側壁に沿ってチャネル領域ＣＨが形成される。したがって、装置の微細化が容易であり、低オン抵抗化が可能である。また、通常のプレーナ構造に比べて、チャネル長が装置サイズに及ぼす影響が小さいため、十分なチャネル長を確保することができる。したがって、高い閾値電圧を有することができる。このように、炭化珪素半導体装置２０１によれば、高耐圧であり、高い閾値電圧と低オン抵抗とを両立した炭化珪素半導体装置が実現可能である。 According to silicon carbide semiconductor device 201, since bottom portion BT of trench TR is located in second layer 82, a strong electric field is not applied to gate insulating film 91, and a high breakdown voltage can be exhibited. Similarly to the semiconductor device having the trench gate structure, the channel region CH is formed along the side wall of the trench TR. Therefore, the device can be easily miniaturized and the on-resistance can be reduced. Further, since the influence of the channel length on the device size is small as compared with a normal planar structure, a sufficient channel length can be ensured. Therefore, it can have a high threshold voltage. Thus, according to silicon carbide semiconductor device 201, it is possible to realize a silicon carbide semiconductor device having a high breakdown voltage and having both a high threshold voltage and a low on-resistance.
　（２）第１の側壁部ＳＷ１において第２の層８２が表出する部分には、面方位｛０－３３－８｝を有する第１の面Ｓ１を含む表面が設けられていることが好ましい。 (2) It is preferable that a portion including the first surface S1 having a plane orientation {0-33-8} is provided in a portion where the second layer 82 is exposed in the first sidewall portion SW1. .
　閾値電圧をさらに高くするためには、チャネル領域ＣＨを構成する第２の層８２における不純物濃度を高くすることが考えられる。しかしながら、通常、第２の層８２における不純物濃度を高くすると、ドーパントが増加したことによる不純物の散乱が顕著となるため、チャネル移動度が大幅に低下し、オン抵抗が増大する。しかし、第１の側壁部ＳＷ１において第２の層８２が表出する部分が、面方位{０－３３－８}を有する第１の面Ｓ１を含むことにより、第２の層８２における不純物濃度を高くしても、チャネル移動度を大きく低下させることがない。したがって、このような構成を採用することにより、高い閾値電圧と低オン抵抗とを高度に両立することができる。 In order to further increase the threshold voltage, it is conceivable to increase the impurity concentration in the second layer 82 constituting the channel region CH. However, usually, when the impurity concentration in the second layer 82 is increased, the scattering of impurities due to the increase in dopant becomes significant, so that the channel mobility is greatly reduced and the on-resistance is increased. However, the portion of the first sidewall portion SW1 where the second layer 82 is exposed includes the first surface S1 having the plane orientation {0-33-8}, so that the impurity concentration in the second layer 82 is increased. Even if the channel height is increased, the channel mobility is not greatly decreased. Therefore, by adopting such a configuration, it is possible to achieve both high threshold voltage and low on-resistance at a high level.
　（３）トレンチＴＲの断面形状は、Ｖ字形状であることが好ましい。従来、トレンチＴＲの断面形状がＶ字形状であると、ゲート絶縁膜９１が底部ＢＴにおいて大きく突出するため、当該部分に電界が集中しやすく、耐圧が低下していた。しかし、炭化珪素半導体装置２０１によれば、底部ＢＴは第２の層８２内に位置し、電界が集中しないため、Ｖ字形状としても耐圧が低下することがない。そして、Ｖ字形状を採用することにより、トレンチＴＲの第１の側壁部ＳＷ１に、前述の面方位｛０－３３－８｝を有する第１の面Ｓ１を容易に含ませることができる。すなわち、高い閾値電圧と低オン抵抗とを高度に両立することができる。 (3) The cross-sectional shape of the trench TR is preferably V-shaped. Conventionally, when the cross-sectional shape of the trench TR is V-shaped, the gate insulating film 91 protrudes greatly at the bottom portion BT, so that the electric field is easily concentrated on the portion, and the withstand voltage is reduced. However, according to silicon carbide semiconductor device 201, bottom portion BT is located in second layer 82, and the electric field does not concentrate, so that the withstand voltage does not decrease even when the shape is V-shaped. Then, by adopting the V shape, the first surface S1 having the aforementioned plane orientation {0-33-8} can be easily included in the first side wall portion SW1 of the trench TR. That is, high threshold voltage and low on-resistance can be achieved at a high level.
　（４）トレンチＴＲは、第１の側壁部ＳＷ１と対向配置されるとともに底部ＢＴと連なる第２の側壁部ＳＷ２を有し、第２の側壁部ＳＷ２では、第２の層８２と第３の層８３とが表出することが好ましい。 (4) The trench TR has a second side wall part SW2 that is disposed opposite to the first side wall part SW1 and that is continuous with the bottom part BT. In the second side wall part SW2, the second layer 82 and the third side wall part SW2 are arranged. It is preferable that the layer 83 is exposed.
　この構成において、チャネル領域ＣＨは、第１の側壁部ＳＷ１、底部ＢＴおよび第２の側壁部ＳＷ２に沿って形成される。これにより、チャネル長は、実質的にトレンチＴＲの断面形状に依存して決定されることとなるため、チャネル長の制御が容易になるとともに、チャネル長のばらつきが顕著に低減される。 In this configuration, the channel region CH is formed along the first side wall part SW1, the bottom part BT, and the second side wall part SW2. As a result, the channel length is determined substantially depending on the cross-sectional shape of the trench TR, so that the control of the channel length is facilitated and the variation in the channel length is remarkably reduced.
　（５）ゲート電極９２に電圧を印加したときに、トレンチＴＲの少なくとも第１の側壁部ＳＷ１に表出する第２の層８２および底部ＢＴを含む領域はチャネル領域ＣＨとなり、チャネル領域ＣＨのチャネル長は、０．６μｍ以上であることが好ましい。 (5) When a voltage is applied to the gate electrode 92, the region including the second layer 82 and the bottom portion BT exposed at least in the first side wall portion SW1 of the trench TR becomes the channel region CH, and the channel of the channel region CH The length is preferably 0.6 μm or more.
　チャネル長を０．６μｍ以上とすることにより、閾値電圧をさらにプラス側へシフトさせ、炭化珪素半導体装置２０１を安定したノーマリーオフ型とすることができる。 By setting the channel length to 0.6 μm or more, the threshold voltage is further shifted to the positive side, and the silicon carbide semiconductor device 201 can be made a stable normally-off type.
　（６）第２の層８２における不純物濃度は、５×１０16ｃｍ-3以上であることが好ましい。前述のように、本実施の形態では、第１の側壁部ＳＷ１が、面方位｛０－３３－８｝を有する第１の面Ｓ１を含むことができるため、第２の層８２における不純物濃度を５×１０16ｃｍ-3以上という高濃度とすることが可能である。これにより、閾値電圧をより一層高くすることができる。 (6) The impurity concentration in the second layer 82 is preferably 5 × 10 16 cm −3 or more. As described above, in the present embodiment, since the first sidewall portion SW1 can include the first surface S1 having the plane orientation {0-33-8}, the impurity concentration in the second layer 82 Can be made as high as 5 × 10 16 cm −3 or more. Thereby, the threshold voltage can be further increased.
　（７）第１の導電型はｎ型であり、第２の導電型はｐ型であることが好ましい。これにより、第２の層８２内に形成されたチャネル領域ＣＨがｐ型半導体となることができるため、閾値電圧をより一層高くすることができる。 (7) Preferably, the first conductivity type is n-type, and the second conductivity type is p-type. Thereby, since the channel region CH formed in the second layer 82 can be a p-type semiconductor, the threshold voltage can be further increased.
　[本願発明の実施の形態の詳細]
　以下、本実施の形態に係る炭化珪素半導体装置について、より詳細に説明するが、本実施形態はこれらに限定されるものではない。 [Details of the embodiment of the present invention]
Hereinafter, although the silicon carbide semiconductor device which concerns on this Embodiment is demonstrated in detail, this embodiment is not limited to these.
　＜炭化珪素半導体装置＞
　図１に示す実施の形態に係る炭化珪素半導体装置２０１は、縦型ＭＯＳＦＥＴ（Metal　Oxide Semiconductor Field Effect Transistor）として構成されている。炭化珪素半導体装置２０１は、単結晶基板８０と、炭化珪素層１０１（エピタキシャル層）と、ゲート絶縁膜９１、ゲート電極９２、層間絶縁膜９３と、ソース電極９４と、ソース配線層９５と、ドレイン電極９８とを有する。単結晶基板８０は、炭化珪素からなり、ｎ型（第１の導電型）を有する。単結晶基板８０上には、炭化珪素層１０１が設けられている。 <Silicon carbide semiconductor device>
A silicon carbide semiconductor device 201 according to the embodiment shown in FIG. 1 is configured as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 201 includes single crystal substrate 80, silicon carbide layer 101 (epitaxial layer), gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring layer 95, drain And an electrode 98. Single crystal substrate 80 is made of silicon carbide and has an n-type (first conductivity type). Silicon carbide layer 101 is provided on single crystal substrate 80.
　炭化珪素層１０１は、単結晶基板８０上にエピタキシャルに成長させられた炭化珪素層である。炭化珪素層１０１は、ポリタイプ４Ｈの六方晶の結晶構造を有する。かかる結晶構造を採用することにより、炭化珪素半導体装置２０１のオン抵抗を低くすることができる。炭化珪素層１０１は、単結晶基板８０に面する下面Ｐ１（第１の主面）と、下面Ｐ１と反対の上面Ｐ２（第２の主面）とを有する。炭化珪素層１０１は、ｎドリフト層８１（第１の層）と、ｐボディ層８２（第２の層）と、ｎ＋層８３（第３の層）と、ｐコンタクト領域８４とを有する。 Silicon carbide layer 101 is a silicon carbide layer epitaxially grown on single crystal substrate 80. Silicon carbide layer 101 has a polytype 4H hexagonal crystal structure. By adopting such a crystal structure, the on-resistance of silicon carbide semiconductor device 201 can be lowered. Silicon carbide layer 101 has a lower surface P1 (first main surface) facing single crystal substrate 80 and an upper surface P2 (second main surface) opposite to lower surface P1. Silicon carbide layer 101 has n drift layer 81 (first layer), p body layer 82 (second layer), n + layer 83 (third layer), and p contact region 84.
　ｎドリフト層８１は、ｎ型を有する。ｎドリフト層８１は、炭化珪素層１０１の下面Ｐ１を構成している。ｎドリフト層８１の不純物濃度は、単結晶基板８０の不純物濃度よりも低いことが好ましい。ここで、ｎドリフト層８１の不純物濃度は、好ましくは１×１０15ｃｍ-3以上５×１０16ｃｍ-3以下である。 N drift layer 81 has n type. N drift layer 81 constitutes lower surface P <b> 1 of silicon carbide layer 101. The impurity concentration of n drift layer 81 is preferably lower than the impurity concentration of single crystal substrate 80. Here, the impurity concentration of the n drift layer 81 is preferably 1 × 10 15 cm −3 or more and 5 × 10 16 cm −3 or less.
　ｐボディ層８２は、ｐ型（第１の導電型と異なる第２の導電型）を有する。ｐボディ層８２は、ｎドリフト層８１内に設けられている。ｐボディ層８２の不純物濃度は、５×１０16ｃｍ-3以上２×１０18ｃｍ-3以下であることが好ましい。 P body layer 82 has p type (second conductivity type different from the first conductivity type). P body layer 82 is provided in n drift layer 81. The impurity concentration of p body layer 82 is preferably 5 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less.
　ｎ＋層８３は、ｎ型を有する。ｎ＋層８３は、ｎドリフト層８１およびｐボディ層８２内に設けられており、ｐコンタクト領域８４とともに炭化珪素層１０１の上面Ｐ２を構成している。すなわち、ｎ＋層８３は、ｐボディ層８２内からｎドリフト層８１にまで延びるように形成され、炭化珪素層１０１の上面の一部を構成している。 The n + layer 83 has an n type. N + layer 83 is provided in n drift layer 81 and p body layer 82, and constitutes upper surface P <b> 2 of silicon carbide layer 101 together with p contact region 84. That is, n + layer 83 is formed so as to extend from within p body layer 82 to n drift layer 81, and constitutes a part of the upper surface of silicon carbide layer 101.
　炭化珪素層１０１の上面Ｐ２には、トレンチＴＲが設けられている。トレンチＴＲは、平面視（図２）において、ｐコンタクト領域８４およびｎ＋層８３の一部を取り囲むように六角形状に形成されている。トレンチＴＲは、第１の側壁部ＳＷ１と、第１の側壁部ＳＷ１と連なる底部ＢＴと、第１の側壁部ＳＷ１と対向配置されるとともに底部ＢＴと連なる第２の側壁部ＳＷ２とを有している。第１の側壁部ＳＷ１および第２の側壁部ＳＷ２には、各々ｐボディ層８２とｎ＋層８３とが表出している。また、底部ＢＴはｐボディ層８２内に位置している。なお、本明細書では、第１の側壁部ＳＷ１および第２の側壁部ＳＷ２を総称して、単に「側壁部ＳＷ」と記すことがある。すなわち、「側壁部ＳＷ」は、第１の側壁部ＳＷ１および第２の側壁部ＳＷ２の少なくともいずれかを示す。 A trench TR is provided on the upper surface P2 of the silicon carbide layer 101. Trench TR is formed in a hexagonal shape so as to surround part of p contact region 84 and n + layer 83 in plan view (FIG. 2). Trench TR has a first side wall part SW1, a bottom part BT continuous with first side wall part SW1, and a second side wall part SW2 arranged opposite to first side wall part SW1 and continuous with bottom part BT. ing. A p body layer 82 and an n + layer 83 are exposed on the first sidewall portion SW1 and the second sidewall portion SW2, respectively. Further, bottom portion BT is located in p body layer 82. In the present specification, the first side wall portion SW1 and the second side wall portion SW2 may be collectively referred to simply as “side wall portion SW”. That is, the “side wall part SW” indicates at least one of the first side wall part SW1 and the second side wall part SW2.
　ゲート絶縁膜９１は、トレンチＴＲ上に形成されており、トレンチＴＲの第１の側壁部ＳＷ１、底部ＢＴおよび第２の側壁部ＳＷ２の各々を覆っている。ゲート絶縁膜９１は酸化珪素膜であることが好適である。そして、ゲート絶縁膜９１上には、ゲート電極９２が設けられている。層間絶縁膜９３はゲート電極９２上に設けられ、ゲート電極９２とソース電極９４との間を絶縁している。ソース配線層９５は、層間絶縁膜９３およびソース電極９４に接している。ソース配線層９５は、たとえばアルミニウム層である。ドレイン電極９８は、炭化珪素層１０１の下面Ｐ１上に単結晶基板８０を介して設けられている。 The gate insulating film 91 is formed on the trench TR and covers each of the first sidewall portion SW1, the bottom portion BT, and the second sidewall portion SW2 of the trench TR. The gate insulating film 91 is preferably a silicon oxide film. A gate electrode 92 is provided on the gate insulating film 91. The interlayer insulating film 93 is provided on the gate electrode 92 and insulates between the gate electrode 92 and the source electrode 94. The source wiring layer 95 is in contact with the interlayer insulating film 93 and the source electrode 94. Source wiring layer 95 is, for example, an aluminum layer. Drain electrode 98 is provided on lower surface P <b> 1 of silicon carbide layer 101 via single crystal substrate 80.
　以上の構成を有する炭化珪素半導体装置２０１では、トレンチＴＲの底部ＢＴがｐボディ層８２内に位置している。したがって、ゲート絶縁膜９１に強電界が印加されることがなく、極めて高い耐圧を実現することが可能である。 In silicon carbide semiconductor device 201 having the above configuration, bottom portion BT of trench TR is located in p body layer 82. Therefore, a strong electric field is not applied to the gate insulating film 91 and an extremely high breakdown voltage can be realized.
　また、炭化珪素半導体装置２０１は、ｎドリフト層８１内に、一対のｐボディ層８２に挟まれたＪＦＥＴ領域８５を有する。ＪＦＥＴ領域８５は、ｎドリフト層８１の一部であり、ｎ型の導電型を有する。本実施の形態では、ＪＦＥＴ領域８５は、ｎドリフト層８１よりも不純物濃度が高いことが好ましい。ＪＦＥＴ領域８５の不純物濃度は、たとえば、ｎ型の不純物をｎドリフト層８１にイオン注入することによって、ｎドリフト層８１のうちＪＦＥＴ領域８５を除く部分よりも高くすることができる。なお、より好ましくは、ＪＦＥＴ領域８５は、ｎ＋層８３よりも不純物濃度が低い。 Moreover, silicon carbide semiconductor device 201 has JFET region 85 sandwiched between a pair of p body layers 82 in n drift layer 81. JFET region 85 is a part of n drift layer 81 and has n type conductivity. In the present embodiment, JFET region 85 preferably has a higher impurity concentration than n drift layer 81. The impurity concentration of JFET region 85 can be made higher than the portion of n drift layer 81 excluding JFET region 85 by ion-implanting n-type impurities into n drift layer 81, for example. More preferably, JFET region 85 has a lower impurity concentration than n + layer 83.
　通常のプレーナ構造では、装置の耐圧を確保するため、ＪＦＥＴ領域の不純物濃度は低く設定される。そのため、装置のオン抵抗は高くならざるを得ない。これに対して、炭化珪素半導体装置２０１では、トレンチＴＲの底部ＢＴがｐボディ層８２内に位置することにより、十分な耐圧が確保されているため、ＪＦＥＴ領域８５の不純物濃度を高めることができ、半導体装置のさらなる低オン抵抗化が可能である。 In the normal planar structure, the impurity concentration in the JFET region is set low in order to ensure the breakdown voltage of the device. Therefore, the on-resistance of the device must be high. On the other hand, in silicon carbide semiconductor device 201, since bottom BT of trench TR is located in p body layer 82, a sufficient breakdown voltage is ensured, so that the impurity concentration of JFET region 85 can be increased. Further, the on-resistance of the semiconductor device can be further reduced.
　すなわち、本実施の形態の炭化珪素半導体装置２０１は、第１の層８１内に一対の第２の層８２に挟まれた第１の導電型を有するＪＦＥＴ領域８５を含み、ＪＦＥＴ領域８５は第１の層８１よりも不純物濃度が高いことが好ましい。 That is, silicon carbide semiconductor device 201 of the present embodiment includes a JFET region 85 having a first conductivity type sandwiched between a pair of second layers 82 in first layer 81, and JFET region 85 is The impurity concentration is preferably higher than that of the first layer 81.
　また、第１の側壁部ＳＷ１に表出するｐボディ層８２の部分、第２の側壁部ＳＷ２に表出するｐボディ層８２の部分、および底部ＢＴを含む領域は、ゲート電極９２にゲート電圧を印加したときに、チャネル領域ＣＨを構成する。すなわち、チャネル領域ＣＨは、トレンチＴＲの第１の側壁部ＳＷ１から、底部ＢＴを通って、第２の側壁部ＳＷ２に到るように形成される。つまり、チャネル領域ＣＨは、第１の側壁部ＳＷ１に連なるｎ＋層８３とｎドリフト層８１とを電気的に接続可能に形成される。このように、本実施の形態では、チャネル領域ＣＨを装置の縦方向に形成するため、装置の微細化が容易であり、オン抵抗を低減することができる。また、この構造において、チャネル長は、主にトレンチＴＲの深さおよび側壁部ＳＷの傾斜角度によって、容易に制御することができる。よって、チャネル長を制御することにより、高い閾値電圧を得ることも可能である。 Further, the region including the portion of the p body layer 82 exposed on the first side wall portion SW1, the portion of the p body layer 82 exposed on the second side wall portion SW2, and the bottom portion BT has a gate voltage applied to the gate electrode 92. Is applied, the channel region CH is formed. That is, the channel region CH is formed so as to reach the second side wall portion SW2 from the first side wall portion SW1 of the trench TR through the bottom portion BT. That is, the channel region CH is formed so that the n + layer 83 and the n drift layer 81 connected to the first sidewall portion SW1 can be electrically connected. Thus, in this embodiment, since the channel region CH is formed in the vertical direction of the device, the device can be easily miniaturized and the on-resistance can be reduced. In this structure, the channel length can be easily controlled mainly by the depth of the trench TR and the inclination angle of the side wall portion SW. Therefore, a high threshold voltage can be obtained by controlling the channel length.
　図１に示すように、炭化珪素半導体装置２０１では、トレンチＴＲの断面形状はＶ字形状を有している。Ｖ字形状は、製造プロセスを簡略化できるため好適である。なおここで、トレンチＴＲの断面形状は、Ｖ字形状に限定されるものではなく、たとえば、図５に示すような台形状であってもよいし、図６に示すような矩形状であってもよいが、トレンチＴＲの第１の側壁部ＳＷ１および第２の側壁部ＳＷ２は、炭化珪素層１０１の上面Ｐ２に対して傾斜していることが好ましい。トレンチＴＲの側壁が傾斜することにより、チャネル長を減少させたとき、短チャネル効果の発現が緩やかとなり、高い閾値電圧を維持しながら低オン抵抗化が可能である。 As shown in FIG. 1, in silicon carbide semiconductor device 201, the cross-sectional shape of trench TR has a V shape. The V shape is preferable because the manufacturing process can be simplified. Here, the cross-sectional shape of trench TR is not limited to the V shape, and may be, for example, a trapezoidal shape as shown in FIG. 5 or a rectangular shape as shown in FIG. However, it is preferable that first sidewall portion SW1 and second sidewall portion SW2 of trench TR are inclined with respect to upper surface P2 of silicon carbide layer 101. By tilting the side wall of the trench TR, when the channel length is reduced, the short channel effect appears moderately, and a low on-resistance can be achieved while maintaining a high threshold voltage.
　ここで、短チャネル効果は、主に、ｐｎ接合による空乏層がチャネル領域ＣＨにまで広がることによって発現する。一般に、短チャネル効果の抑制には、チャネル領域ＣＨの不純物濃度を高くして、空乏層の広がりを抑制することが有効である。したがって、ｐ型半導体層をチャネル領域ＣＨに用いる場合、ｐ型半導体層におけるアクセプタ数（Ｎｐ）を、ｎ型半導体層におけるドナー数（Ｎｎ）に対して多くする（すなわちＮｐ／Ｎｎを大きくする）ことが有効である。炭化珪素半導体装置２０１では、ｎ＋層８３およびｐボディ層８２の一部が除去されることにより、上面Ｐ２に向かってテーパ状に開口するトレンチＴＲが形成されている。そのため、トレンチＴＲの形成によって、ｎ＋層８３からは、ｐボディ層８２に比べてより多くの体積が除去されている。これにより、トレンチＴＲの形成前に比べて、ＮｐをＮｎで除した値（Ｎｐ／Ｎｎ）を増加させることができている。よって、炭化珪素半導体装置２０１のように、側壁部ＳＷが傾斜したトレンチを設けることにより短チャネル効果を抑制することができる。 Here, the short channel effect is manifested mainly when the depletion layer due to the pn junction extends to the channel region CH. In general, to suppress the short channel effect, it is effective to increase the impurity concentration of the channel region CH to suppress the spread of the depletion layer. Therefore, when the p-type semiconductor layer is used for the channel region CH, the number of acceptors (Np) in the p-type semiconductor layer is increased with respect to the number of donors (Nn) in the n-type semiconductor layer (that is, Np / Nn is increased). Is effective. In silicon carbide semiconductor device 201, a part of n + layer 83 and p body layer 82 is removed to form trench TR that opens in a tapered shape toward upper surface P2. Therefore, a larger volume is removed from n + layer 83 than p body layer 82 by forming trench TR. As a result, the value obtained by dividing Np by Nn (Np / Nn) can be increased as compared to before formation of the trench TR. Therefore, the short channel effect can be suppressed by providing a trench in which side wall part SW is inclined like silicon carbide semiconductor device 201.
　ここで、トレンチＴＲにおける側壁部ＳＷの傾斜は、具体的には次のような態様であることが好ましい。すなわち、側壁部ＳＷの面方位は、{０００１}面に対して５０°以上６５°以下傾斜していることが好ましく、（０００－１）面に対して５０°以上６５°以下傾斜していることが好ましい。このような傾斜を有する側壁部ＳＷにチャネル領域ＣＨを形成することにより、チャネル領域ＣＨを構成するｐボディ層８２における不純物濃度を高くしても、チャネル移動度が低下することがない。したがって、ｐボディ層８２の不純物濃度を高くすることができ、以って高い閾値電圧を得ることができる。ここで、ｐボディ層８２における不純物濃度は５×１０16ｃｍ-3以上であることが好ましい。不純物濃度が５×１０16ｃｍ-3以上であることにより、半導体装置をノーマリーオフ型に近付けることができる。より安定したノーマリーオフ型とするとの観点から、ｐボディ層８２における不純物濃度は、より好ましくは１×１０17ｃｍ-3以上であり、特に好ましくは５×１０17ｃｍ-3以上であり、さらに好ましくは１×１０18ｃｍ-3以上である。 Here, the inclination of the side wall SW in the trench TR is preferably in the following manner. That is, the plane orientation of the side wall SW is preferably tilted from 50 ° to 65 ° with respect to the {0001} plane, and tilted from 50 ° to 65 ° with respect to the (000-1) plane. It is preferable. By forming the channel region CH in the sidewall portion SW having such an inclination, the channel mobility does not decrease even if the impurity concentration in the p body layer 82 constituting the channel region CH is increased. Therefore, the impurity concentration of p body layer 82 can be increased, and thus a high threshold voltage can be obtained. Here, the impurity concentration in the p body layer 82 is preferably 5 × 10 16 cm −3 or more. When the impurity concentration is 5 × 10 16 cm −3 or more, the semiconductor device can be brought close to a normally-off type. From the viewpoint of a more stable normally-off type, the impurity concentration in the p body layer 82 is more preferably 1 × 10 17 cm −3 or more, and particularly preferably 5 × 10 17 cm −3 or more. More preferably, it is 1 × 10 18 cm −3 or more.
　≪特殊面≫
　側壁部ＳＷが、上面Ｐ２に対して傾斜している場合、側壁部ＳＷは、特にｐボディ層８２上の部分において、所定の結晶面（以下「特殊面」と称する）を有することが好ましい。チャネル領域ＣＨを構成している側壁部ＳＷに表出したｐボディ層８２が、特殊面を有することにより、半導体装置のオン抵抗のうちチャネル抵抗成分が低減される。すなわち、半導体装置の低オン抵抗化が可能である。 ≪Special surface≫
When sidewall portion SW is inclined with respect to upper surface P2, sidewall portion SW preferably has a predetermined crystal plane (hereinafter referred to as “special plane”), particularly in a portion on p body layer 82. The p body layer 82 exposed on the side wall portion SW constituting the channel region CH has a special surface, so that the channel resistance component of the on-resistance of the semiconductor device is reduced. That is, the on-resistance of the semiconductor device can be reduced.
　特殊面が設けられた側壁部ＳＷは、図１１に示すように、面方位｛０－３３－８｝を有する面Ｓ１（第１の面）を含む。換言すれば、トレンチＴＲの側壁部ＳＷのｐボディ層８２には、面Ｓ１を含む表面が設けられている。面Ｓ１は好ましくは面方位（０－３３－８）を有する。 As shown in FIG. 11, the side wall portion SW provided with the special surface includes a surface S1 (first surface) having a surface orientation {0-33-8}. In other words, the p body layer 82 of the sidewall portion SW of the trench TR is provided with a surface including the surface S1. The plane S1 preferably has a plane orientation (0-33-8).
　さらに、より好ましくは、側壁部ＳＷは面Ｓ１を微視的に含み、側壁部ＳＷは面方位{０－１１－１}を有する面Ｓ２（第２の面）を微視的に含む。ここで「微視的」とは、「原子間隔の２倍程度の寸法を少なくとも考慮する程度に詳細に」ということを意味している。このように微視的な構造の観察方法としては、たとえばＴＥＭ（Transmission Electron Microscope）を用いることができる。なお、面Ｓ２は好ましくは面方位（０－１１－１）を有する。 More preferably, the side wall portion SW microscopically includes the surface S1, and the side wall portion SW microscopically includes the surface S2 (second surface) having the surface orientation {0-11-1}. Here, “microscopic” means “detailed to such an extent that at least a dimension about twice the atomic spacing is taken into consideration”. As a microscopic structure observation method, for example, TEM (Transmission Electron Microscope) can be used. The plane S2 preferably has a plane orientation (0-11-1).
　さらに、好ましくは側壁部ＳＷにおける面Ｓ１および面Ｓ２は、面方位{０－１１－２}を有する複合面ＳＲを構成している。すなわち複合面ＳＲは、面Ｓ１およびＳ２が周期的に繰り返されることによって構成されている。このような周期的構造は、たとえばＴＥＭまたはＡＦＭ（Atomic Force Microscopy）により観察することができる。この場合、複合面ＳＲは{０００－１}面に対して巨視的に６２°のオフ角を有する。ここで「巨視的」とは、原子間隔程度の寸法を有する微細構造を無視することを意味している。このように、巨視的なオフ角の測定方法としては、たとえば一般的なＸ線回折を用いた方法を挙げることができる。また複合面ＳＲは、面方位（０－１１－２）を有することが好ましい。この場合、複合面ＳＲは（０００－１）面に対して巨視的に６２°のオフ角を有する。 Further, preferably, the surface S1 and the surface S2 in the side wall portion SW constitute a composite surface SR having a surface orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. Thus, as a macroscopic off angle measurement method, for example, a method using general X-ray diffraction can be cited. The composite surface SR preferably has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the (000-1) plane.
　また、好ましくは、チャネル面上においてキャリアが流れる方向〔すなわちＭＯＳＦＥＴの厚さ方向（図１等における縦方向）〕であるチャネル方向ＣＤは、上述した周期的繰り返しが行なわれる方向に沿っている。次に複合面ＳＲの詳細な構造について説明する。 Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface [that is, the thickness direction of the MOSFET (the vertical direction in FIG. 1 and the like)], is along the direction in which the above-described periodic repetition is performed. Next, the detailed structure of the composite surface SR will be described.
　一般に、ポリタイプ４Ｈの炭化珪素単結晶を（０００－１）面から見ると、図１２に示すように、Ｓｉ原子（またはＣ原子）は、Ａ層の原子（図中の実線）と、この下に位置するＢ層の原子（図中の破線）と、この下に位置するＣ層の原子（図中の一点鎖線）と、この下に位置するＢ層の原子（図示せず）とが繰り返し設けられている。つまり４つの層ＡＢＣＢを１周期としてＡＢＣＢＡＢＣＢＡＢＣＢ・・・のような周期的な積層構造が設けられている。 In general, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 12, Si atoms (or C atoms) are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.
　図１３に示すように、（１１－２０）面（図１２の線ＸＩＩＩ－ＸＩＩＩの断面）において、上述した１周期を構成する４つの層ＡＢＣＢの各層の原子は、（０－１１－２）面に完全に沿うようには配列されていない。図１３においてはＢ層の原子の位置を通るように（０－１１－２）面が示されており、この場合、Ａ層およびＣ層の各々の原子は（０－１１－２）面からずれていることがわかる。このため、炭化珪素単結晶の表面の巨視的な面方位、すなわち原子レベルの構造を無視した場合の面方位が（０－１１－２）に限定されたとしても、この表面は微視的には様々な構造をとり得る。 As shown in FIG. 13, in the (11-20) plane (cross section taken along line XIII-XIII in FIG. 12), the atoms in each of the four layers ABCB constituting one period described above are (0-11-2) It is not arranged to be completely along the plane. In FIG. 13, the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer. In this case, the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), this surface is microscopically Can take various structures.
　図１４に示すように、複合面ＳＲは、面方位（０－３３－８）を有する面Ｓ１と、面Ｓ１につながりかつ面Ｓ１の面方位と異なる面方位を有する面Ｓ２とが交互に設けられることによって構成されている。面Ｓ１および面Ｓ２の各々の長さは、Ｓｉ原子（またはＣ原子）の原子間隔の２倍である。なお面Ｓ１および面Ｓ２が平均化された面は、（０－１１－２）面に対応する。 As shown in FIG. 14, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). The surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface.
　図１５に示すように、複合面ＳＲを（０１－１０）面から見て単結晶構造は、部分的に見て立方晶と等価な構造（面Ｓ１の部分）を周期的に含んでいる。具体的には複合面ＳＲは、上述した立方晶と等価な構造における面方位（００１）を有する面Ｓ１と、面Ｓ１につながりかつ面Ｓ１の面方位と異なる面方位を有する面Ｓ２とが交互に設けられることによって構成されている。このように、立方晶と等価な構造における面方位（００１）を有する面（図１５においては面Ｓ１）と、この面につながりかつこの面方位と異なる面方位を有する面（図１５においては面Ｓ２）とによって表面を構成することは４Ｈ以外のポリタイプにおいても可能である。ポリタイプは、たとえば６Ｈまたは１５Ｒであってもよい。 As shown in FIG. 15, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (surface S1 portion) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 15) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 15) It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.
　次に図１６を参照して、側壁部ＳＷの結晶面と、チャネル面の移動度ＭＢとの関係について説明する。図１６のグラフにおいて、横軸は、チャネル面を有する側壁部ＳＷの巨視的な面方位と（０００－１）面とのなす角度Ｄ１（°）を示し、縦軸は移動度ＭＢを示す。プロット群ＣＭは側壁部ＳＷが熱エッチングによる特殊面として仕上げられた場合に対応し、プロット群ＭＣはそのような熱エッチングがなされない場合に対応する。なお、熱エッチング等の製造方法については後述する。 Next, the relationship between the crystal plane of the sidewall portion SW and the mobility MB of the channel surface will be described with reference to FIG. In the graph of FIG. 16, the horizontal axis indicates the angle D1 (°) between the macroscopic plane orientation of the side wall portion SW having the channel surface and the (000-1) plane, and the vertical axis indicates the mobility MB. The plot group CM corresponds to the case where the side wall SW is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed. A manufacturing method such as thermal etching will be described later.
　プロット群ＭＣにおける移動度ＭＢは、チャネル面の表面の巨視的な面方位が（０－３３－８）のときに最大となった。この理由は、熱エッチングが行われない場合、すなわちチャネル表面の微視的な構造が特に制御されない場合においては、巨視的な面方位が（０－３３－８）とされることによって、微視的な面方位（０－３３－８）、つまり原子レベルまで考慮した場合の面方位（０－３３－８）が形成される割合が確率的に高くなったためと考えられる。 The mobility MB in the plot group MC was maximized when the macroscopic surface orientation of the channel surface was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the general plane orientation (0-33-8), that is, the plane orientation (0-33-8) considering the atomic level has stochastically increased.
　一方、プロット群ＣＭにおける移動度ＭＢは、チャネル面の表面の巨視的な面方位が（０－１１－２）のとき（矢印ＥＸ）に最大となった。この理由は、図１４および図１５に示すように、面方位（０－３３－８）を有する多数の面Ｓ１が面Ｓ２を介して規則正しく稠密に配置されることで、チャネル面の表面において微視的な面方位（０－３３－８）が占める割合が高くなったためと考えられる。 On the other hand, the mobility MB in the plot group CM was maximized when the macroscopic surface orientation of the channel surface was (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 14 and 15, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is minute. This is probably because the proportion of the visual plane orientation (0-33-8) has increased.
　なお移動度ＭＢは複合面ＳＲ上において方位依存性を有する。図１７に示すグラフにおいて、横軸はチャネル方向と＜０－１１－２＞方向との間の角度Ｄ２（°）を示し、縦軸はチャネル面の移動度ＭＢ（任意単位）を示す。破線はグラフを見やすくするために補助的に付してある。このグラフから、チャネル移動度ＭＢを大きくするには、チャネル方向ＣＤ（図１１）が有する角度Ｄ２（°）は、０°以上６０°以下であることが好ましく、ほぼ０°であることがより好ましいことがわかった。 The mobility MB has an orientation dependency on the composite surface SR. In the graph shown in FIG. 17, the horizontal axis indicates the angle D2 (°) between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 (°) of the channel direction CD (FIG. 11) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. It turned out to be preferable.
　図１８に示すように、側壁部ＳＷは、複合面ＳＲに加えてさらに面Ｓ３（第３の面）を含んでもよい。より具体的には、面Ｓ３および複合面ＳＲが周期的に繰り返されることによって構成された複合面ＳＱを側壁部ＳＷが含んでもよい。この場合、側壁部ＳＷの｛０００－１｝面に対するオフ角は、理想的な複合面ＳＲのオフ角である６２°からずれる。このずれは小さいことが好ましく、±１０°の範囲内であることが好ましい。このような角度範囲に含まれる表面としては、たとえば、巨視的な面方位が{０－３３－８}面となる表面がある。より好ましくは、側壁部ＳＷの（０００－１）面に対するオフ角は、理想的な複合面ＳＲのオフ角である６２°からずれる。このずれは小さいことが好ましく、±１０°の範囲内であることが好ましい。このような角度範囲に含まれる表面としては、たとえば、巨視的な面方位が（０－３３－８）面となる表面がある。このような周期的構造は、たとえば、ＴＥＭまたはＡＦＭにより観察し得る。 As shown in FIG. 18, the sidewall SW may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the sidewall portion SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. In this case, the off angle of the side wall portion SW with respect to the {000-1} plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle with respect to the (000-1) plane of the side wall portion SW deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane. Such a periodic structure can be observed, for example, by TEM or AFM.
　上述した理由により、トレンチＴＲの第１の側壁部ＳＷ１（図１）上においてｐボディ層８２には、面方位｛０－３３－８｝を有する面Ｓ１（図１１）を含む表面が設けられていることが好ましい。また、より好ましくは第１の側壁部ＳＷ１および第２の側壁部ＳＷ２上においてｐボディ層８２には、面方位｛０－３３－８｝を有する面Ｓ１（図１１）を含む表面が設けられていることが好適である。これにより、炭化珪素半導体装置２０１のオン抵抗のうち、ｐボディ層８２によって構成されるチャネル部分の抵抗を小さくすることができる。よってｎドリフト層８１の抵抗がより大きくても許容される。よってｎドリフト層８１の不純物濃度をより小さくすることができる。これにより炭化珪素半導体装置のさらなる高耐圧化が可能となる。 For the reasons described above, the surface including the surface S1 (FIG. 11) having the plane orientation {0-33-8} is provided on the p body layer 82 on the first sidewall portion SW1 (FIG. 1) of the trench TR. It is preferable. More preferably, p body layer 82 is provided with a surface including surface S1 (FIG. 11) having a plane orientation {0-33-8} on first sidewall portion SW1 and second sidewall portion SW2. It is suitable. Thereby, of the on-resistance of silicon carbide semiconductor device 201, the resistance of the channel portion formed by p body layer 82 can be reduced. Therefore, even if resistance of n drift layer 81 is larger, it is permissible. Therefore, the impurity concentration of n drift layer 81 can be further reduced. Thereby, it is possible to further increase the breakdown voltage of the silicon carbide semiconductor device.
　なお、この表面は面Ｓ１を微視的に含んでもよく、表面はさらに、面方位｛０－１１－１｝を有する面Ｓ２（図１１）を微視的に含んでもよい。この表面の面Ｓ１およびＳ２は、面方位｛０－１１－２｝を有する複合面ＳＲ（図１１）を構成することが好ましい。またこの表面は｛０００－１｝面に対して、巨視的に６２°±１０°のオフ角を有することがより好ましい。これによりチャネル部分の抵抗をより小さくすることができる。 Note that this surface may microscopically include the surface S1, and the surface may further microscopically include a surface S2 (FIG. 11) having a plane orientation {0-11-1}. The surface planes S1 and S2 preferably constitute a composite plane SR (FIG. 11) having a plane orientation {0-11-2}. It is more preferable that this surface has an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane. As a result, the resistance of the channel portion can be further reduced.
　≪チャネル長≫
　チャネル長は、０．６μｍ以上であることが好ましい。これにより、炭化珪素半導体装置を、ノーマリーオフ型とすることができる。図１９は、炭化珪素半導体装置において、ｐボディ層における不純物濃度を３×１０17ｃｍ-3に固定し、チャネル長（Ｌch）を変化させたときの、弱反転領域における閾値電圧と特性オン抵抗（オン抵抗×装置活性領域の面積）との関係を示す図である。図１９中、縦軸は特性オン抵抗（単位：ｍΩ・ｃｍ2）を示し、横軸は弱反転領域における閾値電圧（単位：Ｖ）を示す。 ≪Channel length≫
The channel length is preferably 0.6 μm or more. Thereby, a silicon carbide semiconductor device can be made into a normally-off type. FIG. 19 shows the threshold voltage and the characteristic on in the weak inversion region when the impurity concentration in the p body layer is fixed to 3 × 10 17 cm −3 and the channel length (L ch ) is changed in the silicon carbide semiconductor device. It is a figure which shows the relationship with resistance (ON resistance x area of a device active region). In FIG. 19, the vertical axis represents the characteristic on-resistance (unit: mΩ · cm 2 ), and the horizontal axis represents the threshold voltage (unit: V) in the weak inversion region.
　ここで、図１９および後述する図２０におけるチャネル長（Ｌch）は、不純物注入時のマスク寸法から求めた値である。半導体装置における実際のチャネル長（実効的なチャネル長）は、このＬchに０．２μｍを加えた値となる。このように実際のチャネル長が、マスク寸法から求めたチャネル長より０．２μｍ長いことは、たとえば、ＳＣＭ（Scanning Capacitance Microscopy）法によって、ｐｎ接合の界面近傍におけるキャリア分布を観察することにより確かめることができる。 Here, the channel length (L ch ) in FIG. 19 and FIG. 20 described later is a value obtained from the mask dimension at the time of impurity implantation. The actual channel length (effective channel length) in the semiconductor device is a value obtained by adding 0.2 μm to this L ch . The fact that the actual channel length is 0.2 μm longer than the channel length obtained from the mask dimensions as described above is confirmed by, for example, observing the carrier distribution near the interface of the pn junction by the SCM (Scanning Capacitance Microscopy) method. Can do.
　図１９に示すように、チャネル長（Ｌch）が増加するに従って、閾値電圧と特性オン抵抗は緩やかに増加していく。そして、チャネル長（Ｌch）が０．６μｍでは、閾値電圧は完全にプラスの値を示している。すなわち、ノーマリーオフ型となっている。チャネル長（Ｌch）が、０．８μｍ、１．２μｍとさらに増加すると特性オン抵抗は急激に増加していく。したがって、高い閾値電圧と低オン抵抗を両立するとの観点から、チャネル長は好ましくは１．２μｍ以下であり、より好ましくは０．８μｍ以下である。すなわち、半導体装置における実際のチャネル長は、０．８μｍ以上１．４μｍ以下であることが好ましく、０．８μｍ以上１．０μｍ以下であることがより好ましい。 As shown in FIG. 19, the threshold voltage and the characteristic on-resistance gradually increase as the channel length (L ch ) increases. When the channel length (L ch ) is 0.6 μm, the threshold voltage is completely positive. That is, it is a normally-off type. When the channel length (L ch ) further increases to 0.8 μm and 1.2 μm, the characteristic on-resistance increases rapidly. Therefore, from the viewpoint of achieving both a high threshold voltage and a low on-resistance, the channel length is preferably 1.2 μm or less, and more preferably 0.8 μm or less. That is, the actual channel length in the semiconductor device is preferably 0.8 μm or more and 1.4 μm or less, and more preferably 0.8 μm or more and 1.0 μm or less.
　図２０は、ｐボディ層における不純物濃度を４×１０16ｃｍ-3に固定し、チャネル長（Ｌch）を変化させたときの、弱反転領域における閾値電圧と特性オン抵抗との関係を示す図である。図２０に示すように、この場合も、チャネル長（Ｌch）が増加するに従って、閾値電圧と特性オン抵抗は緩やかに増加していき、チャネル長（Ｌch）が０．６μｍとなる付近から閾値電圧はプラス側へと転じ、その後は特性オン抵抗が急激に上昇していく。したがって、この場合も、炭化珪素半導体装置をノーマリーオフ型とするためには、チャネル長（Ｌch）は０．６μｍ以上であることが好ましい。また、高い閾値電圧と低オン抵抗を両立するとの観点から、チャネル長は好ましくは１．２μｍ以下であり、より好ましくは０．８μｍ以下である。すなわち、半導体装置における実際のチャネル長は、０．８μｍ以上１．４μｍ以下であることが好ましく、０．８μｍ以上１．０μｍ以下であることがより好ましい。 FIG. 20 shows the relationship between the threshold voltage and the characteristic on-resistance in the weak inversion region when the impurity concentration in the p body layer is fixed to 4 × 10 16 cm −3 and the channel length (L ch ) is changed. FIG. As shown in FIG. 20, also in this case, as the channel length (L ch ) increases, the threshold voltage and the characteristic on-resistance gradually increase, from the vicinity where the channel length (L ch ) becomes 0.6 μm. The threshold voltage turns to the positive side, and thereafter the characteristic on-resistance increases rapidly. Therefore, also in this case, in order to make the silicon carbide semiconductor device normally-off type, the channel length (L ch ) is preferably 0.6 μm or more. From the viewpoint of achieving both a high threshold voltage and a low on-resistance, the channel length is preferably 1.2 μm or less, and more preferably 0.8 μm or less. That is, the actual channel length in the semiconductor device is preferably 0.8 μm or more and 1.4 μm or less, and more preferably 0.8 μm or more and 1.0 μm or less.
　また、図１９と図２０とを比較すると、不純物濃度が低い場合（図２０）の方が、チャネル長（Ｌch）を増加させていったとき、特性オン抵抗が急激に上昇し始める閾値電圧が低い。したがって、低オン抵抗と高い閾値電圧を両立するためには、ｐボディ層８２の不純物濃度は高い方が好ましい。しかし、ｐボディ層８２の不純物濃度が高くなると、通常は不純物の散乱が顕著となりチャネル移動度が低下し、オン抵抗が増大する。上述のように、本実施の形態では、少なくとも第１の側壁部ＳＷ１が特殊面を含むことにより、不純物濃度を高めても、チャネル移動度が低下しないため、高い閾値電圧と低オン抵抗とを両立することが可能である。 Further, comparing FIG. 19 and FIG. 20, when the impurity concentration is low (FIG. 20), the threshold voltage at which the characteristic on-resistance starts to increase more rapidly when the channel length (L ch ) is increased. Is low. Therefore, in order to achieve both a low on-resistance and a high threshold voltage, the p body layer 82 preferably has a high impurity concentration. However, when the impurity concentration of the p body layer 82 increases, the impurity scattering usually becomes remarkable, the channel mobility decreases, and the on-resistance increases. As described above, in this embodiment, since at least the first sidewall portion SW1 includes a special surface, even if the impurity concentration is increased, the channel mobility does not decrease. Therefore, a high threshold voltage and a low on-resistance are obtained. It is possible to achieve both.
　＜炭化珪素半導体装置の製造方法＞
　次に本実施の形態に係る炭化珪素半導体装置の製造方法について説明する。図３は、本実施の形態に係る炭化珪素半導体装置の製造方法の概略を示すフローチャートである。図３に示すように、ステップ１（Ｓ１０１）～ステップ７（Ｓ１０７）を実行することにより、本実施の形態の炭化珪素半導体装置を製造することができる。 <Method for Manufacturing Silicon Carbide Semiconductor Device>
Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described. FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment. As shown in FIG. 3, the silicon carbide semiconductor device of the present embodiment can be manufactured by executing Step 1 (S101) to Step 7 (S107).
　≪ステップ１（Ｓ１０１）≫
　ステップ１（Ｓ１０１）では炭化珪素の単結晶基板８０を準備する。 << Step 1 (S101) >>
In step 1 (S101), a silicon carbide single crystal substrate 80 is prepared.
　≪ステップ２（Ｓ１０２）≫
　ステップ２（Ｓ１０２）では、上記で準備された単結晶基板８０上に、エピタキシャル成長によって、ｎドリフト層８１を形成する。このエピタキシャル成長は、たとえば原料ガスとしてシラン（ＳｉＨ4）とプロパン（Ｃ3Ｈ8）との混合ガスを用い、キャリアガスとしてたとえば水素ガス（Ｈ2）を用いたＣＶＤ（Chemical Vapor Deposition）法により行うことができる。この際、不純物として、たとえば窒素（Ｎ）やリン（Ｐ）を導入することが好ましい。 << Step 2 (S102) >>
In step 2 (S102), n drift layer 81 is formed by epitaxial growth on single crystal substrate 80 prepared as described above. This epitaxial growth is performed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a source gas and using, for example, hydrogen gas (H 2 ) as a carrier gas. be able to. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.
　≪ステップ３（Ｓ１０３）≫
　ステップ３（Ｓ１０３）では、イオン注入によって、図７に示すように、ｎドリフト層８１内にｐボディ層８２、ｎ＋層８３およびｐコンタクト領域８４を形成する。これらの形成は、たとえば、ｎドリフト層８１へのイオン注入により行なうことができる。ｐボディ層８２およびｐコンタクト領域８４を形成するためのイオン注入においては、たとえばアルミニウム（Ａｌ）などの、ｐ型を付与するための不純物を用いることができる。またｎ＋層８３を形成するためのイオン注入においては、たとえばリン（Ｐ）等のｎ型を付与するための不純物を用いることができる。イオン注入によって形成されるｐボディ層８２の深さは、たとえば、深さ０．７～０．８μｍ程度とすることができる。なおこのとき、１対のｐボディ層８２に挟まれたＪＦＥＴ領域８５に、ｎ型の不純物を注入し、ＪＦＥＴ領域８５の不純物濃度を、ｎドリフト層８１のうちＪＦＥＴ領域８５を除く部分よりも高くすることもできる。 << Step 3 (S103) >>
In step 3 (S103), p body layer 82, n + layer 83, and p contact region 84 are formed in n drift layer 81 by ion implantation, as shown in FIG. These can be formed by ion implantation into the n drift layer 81, for example. In ion implantation for forming p body layer 82 and p contact region 84, an impurity for imparting p-type, such as aluminum (Al), can be used. In the ion implantation for forming the n + layer 83, an impurity for imparting an n-type such as phosphorus (P) can be used. The depth of the p body layer 82 formed by ion implantation can be about 0.7 to 0.8 μm, for example. At this time, an n-type impurity is implanted into the JFET region 85 sandwiched between the pair of p body layers 82, and the impurity concentration of the JFET region 85 is set to be higher than that of the portion of the n drift layer 81 excluding the JFET region 85. It can also be raised.
　また、イオン注入の代わりに、不純物の添加をともなうにエピタキシャル成長を行なってもよい。 Further, instead of ion implantation, epitaxial growth may be performed with addition of impurities.
　次に、不純物を活性化するための熱処理を行なう。この熱処理の温度は、好ましくは１５００℃以上１９００℃以下であり、たとえば１７００℃程度である。熱処理の時間は、たとえば３０分程度である。熱処理の雰囲気は、好ましくは不活性ガス雰囲気であり、たとえばＡｒ雰囲気である。 Next, heat treatment is performed to activate the impurities. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
　≪ステップ４（Ｓ１０４）≫
　ステップ４（Ｓ１０４）では、図８に示すように、上面Ｐ２にトレンチＴＲを形成する。図８に示すようなＶ字形状の断面形状を有するトレンチＴＲは、たとえば、少なくとも１種以上のハロゲン原子を有する反応性ガスを含む雰囲気中での加熱、すなわち熱エッチングによって、形成することができる。 << Step 4 (S104) >>
In step 4 (S104), as shown in FIG. 8, trench TR is formed in upper surface P2. The trench TR having a V-shaped cross section as shown in FIG. 8 can be formed by, for example, heating in an atmosphere containing a reactive gas having at least one halogen atom, that is, thermal etching. .
　エッチング箇所の特定は、マスク層により行なう。マスク層としては、たとえば、酸化珪素膜を使用することができる。酸化珪素膜は、上面Ｐ２を熱酸化することにより容易に形成できるため好適である。 The etching location is specified by the mask layer. As the mask layer, for example, a silicon oxide film can be used. The silicon oxide film is preferable because it can be easily formed by thermally oxidizing the upper surface P2.
　ここで、少なくとも１種以上のハロゲン原子は、塩素（Ｃｌ）原子およびフッ素（Ｆ）原子の少なくともいずれかを含むことが好ましい。この雰囲気は、たとえば、Ｃｌ2、ＢＣl3、ＳＦ6またはＣＦ4である。また、たとえば塩素ガスと酸素ガスとの混合ガスを反応ガスとして用いて、熱処理温度を７００℃以上１０００℃以下とすることもできる。 Here, it is preferable that at least one or more halogen atoms include at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl 2 , BCl 3 , SF 6 or CF 4 . Further, for example, a heat treatment temperature can be set to 700 ° C. or higher and 1000 ° C. or lower by using a mixed gas of chlorine gas and oxygen gas as a reaction gas.
　また反応ガスは、上述した塩素ガスと酸素ガスとに加えて、キャリアガスを含んでいてもよい。キャリアガスとしては、たとえば窒素（Ｎ2）ガス、アルゴンガス、ヘリウムガスなどを用いることができる。そして、上述のように熱処理温度を７００℃以上１０００℃以下とした場合、炭化珪素のエッチング速度はたとえば約７０μｍ／時になる。またこの場合に、酸化珪素から作られたマスク層は、炭化珪素に対する選択比が極めて大きいので、炭化珪素のエッチング中に実質的にエッチングされない。これにより、第１の側壁部ＳＷ１および第２の側壁部ＳＷ２上、特にｐボディ層８２上において、特殊面が自己形成される。なお、ここで用いたマスク層はエッチングなど任意の方法により除去することができる。また、炭化珪素半導体装置２０１のチャネル長が実質的に０．６μｍ以上となるようにトレンチＴＲの深さを調整することが好ましい。トレンチＴＲの深さは、たとえばエッチング時間により調整することができる。 The reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. As the carrier gas, for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of silicon carbide is about 70 μm / hour, for example. Further, in this case, the mask layer made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide. Thereby, a special surface is self-formed on the first sidewall portion SW1 and the second sidewall portion SW2, particularly on the p body layer 82. Note that the mask layer used here can be removed by an arbitrary method such as etching. Moreover, it is preferable to adjust the depth of trench TR so that the channel length of silicon carbide semiconductor device 201 is substantially 0.6 μm or more. The depth of trench TR can be adjusted by, for example, etching time.
　また図６に示すように、トレンチＴＲの断面形状を矩形状とするためには（すなわち垂直トレンチを形成するためには）、たとえば反応性イオンエッチング（ＲＩＥ）や誘導結合プラズマ（ＩＣＰ）ＲＩＥを用いることができる。具体的には、たとえば反応ガスとしてＳＦ6またはＳＦ6とＯ2との混合ガスを用いたＩＣＰ－ＲＩＥを用いることができる。 As shown in FIG. 6, in order to make the cross-sectional shape of the trench TR rectangular (that is, to form a vertical trench), for example, reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE is performed. Can be used. Specifically, for example, ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 as a reaction gas can be used.
　さらに図５に示すように、トレンチＴＲの断面形状を台形状とするためには、一旦、断面形状が矩形状である垂直トレンチを形成した後、上述の熱エッチングを行なうことができる。熱エッチングにより、トレンチＴＲの側壁部ＳＷが選択的にエッチングされ、第１の側壁部ＳＷ１および第２の側壁部ＳＷ２上、特にｐボディ層８２上に特殊面を有するトレンチＴＲが形成される。 Further, as shown in FIG. 5, in order to make the cross-sectional shape of the trench TR trapezoidal, the above-described thermal etching can be performed once a vertical trench having a rectangular cross-sectional shape is formed. By thermal etching, side wall portion SW of trench TR is selectively etched, and trench TR having a special surface is formed on first side wall portion SW1 and second side wall portion SW2, particularly on p body layer 82.
　≪ステップ５（Ｓ１０５）≫
　ステップ５（Ｓ１０５）では、図９に示すように、トレンチＴＲの第１の側壁部ＳＷ１、第２の側壁部ＳＷ２および底部ＢＴの各々を覆うように、ゲート絶縁膜９１を形成する。ゲート絶縁膜９１は、たとえば熱酸化により形成することができる。 << Step 5 (S105) >>
In step 5 (S105), as shown in FIG. 9, gate insulating film 91 is formed so as to cover each of first side wall portion SW1, second side wall portion SW2 and bottom portion BT of trench TR. The gate insulating film 91 can be formed by thermal oxidation, for example.
　ゲート絶縁膜９１が形成した後に、雰囲気ガスとして一酸化窒素（ＮＯ）ガスを用いるＮＯアニールを行なってもよい。温度プロファイルは、たとえば、温度１１００℃以上１３００℃以下、保持時間１時間程度の条件とすることができる。これにより、ゲート絶縁膜９１とｐボディ層８２との界面領域に窒素原子が導入される。その結果、界面領域における界面準位の形成が抑制されることで、チャネル移動度を向上させることができる。なお、このような窒素原子の導入が可能であれば、ＮＯガス以外のガスを雰囲気ガスとして用いてもよい。 After the gate insulating film 91 is formed, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed. For example, the temperature profile can be set to a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. As a result, nitrogen atoms are introduced into the interface region between gate insulating film 91 and p body layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. If such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas.
　このＮＯアニールの後にさらに、雰囲気ガスとしてアルゴン（Ａｒ）を用いるＡｒアニールを行なってもよい。Ａｒアニールの加熱温度は、上記ＮＯアニールの加熱温度よりも高く、ゲート絶縁膜９１の融点よりも低いことが好ましい。この加熱温度が保持される時間は、たとえば１時間程度とすることができる。これにより、ゲート絶縁膜９１とｐボディ層８２との界面領域における界面準位の形成がさらに抑制される。なお、雰囲気ガスとして、Ａｒガスに代えて窒素ガスなどの他の不活性ガスを用いてもよい。 After this NO annealing, Ar annealing using argon (Ar) as an atmospheric gas may be further performed. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate insulating film 91. The time during which this heating temperature is maintained can be set to about 1 hour, for example. Thereby, the formation of interface states in the interface region between gate insulating film 91 and p body layer 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
　≪ステップ６（Ｓ１０６）≫
　ステップ６（Ｓ１０６）では、図１０に示すように、ゲート絶縁膜９１上にゲート電極９２を形成する。具体的には、トレンチＴＲの内部の領域をゲート絶縁膜９１を介して埋めるように、ゲート絶縁膜９１上にゲート電極９２を形成する。ゲート電極９２の形成方法は、たとえば、導体またはドープトポリシリコンの成膜とＣＭＰ（Chemical Mechanical Polishing）またはＲＩＥとによって行なうことができる。 << Step 6 (S106) >>
In step 6 (S106), a gate electrode 92 is formed on the gate insulating film 91 as shown in FIG. Specifically, gate electrode 92 is formed on gate insulating film 91 so as to fill the region inside trench TR with gate insulating film 91 interposed therebetween. The gate electrode 92 can be formed by, for example, forming a conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing) or RIE.
　≪ステップ７（Ｓ１０７）≫
　ステップ７（Ｓ１０７）では、ソース電極９４およびドレイン電極９８等を形成する後工程が実行され、図１に示す炭化珪素半導体装置２０１が製造される。具体的には、ゲート電極９２の露出面を覆うように、ゲート電極９２およびゲート絶縁膜９１上に層間絶縁膜９３を形成した後、層間絶縁膜９３およびゲート絶縁膜９１に開口部が形成されるようにエッチングを行なう。これにより、当該開口部から、上面Ｐ２上にｎ＋層８３およびｐコンタクト領域８４の各々が露出する。次に上面Ｐ２上においてｎ＋層８３およびｎコンタクト領域８４の各々に接するソース電極９４を形成する。そして、ｎドリフト層８１からなる下面Ｐ１上に単結晶基板８０を介してドレイン電極９８を形成する。 << Step 7 (S107) >>
In step 7 (S107), a post-process for forming source electrode 94, drain electrode 98, and the like is performed, and silicon carbide semiconductor device 201 shown in FIG. 1 is manufactured. Specifically, an interlayer insulating film 93 is formed on the gate electrode 92 and the gate insulating film 91 so as to cover the exposed surface of the gate electrode 92, and then an opening is formed in the interlayer insulating film 93 and the gate insulating film 91. Etching is performed as shown. As a result, each of n + layer 83 and p contact region 84 is exposed on upper surface P2 from the opening. Next, source electrode 94 in contact with each of n + layer 83 and n contact region 84 is formed on upper surface P2. Then, drain electrode 98 is formed on lower surface P <b> 1 made of n drift layer 81 through single crystal substrate 80.
　＜変形例＞
　次に、図４Ａおよび図４Ｂを参照して、本実施の形態に係る炭化珪素半導体装置の変形例について説明する。 <Modification>
Next, a modification of the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGS. 4A and 4B.
　図４Ａに示す炭化珪素半導体装置３０１は、トレンチＴＲの第２の側壁部ＳＷ２には、ｎ＋層８３が表出していない点で、図１に示す炭化珪素半導体装置２０１と相違する。 4A is different from silicon carbide semiconductor device 201 shown in FIG. 1 in that n + layer 83 is not exposed on second side wall portion SW2 of trench TR.
　この構成では、図１に示す炭化珪素半導体装置２０１と同様に、トレンチＴＲの側壁部ＳＷに沿ってチャネル領域ＣＨが形成されているため、短チャネル効果の発現を抑制し、高い閾値電圧と低オン抵抗とを両立することができる。また、トレンチＴＲの底部ＢＴがｐボディ層８２内に位置しているため、トレンチＴＲの底部ＢＴを覆うゲート絶縁膜９１の部分に電界が集中しない。さらに、トレンチＴＲの第２の側壁部ＳＷ２をｐボディ層８２内に形成するという制約がないため、ｐボディ層８２を小さくすることも可能である。すなわち、トレンチＴＲの底部ＢＴにおける電界集中を回避した上で、半導体装置のさらなる微細化が可能となる。 In this configuration, similarly to silicon carbide semiconductor device 201 shown in FIG. 1, channel region CH is formed along side wall portion SW of trench TR, so that the occurrence of the short channel effect is suppressed, and a high threshold voltage and a low threshold voltage are achieved. Both on-resistance and resistance can be achieved. Further, since bottom portion BT of trench TR is located in p body layer 82, the electric field does not concentrate on the portion of gate insulating film 91 covering bottom portion BT of trench TR. Furthermore, since there is no restriction that the second sidewall portion SW2 of the trench TR is formed in the p body layer 82, the p body layer 82 can be made small. That is, the semiconductor device can be further miniaturized while avoiding electric field concentration at the bottom BT of the trench TR.
　図４Ａに示す炭化珪素半導体装置３０１では、第２の側壁部ＳＷ２にはｎ＋層８３が表出していない。この構造では、たとえば、図４Ｂに示す炭化珪素半導体装置４０１ように、トレンチＴＲの形成位置（底部ＢＴの位置）が、図４Ｂの平面方向へずれた場合、チャネル長が変化することになる。これに対して図１に示す炭化珪素半導体装置２０１では、第１の側壁部ＳＷ１および第２の側壁部ＳＷ２の両方にｎ＋層８３が表出するように、トレンチＴＲが形成されている。したがって、チャネル長は、トレンチＴＲの平面方向の位置に影響されない。よって、図１に示す炭化珪素半導体装置２０１は、チャネル長のばらつきが極めて小さく、性能の安定した炭化珪素半導体装置となることができる。 In the silicon carbide semiconductor device 301 shown in FIG. 4A, the n + layer 83 is not exposed on the second side wall portion SW2. In this structure, for example, as in silicon carbide semiconductor device 401 shown in FIG. 4B, the channel length changes when the position where trench TR is formed (the position of bottom portion BT) is shifted in the plane direction of FIG. 4B. In contrast, in silicon carbide semiconductor device 201 shown in FIG. 1, trench TR is formed such that n + layer 83 is exposed on both first sidewall portion SW1 and second sidewall portion SW2. Therefore, the channel length is not affected by the position of trench TR in the planar direction. Therefore, silicon carbide semiconductor device 201 shown in FIG. 1 can be a silicon carbide semiconductor device having extremely small variations in channel length and stable performance.
　以上のように本発明の実施の形態について説明を行なったが、上述した各実施の形態の構成を適宜組み合わせることも当初から予定している。 As described above, the embodiments of the present invention have been described, but it is also planned from the beginning to appropriately combine the configurations of the embodiments described above.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと解されるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　８０　単結晶基板、８１　ｎドリフト層（第１の層）、８２　ｐボディ層（第２の層）、８３　ｎ＋層（第３の層）、８４　ｐコンタクト層、８５　ＪＦＥＴ領域、９１　ゲート絶縁膜、９２　ゲート電極、９３　層間絶縁膜、９４　ソース電極、９５　ソース配線層、９８　ドレイン電極、１０１　炭化珪素層、２０１，３０１，４０１　炭化珪素半導体装置、ＴＲ　トレンチ、ＢＴ　底部、ＳＷ　側壁部、ＳＷ１　第１の側壁部、ＳＷ２　第２の側壁部、ＣＤ　チャネル方向、ＣＨ　チャネル領域、Ｐ１　下面（第１の主面）、Ｐ２　上面（第２の主面）、Ｓ１　第１の面、Ｓ２　第２の面、ＳＱ，ＳＲ　複合面。 80 single crystal substrate, 81 n drift layer (first layer), 82 p body layer (second layer), 83 n + layer (third layer), 84 p contact layer, 85 JFET region, 91 gate insulating film , 92 gate electrode, 93 interlayer insulation film, 94 source electrode, 95 source wiring layer, 98 drain electrode, 101 silicon carbide layer, 201, 301, 401 silicon carbide semiconductor device, TR trench, BT bottom, SW side wall, SW1 No. 1 side wall portion, SW2 second side wall portion, CD channel direction, CH channel region, P1 lower surface (first main surface), P2 upper surface (second main surface), S1 first surface, S2 second Surface, SQ, SR composite surface.

Claims (7)

  1. 　第１の主面と、前記第１の主面と反対の第２の主面とを有する炭化珪素層を備え、
    　前記炭化珪素層は、前記第１の主面を構成し第１の導電型を有する第１の層と、
    　前記第１の層内に設けられ前記第１の導電型と異なる第２の導電型を有する第２の層と、
    　少なくとも前記第２の層内に設けられ前記第２の主面の一部を構成しかつ前記第１の導電型を有する第３の層と、を含み、
    　前記炭化珪素層の前記第２の主面にはトレンチが設けられており、
    　前記トレンチは前記第２の層と前記第３の層とが表出する第１の側壁部と前記第１の側壁部に連なり前記第２の層内に位置する底部とを有し、さらに、
    　前記第１の側壁部および前記底部の各々を覆うゲート絶縁膜と、
    　前記ゲート絶縁膜上に設けられたゲート電極と、を備える、炭化珪素半導体装置。     A silicon carbide layer having a first main surface and a second main surface opposite to the first main surface;
    The silicon carbide layer includes a first layer constituting the first main surface and having a first conductivity type;
    A second layer provided in the first layer and having a second conductivity type different from the first conductivity type;
    A third layer provided in at least the second layer and constituting a part of the second main surface and having the first conductivity type,
    A trench is provided in the second main surface of the silicon carbide layer,
    The trench has a first side wall portion where the second layer and the third layer are exposed, and a bottom portion which is connected to the first side wall portion and located in the second layer, and
    A gate insulating film covering each of the first side wall and the bottom;
    A silicon carbide semiconductor device comprising: a gate electrode provided on the gate insulating film.
  2. 　前記第１の側壁部において前記第２の層が表出する部分には、面方位｛０－３３－８｝を有する第１の面を含む表面が設けられている、請求項１に記載の炭化珪素半導体装置。 2. The surface including the first surface having a plane orientation {0-33-8} is provided in a portion of the first side wall portion where the second layer is exposed. Silicon carbide semiconductor device.
  3. 　前記トレンチの断面形状は、Ｖ字形状である、請求項１または請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1 or 2, wherein a cross-sectional shape of the trench is V-shaped.
  4. 　前記トレンチは、前記第１の側壁部と対向配置されるとともに前記底部と連なる第２の側壁部を有し、
    　前記第２の側壁部では、前記第２の層と前記第３の層とが表出する、請求項１～請求項３のいずれか１項に記載の炭化珪素半導体装置。     The trench has a second side wall portion arranged opposite to the first side wall portion and continuous with the bottom portion,
    The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the second layer and the third layer are exposed at the second side wall portion.
  5. 　前記ゲート電極に電圧を印加したときに、前記トレンチの少なくとも前記第１の側壁部に表出する前記第２の層および前記底部を含む領域はチャネル領域となり、
    　前記チャネル領域のチャネル長は、０．６μｍ以上である、請求項１～請求項４のいずれか１項に記載の炭化珪素半導体装置。     When a voltage is applied to the gate electrode, a region including at least the second layer and the bottom portion exposed on the first side wall portion of the trench is a channel region,
    The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein a channel length of the channel region is 0.6 袖 m or more.
  6. 　前記第２の層における不純物濃度は、５×１０16ｃｍ-3以上である、請求項１～請求項５のいずれか１項に記載の炭化珪素半導体装置。 6. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration in the second layer is 5 × 10 16 cm −3 or more.
  7. 　前記第１の導電型はｎ型であり、前記第２の導電型はｐ型である、請求項１～請求項６のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
PCT/JP2014/066818 2013-08-07 2014-06-25 Silicon carbide semiconductor device WO2015019731A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013164008A JP6135383B2 (en) 2013-08-07 2013-08-07 Silicon carbide semiconductor device
JP2013-164008 2013-08-07

Publications (1)

Publication Number Publication Date
WO2015019731A1 true WO2015019731A1 (en) 2015-02-12

Family

ID=52461070

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/066818 WO2015019731A1 (en) 2013-08-07 2014-06-25 Silicon carbide semiconductor device

Country Status (2)

Country Link
JP (1) JP6135383B2 (en)
WO (1) WO2015019731A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466755A (en) * 2020-11-17 2021-03-09 深圳宝铭微电子有限公司 MOS transistor and manufacturing process thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6336055B2 (en) * 2014-05-23 2018-06-06 株式会社日立製作所 Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and railway vehicle
JP6288298B2 (en) 2014-11-12 2018-03-07 富士電機株式会社 Silicon carbide semiconductor switching element and method for manufacturing the same
JP2019091754A (en) * 2017-11-13 2019-06-13 株式会社日立製作所 Silicon carbide semiconductor device, power conversion system and silicon carbide semiconductor device manufacturing method
JP7002998B2 (en) * 2018-05-28 2022-01-20 株式会社日立製作所 Semiconductor devices and their manufacturing methods, power conversion devices, three-phase motor systems, automobiles, and railroad vehicles

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354788A (en) * 1998-06-12 1999-12-24 Nissan Motor Co Ltd Semiconductor device and its manufacture
JP2008141056A (en) * 2006-12-04 2008-06-19 Toyota Central R&D Labs Inc Semiconductor device
JP2013143523A (en) * 2012-01-12 2013-07-22 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354788A (en) * 1998-06-12 1999-12-24 Nissan Motor Co Ltd Semiconductor device and its manufacture
JP2008141056A (en) * 2006-12-04 2008-06-19 Toyota Central R&D Labs Inc Semiconductor device
JP2013143523A (en) * 2012-01-12 2013-07-22 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466755A (en) * 2020-11-17 2021-03-09 深圳宝铭微电子有限公司 MOS transistor and manufacturing process thereof

Also Published As

Publication number Publication date
JP6135383B2 (en) 2017-05-31
JP2015032813A (en) 2015-02-16

Similar Documents

Publication Publication Date Title
US9608074B2 (en) Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
US8941120B2 (en) Semiconductor device and method for manufacturing the same
US20150372128A1 (en) Silicon carbide semiconductor device and method for manufacturing same
WO2014141754A1 (en) Silicon carbide semiconductor device
TW201251023A (en) Semiconductor device
US9799515B2 (en) Silicon carbide semiconductor device and method of manufacturing the same
TW201304146A (en) Semiconductor device and method of manufacturing same
WO2014199748A1 (en) Silicon carbide semiconductor device
JP6171678B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US10014376B2 (en) Silicon carbide semiconductor device having a trench with side walls and method for manufacturing same
JP6075120B2 (en) Silicon carbide semiconductor device
WO2015019731A1 (en) Silicon carbide semiconductor device
US9299790B2 (en) Silicon carbide semiconductor device
US20150279967A1 (en) Method for manufacturing silicon carbide semiconductor device
JPWO2014148130A1 (en) Silicon carbide semiconductor device and manufacturing method thereof
WO2014002589A1 (en) Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
WO2013172124A1 (en) Silicon carbide semiconductor device
US9728633B2 (en) Silicon carbide semiconductor device and method for manufacturing the same
WO2014041879A1 (en) Silicon carbide semiconductor device
WO2014171211A1 (en) Method for manufacturing silicon carbide semiconductor device
JP2013243180A (en) Silicon carbide semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14834288

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14834288

Country of ref document: EP

Kind code of ref document: A1