JPH11354788A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing the breakdown of a gate electrode when a surge voltage is applied to a drain electrode, and its manufacturing method. SOLUTION: A semiconductor device consists of a U-shaped groove 108 that is formed so that it reaches a low-concentration n-type epitaxial layer 192 from the surface of a p-type base region 105 being formed on the surface of the low-concentration n-type epitaxial layer 102, a U-shaped gate electrode 111 that is formed on the surface of the U-shaped groove 108 via an interlayer insulation film 113, and an n-type source region 107 that is formed at a position in contact with the interlayer insulation film 113 on the surface of the p-type base region 105. In this case, the bottom part of the p-type base region 105 touches the interlayer insulation film 113 at a shallower position than the depth of the U-shaped groove and at the same time, has a deeper part than the depth of the U-shaped groove 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a U-shaped gate MOSFET (hereinafter referred to as U-shaped gate MOSFET).
MOS) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 17 to 21 show a conventional vertical UMO.
It is a figure showing the manufacturing process of S. First, as shown in FIG. 17, a low-concentration n-type epitaxial layer 202 is formed on the upper surface of a high-concentration n-type semiconductor substrate 201. Next, as shown in FIG. 18, a p-type impurity is ion-implanted into the surface of the low-concentration n-type epitaxial layer 202, and thermal diffusion is performed to form a p-type base region 203. Then, as shown in FIG.
An n-type impurity and a p-type impurity are ion-implanted into predetermined regions of the surface of the mold base region 203, respectively, and thermally diffused to form an n-type source region 204 and a p-type base contact region 205, respectively. Then, as shown in FIG. 20, from the surface of n-type source region 204 to p-type base region 2
A U-shaped groove 206 is formed to a depth that penetrates through the substrate 03 and reaches the low-concentration n-type epitaxial layer 202. A gate oxide film 207 is formed on the bottom and side surfaces of the U-shaped groove 206. Thereafter, the U-shaped groove 206 is filled with high-concentration n-type polycrystalline silicon 208 to form a U-shaped gate electrode 209. Next, as shown in FIG.
9, an oxide film 210 is formed on the upper surface,
Form one. Then, a source electrode 212 is formed so as to be connected to the n-type source region 204 and the p-type base contact region 205. The high-concentration n-type polycrystalline silicon 208 in the U-shaped gate electrode 209 is insulated from the source electrode 212 by the cap oxide film 210 and the interlayer insulating film 211. Further, a drain electrode 213 is formed on the lower surface of the high-concentration n-type semiconductor substrate 201. The UMOS formed by the above process has a JF
Since there is no ET resistance component, more M
Since an OS can be formed, miniaturization of an element and increase in cell density can be performed, and as a result, on-resistance, which is important as a characteristic of a power MOSFET, can be reduced. UMOS
Has a structure in which a U-shaped gate electrode 209 penetrates the p-type base region 203. Also, the p-type base region 20
A depletion layer spreads at the junction between the drain region 3 and the drain region. This depletion layer also extends to the drain region below the U-shaped gate electrode 209 as shown in FIG. 21 to prevent the electric field from being concentrated at the corner at the bottom of the U-shaped gate electrode 209. However, when a surge voltage is applied to the drain electrode 213, there is a problem that an electric field concentrates on a corner portion at the bottom of the U-shaped gate electrode 209 and the gate oxide film 207 may be broken.

[0003]

The present invention solves the above-mentioned problems. That is, the present invention proposes a structure and a manufacturing method of a UMOS having a structure for preventing the destruction of the U-shaped gate electrode 209 when a surge voltage is applied to the drain electrode 213.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor region serving as a drain region of a first conductivity type; and a first semiconductor region formed on a surface of the first semiconductor region. A second semiconductor region of a second conductivity type serving as a base region; a plurality of first grooves formed so as to reach the first semiconductor region from a surface of the second semiconductor region; A gate electrode formed on the surface via an insulating film, a first conductive type third semiconductor region serving as a source region formed on the surface of the second semiconductor region and in contact with the insulating film; And a bottom portion of the second semiconductor region is in contact with the insulating film at a position shallower than the depth of the groove, and has a portion deeper than the depth of the groove. According to a second aspect of the present invention, a first semiconductor region serving as a drain region of a first conductivity type, a second semiconductor region of a second conductivity type serving as a base region formed on a surface of the first semiconductor region, A plurality of first grooves formed from the surface of the second semiconductor region to the first semiconductor region; a gate electrode formed on the surface of each first groove via an insulating film; And a third semiconductor region of a first conductivity type serving as a source region formed at a position in contact with the insulating film on a surface of the second semiconductor region. It is characterized in that the thickness is larger than the thickness of the other first semiconductor regions. According to a third aspect of the present invention, a first region having a first depth and a second depth greater than the first depth is formed on a surface of the first semiconductor region of the first electric type which is a drain region. Forming two semiconductor regions, and forming a groove reaching the first semiconductor region from the surface of the second semiconductor region and having a bottom portion deeper than the first depth and shallower than the second depth. A step of forming a gate electrode via an insulating film formed on the surface of the first groove; and a step of forming a source region at a position on the surface of the second semiconductor region and in contact with the insulating film. Forming a third semiconductor region of a conductivity type. According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the step of forming the second semiconductor region includes the step of selectively forming a second groove in a surface of the first semiconductor region. And a step of embedding a polycrystalline semiconductor in which an impurity is introduced into the second groove, and a step of diffusing the impurity into the first semiconductor region. According to a fifth aspect of the present invention, a first semiconductor region serving as a drain region of the first conductivity type and a second groove are selectively formed on a surface of the first semiconductor region, and impurities are contained in the second groove. A first depth and a second depth deeper than the first depth are formed on the surface of the first semiconductor region formed by embedding the introduced polycrystalline semiconductor and diffusing the impurity into the first semiconductor region. A second semiconductor region serving as a base region having a depth of, a plurality of first grooves formed so as to reach the first semiconductor region from the surface of the second semiconductor region, A gate electrode formed on the surface via an insulating film, a first conductive type third semiconductor region serving as a source region formed on the surface of the second semiconductor region and in contact with the insulating film; In a semiconductor device comprising
The bottom of the second semiconductor region is in contact with the insulating film at a position shallower than the depth of the groove, and has a portion deeper than the depth of the groove.

[0005]

According to the method of manufacturing a semiconductor device, a UMOS having a structure having a convex portion at the bottom of the base region can be formed. In this UMOS, when a surge voltage is applied to the drain electrode, the electric field is concentrated at the convex portion at the bottom of the base region, which is short from the drain electrode, thereby suppressing the electric field concentration at the corner at the bottom of the gate electrode. And
Destruction of the gate electrode can be prevented.

[0006]

Embodiments of the present invention will be described below. FIGS. 1 to 6 are views showing the manufacturing process of the first embodiment of the present invention. This is a view showing a manufacturing process of the vertical UMOS.

First, as shown in FIG. 1, a low-concentration n-type epitaxial layer 102 is formed on a high-concentration n-type semiconductor substrate 101. Next, as shown in FIG. 2, an impurity introduction groove 103 is formed on the surface of the low-concentration n-type epitaxial layer 102.

Then, as shown in FIG. 3, a p-type impurity is introduced into the bottom and side surfaces of the impurity
A region 104 containing a type impurity is formed. As a method of forming the region 104 containing the p-type impurity, for example, a method of forming boron glass on the bottom surface and side surfaces of the impurity introduction groove 103 and thermally diffusing the same may be considered. Next, as shown in FIG. 4, heat treatment is performed, and the p-type base region 105 is formed by impurity diffusion in the region 104 containing the p-type impurity.
To form Further, inside the impurity introduction groove 103,
A high concentration p-type polycrystalline silicon 106 is buried.

Then, as shown in FIG. 5, after forming an n-type source region 107 by ion implantation and thermal diffusion, a U-shaped gate electrode 111 is formed. To form the U-shaped gate electrode 111, first, a U-shaped groove 108 is formed, and the gate oxide film 10 is formed on the bottom and side surfaces of the U-shaped groove 108.
9 is formed, and then a high-concentration n-type polysilicon 110 is formed in the U-shaped groove 108. Then, as shown in FIG. 6, the surface of the high-concentration n-type polycrystalline silicon 110 is oxidized,
Forming a cap oxide film 112;
Form 3 Then, source electrode 114 is formed so as to be connected to n-type source region 107 and high-concentration p-type polycrystalline silicon 106. Further, a drain electrode 115 is formed on the lower surface of the high-concentration n-type semiconductor substrate 101.

Here, the impurity introducing groove 103 and the p-type base region 105 are formed so as to satisfy the following conditions.
First, the depth of the impurity introducing groove 103 must be less than the depth of the U-shaped gate electrode 111. When the depth of the impurity introducing groove 103 is deeper than the depth of the U-shaped gate electrode 111, as shown in FIG.
The structure does not penetrate the mold base region 105. In this structure, even when a predetermined voltage is applied to the U-shaped gate electrode 111, the channel does not open and does not operate as a UMOS. The lateral diffusion distance of the p-type base region 105 reaches the side surface of the U-shaped gate electrode 111, and
It is formed so as to obtain a predetermined threshold voltage of S. When the p-type base region 105 does not reach the side surface of the U-shaped gate electrode 111, the drain electrode 115 and the source electrode 114 are connected by an n-type region as shown in FIG.
Does not operate as S. On the other hand, the diffusion distance in the vertical direction must be a certain depth or more so that the electric field does not concentrate on the corner at the bottom of the U-shaped gate electrode 111. However, if it is too deep, the breakdown voltage of the element will decrease. Therefore, the vertical diffusion distance of p-type base region 105 is defined in a certain range.

The diffusion distance in the vertical and horizontal directions of the p-type base region 105 is determined by the width and depth of the impurity introducing groove 103 (the depth is U
The depth is controlled by a diffusion step or the like.

The vertical UM formed by the above manufacturing method
In the OS, the bottom of the p-type base region 105 is formed in a convex shape. As a result, when a surge voltage is applied to the drain electrode 115, the electric field concentrates on this convex portion. Therefore, it is possible to prevent the gate from being broken due to the concentration of the electric field at the bottom corner of the U-shaped gate electrode 111.

Although FIGS. 1 to 6 show the steps of manufacturing a vertical UMOS, the same effects can be obtained by applying the invention to a horizontal UMOS. FIG. 9 is a diagram showing a device structure when the manufacturing method of the present embodiment is applied to a horizontal UMOS. In this case, the drain electrode 119
And a source electrode 120 are formed on the same surface side of the high-concentration n-type semiconductor substrate. Here, 116 is a low concentration p-type semiconductor substrate, 117 is a high concentration n-type buried layer, and 118 is a high concentration drain contact region. The drain electrode 119 is connected to the high-concentration n-type drain contact region 118.

FIGS. 10 to 15 are views showing a manufacturing process according to the second embodiment of the present invention. This configuration corresponds to the first embodiment.
In the manufacturing process, the method of forming the p-type base region 105 is changed. That is, as shown in FIG. 12, high-concentration p-type polysilicon 1
Embed 21. By performing the heat treatment in FIG. 13, the solid layer diffusion from the high-concentration p-type polycrystalline silicon 121 causes
A p-type base region 122 is formed. In FIG. 15, source electrode 114 is connected to n-type source region 107 and high-concentration p-type polycrystalline silicon 121. With such a configuration, the number of steps can be reduced as compared with the case of the first embodiment.

FIG. 16 shows a UMO according to a third embodiment of the present invention.
It is a figure showing the device structure manufactured by the manufacturing process of S. This embodiment is different from the second embodiment in that a step of forming a p-type base contact region 123 is added. When a long diffusion distance is required in the p-type base region 122, the surface concentration of the high-concentration p-type polycrystalline silicon 121 is reduced, and ohmic characteristics cannot be obtained at the junction with the source electrode 114. But even in that case p
By adding the step of forming the mold base contact region 123, an ohmic junction between the source electrode 114 and the high-concentration p-type polycrystalline silicon 121 can be realized. Also in the first embodiment, a source electrode 11 can be formed by adding a step of forming a p-type base contact region.
4 and the high-concentration p-type polycrystalline silicon 106 can be improved in ohmic contact and reduced in contact resistance.

[0016]

According to the present invention, the following effects can be obtained. First, an impurity diffusion groove is formed on the first main surface of an n-type semiconductor substrate serving as an n-type drain region in a UMOS, and p-type impurities are introduced into the bottom and side surfaces of the impurity diffusion groove. Forming a p-type base region having a convex bottom by thermal diffusion prevents gate breakdown due to electric field concentration at the bottom corner of the U-shaped gate electrode when a surge voltage is applied to the drain electrode. be able to. Second, by implanting high-concentration p-type polycrystalline silicon in the impurity diffusion trenches and performing heat treatment, that is, by forming a p-type base region by solid-phase diffusion from high-concentration p-type polycrystalline silicon, P-type impurities are introduced into the bottom and side surfaces of the impurity introduction groove by any method, such as forming boron glass on the bottom surface and side surfaces of the introduction groove and thermally diffusing the same. The number of steps can be reduced as compared with the method of embedding silicon. Third, in the above structure, by adding a step of forming a p-type base contact region, it is possible to improve the ohmic property of the junction between the source electrode and the p-type base region and reduce the contact resistance. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a UMOS according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the UMOS according to the first embodiment;

FIG. 3 is a view showing a manufacturing process of the UMOS according to the first embodiment;

FIG. 4 is a diagram illustrating a manufacturing process of the UMOS according to the first embodiment;

FIG. 5 is a diagram showing a manufacturing process of the UMOS of the first embodiment.

FIG. 6 is a diagram illustrating a manufacturing process of the UMOS according to the first embodiment;

FIG. 7 is a diagram illustrating conditions for forming a p-type base region.

FIG. 8 is a diagram illustrating conditions for forming a p-type base region.

FIG. 9 is a cross-sectional view of a UMOS manufacturing process
FIG. 3 is a diagram illustrating a device structure manufactured when applied to an OS.

FIG. 10 is a diagram showing a manufacturing process of the UMOS according to the second embodiment.

FIG. 11 is a view showing a manufacturing process of the UMOS according to the second embodiment;

FIG. 12 is a diagram showing a manufacturing process of the UMOS according to the second embodiment.

FIG. 13 is a diagram showing a manufacturing process of the UMOS according to the second embodiment.

FIG. 14 is a diagram illustrating a manufacturing process of the UMOS according to the second embodiment;

FIG. 15 is a diagram illustrating a manufacturing process of the UMOS according to the second embodiment;

FIG. 16 is a diagram showing a device structure manufactured by the UMOS manufacturing process of the third embodiment.

FIG. 17 is a view showing a manufacturing process of a conventional UMOS.

FIG. 18 is a view showing a manufacturing process of a conventional UMOS.

FIG. 19 is a diagram showing a manufacturing process of a conventional UMOS.

FIG. 20 is a diagram showing a manufacturing process of a conventional UMOS.

FIG. 21 is a diagram showing a manufacturing process of a conventional UMOS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 High-concentration n-type semiconductor substrate 102 Low-concentration n-type epitaxial layer 103 Impurity introduction groove 104 P-type impurity-containing region 105 p-type base region 106 high-concentration p-type polycrystalline silicon 107 n-type source region 108 U-shaped Groove 109 Gate oxide film 110 High-concentration n-type polycrystalline silicon 111 U-shaped gate electrode 112 Cap oxide film 113 Interlayer insulating film 114 Source electrode 115 Drain electrode 116 Low-concentration p-type semiconductor substrate 117 High-concentration n-type buried layer 118 High-concentration Drain contact region 119 drain electrode 120 source electrode 121 high-concentration p-type polycrystalline silicon 122 p-type base region 123 p-type base contact region 201 high-concentration n-type semiconductor substrate 202 low-concentration n-type epitaxial layer 203 p-type base region 204 n-type Source area 05 p-type base contact region 206 U-shaped groove 207 gate oxide film 208 high-concentration n-type polycrystalline silicon 209 U-shaped gate electrode 210 cap oxide film 211 interlayer insulating film 212 source electrode 213 drain electrode

Claims (5)

[Claims] A first semiconductor region serving as a drain region of a first conductivity type; a second semiconductor region of a second conductivity type serving as a base region formed on a surface of the first semiconductor region; A plurality of first grooves formed from the surface of the region to the first semiconductor region; a gate electrode formed on the surface of each first groove via an insulating film; and the second semiconductor region A third region of the first conductivity type which is a source region formed at a position in contact with the insulating film on the surface of
A semiconductor region comprising a semiconductor region, wherein a bottom of the second semiconductor region is in contact with the insulating film at a position shallower than the depth of the groove, and has a portion deeper than the depth of the groove. Semiconductor device. A first semiconductor region serving as a drain region of the first conductivity type; a second semiconductor region of a second conductivity type serving as a base region formed on a surface of the first semiconductor region; A plurality of first grooves formed from the surface of the region to the first semiconductor region; a gate electrode formed on the surface of each first groove via an insulating film; and the second semiconductor region A third region of the first conductivity type which is a source region formed at a position in contact with the insulating film on the surface of
A semiconductor device comprising a semiconductor region, wherein a thickness of the first semiconductor region below the trench is larger than a thickness of another first semiconductor region. 3. A second semiconductor region serving as a base region having a first depth and a second depth greater than the first depth, on a surface of the first electric type first semiconductor region serving as a drain region. Forming a groove reaching the first semiconductor region from the surface of the second semiconductor region and having a bottom deeper than the first depth and shallower than the second depth; Forming a gate electrode via an insulating film formed on the surface of the first groove; and forming a source region at a position on the surface of the second semiconductor region in contact with the insulating film, the first conductive type being a source region. Forming a third semiconductor region. 4. The step of forming the second semiconductor region, the step of selectively forming a second groove in the surface of the first semiconductor region, and the step of: forming a polycrystalline structure in which impurities are introduced into the second groove. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising: burying a semiconductor; and diffusing the impurity into the first semiconductor region. 5. A first semiconductor region serving as a drain region of a first conductivity type, and a second groove is selectively formed on a surface of the first semiconductor region, and an impurity is introduced into the second groove. A surface of the first semiconductor region, which is formed by embedding a polycrystalline semiconductor and diffusing the impurity into the first semiconductor region,
A second semiconductor region serving as a base region having a first depth and a second depth greater than the first depth; and a second semiconductor region formed to reach the first semiconductor region from a surface of the second semiconductor region. A plurality of first trenches; a gate electrode formed on the surface of each first trench via an insulating film; and a gate electrode formed on a surface of the second semiconductor region and in contact with the insulating film. Third of the first conductivity type serving as a source region
A semiconductor region comprising a semiconductor region, wherein a bottom of the second semiconductor region is in contact with the insulating film at a position shallower than the depth of the groove, and has a portion deeper than the depth of the groove. Semiconductor device.