JP3448015B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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JP3448015B2
JP3448015B2 JP2000224985A JP2000224985A JP3448015B2 JP 3448015 B2 JP3448015 B2 JP 3448015B2 JP 2000224985 A JP2000224985 A JP 2000224985A JP 2000224985 A JP2000224985 A JP 2000224985A JP 3448015 B2 JP3448015 B2 JP 3448015B2
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誠治 十河
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松下電器産業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66659Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、高耐圧特性を有しながらオン抵抗を低くすることができる横型半導体装置及びその製造方法に関する。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention relates to a lateral semiconductor device and a manufacturing method thereof can be reduced on-resistance while having a high withstand voltage characteristics. 【0002】 【従来の技術】高耐圧特性を有しながらオン抵抗を低くすることができる横型半導体装置については、従来から様々な構造が提案されており、その一例として、特許公報第3016762号に示されている半導体装置について、図6を参照しながら説明する。 [0002] The lateral semiconductor device that can reduce the on-resistance while having the Related Art High-voltage characteristics, and various structures conventionally been proposed, as an example, in Japanese Patent No. 3016762 a semiconductor device shown will now be described with reference to FIG. 【0003】図6に示すように、p型の半導体基板10 [0003] As shown in FIG. 6, p-type semiconductor substrate 10 of
には、n型領域からなるソース領域11及びn型領域からなる延長ドレイン領域12がそれぞれ形成されている。 , The extended drain region 12 composed of the source region 11 and the n-type region consisting of n-type region are respectively formed. 【0004】延長ドレイン領域12の表面部にはn型高濃度領域13が形成されていると共に、延長ドレイン領域12におけるn型高濃度領域13の下方にはp型埋め込み領域14が形成されている。 [0004] with n-type high-concentration region 13 in a surface portion of the extended drain region 12 is formed, p-type buried region 14 below the n-type high-concentration region 13 in the extended drain region 12 is formed . n型高濃度領域13はドレイン電極15と接続されていると共に、p型埋め込み領域14は半導体基板10と接続されている。 n-type high concentration region 13 with is connected to the drain electrode 15, p-type buried region 14 is connected to the semiconductor substrate 10. 【0005】半導体基板10の表面部にはソース領域1 [0005] The source region in a surface portion of the semiconductor substrate 10 1
1と隣接するようにp型の基板コンタクト領域16が形成されており、ソース領域11及び基板コンタクト領域16はソース電極17に接続されている。 1 and p-type substrate contact region 16 is formed adjacent the source region 11 and the substrate contact region 16 is connected to the source electrode 17. これによって、ソース領域11は半導体基板10と同電位に設定される。 Thus, the source region 11 is set to the semiconductor substrate 10 the same potential. また、半導体基板10にはソース領域11及び基板コンタクト領域16を囲むようにp型のアンチパンチスルー領域18が形成されている。 Moreover, the anti-punchthrough region 18 of the p-type so as to surround the source region 11 and the substrate contact region 16 is formed in the semiconductor substrate 10. 【0006】半導体基板10の上におけるソース領域1 [0006] The source region in the top of the semiconductor substrate 10 1
1と延長ドレイン領域12との間にはゲート絶縁膜を介してゲート電極19が形成されており、半導体基板10 1 and the gate electrode 19 is formed via a gate insulating film between the extended drain region 12, the semiconductor substrate 10
におけるゲート電極19の下側の領域はチャネル領域として機能する。 The region below the gate electrode 19 in the functions as a channel region. ゲート電極19を含む半導体基板10の表面は絶縁膜20により覆われている。 Surface of the semiconductor substrate 10 including the gate electrode 19 is covered with the insulating film 20. 【0007】前記従来例の半導体装置の特徴は、n型領域からなる延長ドレイン領域12の内部に、n型高濃度領域13及びp型埋め込み領域14を備えていることである。 [0007] wherein the conventional semiconductor device, the inside of the extended drain region 12 of n-type region, is that it comprises a n-type high concentration region 13 and the p-type buried region 14. 【0008】p型埋め込み領域14は半導体基板10を介して基準電位に設定されているため、延長ドレイン領域12に高電圧が印加されると、延長ドレイン領域12 [0008] Since the p-type buried region 14 is set to the reference potential via a semiconductor substrate 10, a high voltage is applied to the extended drain region 12, extended drain region 12
と、半導体基板10及びp型埋め込み領域14とは逆バイアス状態になる。 If, it becomes reverse biased and the semiconductor substrate 10 and the p-type buried region 14. このため、延長ドレイン領域12とp型埋め込み領域14との接合部から空乏層が拡がると共に、延長ドレイン領域12と半導体基板10との接合部からも空乏層が拡がる。 Therefore, the depletion layer spreads from the junction between the extended drain region 12 and the p-type buried region 14, the depletion layer spreads from the junction between the extended drain region 12 and the semiconductor substrate 10. これらの空乏層の絶縁耐圧特性を利用することにより、MOS型トランジスタの高耐圧化を図ることができる。 By utilizing the dielectric breakdown voltage characteristics of these depletion layers, it is possible to increase the withstand voltage of the MOS transistor. 【0009】ゲート電極20に電圧が印加されると、M [0009] When a voltage is applied to the gate electrode 20, M
OS型トランジスタのチャネル領域が導通するので、破線の矢印で示すように、電流は主として、延長ドレイン領域12の内部におけるn型不純物濃度が高い領域、つまりn型高濃度領域13とp型埋め込み領域14の下方の領域とを流れる。 Since the channel region of the OS-type transistor becomes conductive, as shown by the dashed arrows, the current primarily, n-type impurity concentration is high region inside the extended drain region 12, that is n-type high-concentration region 13 and the p-type buried region 14 through a lower region of the. 【0010】ところで、通常行なわれているように、基板表面からの拡散により延長ドレイン領域12の表面部にp型領域を形成すると、延長ドレイン領域12における不純物濃度の最も高い表面部におけるn型不純物の濃度は著しく低下するため、オン抵抗は高くなってしまう。 By the way, as is usually done, to form a p-type region in a surface part of the extended drain region 12 by diffusion from the substrate surface, n-type impurity in the highest surface portion of the impurity concentration in the extended drain region 12 since the concentration significantly reduced, the on-resistance becomes higher. 【0011】そこで、前記従来例においては、延長ドレイン領域12の内部にp型埋め込み領域14を形成することにより、延長ドレイン領域12の表面部におけるn [0011] Therefore, in the conventional example, by forming a p-type buried region 14 inside the extended drain region 12, n in the surface portion of the extended drain region 12
型不純物の濃度の低下を防止して、オン抵抗の低減を図っている。 And prevent the decrease in the concentration of the impurity, thereby reducing the on-resistance. 【0012】さらに、前記従来例においては、延長ドレイン領域12の表面部にn型高濃度領域13を設けて、 Furthermore, in the conventional example, the n-type high-concentration region 13 is provided on the surface portion of the extended drain region 12,
延長ドレイン領域12の表面部におけるn型不純物濃度を高くすることにより、オン抵抗の一層の低減を図っている。 By increasing the n-type impurity concentration in the surface portion of the extended drain region 12, thereby achieving a further reduction in on-resistance. 【0013】 【発明が解決しようとする課題】ところで、前記従来の構造においては、MOS型トランジスタが動作する際の電流経路は、延長ドレイン領域12における、n型高濃度領域(表面領域)13とp型埋め込み領域14の下方の領域(底部領域)とに分かれているため、高耐圧特性を得るためには、延長ドレイン領域12におけるp型埋め込み領域14の下方の領域の不純物濃度を低くして、 [0013] [SUMMARY OF THE INVENTION Incidentally, in the conventional structure, the current path when the MOS transistor operates, in the extended drain region 12, n-type high concentration region (surface region) 13 and since is divided into a region below the p-type buried region 14 (bottom area), in order to obtain a high breakdown voltage characteristics, by lowering the impurity concentration of the lower region of the p-type buried region 14 in the extended drain region 12 ,
逆バイアス電圧を印加したときに接合部から拡がる空乏層の領域を大きくすることが好ましい。 It is preferable to increase the area of ​​the depletion layer that spreads from the junction when a reverse bias voltage is applied. そして、延長ドレイン領域12におけるp型埋め込み領域14の下方の領域の不純物濃度を低くするためには、延長ドレイン領域12を形成する工程において、ドーピングされる不純物の濃度を低くすると共に該不純物を熱拡散させる必要がある。 Then, in order to lower the impurity concentration of the lower region of the p-type buried region 14 in the extended drain region 12, in the step of forming the extended drain region 12, heat the impurities as well as lower the concentration of impurities to be doped there is a need to diffuse. 【0014】ところが、延長ドレイン領域12におけるp型埋め込み領域14の下方の領域の不純物濃度を低くすると、オン抵抗が高くなってしまうので、延長ドレイン領域12におけるp型埋め込み領域14の下方の領域の不純物濃度を低くすることは好ましくない。 [0014] However, lowering the impurity concentration in the region below the p-type buried region 14 in the extended drain region 12, since the on-resistance becomes higher, the lower region of the p-type buried region 14 in the extended drain region 12 lowering the impurity concentration is not preferable. 従って、 Therefore,
高耐圧特性を確保しながらオン抵抗を低減するためには、表面に位置するn型高濃度領域13の不純物濃度を高くしなければならない。 In order to reduce the on-resistance while maintaining a high breakdown voltage must increase the impurity concentration of the n-type high-concentration region 13 located on the surface. 【0015】しかしながら、n型高濃度領域13の不純物濃度を高くしようとすると、n型の不純物がp型埋め込み領域14に拡散してp型埋め込み領域14の不純物濃度が低下してしまうため、逆バイアス電圧を印加したときの空乏層の拡がりが十分でなくなるので、電界分布が変化して高耐圧特性が劣化してしまうという問題が発生する。 [0015] However, an attempt to increase the impurity concentration of the n-type high-concentration region 13, the impurity concentration of the p-type buried region 14 n-type impurity is diffused into the p-type buried region 14 is decreased, the reverse since the spread of the depletion layer is not sufficient at the time of applying a bias voltage, a problem that electric field distribution high withstand voltage characteristics change deteriorates occurs. このため、n型高濃度領域13の不純物濃度を高くすることは好ましくない。 Therefore, increasing the impurity concentration of the n-type high-concentration region 13 is not preferable. 【0016】従って、前記従来の構造によると、高耐圧特性の確保とオン抵抗の低減との両立を図っているが、 [0016] Therefore, according to the conventional structure, thereby achieving the compatibility between the reduction of security and on-resistance of the high breakdown voltage characteristics,
この両立は十分であるとは言えない。 This compatibility can not be said to be sufficient. 【0017】前記に鑑み、本発明は、高耐圧特性を確保しつつ、オン抵抗を確実に低減できるようにすることを目的とする。 [0017] In view of the above, the present invention is, while ensuring a high withstand voltage characteristics, and an object thereof is to ensure that reduce the on-resistance. 【0018】 【課題を解決するための手段】前記の目的を達成するため、本発明は、延長ドレイン領域の内部における反対導電型の埋め込み領域の上方又は下方にさらに反対導電型の埋め込み領域を設けることにより、延長ドレイン領域の底部における不純物濃度を低くすることなく、高耐圧特性を向上させるものである。 [0018] [Means for Solving the Problems] To achieve the above object, the present invention is provided with upper or even the opposite conductivity type buried region under the opposite conductivity type buried region inside the extended drain region it makes no reducing the impurity concentration at the bottom of the extended drain region, thereby improving the high withstand voltage characteristics. 【0019】具体的には、本発明に係る半導体装置は、 [0019] Specifically, the semiconductor device according to the present invention,
第1導電型の半導体基板にそれぞれ形成された第2導電型のドレイン領域及びソース領域と、ドレイン領域に互いに間隔をおいて形成された第1導電型の不純物層からなり、下側に位置する第1の埋め込み領域及び上側に位置する第2の埋め込み領域と、ドレイン領域における第1の埋め込み領域と第2の埋め込み領域との間に形成された第2導電型の高濃度不純物領域とを備えている。 A second conductivity type drain region and a source region formed respectively on the first conductivity type semiconductor substrate comprises a first conductive type impurity layer formed spaced apart from each other in the drain region, located on the lower side comprising a second buried region located in the first buried region and the upper, and the first buried region and the high concentration impurity region of the second conductivity type formed between the second buried region in the drain region ing. 【0020】本発明に係る半導体装置によると、ドレイン領域には、互いに間隔をおいて形成された第1導電型の第1の埋め込み領域及び第2の埋め込み領域と、第1 [0020] According to the semiconductor device according to the present invention, the drain region includes a first buried region and the second buried region of the first conductivity type formed spaced apart from each other, the first
の埋め込み領域と第2の埋め込み領域との間に形成された第2導電型の高濃度不純物領域とを備えているため、 Due to the provision of the buried region and the high concentration impurity region of the second conductivity type formed between the second buried region,
ドレイン領域に半導体基板に対して逆バイアスとなる電圧が印加されると、ドレイン領域と第1及び第2の埋め込み領域との各接合部並びにドレイン領域と半導体基板との接合部からそれぞれ空乏層が拡がるため、MOS型トランジスタの高耐圧特性を確保することができる。 If the voltage is reverse biased with respect to the semiconductor substrate in the drain region is applied, each depletion layer from the junction between the junction and the drain region and the semiconductor substrate between the drain region and the first and second buried region It spreads, it is possible to ensure a high breakdown voltage characteristics of the MOS transistor. また、ドレイン領域とソース領域とが導通状態になったときには、電流は第1の埋め込み領域と第2の埋め込み領域との間に形成されている高濃度不純物領域を流れるため、オン抵抗を低減することができる。 Further, when the drain region and the source region becomes conductive state, the current to flow to the high concentration impurity region formed between the first buried region and the second buried region, to reduce the on-resistance be able to. 従って、本発明に係る半導体装置によると、高耐圧特性を確保しつつ、 Therefore, in the semiconductor device according to the present invention, while ensuring a high withstand voltage characteristics,
オン抵抗を確実に低減することができる。 The on-resistance can be reliably reduced. 【0021】本発明に係る半導体装置は、ドレイン領域における第2の埋め込み領域の上側に形成された第2導電型の上方高濃度不純物領域をさらに備えていることが好ましい。 [0021] The semiconductor device according to the present invention preferably further includes an upper high-concentration impurity region of a second conductivity type formed on the upper side of the second buried region in the drain region. 【0022】このようにすると、ドレイン領域とソース領域とが導通状態になったときに、電流は上方高濃度不純物領域にも流れるため、オン抵抗を一層低減することができる。 [0022] Thus, when the drain region and the source region becomes conductive, the current to flow in the upper high-concentration impurity regions, it is possible to further reduce the on-resistance. 【0023】本発明に係る半導体装置は、ドレイン領域における第1の埋め込み領域の下側に、該第1の埋め込み領域との間に間隔をおいて形成された第1導電型の不純物層からなる下方埋め込み領域と、ドレイン領域における第1の埋め込み領域と下方埋め込み領域との間に形成された第2導電型の下方高濃度不純物領域とをさらに備えていることが好ましい。 The semiconductor device according to the present invention, under the first buried region in the drain region, a first conductivity type impurity layer formed at intervals between the first buried region a lower embedding region, it preferably further includes a formed lower high-concentration impurity region of the second conductivity type are between the first buried region and the lower buried region in the drain region. 【0024】このようにすると、ドレイン領域に、第1 [0024] In this manner, the drain region, the first
及び第2の埋め込み領域並びに半導体基板に対して逆バイアスとなる電圧が印加されると、空乏層はドレイン領域と下方埋め込み領域との接合部からも拡がるため、M And when the voltage becomes a reverse bias is applied to the second buried region and the semiconductor substrate, since the depletion layer spreads from the junction between the drain region and the lower buried regions, M
OS型トランジスタの高耐圧特性が一層向上する。 High breakdown voltage characteristic of the OS-type transistor is further improved. また、ドレイン領域とソース領域とが導通状態になったときには、電流は下方高濃度不純物領域をも流れるため、 Further, since when the drain region and the source region becomes conductive state, current flows also lower high concentration impurity regions,
オン抵抗を一層低減することができる。 The on-resistance can be further reduced. 従って、高耐圧特性を確保とオン抵抗の低減との両立を一層図ることができる。 Therefore, it is possible to further achieve both reduction of securing the on-resistance of high withstand voltage characteristics. 【0025】本発明に係る半導体装置において、第1及び第2の埋め込み領域は、半導体基板と電気的に接続されていることが好ましい。 [0025] In the semiconductor device according to the present invention, the first and second buried region is preferably connected to the semiconductor substrate and electrically. 【0026】このように、半導体装置が、第1及び第2 [0026] Thus, a semiconductor device, first and second
の埋め込み領域と半導体基板とが電気的に接続された構造を有していると、ドレイン領域に半導体基板に対して逆バイアスとなる電圧が印加されたときに、ドレイン領域と第1及び第2の埋め込み領域との接合部から空乏層が確実に拡がるため、MOS型トランジスタの高耐圧特性が向上する。 When the buried region and the semiconductor substrate has an electrical connection structure, when a voltage as a reverse bias relative to the semiconductor substrate in the drain region is applied, the drain region and the first and second for spreads from the junction between the buried region of ensuring a depletion layer, a high withstand voltage characteristics of the MOS transistor is improved. 【0027】本発明に係る半導体装置の製造方法は、第1導電型の半導体基板に第2導電型のドレイン領域及びソース領域をそれぞれ形成する工程と、ドレイン領域に第1導電型の第1の埋め込み領域を形成する工程と、ドレイン領域における第1の埋め込み領域の上側に第2導電型の高濃度不純物領域を形成する工程と、ドレイン領域における第2導電型の高濃度不純物領域の上側に第1 The method of manufacturing a semiconductor device according to the present invention includes the steps of forming each of the second conductivity type drain region and the source region of the first conductivity type semiconductor substrate, a first conductivity type in the drain region first forming a buried region, forming a first buried region heavily doped impurity regions above the second conductivity type in the drain region, the second above the high concentration impurity region of a second conductivity type in the drain region 1
導電型の第2の埋め込み領域を形成する工程とを備えている。 And a step of forming a second buried region of the conductivity type. 【0028】本発明に係る半導体装置の製造方法によると、ドレイン領域に、互いに間隔をおいて第1導電型の第1の埋め込み領域と第2の埋め込み領域とを形成することができると共に、第1の埋め込み領域と第2の埋め込み領域との間に第2導電型の高濃度不純物領域を形成することができるため、高耐圧特性を確保しつつオン抵抗を低減できる本発明に係る半導体装置を確実に製造することができる。 [0028] According to the manufacturing method of a semiconductor device according to the present invention, the drain region, it is possible to form a first buried region and the second buried region of the first conductivity type spaced apart from each other, the it is possible to form a high concentration impurity region of the second conductivity type between the first buried region and the second buried region, the semiconductor device according to the present invention can reduce the on-resistance while ensuring high withstand voltage characteristics it can be reliably manufactured. 【0029】本発明に係る半導体装置の製造方法は、ドレイン領域における第2の埋め込み領域の上側に第2導電型の上方高濃度不純物領域を形成する工程をさらに備えていることが好ましい。 The method of manufacturing a semiconductor device according to the [0029] present invention preferably further comprises a step of forming an upper high-concentration impurity region of a second conductivity type on the upper side of the second buried region in the drain region. 【0030】このようにすると、ドレイン領域とソース領域とが導通状態になったときに、電流は上方高濃度不純物領域にも流れるため、オン抵抗を一層低減することができる。 [0030] Thus, when the drain region and the source region becomes conductive, the current to flow in the upper high-concentration impurity regions, it is possible to further reduce the on-resistance. 【0031】本発明に係る半導体装置の製造方法において、第1の埋め込み領域及び第2の埋め込み領域は、それぞれイオン注入法により形成されることが好ましい。 [0031] In the method of manufacturing a semiconductor device according to the present invention, the first buried region and the second buried region is preferably each formed by ion implantation. 【0032】このようにすると、ドレイン領域に互いに間隔をおいて第1の埋め込み領域と第2の埋め込み領域とを確実に形成することができる。 [0032] Thus, a first buried region and the second buried regions at a distance from each other in the drain region can be reliably formed. 【0033】この場合、高濃度不純物領域はイオン注入法により形成されることが好ましい。 [0033] In this case, it is preferable that the high concentration impurity region is formed by ion implantation. 【0034】このようにすると、ドレイン領域における第1の埋め込み領域と第2の埋め込み領域との間に高濃度不純物領域を確実に形成することができる。 [0034] Thus, it is possible to reliably form the high concentration impurity region between the first buried region and the second buried region in the drain region. 【0035】 【発明の実施の形態】(第1の実施形態)以下、本発明の第1の実施形態に係る半導体装置について図1(a) [0035] PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a semiconductor device according to a first embodiment of the present invention FIGS. 1 (a)
〜(c)を参照しながら説明する。 ~ It will be described with reference to (c). 【0036】図1(a)に示すように、p型の半導体基板(不純物濃度:約1×10 14 〜約3×10 14 /c As shown in FIG. 1 (a), p-type semiconductor substrate (impurity concentration: about 1 × 10 14 ~ about 3 × 10 14 / c
3 )100には、6.5μm程度の深さを有するn型不純物層(不純物濃度:5×10 14 /cm 3 )からなる延長ドレイン領域101が形成されており、該延長ドレイン領域101は、半導体基板100の上に形成された絶縁膜109を貫通して延びるドレイン電極111に接続されている。 The m 3) 100, n-type impurity layer having a depth of about 6.5 [mu] m (impurity concentration: 5 × 10 14 / cm 3 ) extended drain region 101 is formed consisting of the extension drain region 101 It is connected to the drain electrode 111 extending through the insulating film 109 formed on the semiconductor substrate 100. 【0037】延長ドレイン領域101における3.5μ [0037] 3.5μ in the extended drain region 101
m程度の深さの領域には第1のp型埋め込み領域(不純物濃度:1.5×10 16 /cm 3 )103Aが形成されていると共に、延長ドレイン領域101における1.0 The area of m to a depth of about the first p-type buried region (impurity concentration: 1.5 × 10 16 / cm 3 ) 103A together are formed, 1.0 in the extended drain region 101
μm程度の深さの領域には第2のp型埋め込み領域(不純物濃度:2.5×10 16 /cm 3 )103Bが形成されている。 The region of μm depth of about a second p-type buried region (impurity concentration: 2.5 × 10 16 / cm 3 ) 103B is formed. 第1及び第2のp型埋め込み領域103A、 First and second p-type buried region 103A,
103Bは、半導体基板100と電気的に接続されているか又は浮遊状態である。 103B is or suspension are electrically connected to the semiconductor substrate 100. 【0038】延長ドレイン領域101における第1のp The first p in the extended drain region 101
型埋め込み領域103Aと第2のp型埋め込み領域10 -Type buried region 103A and the second p-type buried region 10
3Bとの間には、第1のn型高濃度不純物領域(不純物濃度:5.0×10 16 /cm 3 )104Aが形成されていると共に、延長ドレイン領域101における第2のp Between 3B, the first n-type high concentration impurity regions (impurity concentration: 5.0 × 10 16 / cm 3 ) 104A together is formed, the second p in the extended drain region 101
型埋め込み領域103Bの上側には第2のn型高濃度領域(不純物濃度:5.0×10 16 /cm 3 )104Bが形成されており、該第2のn型高濃度領域104Bは絶縁膜109を貫通して延びるドレイン電極111に接続されている。 Type on the upper side of the buried region 103B a second n-type high-concentration region (impurity concentration: 5.0 × 10 16 / cm 3 ) 104B is formed, n-type high-concentration region 104B of the second insulating film 109 is connected to the drain electrode 111 extending through the. これによって、延長ドレイン領域101はドレイン電極111と電気的に接続されている。 Thus, the extended drain region 101 is electrically connected to the drain electrode 111. 【0039】半導体基板100の表面部には、延長ドレイン領域101との間に間隔をおいて、n型領域からなるソース領域105と、p ++型領域からなる基板コンタクト領域106とが形成されており、基板コンタクト領域106は半導体基板100と電気的に接続されている。 [0039] surface of a semiconductor substrate 100, with an interval between the extended drain region 101, a source region 105 composed of n-type region, and the substrate contact region 106 made of p ++ type region is formed and which, substrate contact region 106 is a semiconductor substrate 100 and electrically connected. また、ソース領域105及び基板コンタクト領域1 The source region 105 and the substrate contact region 1
06は絶縁膜109を貫通して延びるソース電極112 The source electrode 112 06 extending through the insulating film 109
に接続されており、ソース領域105は半導体基板10 Is connected to the source region 105 is a semiconductor substrate 10
0と同電位に設定される。 0 and is set to the same potential. 【0040】半導体基板100の上における延長ドレイン領域101とソース領域105との間にはゲート絶縁膜107を介してゲート電極108が形成されており、 [0040] A gate electrode 108 is formed via a gate insulating film 107 is formed between the extended drain region 101 and source region 105 in the top of the semiconductor substrate 100,
半導体基板100におけるゲート電極108の下側の領域はチャネル領域として機能する。 The region below the gate electrode 108 in the semiconductor substrate 100 functions as a channel region. 【0041】ソース領域105及び基板コンタクト領域106は、半導体基板100よりも不純物濃度が高いp The source region 105 and the substrate contact region 106 is higher in impurity concentration than the semiconductor substrate 100 p
+型のアンチパンチスルー領域101に囲まれており、 + Type is surrounded by anti-punch-through area 101,
延長ドレイン領域101からチャネル領域側に拡がる空乏層はアンチパンチスルー領域101により拡がりが抑制されるので、パンチスルー現象は防止される。 Since a depletion layer from the extended drain region 101 extends into the channel region side spreads is inhibited by anti-punchthrough region 101, the punch-through phenomenon is prevented. 【0042】第1の実施形態に係る半導体装置によると、延長ドレイン領域101には、互いに間隔をおいて第1のp型埋め込み領域103Aと第2のp型埋め込み領域103Bとが形成されているため、延長ドレイン領域101に高電圧が印加されると、延長ドレイン領域1 [0042] According to the semiconductor device of the first embodiment, the extended drain region 101 is formed in the first p-type buried region 103A and the second p-type buried region 103B spaced apart from each other Therefore, when a high voltage is applied to the extended drain region 101, extended drain region 1
01と、半導体基板100、第1及び第2のp型埋め込み領域103A、103Bとは互いに逆バイアス状態になる。 01, the semiconductor substrate 100, first and second p-type buried region 103A, becomes reverse biased each other and 103B. このため、図1(b)において破線で示すように、第1のp型埋め込み領域103Aと延長ドレイン領域101及び第1のn型高濃度領域104Aとの各接合部、第2のp型埋め込み領域103Bと第1のn型高濃度領域104A及び第2のn型高濃度領域104Bとの各接合部、並びに延長ドレイン領域101と半導体基板100との接合部からそれぞれ空乏層が拡がると共に、 Therefore, as shown by the broken line in FIG. 1 (b), the respective joint between the first p-type buried region 103A and the extended drain region 101 and the first n-type high concentration region 104A, the buried second p-type each junction between region 103B and the first n-type high-concentration region 104A and the second n-type high-concentration region 104B, and the junction of the extended drain region 101 and the semiconductor substrate 100 with a depletion layer, respectively spreading,
各空乏層が互いに連続するため、空乏層の領域が大きくなるので、MOS型トランジスタの高耐圧化を図ることができる。 Because each depletion layer contiguous with each other, a depletion layer region is increased, it is possible to increase the withstand voltage of the MOS transistor. 【0043】また、第1の実施形態に係る半導体装置によると、ゲート電極108に電圧が印加されて、MOS [0043] According to the semiconductor device of the first embodiment, when a voltage is applied to the gate electrode 108, MOS
型トランジスタのチャネル領域が導通したときには、電流は、図1(c)において矢印で示すように、延長ドレイン領域101における、第1のn型高濃度領域104 Type when the channel region of the transistor is conductive, the current, as indicated by the arrows in FIG. 1 (c), the in extended drain region 101, a first n-type high-concentration region 104
A、第2のn型高濃度領域104B及び第1のp型埋め込み領域103Aの下側領域をそれぞれ流れる。 Through A, the lower region of the second n-type high-concentration region 104B and the first p-type buried region 103A, respectively. このように、従来の構造に比べて、電流の流れる経路が増加しているため、MOS型トランジスタのオン抵抗は大きく低減する。 Thus, as compared with the conventional structure, since the current flow paths is increased, the ON resistance of the MOS transistor is reduced greatly. 【0044】以上説明したように、第1の実施形態によると、n型の延長ドレイン領域101にp型の第1及び第2のp型埋め込み領域103A、103Bを設けたと共に、第1のp型埋め込み領域103Aと第2のp型埋め込み領域103Bとの間に第1のn型高濃度領域10 [0044] As described above, according to the first embodiment, first and second p-type buried region 103A of the p-type extended drain region 101 of n-type, with provided 103B, first p the first n-type high-concentration region 10 between the buried region 103A and the second p-type buried region 103B
4Aを設けたため、高耐圧特性を確保しつつ、オン抵抗を大きく低減することができる。 Because provided 4A, while ensuring a high breakdown voltage, it is possible to greatly reduce the ON resistance. 【0045】以下、第1の実施形態に係る半導体装置の製造方法について、図2(a)〜(c)及び図3 [0045] Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment, FIG. 2 (a) ~ (c) and 3
(a)、(b)を参照しながら説明する。 (A), it will be described with reference to (b). 【0046】まず、図2(a)に示すように、1×10 [0046] First, as shown in FIG. 2 (a), 1 × 10
14 〜3×10 14 cm 3程度の不純物濃度を有するp型の半導体基板100のドレイン形成領域にn型不純物例えばリンをイオン注入すると共に、半導体基板100のソース形成領域にp型不純物例えばボロンをイオン注入した後、n型及びp型の不純物を熱拡散させて、6.5μ The n-type impurity such as phosphorus into the drain forming region of a semiconductor substrate 100 of p-type having an impurity concentration of 14 approximately to 3 × 10 14 cm 3 with ion implantation, a p-type impurity such as boron into the source forming region of the semiconductor substrate 100 after ion implantation, and the n-type and p-type impurity is thermally diffused, 6.5Myu
m程度の深さを有するn型の延長ドレイン領域101 Extended drain region 101 of the n-type having a depth of about m
と、p +型のアンチパンチスルー領域102とを形成する。 When, to form the anti-punchthrough region 102 of p + -type. 【0047】次に、図2(b)に示すように、延長ドレイン領域101にp型不純物例えばボロンを2.0〜 Next, as shown in FIG. 2 (b), the p-type impurity such as boron in the extended drain region 101 2.0
3.0MeVの注入エネルギーでイオン注入して、3. And an implantation energy of 3.0 MeV, 3.
5μm程度の深さの領域に第1のp型埋め込み領域10 The first p-type buried region in the depth of the region of about 5 [mu] m 10
3Aを形成した後、延長ドレイン領域101にn型不純物例えばリンを2.0MeVの注入エネルギーでイオン注入して、第1のp型埋め込み領域103Aの上側に第1のn型高濃度領域104Aを形成する。 After forming the 3A, the extended drain region 101 by ion-implanting the n-type impurity such as phosphorus with an implantation energy of 2.0 MeV, the first n-type high concentration region 104A on the upper side of the first p-type buried region 103A Form. 【0048】次に、図2(c)に示すように、延長ドレイン領域101にp型不純物例えばボロンを1.0〜 Next, as shown in FIG. 2 (c), 1.0 to the p-type impurity such as boron in the extended drain region 101
1.5MeVの注入エネルギーでイオン注入して、1. And an implantation energy of 1.5 MeV, 1.
0μm程度の深さの領域に第2のp型埋め込み領域10 The second p-type buried region in the region of 0μm a depth of about 10
3Bを形成する。 3B to the formation. 次に、延長ドレイン領域101及びアンチパンチスルー領域102にn型不純物例えばリンを100keV程度の注入エネルギーでイオン注入して、 Next, the extended drain region 101 and the anti-punchthrough region 102 by ion-implanting the n-type impurity such as phosphorus at an implantation energy of about 100 keV,
第2のp型埋め込み領域103Bの上側に第2のn型高濃度不純物層104Bを形成すると共に、アンチパンチスルー領域102にソース領域105を形成する。 And forming a second n-type high concentration impurity layer 104B on the upper side of the second p-type buried region 103B, to form a source region 105 in the anti-punchthrough region 102. 次に、アンチパンチスルー領域102にp型不純物例えばボロンを4.5×10 12 /cm 2程度のドーズ量でイオン注入してp ++型の基板コンタクト領域106を形成する。 Then, by ion-implanting a p-type impurity such as boron at 4.5 × 10 12 / cm 2 dose of about forming the p ++ type substrate contact region 106 in the anti-punchthrough region 102. 【0049】次に、図3(a)に示すように、半導体基板100の上における、延長ドレイン領域101とソース領域105との間にゲート絶縁膜107を介してポリシリコン膜からなるゲート電極108を形成した後、半導体基板100の上に全面に亘って絶縁膜109を形成する。 Next, as shown in FIG. 3 (a), definitive on the semiconductor substrate 100, a gate electrode made of a polysilicon film via a gate insulating film 107 between the extended drain region 101 and source region 105 108 after forming, thereby forming an insulating film 109 on the entire surface of the semiconductor substrate 100. 【0050】次に、図3(b)に示すように、絶縁膜1 Next, as shown in FIG. 3 (b), the insulating film 1
09にコンタクトホール110を形成した後、絶縁膜1 After forming the contact hole 110 to 09, the insulating film 1
09の上にコンタクトホール110が埋め込まれるようにドレイン電極111及びソース電極112を形成すると、第1の実施形態に係る半導体装置が得られる。 When the drain electrode 111 and source electrode 112 such that the contact hole 110 on the 09 is embedded, the semiconductor device can be obtained according to the first embodiment. 【0051】(第2の実施形態)以下、本発明の第2の実施形態に係る半導体装置について図4(a)、(b) [0051] (Second Embodiment) Hereinafter, a semiconductor device according to a second embodiment of the present invention FIG. 4 (a), (b)
を参照しながら説明する。 It refers to the will be described. 尚、第2の実施形態は、第1 The second embodiment, first
の実施形態と比べて延長ドレイン領域101の構造が異なるのみであるから、以下においては、延長ドレイン領域101についてのみ説明する。 Since the structure of the extended drain region 101 as compared to the embodiment of the only difference is, a description will be given only to the extended drain region 101. 【0052】延長ドレイン領域101の深さは6.5μ [0052] The depth of the extended drain region 101 is 6.5μ
m程度であると共に、延長ドレイン領域101の底部の不純物濃度は5×10 14 cm 3程度であって、第1の実施形態と同様である。 together is about m, the impurity concentration of the bottom of the extended drain region 101 is of the order of 5 × 10 14 cm 3, is the same as the first embodiment. 【0053】第2の実施形態の特徴として、延長ドレイン領域101における6.0μm程度の深さの領域には第1のp型埋め込み領域(不純物濃度:1.0×10 16 [0053] As a feature of the second embodiment, in the region of 6.0μm order of depth in the extended drain region 101 first p-type buried region (impurity concentration: 1.0 × 10 16
/cm 3 )103Aが形成され、延長ドレイン領域10 / Cm 3) 103A is formed, extended drain region 10
1における4.0μm程度の深さの領域には第2のp型埋め込み領域(不純物濃度:1.5×10 16 /cm 3 The depth of the region of about 4.0μm in one second p-type buried region (impurity concentration: 1.5 × 10 16 / cm 3 )
103Bが形成され、延長ドレイン領域101における1.0μm程度の深さの領域には第3のp型埋め込み領域(不純物濃度:1.0×10 16 /cm 3 )103Cが形成されている。 103B is formed, the third p-type buried region in the region of 1.0μm order of depth in the extended drain region 101 (impurity concentration: 1.0 × 10 16 / cm 3 ) 103C are formed. これら第1、第2及び第3のp型埋め込み領域103A、103B、103Cは、半導体基板100と電気的に接続されているか又は浮遊状態である。 These first, second and third p-type buried region 103A, 103B, 103C are or suspension are electrically connected to the semiconductor substrate 100. 【0054】また、延長ドレイン領域101における第1のp型埋め込み領域103Aと第2のp型埋め込み領域103Bとの間には第1のn型高濃度領域(不純物濃度:5.0×10 16 /cm 3 )104Aが形成され、第2のp型埋め込み領域103Bと第3のp型埋め込み領域103Cとの間には第2のn型高濃度領域(不純物濃度:5.0×10 16 /cm 3 )104Bが形成され、延長ドレイン領域101における第3のp型埋め込み領域103Cの上側には第3のn型高濃度領域(不純物濃度:5.0×10 16 /cm 3 )104Cが形成されている。 [0054] The first n-type high-concentration region (impurity concentration between the first p-type buried region 103A and the second p-type buried region 103B in the extended drain region 101: 5.0 × 10 16 / cm 3) 104A is formed, the second p-type buried region 103B and a second n-type high-concentration region (impurity concentration between the third p-type buried region 103C: 5.0 × 10 16 / cm 3) 104B is formed, the upper side the third n-type high-concentration region (impurity concentration of the third p-type buried region 103C in the extended drain region 101: 5.0 × 10 16 / cm 3) 104C is formed It is. 第3のn型高濃度領域104Cは絶縁膜109を貫通して延びるドレイン電極111に接続されており、これによって、延長ドレイン領域101はドレイン電極1 The third n-type high-concentration region 104C is connected to the drain electrode 111 extending through the insulating film 109, thereby, extended drain region 101 is the drain electrode 1
11と電気的に接続されている。 11 and are electrically connected. 【0055】第2の実施形態の特徴は、第1の実施形態に比べて、p型埋め込み領域及びn型高濃度領域の数がそれぞれ多いと共に、第1及び第2のp型埋め込み領域103A、103Bに比べて不純物濃度が低い第3のp [0055] A feature of the second embodiment, as compared with the first embodiment, with the number of p-type buried region and the n-type high-concentration region is large, respectively, first and second p-type buried region 103A, low impurity concentration compared to the 103B third p
型埋め込み領域103Cが設けられていることである。 -Type buried region 103C is that are provided. 【0056】従って、延長ドレイン領域101に高電圧が印加されたときには、図4(b)において破線で示すように、空乏層が拡がる。 [0056] Therefore, when a high voltage is applied to the extended drain region 101, as indicated by a broken line in FIG. 4 (b), the depletion layer spreads. すなわち、第1、第2及び第3のn型高濃度領域104A、104B、104Cの各高さが小さいために空乏層が拡がり易い。 That is, first, second and third n-type high concentration region 104A, 104B, easily spread the depletion layer due to the small individual height of 104C. また、不純物濃度が低い第3のp型埋め込み領域103Cと、第2のn型高濃度領域104B及び第3のn型高濃度領域10 Further, a third p-type buried region 103C low impurity concentration, a second n-type high-concentration region 104B and the third n-type high concentration region 10
4Cとの各接合部から空乏層が拡がり易い。 Easily spread the depletion layer from the junction with the 4C. このため、 For this reason,
高耐圧特性を確保し易いので、高耐圧特性の確保とオン抵抗の低減との両立が図り易くなる。 Because it is easy to ensure high breakdown voltage characteristics, easily achieving the compatibility between the reduction of security and on-resistance of the high breakdown voltage characteristics. また、高耐圧特性を確保し易いので、第1、第2及び第3のn型高濃度領域104A、104B、104Cの不純物濃度を高くしてオン抵抗を低減することも容易である。 Moreover, because it is easy to ensure a high breakdown voltage, the first, second and third n-type high concentration region 104A, 104B, it is easy to reduce the high to the on-resistance impurity concentration of 104C. 【0057】従って、第2の実施形態によると、高耐圧特性の確保とオン抵抗の低減との両立を一層図り易くなる。 [0057] Therefore, according to the second embodiment, becomes even easier achieving compatibility between the reduction of security and on-resistance of the high breakdown voltage characteristics. 【0058】尚、図5に示すように、延長ドレイン領域101に、第1のp型埋め込み領域103A、第2のp [0058] Incidentally, as shown in FIG. 5, the extended drain region 101, a first p-type buried region 103A, second p
型埋め込み領域103B、第3のp型埋め込み領域10 -Type buried region 103B, a 3 p-type buried region 10 of the
3C及び第4のp型埋め込み領域103Dを設けると共に、第1のn型高濃度領域104A、第2のn型高濃度領域104B、第3のn型高濃度領域104C及び第4 Provided with a 3C and the fourth p-type buried region 103D, a first n-type high concentration region 104A, the second n-type high-concentration region 104B, a third n-type high-concentration region 104C and the fourth
のn型高濃度領域104Dを設けてもよい。 n-type high concentration region 104D of may be provided. 【0059】このようにすると、空乏層が一層拡がり易くなるので、高耐圧特性の確保とオン抵抗の低減との両立を一層図り易くなる。 [0059] Thus, the depletion layer is likely more spread becomes more easily achieving compatibility between the reduction of security and on-resistance of the high breakdown voltage characteristics. 【0060】 【発明の効果】本発明に係る半導体装置によると、ドレイン領域に、互いに間隔をおいて形成された第1導電型の第1の埋め込み領域及び第2の埋め込み領域と、第1 [0060] According to the semiconductor device according to the present invention, the drain region, the first and the buried region and the second buried region of the first conductivity type formed spaced apart from each other, the first
の埋め込み領域と第2の埋め込み領域との間に形成された第2導電型の高濃度不純物領域とを備えているため、 Due to the provision of the buried region and the high concentration impurity region of the second conductivity type formed between the second buried region,
高耐圧特性を確保しつつ、オン抵抗を確実に低減することができる。 While ensuring a high withstand voltage characteristics, it is possible to reliably reduce the on-resistance. 【0061】また、本発明に係る半導体装置の製造方法によると、高耐圧特性を確保しつつオン抵抗を低減できる本発明に係る半導体装置を確実に製造することができる。 [0061] According to the manufacturing method of a semiconductor device according to the present invention, it is possible to reliably manufacture a semiconductor device according to the present invention can reduce the on-resistance while ensuring high withstand voltage characteristics.

【図面の簡単な説明】 【図1】(a)は第1の実施形態に係る半導体装置の断面図であり、(b)は第1の実施形態に係る半導体装置において延長ドレイン領域に高電圧が印加されたときに空乏層が拡がる状態を示す断面図であり、(c)は第1 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) is a sectional view of a semiconductor device according to the first embodiment, (b) high voltage to the extended drain region in the semiconductor device according to a first embodiment There is a cross-sectional view showing a state in which a depletion layer spreads when applied, (c) the first
の実施形態に係る半導体装置においてゲート電極に電圧が印加されたときの電流経路を示す断面図である。 It is a sectional view showing a current path when a voltage is applied to the gate electrode in the exemplary semiconductor device according to the embodiment. 【図2】(a)〜(c)は第1の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 Figure 2 (a) ~ (c) are sectional views showing the steps in a manufacturing method of a semiconductor device according to the first embodiment. 【図3】(a)、(b)は第1の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 [3] (a), (b) is a sectional view showing the steps in a manufacturing method of a semiconductor device according to the first embodiment. 【図4】(a)は第2の実施形態に係る半導体装置の断面図であり、(b)は第2の実施形態に係る半導体装置において延長ドレイン領域に高電圧が印加されたときに空乏層が拡がる状態を示す断面図である。 4 (a) is a sectional view of a semiconductor device according to the second embodiment, (b) depleted when a high voltage is applied to the extended drain region in the semiconductor device according to a second embodiment layer is a cross-sectional view showing a state where the spreads. 【図5】第3の実施形態に係る半導体装置の断面図である。 5 is a cross-sectional view of a semiconductor device according to a third embodiment. 【図6】従来の半導体装置の断面図である。 6 is a cross-sectional view of a conventional semiconductor device. 【符号の説明】 100 半導体基板101 延長ドレイン領域102 アンチパンチスルー領域103A 第1のp型埋め込み領域103B 第2のp型埋め込み領域103C 第3のp型埋め込み領域103D 第4のp型埋め込み領域104A 第1のn型高濃度領域104B 第2のn型高濃度領域104C 第3のn型高濃度領域104D 第4のn型高濃度領域105 ソース領域106 基板コンタクト領域107 ゲート絶縁膜108 ゲート電極109 絶縁膜110 コンタクトホール111 ドレイン電極112 ソース電極 [Description of Reference Numerals] 100 semiconductor substrate 101 extended drain region 102 Anti punchthrough region 103A first p-type buried region 103B second p-type buried region 103C third p-type buried region 103D fourth p-type buried region 104A the first n-type high-concentration region 104B a second n-type high-concentration region 104C third n-type high-concentration region 104D fourth n-type high-concentration region 105 source region 106 substrate contact region 107 a gate insulating film 108 gate electrode 109 insulating film 110 a contact hole 111 drain electrode 112 source electrode

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】 第1導電型の半導体基板にそれぞれ形成された第2導電型のドレイン領域及びソース領域と、 前記ドレイン領域に上下に互いに間隔をおいて形成された第1導電型の不純物層からなり、下側に位置する第1 (57) formed at the Patent Claims 1. A drain region and the source region of the second conductivity type formed respectively on the first conductivity type semiconductor substrate, the intervals to each other in the up and down to the drain region It comprises a first conductivity type impurity layer that is first positioned on the lower side
    の埋め込み領域及び上側に位置する第2の埋め込み領域と、 前記ドレイン領域における前記第1の埋め込み領域と前記第2の埋め込み領域との間に形成されており、前記ド A second buried region located buried region and the upper are formed between the first buried region in the drain region and the second buried region, said de
    レイン領域の不純物濃度よりも高い不純物濃度を有する Having a higher impurity concentration than the impurity concentration of the rain region
    第2導電型の高濃度不純物領域と 前記ドレイン領域における前記第2の埋め込み領域の上 And the high concentration impurity region of the second conductivity type, on the second buried region in the drain region
    側に形成されており、前記ドレイン領域の不純物濃度よ Is formed on the side, the impurity concentration of the drain region
    りも高い不純物濃度を有する第2導電型の上方高濃度不 Remote upper high concentration of a second conductivity type having a higher impurity concentration not
    純物領域とを 備えていることを特徴とする半導体装置。 A semiconductor device characterized by comprising a net things region. 【請求項2】 前記ドレイン領域における前記第1の埋め込み領域の下側に、前記第1の埋め込み領域との間に間隔をおいて形成された第1導電型の不純物層からなる下方埋め込み領域と、 前記ドレイン領域における前記第1の埋め込み領域と前記下方埋め込み領域との間に形成されており、前記ドレ To 2. A lower side of the first buried region in the drain region, and the lower buried region of a first conductivity type impurity layer formed at intervals between the first buried region are formed between the first buried region and the lower buried region in said drain region, said drain
    イン領域の不純物濃度よりも高い不純物濃度を有する第2導電型の下方高濃度不純物領域とをさらに備えていることを特徴とする請求項1に記載の半導体装置。 The semiconductor device according to claim 1, characterized by further comprising a second conductive type lower high-concentration impurity region having an impurity concentration higher than that of the in-region. 【請求項3】 前記第1及び第2の埋め込み領域は、前記半導体基板と電気的に接続されていることを特徴とする請求項1に記載の半導体装置。 Wherein the first and second buried region, the semiconductor device according to claim 1, characterized in that connected the semiconductor substrate and electrically. 【請求項4】 第1導電型の半導体基板に第2導電型のドレイン領域及びソース領域をそれぞれ形成する工程と、 前記ドレイン領域に第1導電型の第1の埋め込み領域を形成する工程と、 前記ドレイン領域における前記第1の埋め込み領域の上側に、前記ドレイン領域の不純物濃度よりも高い不純物 A step wherein the first conductivity type semiconductor substrate a drain region and a source region of the second conductivity type are formed, respectively, forming a first buried region of the first conductivity type in the drain region, the upper side of the first buried region in the drain region, higher than the impurity concentration of the drain region impurity
    濃度を有する第2導電型の高濃度不純物領域を形成する工程と、 前記ドレイン領域における前記第2導電型の高濃度不純物領域の上側に第1導電型の第2の埋め込み領域を形成する工程と 前記ドレイン領域における前記第2の埋め込み領域の上 Forming a high concentration impurity region of the second conductivity type having a concentration, and forming a second buried region of the first conductivity type on the upper side of the high concentration impurity region of the second conductivity type in the drain region , on the second buried region in the drain region
    側に前記ドレイン領域の不純物濃度よりも高い不純物濃 Higher impurity concentrated than the impurity concentration of the drain region on the side
    度を有する第2導電型の上方高濃度不純物領域を形成す To form an upper high-concentration impurity region of the second conductivity type having a degree
    る工程と を備えていることを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by and a that step. 【請求項5】 前記第1の埋め込み領域及び前記第2の埋め込み領域は、それぞれイオン注入法により形成されることを特徴とする請求項4に記載の半導体装置の製造方法。 Wherein said first buried region and said second buried region, a method of manufacturing a semiconductor device according to claim 4, each being formed by ion implantation. 【請求項6】 前記高濃度不純物領域及び前記上方高濃 Wherein said high concentration impurity region and the upper level of concentrated
    度不純物領域はイオン注入法により形成されることを特徴とする請求項5に記載の半導体装置の製造方法。 Method for producing degrees impurity regions The semiconductor device according to claim 5, characterized in that it is formed by ion implantation.
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