JP2005085975A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing ON resistance, while keeping high breakdown voltage characteristics. <P>SOLUTION: On the surface part of a semiconductor substrate 1, an n-type source region 2, a p-type substrate contact region 7 adjacent to it and a p-type anti-punch-through region 9 surrounding them are formed. A gate electrode 10 is formed via a gate insulating film between the source region 2 and an extension drain region 3, and the gate electrode 10 and the surface of the semiconductor substrate 1 are covered with an insulating film 12. At a source-terminating part, a sectorial region 14 which does not form the extension drain region is formed so as to surround the source region 2, in order to prevent the concentration of an electric field and further a region 15 which does not inject a p-type embedded region is formed so as to be overlapped with the sector form region 14. In the sectorial regions 14 and 15, the angle of 90° or larger is formed respectively at bottom end parts 16 and 17, and furthermore, the corner part of the sectorial region 15 is formed with curvature. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a lateral semiconductor device capable of reducing on-resistance while having high breakdown voltage characteristics.

  A semiconductor device having a structure in which a first conductivity type region is embedded in a drain region has been proposed for the purpose of reducing on-resistance while having high breakdown voltage characteristics (see Patent Document 1). An example of this will be described with reference to FIGS.

  FIG. 3 is a plan view of a conventional semiconductor device as viewed from above. 4 is a cross-sectional structural view of the semiconductor device shown in FIG. 3, wherein (a) is a cross-sectional view in the CC ′ direction shown in FIG. 3, and (b) is a DD ′ direction shown in FIG. FIG.

  As shown in FIG. 4, the P-type semiconductor substrate 1 is formed with a source region 2 made of an N-type region and an extended drain region 3 made of an N-type region.

  An N-type high concentration region 4 is formed on the surface portion of the extended drain region 3, and a P-type buried region 5 is formed inside the extended drain region 3. The N-type high concentration region 4 is connected to the drain electrode 6, and the P-type buried region 5 is connected to the semiconductor substrate 1.

  A source region 2 and a P-type substrate contact region 7 adjacent to the source region 2 are formed on the surface portion of the semiconductor substrate 1. The source region 2 and the substrate contact region 7 are connected to the source electrode 8, whereby the source region 2 is set to the same potential as the semiconductor substrate 1. In addition, a P-type anti-punch through region 9 is formed in the semiconductor substrate 1 so as to surround the source region 2 and the substrate contact region 7.

  A gate electrode 10 is formed between the source region 2 and the extended drain region 3 in the upper part of the semiconductor substrate 1 via a gate insulating film, and a region under the gate electrode in the semiconductor substrate 1 is a channel region 11. Function. The surfaces of the gate electrode 10 and the semiconductor substrate 1 are covered with an insulating film 12.

  A feature of the conventional semiconductor device is that a P-type buried region 5 is provided inside an extended drain region 3 made of an N-type region.

  Since the P-type buried region 5 is set to a reference potential via the semiconductor substrate 1, when a high voltage is applied to the extended drain region 3, the extended drain region 3, the semiconductor substrate 1 and the P-type buried region 5 Becomes a reverse bias state. Therefore, the depletion layer expands from the junction of extended drain region 3 and semiconductor substrate 1 and extended drain region 3 and P-type buried region 5. By utilizing the withstand voltage characteristics of the depletion layer, it is possible to increase the breakdown voltage of the MOS transistor. When a voltage is applied to the gate electrode 10, the channel region 11 of the MOS transistor becomes conductive, so that the current mainly flows above the P-type buried region 5 inside the extended drain region 3 as indicated by the arrows in the figure. And flow downward.

  By the way, when the P-type region is formed in the surface portion of the extended drain region 3 by diffusion from the substrate surface as is normally done, the concentration of the N-type impurity in the surface portion having the highest impurity concentration in the extended drain region 3 is Since the resistance is significantly reduced, the on-resistance is increased.

  Therefore, in the above conventional example, the P-type buried region 5 is formed inside the extended drain region 3 to prevent the N-type impurity concentration from decreasing in the surface portion of the extended drain region 3.

Further, as shown in FIGS. 3 and 4B, in the source termination portion, in order to avoid electric field concentration due to a small curvature, impurities are semicircularly surrounded so as to surround the source end portion when the extended drain region is implanted. There is a special structure portion 13 that is not implanted but has a reduced concentration and is easily depleted.
US Pat. No. 5,258,636

  In the conventional example, two layers of the P-type buried region are buried, but by further increasing the number of buried regions, the concentration of the extended drain region can be increased and the on-resistance can be reduced.

  However, when the concentration of the extended drain region is increased in order to reduce the on-resistance, in the special structure portion 13 at the source termination portion, N-type impurities are easily diffused, and a portion where the P-type buried region does not exist in the extended drain region is wide. It becomes difficult to be depleted. In particular, when the extended drain region is semicircular, N-type impurities are diffused from both sides at the bottom end portion, and the concentration is further increased, so that the structure is more difficult to be depleted. Therefore, in the special structure portion 13 at the source termination portion, there is a problem that local breakdown occurs without being fully depleted and sufficient breakdown voltage is not generated.

  In order to solve the above problems, a semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a second conductivity type high concentration drain region and an extended drain region formed in the semiconductor substrate, and a second conductivity type. A semiconductor device comprising: a source region; a channel region provided between the source region and the extended drain region; and a gate electrode formed on the channel region via a gate insulating film, wherein the extension At least one first conductivity type buried region having a different depth from the surface in the drain region is provided, and the second conductivity type impurity of the extended drain region is provided above and below the first conductivity type buried region. A region is further provided.

  It is preferable that the extended drain region is not formed in a semicircular shape so as to surround the source region at the source termination portion.

  In the semicircular region where the extended drain region is not formed, the buried region is preferably formed at an angle of 90 ° or more at the semicircular bottom end.

  Further, in the semicircular region where the extended drain region is not formed, the buried region is preferably formed with a curvature at the semicircular bottom end.

  The buried region is preferably electrically connected to the semiconductor substrate.

  The buried region is preferably formed by ion implantation.

  In the present invention, the extended drain region is diffused from both sides and formed at a corner of the semicircular bottom end portion that is difficult to be depleted with an angle of 90 ° or more, and further with a curvature. However, it is possible to completely deplete the electric field strength and to reduce the on-resistance while maintaining a high breakdown voltage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention as viewed from above. 2 is a cross-sectional structural view of the semiconductor device shown in FIG. 1, wherein (a) is a cross-sectional view taken along the line AA ′ shown in FIG. 1, and (b) is a BB ′ direction shown in FIG. FIG.

  In FIG. 2, a P-type semiconductor substrate 1 includes a source region 2 composed of an N-type region, an extended drain region 3 composed of an N-type region, an N-type high concentration region 4 on the surface side of the extended drain region, and an extended drain region. One or more P-type buried regions 5 are respectively formed.

  The N-type high concentration region 4 is connected to the drain electrode 6, and the P-type buried region 5 is connected to the semiconductor substrate 1.

  A source region 2 and a P-type substrate contact region 7 adjacent to the source region 2 are formed on the surface portion of the semiconductor substrate 1. The source region 2 and the substrate contact region 7 are connected to the source electrode 8, whereby the source region 2 is set to the same potential as the semiconductor substrate 1. In addition, a P-type anti-punch through region 9 is formed in the semiconductor substrate 1 so as to surround the source region 2 and the substrate contact region 7.

  A gate electrode 10 is formed between the source region 2 and the extended drain region 3 in the upper part of the semiconductor substrate 1 via a gate insulating film, and a region below the gate electrode 10 in the semiconductor substrate 1 is a channel region 11. Function as. The surfaces of the gate electrode 10 and the semiconductor substrate 1 are covered with an insulating film 12.

In the above semiconductor device, the impurity concentration of the P-type semiconductor substrate 1 is set to about 1 × 10 ^{14 to} 3 × 10 ¹⁴ cm ³ , and the extended drain region 3 has a depth from the substrate surface of about 6 to 10 μm. The impurity concentration is about 1 × 10 ^{15 to} 7 × 10 ¹⁶ cm ³ .

The P-type buried region 5 is formed at a position where the depth from the surface of the semiconductor substrate 1 is about 1 to 4 μm, and the impurity concentration thereof is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ³ . The thickness of each region of the P-type buried region 5 is about 1 to 1.5 μm.

  Since the P-type buried region 5 is set to a reference potential via the semiconductor substrate 1, when a high voltage is applied to the extended drain region 3, the extended drain region 3, the semiconductor substrate 1 and the P-type buried region 5 Becomes a reverse bias state. For this reason, depletion layers expand from the junctions of the extended drain region 3 and the semiconductor substrate 1 and the extended drain region 3 and the P-type buried region 5 respectively.

  By utilizing the withstand voltage characteristics of the depletion layer, it is possible to increase the breakdown voltage of the MOS transistor. When a voltage is applied to the gate electrode 10, the channel region of the MOS transistor becomes conductive, so that the current mainly flows above the P-type buried region 5 inside the extended drain region 3 as indicated by the arrows in the figure. Flows downward.

  In the source termination portion, in order to prevent the concentration of the electric field, a fan-shaped region 14 that does not form an extended drain region is formed so as to surround the source region 2, and a P-type buried region is implanted so as to overlap the fan-shaped region 14. The area 15 not to be formed is formed in a sector shape.

  Further, in the fan-shaped region 14 and the sector-shaped region 15, the bottom end portions 16 and 17 are formed with an angle of 90 ° or more, respectively, and the corners of the sector-shaped region 15 are formed with a curvature.

  According to the present embodiment, at the source termination portion, the angle of the bottom end of the fan-shaped region where the extended drain region is not formed is 90 ° or more, and the corner of the region where the P-type buried region is not implanted is the first conductive region. By making the curvature only in the buried region of the mold, the diffusion length at the corners is shortened and the concentration is reduced, so that even when the concentration of the extended drain region is increased, the singular shape portion can be completely depleted. A semiconductor device capable of reducing on-resistance while maintaining a high breakdown voltage can be realized.

  Next, a method for manufacturing a semiconductor device according to the present invention will be described.

  First, phosphorus ions are implanted into the P-type semiconductor substrate 1 at an acceleration energy of about several hundred keV, thermal diffusion is performed under conditions suitable for forming a plurality of P-type buried regions 5, and an extended drain region is formed. 3 is formed.

  At this time, as shown in FIG. 1, in the source termination portion, a fan-shaped region 14 that does not form an extended drain region is formed so as to surround the source region 2 in order to prevent electric field concentration. It is formed with an angle of 90 ° or more.

  Next, boron ions are implanted at about several hundred keV to form the anti-punch through region 9.

  The P-type buried region 5 is formed by implanting boron ions while appropriately changing acceleration energy between 0.7 and 3.0 MeV. At this time, as shown in FIG. 1, a region 15 where the P-type buried region is not implanted is formed in a fan shape at the source terminal portion, but the bottom end portion 17 has an angle of 90 ° or more. The part is formed with a curvature.

  Thereafter, a gate insulating film is formed, polysilicon is further deposited, and then patterned to form the gate electrode 10. Subsequently, an N-type high concentration region 4, a source region 2, and a substrate contact region 7 are formed. Arsenic ions are implanted at about 50 keV for N-type high concentration region 4 and source region 2, and boron ions are implanted at about 50 keV for substrate contact region 7. Further, a contact window is formed, and a drain electrode 6 and a source electrode 8 are formed to obtain a high breakdown voltage N-channel MOSFET.

  The embodiment of the present invention shows a case where the P-type buried region 4 has two layers, but the number of P-type buried regions is not limited to two layers.

  The semiconductor device according to the present invention is useful as a semiconductor element for high voltage power.

The top view which looked at the semiconductor device in Embodiment 1 of this invention from the top FIG. 2 is a cross-sectional structure diagram of the semiconductor device according to the first embodiment of the present invention, (a) a cross-sectional view in the AA ′ direction shown in FIG. 1, and (b) in the BB ′ direction shown in FIG. Cross section Plan view of a conventional semiconductor device viewed from above 4A and 4B are cross-sectional structural views of a conventional semiconductor device, in which FIG. 3A is a cross-sectional view in the C-C ′ direction shown in FIG. 3, and FIG.

Explanation of symbols

1 P-type semiconductor substrate 2 N-type source region 3 N-type extended drain region 4 N-type high concentration region 5 P-type buried region 6 Drain electrode 7 P-type contact region 8 Source electrode 9 Anti-punch through region 10 Gate electrode 11 Channel region 12 Insulating film 13 Special structure 14 Fan-shaped region not forming N-type extended drain region 15 Fan-shaped region not forming N-type extended drain region and P-type buried region 16 Bottom edge of fan-shaped region not forming N-type extended drain region Part 17 Bottom end of fan-shaped region not forming N-type extended drain region and P-type buried region

Claims (6)

A first conductivity type semiconductor substrate, a second conductivity type high-concentration drain region and an extended drain region formed in the semiconductor substrate, a second conductivity type source region, and the source region and the extension drain region. A semiconductor device having a channel region provided therebetween and a gate electrode formed on the channel region via a gate insulating film,
The extended drain region includes at least one first conductivity type buried region having a different depth from the surface, and the second conductivity type of the extended drain region is provided above and below the first conductivity type buried region. The semiconductor device further comprising the impurity region. The semiconductor device according to claim 1, wherein the extended drain region is not formed in a semicircular shape so as to surround the source region at the source termination portion. 3. The semiconductor device according to claim 2, wherein in the semicircular region where the extended drain region is not formed, the buried region is formed with an angle of 90 [deg.] Or more at the semicircular bottom end. 4. The semiconductor device according to claim 3, wherein in the semicircular region where the extended drain region is not formed, the buried region is formed with a curvature at the semicircular bottom end. The semiconductor device according to claim 1, wherein the embedded region is electrically connected to the semiconductor substrate. 6. The semiconductor device according to claim 1, wherein the buried region is formed by ion implantation.

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