JP2009194127A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical power MOSFET that uses an SiC substrate for improved switching characteristics. <P>SOLUTION: A semiconductor device 100 comprises a DMOSFET region 50 and a SBD region 55 formed on a drift epi layer 20 on a semiconductor substrate 10. The DMOSFET region 50 comprises a well region 22 formed in the drift epi layer 20 as well as a source region 24 and a contact region 26 formed on the well region 22. A silicide layer 28 is formed on the source region 24 and the contact region 26. The SBD region 55 comprises the well region 22 formed on the drift epi layer 20. On the drift epi layer 20 and the well region 22 in the SBD region 55, a metal layer 40 constituting a Schottky electrode 42 is formed. The metal layer 40 extends from the Schottky electrode 42 to contact the silicide layer 28. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a power semiconductor device made of silicon carbide used for high breakdown voltage and large current.

  A power semiconductor device is a semiconductor element that is used for a purpose of flowing a large current with a high breakdown voltage, and is desired to have a low loss. Conventionally, power semiconductor devices using silicon (Si) substrates have been mainstream, but in recent years, power semiconductor devices using silicon carbide (SiC) substrates have attracted attention and are being developed (for example, patent documents). 1-4).

Since silicon carbide (SiC) has a dielectric breakdown voltage that is an order of magnitude higher than that of silicon (Si), the reverse breakdown voltage can be maintained even if the depletion layer at the pn junction or the Schottky junction is thinned. It has the characteristics. Therefore, when SiC is used, the thickness of the device can be reduced and the doping concentration can be increased. Therefore, SiC forms a power semiconductor device with low on-resistance, high withstand voltage, and low loss. Is expected as a material.
JP-A-10-308510 Japanese Patent No. 3773489 Japanese Patent No. 3784393 Japanese Patent No. 352796 JP-A-9-55507

  Patent Document 5 discloses a vertical power MOSFET using a Si substrate. Specifically, a semiconductor device in which a MOSFET element and a Schottky barrier diode (SBD) element are formed on one chip on the same substrate is disclosed. Has been. Patent Document 5 describes that, according to this configuration, a forward current flows through a built-in diode in a vertical power MOSFET element, and the reverse recovery time during the switching operation can be shortened.

  However, the inventor of the present application manufactured a structure in which a MOSFET element and an SBD element are formed on a single substrate by a vertical power MOSFET using an SiC substrate, and an experiment was conducted on the structure, and the SBD characteristics were poor and normal products were obtained. It turns out that it is not. Specifically, in a prototype in which an ohmic electrode and a Schottky electrode are formed at the same time, one of the prototypes can ensure a reverse breakdown voltage, but the forward characteristics (ideal factor) are poor. The reverse breakdown voltage could not be secured.

  Under such circumstances, the inventor of the present application has intensively studied to improve the switching characteristics by incorporating the SBD element in the vertical power MOSFET using the SiC substrate, and as a result, realizes a structure that exhibits such an effect. I was able to.

  The present invention has been made in view of such a point, and a main object thereof is to provide a vertical power MOSFET using a SiC substrate capable of improving switching characteristics and a manufacturing method thereof.

  In the method for manufacturing a semiconductor device according to the present invention, a first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the semiconductor substrate is formed on the main surface of the first conductivity type semiconductor substrate made of silicon carbide. (B) defining a DMOSFET region for forming a DMOSFET element and an SBD region for forming a Schottky barrier diode element at a position different from the DMOSFET region in the silicon carbide epitaxial layer; (C) forming a second conductivity type well region in the DMOSFET region and the SBD region in the silicon carbide epitaxial layer, and forming a first conductivity type in a part of the well region in the DMOSFET region. Forming a source region and a second conductivity type contact region (d); A step (e) of forming a channel epitaxial layer made of silicon carbide on the silicon nitride epitaxial layer, the well region, and the source region; and a step of forming a gate oxide film on the channel epitaxial layer (f) ), Forming a gate electrode on the gate oxide film (g), forming a silicide layer on the contact region and the source region in the DMOSFET region (h), and the DMOSFET region Forming an insulating film that covers the gate electrode and exposes at least a part of the silicide layer, and covers a part of the well region and exposes the silicon carbide epitaxial layer in the SBD region. (I) and the silicide in the DMOSFET region while covering the insulating film When, by forming a metal layer in contact with said silicon carbide epitaxial layer and the well region of the SBD region, and a step (j) for forming the Schottky electrode on the SBD region.

  In a preferred embodiment, the method further includes a step of forming a wiring layer made of aluminum on the metal layer and a step of forming an electrode on the back surface of the semiconductor substrate.

  In a preferred embodiment, the step (h) includes forming an insulating layer having an opening exposing the contact region in the DMOSFET region on the main surface of the semiconductor substrate, the contact region, and the contact region Forming a metal layer made of a metal material for ohmic electrodes on the insulating layer; performing a heat treatment after the formation of the metal layer; and removing the insulating layer to lift off the metal layer. And removing at a step.

  In a preferred embodiment, the metal layer in the step (j) is made of a material selected from the group consisting of Ti, Ta, and nitrides thereof.

  A semiconductor device according to the present invention has a main surface and a back surface opposite to the main surface, and is formed on a first conductivity type semiconductor substrate made of silicon carbide, and the main surface of the semiconductor substrate. A first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the substrate; a DMOSFET region formed in the silicon carbide epitaxial layer to define a DMOSFET element; and a Schottky barrier diode formed in the silicon carbide epitaxial layer. An SBD region defining an element, wherein the DMOSFET region includes a second conductivity type well region formed in the silicon carbide epitaxial layer, a first conductivity type source region formed in the well region, A contact region of a second conductivity type formed in the well region, the source region and the contact region Includes a silicide layer, and the SBD region includes a second conductivity type well region formed in the silicon carbide epitaxial layer, and the silicon carbide epitaxial layer and the well region in the SBD region. A metal layer constituting a Schottky electrode is formed on the silicide layer, and the metal layer extends from the Schottky electrode, and the silicide layer on the contact region in the DMOSFET region Touching.

  In a preferred embodiment, a wiring layer made of aluminum is formed on the metal layer.

  In a preferred embodiment, the metal layer is made of a material selected from the group consisting of Ti, Ta, and nitrides thereof.

  The metal layer is preferably made of Ti nitride.

  In a preferred embodiment, a channel epitaxial layer made of silicon carbide is formed on the silicon carbide epitaxial layer, the well region, and the source region in the DMOSFET region, and the channel epitaxial layer includes the channel epitaxial layer. A portion located on the well region functions as a channel region, and a gate oxide film is formed on the channel epitaxial layer.

  In a preferred embodiment, upper surfaces of the silicon carbide epitaxial layer, the well region, and the source region are located on the same plane.

  According to the present invention, since the Schottky electrode is formed in the SBD region by forming the metal layer in contact with the silicide layer in the DMOSFET region and the silicon carbide epitaxial layer in the SBD region, the switching characteristics are improved by the SBD element. Can be planned. In addition, since the metal layer having the same structure as the Schottky electrode material is formed on the silicide layer in the contact region, the metal layer becomes a barrier metal, and therefore, the metal layer in contact with the contact region via the silicide layer. Even when a wiring layer made of aluminum is formed thereon, diffusion of aluminum can be suppressed by the barrier metal. This also suppresses an increase in ohmic contact resistance and a decrease in gate oxide film reliability, leading to improved reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.

  FIG. 1 schematically shows a cross-sectional configuration of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this embodiment shown in FIG. 1 is a vertical power MOSFET using a SiC substrate. Specifically, a DMOSFET element and an SBD element are formed on the SiC substrate. “DMOSFET” is an abbreviation for double diffused metal oxide semiconductor (MOS), and “SBD” is an abbreviation for Schottky barrier diode.

  The semiconductor device 100 of this embodiment is formed on a first conductivity type semiconductor substrate (SiC substrate) 10 made of silicon carbide (SiC) and a main surface 10 a of the semiconductor substrate 10, and has a dopant concentration lower than that of the semiconductor substrate 10. And a first conductivity type silicon carbide epitaxial layer 20 having the following structure. In the silicon carbide epitaxial layer 20, a DMOSFET region 50 that defines a DMOSFET element and an SBD region 55 that defines an SBD element are defined.

  The DMOSFET region 50 includes a second conductivity type well region 22 formed in the silicon carbide epitaxial layer 20, a first conductivity type source region 24 formed in the well region 22, and a first conductivity type formed in the well region 22. A contact region 26 of two conductivity type is provided. A silicide layer 28 is formed on the contact region 26 and the source region 24 of the present embodiment. A method for forming the silicide layer 28 will be described later. Further, the upper surfaces of the drift epi layer 20, the well region 22, and the source region 24 in the DMOSFET region 50 of the present embodiment are located on the same plane.

  The SBD region 55 is provided with a second conductivity type well region 22 formed in the silicon carbide epitaxial layer 20. On the silicon carbide epitaxial layer 20 in the SBD region 55, the metal layer 40 constituting the Schottky electrode 42 is formed. The metal layer 40 is made of, for example, titanium (Ti) or tantalum (Ta). The metal layer 40 extends from the Schottky electrode 42 and is in contact with the silicide layer 28 formed on the source region 24 and the contact region 26 in the DMOSFET region 50.

  Furthermore, in the configuration of the present embodiment, a channel epitaxial layer 30 made of silicon carbide is formed on the silicon carbide epitaxial layer 20, the well region 22, and the source region 24 in the DMOSFET region 50. Further, a portion of the channel epitaxial layer 30 located on the well region 22 functions as the channel region 35. In the present embodiment, the “epitaxial layer” may be referred to as “epi layer”, the silicon carbide epitaxial layer 20 is referred to as “drift epi layer 20”, and the channel epitaxial layer 30 is referred to as “channel epi layer 30”. It may be called.

  A gate oxide film 32 is formed on the channel epitaxial layer 30. The gate oxide film 32 is, for example, a silicon oxide film. In addition, a gate electrode 34 is formed on the gate oxide film 32. The gate electrode 34 is made of, for example, polysilicon.

  An insulating film 36 is formed on the gate electrode 34. The insulating film 36 is, for example, silicon oxide. In the configuration of this embodiment, the insulating film 36 covers the gate electrode 34 in the DMOSFET region 50, and the insulating film 36 has an opening (contact hole) 37 exposing at least a part of the silicide layer 28. Is formed. A metal layer 40 extending from an electrode (barrier metal) 41 in contact with the silicide layer 28 is formed on the insulating film 36.

  Further, the insulating film 36 is also formed on a part of the well region 22 in the SBD region 55. Specifically, an opening (contact hole) 43 exposing a part of the well region 22 in the SBD region 55 and the drift epitaxial layer 20 surrounded by the well region 22 is formed in the insulating film 36. Then, the metal layer 40 formed in the DMOSFET region 50 extends to the Schottky electrode 42 through the insulating film 36 in the SBD region 55.

  A wiring layer 44 is formed on the metal layer 40, and the wiring layer 44 of this embodiment is made of aluminum. In the example shown in FIG. 1, the aluminum wiring layer 44 located in the contact hole 37 in the DMOSFET region 50 is connected to the silicide layer 28 through a part of the metal layer 40 (electrode 41). On the other hand, the aluminum wiring layer 44 located in the contact hole 43 in the SBD region 55 is connected to the well region 22 and the drift epitaxial layer 20 through a part of the metal layer 40 (Schottky electrode 42).

  An electrode (drain electrode) 80 is formed on the back surface 10 b of the semiconductor substrate 10. The electrode (back electrode) 60 of the present embodiment has a laminated structure of Ti layer 82 / Ni layer 84 / Ag layer 86 in order from the substrate 10 side, and also the Ti layer 82 of the electrode 80 and the semiconductor substrate 10. A backside silicide layer 81 is formed between the backside 10b.

In the example of the present embodiment, the first conductivity type is n-type. In the example illustrated in FIG. 1, the semiconductor substrate 10 is an n-type SiC semiconductor substrate (n ⁺ SiC substrate), and the drift epi layer 20 is n ^−. It is a SiC layer. The well region 22 is a p ⁻ layer, and the source region 24 is an n ⁺ layer. The contact region is a p ⁺ layer. Note that “+”, “−”, and the like are symbols representing the relative dopant concentration of n-type or p-type.

The channel epi layer 30 of the present embodiment is an insulating layer (or substantially an insulating layer) and may be referred to as an “i layer” or a “channel epi i layer”. However, the channel epi layer 30 may be a low-concentration first conductivity type (n ⁻ ) layer, and the channel epi layer 30 may have a concentration change in the depth direction. .

  The semiconductor device 100 of this embodiment is a power semiconductor device made of SiC, and is preferably used for high withstand voltage and large current. The conditions of the configuration of the present embodiment will be described as an example as follows.

The n ⁺ SiC substrate 10 is made of hexagonal silicon carbide. The thickness of the n ⁺ SiC substrate 10 is, for example, 250 to 350 μm, and the concentration of the n ⁺ SiC substrate 10 is, for example, 8E18 cm ⁻³ . Here, 8E18 cm− ³ means 8 × 10 ¹⁸ cm ⁻³ , and hereinafter, in this specification, the same notation may be given for the concentration. In the case of the n ^- SiC substrate 10, a substrate made of cubic silicon carbide can also be used.

  Drift epi layer 20 is an SiC layer formed epitaxially on main surface 10 a of SiC substrate 10. The thickness of the drift epi layer 20 is, for example, 4 to 15 μm, and the concentration thereof is, for example, 5E15 cm −3. An additional SiC epi layer (for example, an SiC epi layer having a concentration of 6E16 cm −3) may be provided between the n + SiC substrate 10 and the drift epi layer 20.

The thickness of the well region 22 (that is, the depth from the upper surface of the drift epi layer 20) is, for example, 0.5 to 1.0 μm, and the concentration of the well region 22 is, for example, 1.5E18 cm −3. . The thickness of the source region 24 (that is, the depth from the upper surface of the drift epi layer 20) is, for example, 0.25 μm, and the concentration of the source region 24 is, for example, 5E19 cm −3. The thickness of the contact layer (p ⁺ layer) 26 is, for example, 0.3 μm, and the concentration thereof is, for example, 2E20 cm−3. Note that a JFET region is defined in the drift epitaxial layer 20 between the well regions 22 in the DMOSFET region 50, and the length (width) of the JFET region is, for example, 3 μm.

The channel epi layer 30 is an SiC layer epitaxially formed on the drift epi layer 20, and the thickness of the channel epi layer 30 is, for example, 30 nm to 150 nm. The length (width) of the channel region 35 is, for example, 0.5 μm. The gate oxide film 32 is made of SiO ₂ (silicon oxide) and has a thickness of 70 nm, for example. The gate electrode 34 is made of poly-Si (polysilicon) and has a thickness of, for example, 500 nm.

  Furthermore, as described above, in the configuration of this embodiment, the silicide layer 28 is formed. Specifically, the source electrode is made of an alloy of Ti (titanium) and Si (silicon), and the thickness thereof is For example, 50 nm. The drain electrode (silicide layer 81 of the back electrode) is also made of an alloy of Ti (titanium) and Si (silicon), and the thickness thereof is, for example, 100 nm. Note that Ni and Ag or Ni and Au may be deposited on the drain electrode in order to facilitate soldering when the SiC chip is mounted on the plastic package.

  According to the configuration of the semiconductor device 100 of the present embodiment, the DMOSFET region 50 and the SBD region 55 are formed in the semiconductor substrate 10, and the metal that contacts the silicide layer 28 of the DMOSFET region 50 and the drift epi layer 20 of the SBD region 55. Since the layer 40 is formed and the Schottky electrode 42 is formed in the SBD region 55 by the metal layer 40, switching characteristics can be improved by the SBD element formed in the SBD region 55.

  A silicide layer 28 is formed in the source region 24 and the contact region 26. Therefore, even when the wiring layer 44 made of aluminum is formed on the metal layer 40 in contact with the source region 24 and the contact region 26 through the silicide layer 28, the metal layer 40 acts as a barrier metal, so It becomes possible to suppress diffusion. That is, according to the configuration of the present embodiment, the phenomenon in which aluminum diffuses into the polysilicon constituting the gate electrode 34 and reaches the gate oxide film 32 is suppressed from the diffusion of aluminum by the metal layer 40. As a result, the ohmic characteristics of the contact region 26 and the source region 24 and the reliability of the gate oxide film 32 can be improved.

  Next, the operation of the semiconductor device 100 of this embodiment will be described.

  First, the operation of the vertical MOSFET will be described. A voltage of several hundred volts to several kilovolts is applied to the source electrode 24 through the external resistor (not shown) and 0 V to the drain electrode 80. In an off state in which a voltage (for example, 0 V) equal to or lower than a threshold value (Vth) is applied to the gate electrode 34, a depletion layer extends between the well region 22 and the drift, and in the JFET region, a depletion layer extending from both sides of the well region 22 is present. It is connected.

  Next, when a voltage (for example, 20 V) higher than the threshold value (Vth) is applied to the gate electrode, electrons flow into the channel epilayer 30 of the channel region 35 through the gate insulating film 32. At this time, since electrons accumulated in the depletion layer formed between the well region 22 and the drift (drift epi layer 20) are also used, the potential of the well region 22 approaches the source potential, By reducing the size, a current path in the JFET region is formed and turned on. At this time, the external resistance is selected so that the drain voltage becomes about 1 to 2 V due to the voltage drop of the external resistance.

  In the conventional configuration, when the SBD element is not mixedly mounted, the reverse recovery time during the switching operation is long, and good switching characteristics cannot be obtained. In addition, when the SBD element and the MOSFET element are mixedly mounted on the same substrate, the forward characteristics (ideal factors, etc.) and the reverse breakdown voltage deteriorate when the ohmic electrode and the aluminum electrode are formed at the same time. It is difficult to obtain.

  On the other hand, in the case of the configuration 100 of the present embodiment, by realizing an SBD element with good Schottky characteristics on the same substrate as the MOSFET element, a reverse recovery time during a switching operation is caused by flowing a forward direction through the SBD. Therefore, the switching characteristics can be improved.

  Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to FIGS. 2 (a) to 4 (b). FIG. 2A to FIG. 4B are process cross-sectional views for explaining the manufacturing method of the present embodiment.

First, an n-type 4H—SiC (0001) substrate is prepared as the n ⁺ SiC substrate 10. This substrate is, for example, a substrate having an n-type doping concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ that is 8 ° or 4 ° offcut in the <11-20> direction.

Next, as illustrated in FIG. 2A, an n ⁻ drift epi layer 20 is formed on the main surface 10 a of the n ⁺ SiC substrate 10 by epitaxial growth. Epitaxial conditions are thermal CVD using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. Thus, a thickness of 10 μm or more is deposited at a concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ .

Next, a predetermined mask (for example, a mask made of an oxide film) for defining the well region 22 is provided on the n ⁻ drift epi layer 20 and, for example, Al ⁺ is ion-implanted to thereby form the n ⁻ drift epi layer. A well region (p ⁻ ) 22 having a predetermined depth is formed on the surface of 20. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 350 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the well region 22 is, for example, 0.5 to 1.0 μm. The surface portion of the n ⁻ drift epi layer 20 defined by the well region 22 becomes a JFET region. The width of the JFET region of this embodiment is 3 μm, for example.

Next, a predetermined mask for defining the source region 24 in the DMOSFET region 50 is provided, and N ⁺ (nitrogen ions) or P ⁺ (phosphorus ions) are ion-implanted into the surface of the well region (p ⁻ ) 22. A source region (n ⁺⁺ ) 24 is formed. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 90 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the source region 24 is, for example, 0.25 μm.

Next, a predetermined mask for defining the contact region 26 in the DMOSFET region 50 is provided, and Al ⁺ (aluminum ions) or B ⁺ (boron ions) are ion-implanted into the surface of the well region (p ⁻ ) 22. Then, a contact region (p ⁺ layer) 26 is formed. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 150 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the contact region (p ⁺ layer) 26 is deeper than the depth of the source region (n ^{+ +} ) 24, for example, 0.3 μm.

  Next, ion implantation is performed by activating annealing the substrate 10 (more precisely, the substrate 10 on which each layer (20, 22, 24, 26) is formed) at a temperature of 1000 ° C. or more, here, about 1700 ° C. Activate the seed.

Next, the channel epitaxial layer 30 in the DMOSFET region 50 is formed by epitaxial growth. The channel epi layer 30 in the present embodiment is an epi i layer made of SiC, and the epitaxial growth conditions thereof are, for example, source gases such as silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a carrier gas. By performing thermal CVD using nitrogen (N ₂ ) gas as a dopant gas with hydrogen (H ₂ ), the concentration is 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ and the thickness is 30 to 30 Deposit 150 nm.

Note that nitrogen (N ₂ ) gas may be introduced during the epitaxial growth so that a part of the channel epitaxial layer has a high concentration. Further, the surface of the epitaxially grown channel epi layer 30 may be subjected to CMP (Chemical Mechanical Polishing). However, the execution of CMP is optional, and it is not necessary to perform CMP.

Next, the channel epi layer 30 is patterned by dry etching through a predetermined mask. Thereafter, a gate oxide film (SiO ₂ ) 32 is formed on the patterned channel epi layer 30. The thickness of the gate oxide film is, for example, 70 nm.

  Next, a gate electrode (poly-Si) 34 is formed on the gate oxide film 32 by using low pressure CVD. Thereafter, the gate electrode 34 is etched and patterned using a predetermined mask. In this way, the structure shown in FIG. 2A is obtained. That is, the structure shown in FIG. 2A is completed through the injection layer formation and the gate formation step. Thereafter, a wiring forming process is performed as shown in FIG.

  First, as shown in FIG. 2B, an opening 61 that exposes the source contact region (24, 26) in the DMOSFET region 50 on the substrate 10 (more precisely, on the drift epi layer 20). An insulating layer 60 having the following is formed. The insulating layer 60 is a layer that becomes a mask for silicide. In this embodiment, since the insulating layer 60 is formed on the entire substrate 10, it is formed not only in the DMOSFET region 50 but also in the SBD region 55.

  The insulating layer 60 is produced, for example, by depositing a p-SiN film about 100 to 200 nm and then forming an opening 61 in the p-SiN film. The opening 61 is formed by making a mask having an opening defining the opening 61 by lithography and then dry etching the p-SiN film by RIE or the like.

  Next, as shown in FIG. 2C, a metal material for the ohmic electrode is deposited on the substrate 10 to form a metal layer 62. By this deposition, the metal layer 62 is formed on the source / contact regions (24, 26) located on the bottom surface in the opening 61. The metal material for the ohmic electrode is made of, for example, Ni or Ti, and the metal layer 62 can be formed by, for example, EB vapor deposition or sputtering. The thickness of the metal layer 62 is, for example, about 100 nm.

Next, as shown in FIG. 3A, the silicide layer 28 is formed on the source region / contact region (24, 26) by performing heat treatment after the formation of the metal layer 62. The heat treatment for forming the silicide layer 28 is performed at 850 ° C. to 1000 ° C. in an Ar or N ₂ atmosphere.

  Next, as shown in FIG. 3B, by removing the insulating layer 60, the metal layer 62 located in a region other than the silicide layer 28 is removed by lift-off. That is, by this lift-off, “unreacted” metal (compound) located in a region other than the silicide layer 28 is removed.

In the present embodiment, a silicide layer (backside silicide layer) 81 is formed on the back surface 10b of the substrate 10 in order to realize ohmic contact on the back surface. The formation of the backside silicide layer 81 is a metal on the back surface 10b of the substrate 10 (e.g., Ni or Ti) after depositing is performed in an Ar or _{N 2} atmosphere at 850 ° C. to 1000 ° C..

  Next, as shown in FIG. 4A, an insulating film (interlayer insulation) in which an opening 61 exposing the source contact region (24, 26) and an opening 71 exposing the Schottky contact region is formed. Film) 36 is formed. The interlayer insulating film 36 is made of, for example, a silicon oxide film (including PSG, BPSG, etc. here). The interlayer insulating film 36 is formed by depositing a silicon oxide film by CVD or the like, and then forming a mask that defines the opening 61 of the DMOSFET region 50 and the opening 71 of the SBD region 55 by lithography, and then silicon by RIE or the like. This is performed by dry etching the oxide film.

  Next, as shown in FIG. 4B, a metal layer 40 is formed. The metal layer 40 constitutes a barrier metal layer 41 in the SBD region 55 and a Schottky electrode 42 in the DMOSFET region 50, and the barrier metal layer 41 made of the metal layer 40 is in contact with the silicide layer 28. Further, the metal layer 40 of this embodiment extends from the Schottky electrode 42, passes over the interlayer insulating film 36, and is connected to the barrier metal layer 41.

  The metal layer 40 is formed by EB vapor deposition or sputtering (for example, reactive sputtering) with a metal material (for example, Ti, Ta, or a nitride thereof) that becomes the barrier metal (41) and the Schottky metal (42). After depositing 100 to 200 nm, patterning is performed. This patterning is performed by wet or dry etching using a predetermined mask so as to leave the barrier metal layer 41 and the Schottky electrode 42 including the overlapping portion. This predetermined mask is formed by lithography. Further, after the formation of the metal layer 40, it is also preferable to perform high-temperature heat treatment at 300 to 500 ° C. in order to improve shot characteristics and nitride the surface of the barrier metal.

  Thereafter, aluminum is deposited on the surface of the substrate 10, more precisely on the structure shown in FIG. 4B, and the aluminum wiring layer 44 is formed by patterning the aluminum. 1 is obtained. The aluminum constituting the Al wiring layer 44 is deposited by EB vapor deposition or sputtering. The thickness of the Al wiring layer 44 is about 4 μm, for example. Patterning of the deposited aluminum is performed by forming a mask defining the Al wiring layer 44 by lithography and then performing wet etching or dry etching through the mask.

  As shown in FIG. 1, the Al wiring layer 44 is finally formed on the surface of the substrate 10 (specifically, on the structure shown in FIG. 4B). The metal layer 40 that connects the silicide layer 28 located on the contact regions (24, 26) and the Schottky electrode 42 may be at least partially removed on the interlayer insulating film 36. That is, even if the metal layer 40 is cut off on the interlayer insulating film 36, electrical connection between the silicide layer 28 and the Schottky electrode 42 can be ensured by the Al wiring layer 44.

  However, if a metal layer (for example, a Ti layer) 40 exists between the interlayer insulating film 36 and the Al wiring layer 44, the adhesion between the interlayer insulating film 36 and the Al wiring layer 44 is improved by the metal layer 40. Can be made. Further, by improving the adhesion, it is possible to suppress the disconnection of the Al wiring layer 44, and as a result, effects such as an improvement in manufacturing yield can be obtained.

  Thereafter, a surface protective film (not shown) can be formed on the structure shown in FIG. The surface protective film can be formed, for example, by depositing p-SiN. Note that after the surface protective film is formed, a mask that defines the pad portion is formed by lithography, and then the surface protective film is removed by RIE using the mask to expose the pad portion to the outside.

  Further, a back electrode (drain electrode) 80 is formed on the back surface 10b of the substrate 10 (specifically, on the bottom surface of the back surface silicide layer). The back electrode 80 can have a laminated structure such as a Ti layer 82 / Ni layer 84 / Ag layer 86, for example.

  Next, experimental results performed by the present inventor will be described with reference to FIGS. 5 (a) and 5 (b). The graphs shown in FIGS. 5A and 5B are the evaluation results of the JV characteristics (current-voltage characteristics) of the SBD element in the semiconductor device 100 of the present embodiment. FIG. The direction JV characteristic is shown, while FIG. 5B shows the JV characteristic in the reverse direction. “Ti” and “TiN” in FIG. 5 indicate examples in which the Schottky electrode 42 which is a part of the metal layer 40 is made of titanium and titanium nitride, respectively. Note that “Al” in FIG. 5 is an example (comparative example) in which the metal layer 40 is not formed and the Al wiring layer 44 directly forms the Schottky electrode 42.

  Further, the results of other conditions (film thickness) and characteristics are as follows.

  Jon @ 2V represents the on-current density when the forward voltage is 2V, Ron represents the on-resistance, and was calculated from the slope of the J-V characteristic (Ron = 1 / S * ΔV / ΔJ * S: area).

  Φb is a Schottky barrier, n is an ideal factor, and both were calculated from the J-V characteristics by data analysis based on theoretical equations. Vbr indicates reverse breakdown voltage.

(1) “TiN”: film thickness [nm] = 200, Jon @ 2V [A / cm ² ] = 496, Ron [mΩcm ² ] = 2.30, φb [eV] = 1.22, n = 1. 1, Vbr (V) = − 1474
(2) “Ti”: film thickness [nm] = 200, Jon @ 2V [A / cm ² ] = 493, Ron [mΩcm ² ] = 2.45, φb [eV] = 1.21, n = 1. 1, Vbr (V) =-1230
(3) “Al”: film thickness [nm] = 3000, Jon @ 2V [A / cm ² ] = 648, Ron [mΩcm ² ] = 2.34, φb [eV] = 0.87, n = 1. 2, Vbr (V) = − 694
From the above results and FIGS. 5A and 5B, the following can be understood. First, φb is larger for Ti and TiN than for Al. In Al, both the n value and the reverse direction characteristic (Vbr) are degraded. Ti and TiN realize a good Schottky characteristic, and particularly TiN realizes a better reverse direction characteristic.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible.

  Since the present invention can provide a vertical power MOSFET using a silicon carbide substrate capable of improving switching characteristics, it is suitable for use in a power semiconductor device made of silicon carbide used for high withstand voltage and large current.

Sectional drawing which shows typically the structure of the semiconductor device 100 which concerns on embodiment of this invention. (A)-(c) is process drawing for demonstrating the manufacturing method of the semiconductor device 100 which concerns on this embodiment. (A) And (b) is process drawing for demonstrating the manufacturing method of the semiconductor device 100 which concerns on this embodiment. (A) And (b) is process drawing for demonstrating the manufacturing method of the semiconductor device 100 which concerns on this embodiment. (A) is a graph showing the JV characteristic in the forward direction of the SBD element, (b) is a graph showing the JV characteristic in the reverse direction of the SBD element.

Explanation of symbols

10 Semiconductor substrate 20 Silicon carbide epitaxial layer (drift epi layer)
22 well region 24 source region 26 contact region 28 silicide layer 30 channel epitaxial layer (channel epi layer)
32 Gate oxide film 34 Gate electrode 35 Channel region 36 Insulating film (interlayer insulating film)
37 contact hole 40 metal layer 41 barrier metal layer 42 Schottky electrode 43 contact hole 44 wiring layer (aluminum wiring layer)
50 DMOSFET region 55 SBD region 60 Insulating layer (p-SiN film)
61 Opening 62 Metal Layer 71 Opening 80 Back Electrode 81 Back Silicide Layer 100 Semiconductor Device

Claims (10)

A step (a) of forming a first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the semiconductor substrate on the main surface of the first conductivity type semiconductor substrate made of silicon carbide;
(B) defining a DMOSFET region for forming a DMOSFET element and an SBD region for forming a Schottky barrier diode element at a position different from the DMOSFET region in the silicon carbide epitaxial layer;
Forming a second conductivity type well region in the DMOSFET region and the SBD region in the silicon carbide epitaxial layer; and
Forming a first conductivity type source region and a second conductivity type contact region in a part of the well region in the DMOSFET region;
Forming a channel epitaxial layer made of silicon carbide on the silicon carbide epitaxial layer, the well region, and the source region;
Forming a gate oxide film on the channel epitaxial layer (f);
Forming a gate electrode on the gate oxide film (g);
Forming a silicide layer on the contact region and the source region in the DMOSFET region (h);
An insulating film that covers the gate electrode in the DMOSFET region and exposes at least a part of the silicide layer, and that covers a part of the well region in the SBD region and exposes the silicon carbide epitaxial layer. Forming step (i);
A Schottky electrode is formed in the SBD region by covering the insulating film and forming a metal layer in contact with the silicide layer in the DMOSFET region and the silicon carbide epitaxial layer and the well region in the SBD region. A method for manufacturing a semiconductor device, comprising the step (j) of: Forming a wiring layer made of aluminum on the metal layer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming an electrode on a back surface of the semiconductor substrate. The step (h)
Forming an insulating layer having an opening exposing the contact region in the DMOSFET region on the main surface of the semiconductor substrate;
Forming a metal layer made of a metal material for ohmic electrodes on the contact region and the insulating layer;
A step of performing a heat treatment after the formation of the metal layer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: removing the metal layer by lift-off by removing the insulating layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer in the step (j) is made of a material selected from the group consisting of Ti, Ta, and nitrides thereof. A first conductivity type semiconductor substrate having a main surface and a back surface opposite to the main surface, and made of silicon carbide;
A silicon carbide epitaxial layer of a first conductivity type formed on a main surface of the semiconductor substrate and having a dopant concentration lower than that of the semiconductor substrate;
A DMOSFET region formed in the silicon carbide epitaxial layer and defining a DMOSFET element;
An SBD region that is formed in the silicon carbide epitaxial layer and that defines a Schottky barrier diode element;
The DMOSFET region is
A second conductivity type well region formed in the silicon carbide epitaxial layer;
A source region of a first conductivity type formed in the well region;
A contact region of a second conductivity type formed in the well region,
A silicide layer is formed on the source region and the contact region,
The SBD region includes a second conductivity type well region formed in the silicon carbide epitaxial layer,
A metal layer constituting a Schottky electrode is formed on the silicon carbide epitaxial layer and the well region in the SBD region,
The semiconductor device, wherein the metal layer extends from the Schottky electrode and is in contact with the silicide layer on the contact region in the DMOSFET region. The semiconductor device according to claim 5, wherein a wiring layer made of aluminum is formed on the metal layer. The semiconductor device according to claim 5, wherein the metal layer is made of a material selected from the group consisting of Ti, Ta, and nitrides thereof. The semiconductor device according to claim 7, wherein the metal layer is made of a nitride of Ti. A channel epitaxial layer made of silicon carbide is formed on the silicon carbide epitaxial layer, the well region, and the source region in the DMOSFET region,
A portion of the channel epitaxial layer located on the well region functions as a channel region,
The semiconductor device according to claim 5, wherein a gate oxide film is formed on the channel epitaxial layer. 10. The semiconductor device according to claim 5, wherein upper surfaces of the silicon carbide epitaxial layer, the well region, and the source region are located on the same plane.

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