JP6325743B2 - Semiconductor device, method of manufacturing the same, and power conversion device - Google Patents

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device.

  As background art of this technical field, US Pat. No. 5,904,510 (Patent Document 1), JP-A-11-261061 (Patent Document 2), Japanese Patent No. 3879129 (Patent Document 3) and Japanese Patent No. 4122230 are disclosed. (Patent Document 4).

In US Pat. No. 5,904,510 (Patent Document 1), the active region between spaced base regions is deeper than the depth of the base region and the impurity concentration is increased to about 3.5 × 10 ¹² atoms / cm ² . There is described an IGBT (Insulated Gate Bipolar Transistor) having a region that has been allowed to pass.

In Japanese Patent Laid-Open No. 11-261061 (Patent Document 2), p-type impurities are externally diffused from a surface layer portion of a p ⁻ -type silicon carbide base region formed in advance, and then ion-implanted into the p ⁻ -type silicon carbide base region. A silicon carbide semiconductor device that improves carrier mobility by forming a surface channel layer is described.

  In Japanese Patent No. 3879129 (Patent Document 3), after selectively oxidizing a region including a surface generated by chemical dry etching of a predetermined region of the surface of the epitaxial layer to form a selective oxide film, p-type A method for manufacturing a semiconductor device is described in which a base layer and a source layer are simultaneously formed by double diffusing n-type impurities to define the channel length.

  In Japanese Patent No. 4122230 (Patent Document 4), after injecting one or more dopants into the surface of a substrate having the first conductivity type so as to have a non-uniform doping profile, the first conductivity is disclosed. A double diffusion field effect transistor is described in which an epitaxial layer having a type is formed and in which one or more body regions having a second conductivity type are formed.

US Pat. No. 5,904,510 Japanese Patent Laid-Open No. 11-261061 Japanese Patent No. 3879129 Japanese Patent No. 4122230

  The power metal, insulating film, and semiconductor field effect transistor (MISFET), which is one of the power semiconductor devices, is a planar type using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate). Power MISFET (hereinafter referred to as SiC power MISFET) is used. SiC power MISFETs are particularly attracting attention in the field of power-saving or environmentally friendly inverter technology because they can achieve high breakdown voltage and low loss.

  By the way, in SiC power MISFET, further reduction of on-resistance is desired. However, in order to reduce the on-resistance, it is desirable to increase the impurity concentration of the JFET region sandwiched between the adjacent body regions, but this may cause a decrease in the breakdown voltage of the SiC power MISFET.

  In order to solve the above-described problems, the present invention provides a SiC power MISFET in which a p-type body region is in contact with a first region having a first depth and outside the first region in plan view. And a second region having a second depth shallower than the formed first depth. The JFET region is formed deeper than the second depth between adjacent p-type body regions, and the second region of the p-type body region is surrounded by the JFET region.

According to the present invention, it is possible to provide a SiC power MISFET having a low on-resistance and a high breakdown voltage.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

FIG. 3 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC power MISFET cells according to Example 1 are arranged. FIG. 2 is a cross-sectional view of a principal part showing a SiC power MISFET according to Example 1 (cross-sectional view taken along the line II in FIG. 1). 6 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC power MISFET cells according to a first modification of Example 1 are arranged. FIG. 6 is a plan view of a principal part showing a part of an element formation region in which a plurality of SiC power MISFET cells according to a second modification of Example 1 are arranged. FIG. 6 is a cross-sectional view of a principal part showing an example of a manufacturing process of the SiC power MISFET according to Embodiment 1. FIG. FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the SiC power MISFET that follows FIG. 5; FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the SiC power MISFET that follows FIG. 6; It is a circuit diagram which shows the 1st example of the power converter device (inverter) which used SiC power MISFET by Example 1 as a switching element. It is a circuit diagram which shows the 2nd example of the power converter device (inverter) using the SiC power MISFET by Example 1 as a switching element. FIG. 6 is a main part sectional view showing a SiC power MISFET according to Example 2 (a sectional view taken along line I-I in FIG. 1); 6 is a cross-sectional view of a principal part showing one example of a production process of a SiC power MISFET according to Example 2. FIG. FIG. 12 is a main-portion cross-sectional view illustrating the manufacturing process of the SiC power MISFET, continued from FIG. 11; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the SiC power MISFET that follows FIG. 12; FIG. 6 is a main part sectional view showing a SiC power MISFET according to Example 3 (a sectional view taken along line I-I in FIG. 1); 12 is a sectional view of a key portion showing one example of a manufacturing process of the SiC power MISFET according to Example 3. FIG. FIG. 16 is a main-portion cross-sectional view illustrating the manufacturing process of the SiC power MISFET, continued from FIG. 15; FIG. 17 is a main-portion cross-sectional view showing the manufacturing process of the SiC power MISFET that follows FIG. 16; FIG. 6 is a cross-sectional view of a principal part showing a SiC power MISFET according to Example 4 (cross-sectional view taken along the line II in FIG. 1). It is principal part sectional drawing which shows the 1st example of SiC power MISFET examined by the present inventors. It is principal part sectional drawing which shows the 2nd example of SiC power MISFET examined by the present inventors.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  First, the SiC power MISFET studied by the present inventors prior to the present invention will be described.

  19 and 20 show an example of the SiC power MISFET studied by the present inventors. FIG. 19 is a cross-sectional view of a main part showing a first example of a SiC power MISFET studied by the present inventors. FIG. 20 is a cross-sectional view of a principal part showing a second example of the SiC power MISFET studied by the present inventors.

As shown in FIG. 19, in the SiC power MISFET, in order to reduce the on-resistance, the impurity concentration of the JFET region 7 sandwiched between the p-type body regions 4 adjacent to each other is changed to a drift layer made of the n ⁻ -type epitaxial layer 2. The impurity concentration is higher than 50. Therefore, the extension of the depletion layer extending from the p-type body region 4 to the drift layer 50 is larger than the extension of the depletion layer extending from the p-type body region 4 to the JFET region 7.

Therefore, when the depth from the surface of the n ⁻ type epitaxial layer 2 of the JFET region 7 is the same as or shallower than the depth from the surface of the n ⁻ type epitaxial layer 2 of the p type body region 4, In the JFET region 7 and the drift layer 50, a path of current flowing from the JFET region 7 toward the drift layer 50 is formed. However, since the impurity concentration of the JFET region 7 is high, the resistance of the JFET region 7 sandwiched between the depletion layers extending from the adjacent p-type body regions 4 is low, but the impurity concentration of the drift layer 50 is low. The resistance of drift layer 50 sandwiched between depletion layers extending from adjacent p-type body regions 4 is increased.

Further, as shown in FIG. 20, n of the JFET region 7 ^- depth from the surface of the type epitaxial layer 2 is, p-type n body region 4 ^- If deeper than the depth from -type epitaxial layer 2 of the surface, Since the electric field concentrates at the corner of p-type body region 4 (corner indicated by C in FIG. 20), the breakdown voltage of the SiC power MISFET decreases.
Accordingly, the present invention provides a SiC power MISFET having a low on-resistance and a high breakdown voltage.

  ≪SiC power MISFET structure≫

  The structure of the SiC power MISFET according to the first embodiment will be described with reference to FIGS. FIG. 1 is a main part plan view showing a part of an element formation region in which a plurality of SiC power MISFET cells according to the first embodiment are arranged. FIG. 2 is a sectional view (a sectional view taken along the line I-I in FIG. 1) showing the SiC power MISFET according to the first embodiment. The SiC power MISFET is a planar type MISFET having a double diffused metal oxide semiconductor (DMOS) structure.

As shown in FIGS. 1 and 2, an n ⁻ type epitaxial layer made of SiC having an impurity concentration lower than that of the n ⁺ type SiC substrate 1 on the surface (first main surface) of the n ⁺ type SiC substrate 1 made of SiC. 2 is formed, and the n ⁺ type SiC substrate 1 and the n ⁻ type epitaxial layer 2 constitute a SiC epitaxial substrate 3. The thickness of the n ⁻ type epitaxial layer 2 is, for example, about 5.0 to 100.0 μm.

In the n ⁻ -type epitaxial layer 2, a plurality of p-type body regions (well regions) 4 having a predetermined depth from the surface of the n ⁻ -type epitaxial layer 2 are formed apart from each other. The p-type body region 4 is formed in contact with the first region 4a around the first region 4a in a plan view, the first region 4a having a first depth from the surface of the n ⁻ -type epitaxial layer 2, and n ^- consists of the surface of the mold epitaxial layer 2 and a second region 4b having a shallower second depth than the first depth. That is, p type body region 4 is formed such that the end of p type body region 4 in plan view is shallower than the central portion of p type body region 4. A first depth of the first region 4a of the p-type body region 4 from the surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 2.0 μm.

An n ⁺ type source region 5 (a region indicated by hatching in FIG. 1) having a predetermined depth from the surface of the n ⁻ type epitaxial layer 2 is formed in the p type body region 4. Yes. The n ⁺ -type source region 5 is formed in the p-type body region 4 so as to be separated from the end side surface of the p-type body region 4, and from the surface of the n ⁻ -type epitaxial layer 2 of the n ⁺ -type source region 5. The depth is, for example, about 0.1 to 0.5 μm.

Further, a p ⁺ type potential fixing region 6 for fixing the potential of the p type body region 4 is formed. The depth of the p ⁺ type potential fixing region 6 from the surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.1 to 0.5 μm.

A region sandwiched between adjacent p-type body regions 4 is a portion that functions as a JFET (Junction Field Effect Transistor) region (doping region) 7. Further, the end side surface of the p-type body region 4 (interface between the JFET region 7 and the p-type body region 4) and the end side surface of the n ⁺ -type source region 5 (p-type body region 4 and n ⁺ -type source region 5 The p-type body region 4 located between the first and second interfaces) functions as the channel region 8.

  JFET region 7 has a first depth of first region 4a of p-type body region 4 between second regions 4b of adjacent p-type body regions 4 and below second region 4b of p-type body region 4. Or deeper than that. That is, the JFET region 7 is formed so as to surround the side surface and the bottom surface of the second region 4b of the p-type body region 4, and is convex when viewed in a cross section along the direction of the adjacent p-type body regions 4. It has a shape.

Of the n ⁻ type epitaxial layer 2, a region where the p-type body region 4 and the JFET region 7 are not formed is a region functioning as a drift layer that plays a role of ensuring a breakdown voltage. Further, the n ⁺ type SiC substrate 1 is a region functioning as a drain layer.

Note that “ ⁻ ” and “ ⁺ ” are signs representing relative impurity concentrations of n-type or p-type conductivity, for example, n-type in the order of “n ⁻ ”, “n”, and “n ⁺ ”. The impurity concentration of the impurity increases, and the impurity concentration of the p-type impurity increases in the order of “p ⁻ ”, “p”, and “p ⁺ ”.

A preferable range of the impurity concentration of the n ⁺ -type SiC substrate 1 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and a preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 2 is, for example, 1 × 10 ¹⁴ to 1. It is about × 10 ¹⁷ cm ⁻³ . In addition, a preferable range of the impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁸ cm ⁻³ , and a preferable range of the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ²⁰ cm ⁻³ , p A preferable range of the impurity concentration of the ⁺ -type potential fixing region 6 is, for example, about 1 × 10 ²⁰ cm ⁻³ , and a preferable range of the impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ .

  A gate insulating film 10 is formed on the channel region 8, and a gate electrode 11 is formed on the gate insulating film 10. The gate electrode 11 is formed in a lattice shape in plan view, and a p-type body region 4 is formed so as to be surrounded by the gate electrode 11.

The gate insulating film 10 and the gate electrode 11 are covered with an interlayer insulating film 12. A part of the n ⁺ type source region 5 and the p ⁺ type potential fixing region 6 are exposed on the bottom surface of the opening 13 formed in the interlayer insulating film 12, and a metal silicide layer 14 is formed on these surfaces.

Further, a part of the n ⁺ type source region 5 and the p ⁺ type potential fixing region 6 are electrically connected to the source wiring electrode 15 through the metal silicide layer 14, and the n ⁺ type SiC substrate 1 is made of metal silicide. The drain wiring electrode 17 is electrically connected through the layer 16. Although illustration is omitted, similarly, the gate electrode 11 is electrically connected to the gate wiring electrode. A source potential is applied to the source wiring electrode 15 from the outside, a drain potential is applied to the drain wiring electrode 17 from the outside, and a gate potential is applied to the gate wiring electrode from the outside.
Next, features of the structure of the SiC power MISFET according to the first embodiment will be described.

  In the SiC power MISFET according to the first embodiment, the p-type body region 4 is formed in contact with the first region 4a around the first region 4a in plan view and the first region 4a having the first depth. The second region 4b has a second depth shallower than the first depth. Then, the JFET region 7 is placed between the second regions 4b of the p-type body region 4 adjacent to each other and below the second region 4b of the p-type body region 4 in the first region 4a of the p-type body region 4. It is the same as 1 depth or deeper than that.

  Thereby, the corner portion formed by the JFET region 7 at the corner portion A of the second region 4b of the p-type body region 4 and the boundary portion between the first region 4a and the second region 4b of the p-type body region 4 is formed. Since B can be surrounded, the electric field applied to the pn junction between the p-type body region 4 and the JFET region 7 can be dispersed in the corners A and B.

  For example, in the SiC power MISFET shown in FIG. 20, the electric field applied to the pn junction between the p-type body region 4 and the JFET region 7 is concentrated on the corner C, and the breakdown voltage is significantly reduced. However, in the SiC power MISFET according to the first embodiment, even if the JFET region 7 is formed in order to obtain a low on-resistance, the electric field applied to the pn junction between the p-type body region 4 and the JFET region 7 is reduced to the corner A and Since it is dispersed in the corner B, it is possible to avoid a decrease in breakdown voltage.

  The layout of the SiC power MISFET in the element formation region is not limited to that shown in FIG. For example, the layout shown in FIGS. 3 and 4 may be used. FIG. 3 is a main part plan view showing a part of an element formation region in which a plurality of SiC power MISFET cells according to a first modification of the first embodiment are arranged. FIG. 4 is a main part plan view showing a part of an element formation region in which a plurality of SiC power MISFET cells according to a second modification of the first embodiment are arranged.

  In the layout of the SiC power MISFET shown in FIG. 1, the plurality of p-type body regions 4 arranged at the first interval along the first direction Y are perpendicular to the first direction Y on the surface of the SiC epitaxial substrate 3. The two p-type body regions 4 are arranged at second intervals along the two directions X, and are positioned so as to be surrounded by the gate electrodes 11 arranged in a lattice pattern.

  In the layout of the SiC power MISFET shown in FIG. 3, the plurality of p-type body regions 4 arranged at the first interval along the first direction Y are alternately positioned at half the first interval. They are arranged at a second interval along the two directions X. The plurality of p-type body regions 4 are arranged in a so-called staggered arrangement.

In the layout of the SiC power MISFET shown in FIG. 4, a plurality of p-type body regions 4 are arranged so as to be separated from each other in the second direction X and extend along the first direction Y, and the plurality of gate electrodes 11 are arranged. , Between the adjacent p-type body regions 4, the first body region 4 extends in the first direction Y.
≪SiC power MISFET manufacturing method≫

  A manufacturing method of the SiC power MISFET according to the first embodiment will be described in the order of steps with reference to FIGS. 5 to 7 are cross-sectional views of relevant parts showing an example of manufacturing steps of the SiC power MISFET according to the first embodiment.

First, as shown in FIG. 5, an n ⁺ -type 4H—SiC substrate 1 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 1. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The n ⁺ type SiC substrate 1 has both a Si surface and a C surface, but the surface of the n ⁺ type SiC substrate 1 may be either the Si surface or the C surface.

Next, an SiC n ⁻ type epitaxial layer 2 is formed on the surface of the n ⁺ type SiC substrate 1 by an epitaxial growth method. In the n ⁻ type epitaxial layer 2, n type impurities lower than the impurity concentration of the n ⁺ type SiC substrate 1 are introduced. Although the impurity concentration of the n ⁻ type epitaxial layer 2 depends on the element rating of the SiC power MISFET, it is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . Moreover, the thickness of the n ⁻ type epitaxial layer 2 is, for example, 5.0 to 100.0 μm. Through the above steps, SiC epitaxial substrate 3 composed of n ⁺ type SiC substrate 1 and n ⁻ type epitaxial layer 2 is formed.

Next, p-type impurities such as aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV. As a result, a p-type body region 4 is formed in the element formation region of the n ⁻ -type epitaxial layer 2 and a floating field limiting ring (FLR) structure is formed in the peripheral formation region although illustration is omitted. Form.

The depth of the p-type body region 4 from the surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . Although the FLR structure is formed at the end portion of the peripheral formation region, it is not limited to this. As a structure of the termination portion, for example, a junction termination extension (JTE) structure may be used.

Next, an n-type impurity, for example, a nitrogen atom (N) is ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 120 keV, and the p-type body region 4 is separated from the side surface of the end of the p-type body region 4. N ⁺ -type source region 5 is formed. The depth of the n ⁺ type source region 5 from the surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.1 to 0.5 μm. Further, the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Next, a p-type impurity, for example, an aluminum atom (Al) is ion-implanted into the n ⁻ -type epitaxial layer 2 at a maximum energy of 150 keV, and a p ⁺ -type potential fixing region 6 is formed in a region for fixing the potential of the p-type body region 4. Form. The depth of the p ⁺ type potential fixing region 6 from the surface of the n ⁻ type epitaxial layer 2 is, for example, about 0.1 to 0.5 μm. Further, the impurity concentration of the p ⁺ -type potential fixing region 6 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Next, as shown in FIG. 6, a mask 18 is formed on the surface of the n ⁻ type epitaxial layer 2. The mask 18 is provided with an opening only in a region where the JFET region 7 is formed in a later process. That is, the mask 18 is provided with an opening so that the p-type body region 4 adjacent to each other and the end of the p-type body region 4 are exposed.

Then, over the mask 18, n ^- n-type impurity -type epitaxial layer 2, for example, nitrogen atom (N) is ion-implanted at a maximum energy 1,000 keV, the p-type body region 4 n ^- -type epitaxial layer 2 The JFET region 7 is formed to be equal to or deeper than the depth from the surface. The impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ .

Thereby, JFET region 7 is formed between adjacent p-type body regions 4 and below the end of p-type body region 4. Specifically, n ^- a first region 4a having a surface -type epitaxial layer 2 a first depth, around the first region 4a in a plan view, in contact with the first region 4a, n ^- -type epitaxial layer The p-type body region 4 is formed which is composed of the second region 4b having the second depth from the surface of 2. Here, the second depth of the second region 4b is shallower than the first depth of the first region 4a. Further, JFET region 7 is formed between second regions 4 b of p-type body regions 4 adjacent to each other and below second region 4 b of p-type body region 4. That is, the JFET region 7 is formed so as to surround the side surface and the bottom surface of the second region 4b of the p-type body region 4. It has a shape.

  Next, after the mask 18 is removed, although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 3 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the surface of the SiC epitaxial substrate 3 with this carbon (C) film, the SiC epitaxial substrate 3 is subjected to heat treatment at a temperature of about 1,700 ° C. for about 2 to 3 minutes. Thereby, each impurity ion-implanted into the SiC epitaxial substrate 3 is activated. After the heat treatment, the carbon (C) film is removed by, for example, oxygen plasma treatment.

Next, as shown in FIG. 7, a gate insulating film 10 made of silicon oxynitride is formed on the surface of the n ⁻ type epitaxial layer 2. The gate insulating film 10 is formed by, for example, forming a silicon oxide (SiO ₂ ) film by a CVD method and then performing a heat treatment in a nitrogen oxide (NO or N ₂ O) atmosphere. The thickness of the gate insulating film 10 is, for example, about 0.05 to 0.15 μm.

  Next, a polycrystalline silicon (Si) film is formed on the gate insulating film 10, and the polycrystalline silicon (Si) film is processed by a dry etching method to form the gate electrode 11. The thickness of the gate electrode 11 is, for example, about 0.2 to 0.5 μm.

Next, an interlayer insulating film 12 is formed on the surface of the n ⁻ -type epitaxial layer 2 so as to cover the gate electrode 11 and the gate insulating film 10 by, for example, a plasma CVD method. Thereafter, the interlayer insulating film 12 and the gate insulating film 10 are processed by dry etching to form a part of the n ⁺ type source region 5 and an opening 13 reaching the p ⁺ type potential fixing region 6.

Next, a metal silicide layer 14, for example, a nickel silicide (NiSi) layer is formed on a part of the n ⁺ -type source region 5 exposed on the bottom surface of the opening 13 and the respective surfaces of the p ⁺ -type potential fixing region 6. . Further, a metal silicide layer 16, for example, a nickel silicide (NiSi) layer is formed on the back surface of the n ⁺ type SiC substrate 1.

  Next, a drain wiring electrode 17 is formed so as to cover the metal silicide layer 16 (see FIG. 2). The thickness of the drain wiring electrode 17 is, for example, about 0.4 μm.

  Next, the interlayer insulating film 12 is processed by a dry etching method to form an opening (not shown) reaching the gate electrode 11.

Next, an opening 13 reaching the metal silicide film 14 formed on a part of the n ⁺ -type source region 5 and the p ⁺ -type potential fixing region 6 and an opening reaching the gate electrode 11 (not shown) ) Is deposited on the inter-layer insulating film 12 including the inside of (). The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the laminated film, the source wiring electrode 15 electrically connected to a part of the n ⁺ type source region 5 and the gate wiring electrically connected to the gate electrode 11 through the metal silicide layer 14. A working electrode (not shown) is formed (see FIG. 2). Thereafter, external wirings are electrically connected to the source wiring electrode 15 and the gate wiring electrode (not shown), respectively.
≪Power conversion device (inverter) ≫

  A power conversion device (inverter) using the SiC power MISFET according to the first embodiment as a switching element will be described with reference to FIGS. FIG. 8 is a circuit diagram showing a first example of a power converter (inverter) using the SiC power MISFET according to the first embodiment as a switch element. FIG. 9 is a circuit diagram showing a second example of a power conversion device (inverter) using the SiC power MISFET according to the first embodiment as a switch element.

  As shown in FIG. 8, the inverter according to the first embodiment includes a control circuit 21 and a power module 22. The control circuit 21 and the power module 22 are connected by a terminal 23 and a terminal 24. The power module 22 is connected to the power supply potential (Vcc) via the terminal 25 and to the ground potential (GND) via the terminal 26. The output of the power module is connected to the three-phase motor 30 via terminals 27, 28 and 29.

The power module 22 includes the SiC power MISFET 33 according to the first embodiment as a switching element. Each SiC power MISFET 33 is connected to an external freewheeling diode 32. The free-wheeling diode 32 is provided to relieve an electric field applied to an interface between a metal and a semiconductor (Schottky interface) when a voltage is applied in the reverse direction, and suppress a leakage current during reverse operation. In FIG. 8, a diode denoted by reference numeral 33 is a body diode including a p ⁺ type potential fixing region 6 and an n ⁺ type SiC substrate 1 formed in the SiC power MISFET (see FIG. 2 and the like).

  In each single phase, the SiC power MISFET 31 and the freewheeling diode 32 are connected in antiparallel between the power supply potential (Vcc) and the input potential of the three-phase motor 30, and the input potential of the three-phase motor 30 and the ground potential ( The SiC power MISFET 31 and the free-wheeling diode 32 are also connected in reverse parallel to the GND). That is, two SiC power MISFETs 31 and two free-wheeling diodes 32 are provided in each single phase of the three-phase motor 30, and six SiC power MISFETs 31 and six free-wheeling diodes 32 are provided in three phases. A control circuit 21 is connected to the gate electrode of each SiC power MISFET 31, and the SiC power MISFET 31 is controlled by the control circuit 21. Therefore, the three-phase motor 30 can be driven by controlling the current flowing in the SiC power MISFET 31 of the power module 22 by the control circuit 21.

  Since the SiC power MISFET 31 according to the first embodiment has a low on-resistance and a high breakdown voltage as described above, a high-performance and highly reliable power module 22 can be realized.

  Further, in the SiC power MISFET 31 according to the first embodiment, the JFET region 7 is in contact with the second region 4b of the p-type body region 4 and the second region 4b of the p-type body region 4 as shown in FIG. It is also formed under. That is, the JFET region 7 is formed so as to surround the second region 4b of the p-type body region 4, and has a convex shape when viewed in a cross section along the direction of the adjacent p-type body regions 4. ing.

Therefore, when a body diode 33 composed of the p ⁺ type potential fixing region 6 and the n ⁺ type SiC substrate 1 is considered, as indicated by an arrow in FIG. 2, the p ⁺ type potential fixing region 6 and the n ⁺ type SiC substrate Since the current flowing between 1 and 1 flows in a distributed manner in the JFET region 7 below the second region 4b of the p-type body region 4, a body diode 33 having a low on-resistance can be obtained.

  As a result, when the SiC power MISFET 31 according to the first embodiment is used, the body diode 33 and the external freewheeling diode 32 are connected in parallel to the SiC power MISFET 31, so that the leakage current during reverse operation is obtained. The suppression effect is further improved.

  Furthermore, as shown in FIG. 9, when the SiC power MISFET 31 according to the first embodiment is used, only the body diode 33 functions as a free-wheeling diode without connecting the external free-wheeling diode 32 to the SiC power MISFET 31. You can also. Thereby, in addition to realizing the high-performance and high-reliability power module 22, it is also possible to reduce the size of the power converter.

  Thus, according to the first embodiment, even when the JFET region 7 is formed in order to obtain a low on-resistance, the electric field applied to the pn junction between the p-type body region 4 and the JFET region 7 can be dispersed. Therefore, the breakdown voltage of the SiC power MISFET can be improved. Thereby, a SiC power MISFET having a low on-resistance and a high breakdown voltage can be provided.

  Further, by using the SiC power MISFET 31 according to the first embodiment in the power conversion device, the body diode 33 having a low on-resistance can be obtained, so that the external free-wheeling diode 32 is not required, and high performance and high reliability are achieved. In addition to realizing the power module 22, it is also possible to reduce the size of the power converter.

  ≪SiC power MISFET structure≫

  The structure of the SiC power MISFET according to the second embodiment will be described with reference to FIG. FIG. 10 is a cross-sectional view of a principal part showing the SiC power MISFET according to the second embodiment (cross-sectional view taken along the line II in FIG. 1). Here, differences from the SiC power MISFET according to the first embodiment will be described.

  In the SiC power MISFET according to Example 1 described above, the p-type body region 4 is composed of the first region 4a having the first depth and the second region 4b having the second depth shallower than the first depth. Then, the depth of the JFET region 7 was made substantially the same as or deeper than the first depth of the p-type body region 4.

  However, as shown in FIG. 10, in the SiC power MISFET according to the second embodiment, the depth of the JFET region 7 is shallower than the first depth of the p-type body region 4 and deeper than the second depth.

The JFET region 7 is formed by ion-implanting n-type impurities into the n ⁻ -type epitaxial layer 2. For this reason, when the impurity concentration distribution of the JFET region 7 is viewed in the depth direction of the n ⁻ type epitaxial layer 2, when the peak value is exceeded, the impurity concentration decreases as the JFET region 7 becomes deeper. Therefore, the impurity concentration of the JFET region 7 in the portion where the corner portion A and the corner portion B of the p-type body region 4 in the second embodiment is located is the same as the corner portion A and the corner of the p-type body region 4 in the first embodiment. It becomes lower than the impurity concentration of the JFET region 7 in the portion where the portion B is located.

As a result, the pn junction breakdown voltage between the p-type body region 4 and the JFET region 7 in Example 2 is higher than the pn junction breakdown voltage between the p-type body region 4 and the JFET region 7 in Example 1 described above. The breakdown voltage of the SiC power MISFET according to the second embodiment is higher than the breakdown voltage of the SiC power MISFET according to the first embodiment.
≪SiC power MISFET manufacturing method≫

  A manufacturing method of the SiC power MISFET according to the second embodiment will be described in the order of steps with reference to FIGS. FIGS. 11 to 13 are cross-sectional views of relevant parts showing an example of manufacturing steps of the SiC power MISFET according to the first embodiment.

First, as shown in FIG. 11, an n ⁻ type epitaxial layer 2 of SiC is formed on the surface of an n ⁺ type SiC substrate 1 in the same manner as in the first embodiment, and the n ⁺ type SiC substrate 1 and n ⁻ A SiC epitaxial substrate 3 composed of the type epitaxial layer 2 is formed.

Next, p-type impurities, for example, aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV to form the p-type body region 4, and the n ⁻ -type epitaxial layer 2 has n-type impurities, For example, nitrogen atoms (N) are ion-implanted with a maximum energy of 120 keV to form an n ⁺ -type source region 5 that is separated from the end side surface of the p-type body region 4 in the p-type body region 4.

Then, n ^- n-type impurity -type epitaxial layer 2, for example, nitrogen atom (N) is ion-implanted at a maximum energy 1,000 keV, the p-type body region 4 n ^- than the depth from -type epitaxial layer 2 of the surface The JFET region 7 is formed deeply. The impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁸ cm ⁻³ , the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the JFET region 7 is, for example, It is about 3 × 10 ¹⁶ cm ⁻³ .

Next, as shown in FIG. 12, a mask 19 is formed on the surface of the n ⁻ type epitaxial layer 2. The mask 19 is provided with an opening only in a region where the p ⁺ -type potential fixing region 6 is formed in a later step.

Then, over the mask 19, n ^- p-type impurity -type epitaxial layer 2, for example, aluminum atom (Al) is ion-implanted at a maximum energy 1,000 keV, n ^- impurity concentration near the surface of the type epitaxial layer 2 , for example, about 1 × ¹⁰ 20 ^{cm -3,} the impurity concentration of the deep region, for example, is formed about 1 × ¹⁰ 18 ^{cm -3} in ^{p +} -type potential fixing region 6. At this time, since the p-type impurity is ion-implanted with high energy, the p-type impurity is ion-implanted deeper than the already formed p-type body region 4 and JFET region 7.

Thereby, the first region 4a having the first depth from the surface of the n ⁻ type epitaxial layer 2 and the first region 4a in contact with the first region 4a in a plan view, the n ⁻ type epitaxial layer 2 A p-type body region 4 composed of a second region 4b having a second depth from the surface is formed. Here, the second depth of the second region 4b is shallower than the first depth of the first region 4a. The JFET region 7 is formed below the second region 4 b of the p-type body region 4, but the depth from the surface of the n ⁻ -type epitaxial layer 2 is larger than that of the second region 4 b of the p-type body region 4. Deeper and shallower than the first region 4a.

  Next, after removing the mask 19, heat treatment is performed at a temperature of about 1,700 ° C. for about 2 to 3 minutes to activate each impurity ion-implanted into the SiC epitaxial substrate 3.

Next, as shown in FIG. 13, the gate insulating film 10, the gate electrode 11, the interlayer insulating film 12, and the metal silicide layer 14 are formed on the surface side of the n ⁺ type SiC substrate 1 in the same manner as in the first embodiment. Then, a metal silicide layer 16 is formed on the back surface side of the n ⁺ -type SiC substrate 1. Further, a source wiring electrode 15, a gate wiring electrode, and a drain wiring electrode 17 are formed (see FIG. 10).

  As described above, according to the second embodiment, the electric field applied to the pn junction between the p-type body region 4 and the JFET region 7 can be further reduced as compared with the first embodiment. The withstand voltage can be improved.

  ≪SiC power MISFET structure≫

  The structure of the SiC power MISFET according to the third embodiment will be described with reference to FIG. FIG. 14 is a cross-sectional view of an essential part showing the SiC power MISFET according to the third embodiment (cross-sectional view taken along the line II in FIG. 1). Here, differences from the SiC power MISFET according to the first embodiment will be described.

In the SiC power MISFET according to Example 1 described above, the surface of the n ⁻ type epitaxial layer 2 on which the n ⁺ type source region 5 is formed is flat, and the impurity concentration of the n ⁺ type source region 5 is changed from the channel region 8 to p. It is almost uniform over the ⁺ -type potential fixing region 6.

However, as shown in FIG. 14, in the SiC power MISFET according to the third embodiment, the surface of the n ⁻ type epitaxial layer 2 on which the n ⁺ type source region 5 on the channel region 8 side is formed is the p ⁺ type potential fixing region. A step is formed on the surface of the n ⁻ type epitaxial layer 2 so as to be lower than the surface of the n ⁻ type epitaxial layer 2 on which the n ⁺ type source region 5 on the 6 side is formed. Further, the n ⁺ -type source region 5 is arranged so that the impurity concentration of the n ⁺ -type source region 5 on the channel region 8 side is lower than the impurity concentration of the n ⁺ -type source region 5 on the p ⁺ -type potential fixing region 6 side. Is formed.

Thus, by forming a step on the surface of the n ⁻ -type epitaxial layer 2, energy for forming the JFET region 7 by ion implantation can be reduced in the SiC power MISFET manufacturing method described later. The JFET region 7 can be formed using general-purpose ion implantation conditions. This improves the productivity of the SiC power MISFET.

In addition, since the impurity concentration of the n ⁺ -type source region 5 in contact with the channel region 8 can be lowered, the pn junction barrier between the p-type body region 4 and the n ⁺ -type source region 5 is lowered, and electrons enter the channel region 8. Easy to enter. As a result, the on-resistance of the SiC power MISFET according to the third embodiment can be made lower than the on-resistance of the SiC power MISFET according to the first embodiment.
≪SiC power MISFET manufacturing method≫

  A manufacturing method of the SiC power MISFET according to the third embodiment will be described in the order of steps with reference to FIGS. 15-17 is principal part sectional drawing which shows an example of the manufacturing process of SiC power MISFET by the present Example 3. FIGS.

First, as shown in FIG. 15, an SiC n ⁻ type epitaxial layer 2 is formed on the surface of an n ⁺ type SiC substrate 1 in the same manner as in Example 1 described above, and the n ⁺ type SiC substrate 1 and n ⁻ A SiC epitaxial substrate 3 composed of the type epitaxial layer 2 is formed.

Next, p-type impurities, for example, aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV to form the p-type body region 4, and the n ⁻ -type epitaxial layer 2 has n-type impurities, For example, nitrogen atoms (N) are ion-implanted with a maximum energy of 120 keV to form an n ⁺ -type source region 5 that is separated from the end side surface of the p-type body region 4 in the p-type body region 4.

Next, a p-type impurity, for example, an aluminum atom (Al) is ion-implanted into the n ⁻ -type epitaxial layer 2 at a maximum energy of 150 keV, and the n ⁺ -type source region 5 in the p-type body region 4 is not formed. A p ⁺ -type potential fixing region 6 is formed. The impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁸ cm ⁻³ , the impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ²⁰ cm ⁻³ , and the impurity of the p ⁺ -type potential fixing region 6 is The concentration is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Next, as shown in FIG. 16, a mask 20 is formed on the surface of n ⁻ type epitaxial layer 2. The mask 20 is made of, for example, silicon oxide (SiO ₂ ), and an opening is provided only in a region where the JFET region 7 is formed in a later process. That is, the mask 20 is provided with an opening between the p-type body regions 4 adjacent to each other so that a part of the channel region 8 and the n ⁺ -type source region 5 on the channel region 8 side is exposed.

Next, the n ⁻ type epitaxial layer 2 exposed from the mask 20 is removed in the depth direction by, for example, about 200 nm by a dry etching method to form a step on the surface of the n ⁻ type epitaxial layer 2.

The n ⁺ type source region 5 is formed by ion-implanting n type impurities into the n ⁻ type epitaxial layer 2. For this reason, when the impurity concentration distribution of the n ⁺ -type source region 5 is viewed in the depth direction of the n ⁻ -type epitaxial layer 2, when the peak value is exceeded, the impurity concentration decreases as the n ⁺ -type source region 5 becomes deeper. . Therefore, when the upper portion of the n ⁺ -type source region 5 is removed by etching, the lower portion of the n ⁺ -type source region 5 having a low impurity concentration remains.

Accordingly, the impurity concentration of the n ⁺ -type source region 5 in contact with the channel region 8 is lowered, so that the pn junction barrier between the p-type body region 4 and the n ⁺ -type source region 5 is lowered, and electrons are likely to enter the channel region 8. Become. As a result, the on-resistance of the SiC power MISFET according to the third embodiment can be made lower than the on-resistance of the SiC power MISFET according to the first embodiment.

Next, an n-type impurity, for example, an aluminum atom (Al) is ion-implanted into the n ⁻ -type epitaxial layer 2 through the mask 20 with a maximum energy of 700 keV to form the JFET region 7. The impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ .

Thereby, JFET region 7 is formed between adjacent p-type body regions 4 and below the end of p-type body region 4. Specifically, n ^- a first region 4a having a surface -type epitaxial layer 2 a first depth, around the first region 4a in a plan view, in contact with the first region 4a, n ^- -type epitaxial layer The p-type body region 4 is formed which is composed of the second region 4b having the second depth from the surface of 2. Further, JFET region 7 is formed between second regions 4 b of p-type body regions 4 adjacent to each other and below second region 4 b of p-type body region 4. That is, the JFET region 7 is formed so as to surround the side surface and the bottom surface of the second region 4b of the p-type body region 4. It has a shape.

In Example 3, since the n ⁻ type epitaxial layer 2 in the region where the JFET region 7 is formed is removed in the depth direction, for example, about 200 nm, the maximum energy of the n-type impurity when forming the JFET region 7 (For example, 700 eV) can be made lower than the maximum energy (for example, 1,000 eV) of the n-type impurity when forming the JFET region 7 in Example 1 described above. Therefore, the JFET region 7 can be formed using general-purpose ion implantation conditions. This improves the productivity of the SiC power MISFET.

  Next, after removing the mask 20, a heat treatment is performed at a temperature of about 1,700 ° C. for about 2 to 3 minutes to activate each impurity ion-implanted into the SiC epitaxial substrate 3.

Next, as shown in FIG. 17, the gate insulating film 10, the gate electrode 11, the interlayer insulating film 12, and the metal silicide layer 14 are formed on the surface side of the n ⁺ -type SiC substrate 1 in the same manner as in the first embodiment. Then, a metal silicide layer 16 is formed on the back surface side of the n ⁺ -type SiC substrate 1. Further, a source wiring electrode 15, a gate wiring electrode, and a drain wiring electrode 17 are formed (see FIG. 14).

As described above, according to the third embodiment, electrons are more likely to enter the channel region 8 from the n ⁺ -type source region 4 than in the first embodiment, so that the on-resistance of the SiC power MISFET can be improved. Can do.

  ≪SiC power MISFET structure≫

  The structure of the SiC power MISFET according to the fourth embodiment will be described with reference to FIG. FIG. 18 is a cross-sectional view of the principal part showing the SiC power MISFET according to the fourth embodiment (cross-sectional view taken along the line II of FIG. 1). Here, differences from the SiC power MISFET according to the first embodiment will be described.

In the SiC power MISFET according to Example 1 described above, the impurity concentration of the JFET region 7 is set to about 3 × 10 ¹⁶ cm ⁻³ .

However, as shown in FIG. 18, in the SiC power MISFET according to the fourth embodiment, the impurity concentration of the upper portion 7A of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ^−3, and the impurity concentration of the lower portion 7B of the JFET region 7 Is lower than the impurity concentration of the upper portion 7A, for example, about 1 × 10 ¹⁶ cm ⁻³ . For example, the upper portion 7A of the JFET region 7 sandwiched between the second regions 4b of the p-type body regions 4 adjacent to each other has a high impurity concentration, and is sandwiched between the first regions 4a of the p-type body regions 4 adjacent to each other. The lower portion 7B of the JFET region 7 is set to a low impurity concentration.

  Then, the JFET region 7 is formed so that at least one corner of the p-type body region 4 is formed in the lower portion 7B where the impurity concentration of the JFET region 7 is low.

  As a result, the pn junction breakdown voltage between the p-type body region 4 and the JFET region 7 in Example 4 is higher than the pn junction breakdown voltage between the p-type body region 4 and the JFET region 7 in Example 1 described above. The breakdown voltage of the SiC power MISFET according to the fourth embodiment is higher than the breakdown voltage of the SiC power MISFET according to the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 n ⁺ type SiC substrate 2 n ⁻ type epitaxial layer 3 SiC epitaxial substrate 4 p type body region 4a first region of p type body region 4b second region of p type body region 5 n ⁺ type source region 6 p ⁺ type potential Fixed region 7 JFET region (doping region)
7A Upper portion of JFET region 7B Lower portion of JFET region 8 Channel region 10 Gate insulating film 11 Gate electrode 12 Interlayer insulating film 13 Opening portion 14 Metal silicide layer 15 Source wiring electrode 16 Metal silicide layer 17 Drain wiring electrodes 18, 19, 20 Mask 21 Control circuit 22 Power module 23, 24, 25, 26, 27, 28, 29 Terminal 30 Three-phase motor 31 SiC power MISFET
32 Reduction diode 33 Body diode

Claims (11)

A first conductive type substrate having a first main surface and a second main surface opposite to the first main surface and made of silicon carbide;
An epitaxial layer of the first conductivity type made of silicon carbide formed on the first main surface of the substrate;
A plurality of body regions of a second conductivity type different from the first conductivity type formed in the epitaxial layer from the surface of the epitaxial layer;
A doping region of the first conductivity type formed between the body regions adjacent to each other;
A source region of the first conductivity type formed in the body region from the surface of the epitaxial layer, spaced from an end side surface of the body region;
A channel region formed in a surface layer portion of the epitaxial layer between an end side surface of the body region and an end side surface of the source region;
A gate insulating film formed in contact with the channel region;
A gate electrode formed in contact with the gate insulating film;
Have
The body region is
A first region having a first depth;
A second region having a second depth shallower than the first depth, formed in contact with the first region on a side where the first regions adjacent to each other in plan view are opposed to each other;
Consisting of
A depth of the doping region is deeper than the second depth;
Be between the second region adjacent to each other, the impurity concentration of the doped region above the lower end of the second region is higher than the impurity concentration of the doped region in contact with the lower end of the second region, the semiconductor apparatus. The semiconductor device according to claim 1,
The semiconductor device, wherein the end of the source region is located between the end of the first region and the end of the second region in plan view. The semiconductor device according to claim 1,
Having a step on the surface of the epitaxial layer where the source region is formed;
The position of the surface of the epitaxial layer at the end of the source region is lower than the position of the surface of the epitaxial layer at the center of the source region;
A semiconductor device, wherein an impurity concentration at an end portion of the source region is lower than an impurity concentration at a central portion of the source region. The semiconductor device according to claim 3 .
The semiconductor device in which the position of the step and the position of the end of the second region overlap in plan view. The semiconductor device according to claim 3 .
A semiconductor device, wherein the doping region is formed under the second region. The semiconductor device according to claim 3 .
The semiconductor device, wherein the end of the source region is located between the end of the first region and the end of the second region in plan view. The semiconductor device according to claim 3 .
The semiconductor device, wherein an impurity concentration of the doping region between the second regions adjacent to each other is higher than an impurity concentration of the doping region under the second region. (A ) forming a first conductive type epitaxial layer made of silicon carbide on a first main surface of a first conductive type substrate made of silicon carbide;
(B) forming a plurality of body regions by ion-implanting a second conductivity type impurity different from the first conductivity type from the surface of the epitaxial layer into the epitaxial layer;
(C) a step of forming a source region by ion-implanting the first conductivity type impurity from the surface of the epitaxial layer into the body region apart from the end side surface of the body region;
(D) forming a mask provided with an opening on the surface of the epitaxial layer so as to expose an end portion of the body region between the adjacent body regions;
(E) in the epitaxial layer exposed from the mask, the impurity of the first conductivity type by ion implantation into the epitaxial layer below the end of and between the body region of the body region adjacent to each other, Doping region Forming a process,
(F) after removing the mask, in contact with the surface of the epitaxial layer, the step of forming a gate insulating film, forming a gate electrode on the gate insulating film,
Have
The body region after the step (e) is
A first region having a first depth;
A second region having a second depth shallower than the first depth, formed in contact with the first region on a side where the first regions adjacent to each other in plan view are opposed to each other;
Consisting of
A semiconductor between the second regions adjacent to each other, the impurity concentration of the doping region above the lower end of the second region being higher than the impurity concentration of the doping region in contact with the lower end of the second region Device manufacturing method. The method of manufacturing a semiconductor device according to claim 8 .
The following steps are further included between the step (d) and the step (e):
(G) Etching the epitaxial layer exposed from the mask to be shallower than the depth of the source region. The method of manufacturing a semiconductor device according to claim 8 .
The manufacturing method of a semiconductor device, wherein an opening end of the mask is located on the source region. A power converter comprising the semiconductor device according to claim 1.

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