WO2014083771A1 - Semiconductor element and method for manufacturing same - Google Patents

Semiconductor element and method for manufacturing same Download PDF

Info

Publication number
WO2014083771A1
WO2014083771A1 PCT/JP2013/006471 JP2013006471W WO2014083771A1 WO 2014083771 A1 WO2014083771 A1 WO 2014083771A1 JP 2013006471 W JP2013006471 W JP 2013006471W WO 2014083771 A1 WO2014083771 A1 WO 2014083771A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
body region
silicon carbide
semiconductor layer
conductivity type
Prior art date
Application number
PCT/JP2013/006471
Other languages
French (fr)
Japanese (ja)
Inventor
恒一郎 佐野
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2014083771A1 publication Critical patent/WO2014083771A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor element used for high withstand voltage or large current and a manufacturing method thereof.
  • Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material having a larger band gap than silicon (Si), and is applied to various semiconductor elements such as power elements, environment-resistant elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power elements, such as a semiconductor element and a rectifier, attracts attention.
  • a power element using SiC has advantages such as a significant reduction in power loss compared to a Si power element. Further, the SiC power element can realize a smaller semiconductor element as compared with the Si power element by utilizing such characteristics.
  • a typical semiconductor element is a metal-insulator-semiconductor field-effect transistor (MISFET) (see, for example, Patent Document 1). .
  • MISFET metal-insulator-semiconductor field-effect transistor
  • MOSFET Metal-oxide-semiconductor field-effect transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • the semiconductor element described in Patent Document 1 includes a body region divided into a first body region and a second body region. According to the semiconductor element described in Patent Document 1, electrical characteristics such as threshold voltage and on-resistance can be controlled by controlling the impurity concentrations of the first body region and the second body region.
  • the technology disclosed in this specification aims to realize a semiconductor element capable of reducing on-resistance.
  • one embodiment of a semiconductor element disclosed in this specification includes a first conductivity type semiconductor substrate, and a first conductivity type first silicon carbide provided on a main surface of the semiconductor substrate.
  • a semiconductor layer, a second conductivity type body region provided on the first silicon carbide semiconductor layer, a first conductivity type impurity region provided on the body region, and the first silicon carbide semiconductor layer A second silicon carbide semiconductor layer of a first conductivity type provided in contact with at least a part of the body region and at least a part of the impurity region, and a gate provided on the second silicon carbide semiconductor layer
  • the body region includes a first body region in contact with a surface of the first silicon carbide semiconductor layer, and a second body in contact with a bottom surface of the first body region.
  • the impurity concentration of the region is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate. At least a part of the two body regions is located below the impurity region.
  • the on-resistance can be reduced.
  • FIG. 1A is a cross-sectional view showing the semiconductor element according to the first embodiment.
  • FIG. 1B and FIG. 1C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the first embodiment.
  • FIG. 2A to FIG. 2D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 3A to FIG. 3D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 4A to FIG. 4C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 5A is a cross-sectional view showing a semiconductor element according to the second embodiment.
  • FIGS. 5B and 5C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the second embodiment.
  • FIG. 6A to FIG. 6D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 7A to FIG. 7D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 8A to FIG. 8C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view showing a main part of a method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a main part of a modified example of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 11 is a graph showing an example of the impurity profile of the body region in the semiconductor element according to the first and second embodiments.
  • FIG. 12 is a graph showing the relationship between the concentration of the JFET region and the depletion layer width at the time of breakdown between the JFET region and the body region in the semiconductor device according to the first and second embodiments, and the concentration of the JFET region And a maximum sidewall width.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a main part of a modified example of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 11 is a graph showing an example of the impurity profile of the body region
  • FIG. 13 is a graph showing the relationship between the amount of overlap between the JFET region and the body region and the threshold voltage in a conventional semiconductor device.
  • FIG. 14 is a graph showing the relationship between the on-resistance and the amount of overlap between the JFET region and the body region in the conventional semiconductor device.
  • FIG. 15A is a cross-sectional view showing a conventional semiconductor device.
  • FIG. 15B is a schematic plan view showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the conventional example.
  • FIG. 16A is a cross-sectional view showing a semiconductor element according to a modification of the first embodiment.
  • FIGS. 16B and 16C are schematic plan views showing the arrangement of a plurality of unit cells constituting a semiconductor element according to a modification of the first embodiment.
  • the semiconductor element disclosed in this specification includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity concentration of the first body region Is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and the second body region At least some of them are located below the impurity regions.
  • a region through which current flows is widened, so that the resistance of a JFET (junction field-effect transistor) region can be reduced.
  • a semiconductor element includes a first conductivity type semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer provided on a main surface of the semiconductor substrate, and a first silicon carbide semiconductor layer.
  • a second conductivity type body region provided in the upper portion; a first conductivity type impurity region provided in the upper portion of the body region; and at least a part of the body region on the first silicon carbide semiconductor layer;
  • a first conductivity type second silicon carbide semiconductor layer provided in contact with at least a part of the impurity region, a gate insulating film provided on the second silicon carbide semiconductor layer, and provided on the gate insulating film
  • the body region includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity in the first body region Concentration is the second body region
  • the second body region is higher than the impurity concentration and is located inside the first body region in a plan view in a direction perpendicular to the main
  • the semiconductor device of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer at a side of the body region, and a lower portion of the injection region is formed shallower than the body region.
  • the body region may be formed by doping a second conductivity type impurity so as to reverse the conductivity type of the implantation region.
  • the semiconductor element of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer on a side of the body region, and the injection region is formed deeper than the body region. It may be.
  • the impurity concentration of the first body region is 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less
  • the impurity concentration of the second body region is 1 ⁇ 10 17. cm -3 or more and is 1 ⁇ 10 19 cm -3 or less
  • the impurity concentration of the implanted region, 5 ⁇ 10 16 cm -3 or more and 5 ⁇ 10 17 cm -3 may be less.
  • the second silicon carbide semiconductor layer includes an upper layer in contact with the gate insulating film and a lower layer in contact with the first silicon carbide semiconductor layer, and the impurity concentration of the upper layer is lower than the impurity concentration of the lower layer. May be.
  • the semiconductor device of one embodiment further includes a first ohmic electrode electrically connected to the impurity region, and a second ohmic electrode provided on a surface of the semiconductor substrate opposite to the first silicon carbide semiconductor layer. It may be.
  • the second body region may be located on the same side as the impurity region or outside the impurity region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate.
  • a method of manufacturing a semiconductor device includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a step of forming the first silicon carbide semiconductor layer.
  • a step of forming a first conductivity type implantation region on the upper portion; a step of selectively forming a second conductivity type first body region on the implantation region; and a lower side of the first body region in the implantation region A step of selectively forming a second body region of the second conductivity type, and a step of selectively forming an impurity region of the first conductivity type on the upper portion of the first body region.
  • the second body region is formed deeper than the implantation region, and the impurity concentration of the second body region is lower than the impurity concentration of the first body region, and with respect to the main surface of the semiconductor substrate.
  • the first body region in plan view in a vertical direction Located inside, at least a portion of the second body region is formed to be located below the impurity regions.
  • At least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the impurity region.
  • a method of manufacturing a semiconductor device includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a first silicon carbide semiconductor layer. And selectively forming one of the second conductivity type first body region and the first conductivity type implantation region on the side of the one region in the first silicon carbide semiconductor layer. And forming the other of the first body region and the implantation region in a self-aligned manner with respect to the one region, and forming a second conductive layer under the first body region in the first silicon carbide semiconductor layer.
  • the region is formed deeper than the second body region, and the second body
  • the impurity concentration of the second body region is lower than the impurity concentration of the first body region and in a plan view in a direction perpendicular to the main surface of the semiconductor substrate,
  • the second body region is formed on the inner side so that at least part of the second body region is located below the impurity region.
  • At least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the implantation region.
  • FIG. 1A schematically shows a cross-sectional configuration of a semiconductor element 100 according to this embodiment.
  • FIG. 1A shows a cross section of two semiconductor elements 100 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 100u, and the semiconductor element 100 according to the present embodiment includes a plurality of unit cells 100u.
  • the present disclosure is not limited to the following embodiments and the like.
  • the numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, process steps, the order of the steps, and the like shown in the following embodiments are all examples.
  • constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements that constitute a preferred embodiment. .
  • Each figure is a schematic diagram and is not necessarily illustrated strictly. The same applies to the semiconductor elements according to other embodiments.
  • a semiconductor element 100 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) located on the main surface of the semiconductor substrate 101. Layer) 102.
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the first conductivity type may be p-type
  • the second conductivity type may be n-type.
  • the semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC).
  • First silicon carbide semiconductor layer 102 is n ⁇ type. The “+” or “ ⁇ ” on the right shoulder of the n or p conductivity type represents the relative concentration of impurities.
  • n + means that the n-type impurity concentration is higher than “n”
  • n ⁇ means that the n-type impurity concentration is lower than “n”.
  • a plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 100u, A one-conductivity type JFET region 102j is formed.
  • the JFET region 102j refers to a first conductivity type region adjacent to the body region 103, that is, a first conductivity type region sandwiched between the body regions 103 of two adjacent unit cells 100u.
  • the second conductivity type body region 103 is formed by introducing a second conductivity type impurity into the first conductivity type implantation region 102 i formed above the first silicon carbide semiconductor layer 102. Is done.
  • the body region 103 includes both the first conductivity type impurity and the second conductivity type impurity, and the second conductivity type impurity concentration is higher than the first conductivity type impurity concentration in the implantation region 102i. Defined as an area that is high. On the bottom surface of body region 103, the first conductivity type impurity concentration in the region in contact with body region 103 in first silicon carbide semiconductor layer 102 is equal to the second conductivity type impurity concentration in body region 103.
  • the body region 103 includes a second conductivity type first body region 103a and a second conductivity type second body region 103b.
  • First body region 103a is in contact with the surface of first silicon carbide semiconductor layer 102, and the upper surface of second body region 103b is in contact with the bottom surface of first body region 103a.
  • the thickness of the first body region 103a is, for example, at least 15 nm, and the thickness of the second body region 103b is, for example, at least 100 nm.
  • the thickness of each of the regions 103a and 103b is a thickness in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the first body region 103a is p + type
  • the second body region 103b is p type.
  • the average impurity concentration of the first body region 103a can be set to be twice or more the average impurity concentration of the second body region 103b.
  • the second body region 103b is located inside the first body region 103a in a so-called planar view as seen from a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is provided such that the width of the second body region 103b is smaller than the width of the first body region 103a.
  • a first conductivity type impurity region 104 is provided on the first body region 103a.
  • the conductivity type of the impurity region 104 is n + type.
  • the second body region 103 b is provided so as to be located at the same position as the impurity region 104 or outside the impurity region 104 in a plan view with respect to the main surface of the semiconductor substrate 101. Accordingly, at least a part of the second body region 103 b is located below the impurity region 104. Thus, in the present embodiment, at least a part of the second body region 103b is provided below the impurity region 104 that is the source region. For this reason, generation
  • a second conductivity type contact region 105 can be provided in the first body region 103a.
  • the conductivity type of contact region 105 may be p + type.
  • Contact region 105 is in contact with second body region 103b.
  • a source electrode (first ohmic electrode) 109 is provided on the impurity region 104.
  • the source electrode 109 is formed on the surfaces of the impurity region 104 and the contact region 105 and is in electrical contact with both the impurity region 104 and the contact region 105.
  • the contact region 105 may not be provided.
  • a contact trench exposing the first body region 103a is provided in the impurity region 104, and the source electrode 109 is formed at the bottom of the provided contact trench, whereby the first body region 103a and the source electrode 109 are directly connected. You may make it contact.
  • the portion where the contact region 105 is formed may be non-implanted so that the first body region 103a is exposed and the first body region 103a and the source electrode 109 are in direct contact with each other. .
  • the JFET region 102j which is the first conductivity type region sandwiched between the body regions 103 in the two unit cells 100u adjacent to each other is formed in the implantation region 102i. Therefore, the impurity concentration in the JFET region 102j is the same as that in the implantation region 102i.
  • the depth of the implantation region 102i is set to a depth at least up to the lower side of the first body region 103a. The reason is that the on-resistance of the semiconductor element 100 is increased by reducing the on-resistance of a region sandwiched between two adjacent first body regions 103a, that is, a region serving as a current path that flows when the semiconductor element 100 is on. Because. In the present embodiment, as shown in FIG. 1A, the depth of the implantation region 102i can be set shallower than the depth of the second body region 103b.
  • a second conductivity type second silicon carbide semiconductor layer 106 is provided in contact with at least part of the body region 103 and at least part of the impurity region 104, respectively.
  • Second silicon carbide semiconductor layer 106 is electrically connected to JFET region 102j adjacent to first body region 103a in impurity region 104 and first silicon carbide semiconductor layer 102, and on top of first body region 103a. Can be formed.
  • the second silicon carbide semiconductor layer 106 is formed by epitaxial growth.
  • Second silicon carbide semiconductor layer 106 includes a channel region 106c in a region in contact with first body region 103a.
  • the length of the channel region 106c corresponds to the length indicated by the two bidirectional arrows shown in FIG. That is, the “channel length” of the MISFET is determined by the length of the upper surface of the first body region 103 a, that is, the length of the interface with the first body region 103 a in the second silicon carbide semiconductor layer 106.
  • the second silicon carbide semiconductor layer (channel layer) 106 has a dopant concentration distribution in a direction perpendicular to the semiconductor substrate 101.
  • the second silicon carbide semiconductor layer 106 is expressed by a two-layered structure, the side in contact with the impurity region 104 is the lower layer 106b, and the layer located above the lower layer 106b is the upper layer 106a.
  • Lower layer 106b of second silicon carbide semiconductor layer 106 has an n-type dopant.
  • the upper layer 106a of the second silicon carbide semiconductor layer 106 is in an undoped state, for example, having a very low dopant concentration.
  • a gate insulating film 107 is provided on the second silicon carbide semiconductor layer 106.
  • a gate electrode 108 is provided on the gate insulating film 107. The gate electrode 108 is located at least above the channel region 106c.
  • An interlayer insulating film 111 is provided on the gate electrode 108 so as to cover the gate electrode 108.
  • An upper wiring 112 is provided on the interlayer insulating film 111.
  • the upper wiring 112 is connected to the source electrode 109 through a contact hole 111 a provided in the interlayer insulating film 111.
  • a drain electrode (second ohmic electrode) 110 is provided on the back surface of the semiconductor substrate 101 opposite to the first silicon carbide semiconductor layer 102.
  • the drain electrode 110 is further provided with a back surface wiring 113.
  • Each unit cell 100u constituting the semiconductor element 100 has, for example, a square shape when the semiconductor element 100 is viewed from the upper wiring 112 side.
  • Each unit cell 100u is not limited to a square shape, and may be a rectangular shape or may have a polygonal shape other than a square shape.
  • FIG. 1B shows an arrangement of a plurality of unit cells 100u. As shown in FIG. 1B, the unit cells 100u are, for example, two-dimensionally arranged in the x direction and the y direction, and the arrangement in the y direction is alternately shifted by half in the x direction. ing. When the unit cells 100u have a rectangular shape extending in one direction, the unit cells 100u may be arranged in parallel as shown in FIG.
  • the semiconductor element 100 is configured by the plurality of unit cells 100u arranged in this way.
  • second silicon carbide semiconductor layer 106 In semiconductor element 100, second silicon carbide semiconductor layer 106, gate electrode 108 that controls current flowing through second silicon carbide semiconductor layer 106, gate insulating film 107, and second silicon carbide semiconductor layer 106 are electrically connected.
  • the source electrode 109 and the drain electrode 110 thus formed constitute a MISFET.
  • the drain electrode 110 potential with reference to the source electrode 109 potential is Vds
  • the gate electrode 108 potential with reference to the source electrode 109 potential is Vgs
  • the threshold voltage of the MISFET (threshold voltage of the forward current) is Vth.
  • the MISFET is turned on when Vgs ⁇ Vth, and when Vds> 0 V, the semiconductor substrate 101, the first silicon carbide semiconductor layer (drift layer) 102, the JFET region 102j, the second carbonization are formed from the drain electrode 110.
  • a current flows to the source electrode 109 through the silicon semiconductor layer (channel layer) 106 and the impurity region 104 which is a source region.
  • the on-resistance in this region is the mobility in the JFET region 102j is ⁇ j, and the interval between two adjacent first body regions 103a is the same.
  • the distance between two adjacent second body regions 103b is a2
  • the dopant concentration of the JFET region 102j is Nj
  • the surface of the first silicon carbide semiconductor layer 102 in the body region 103 corresponds to the channel width as the JFET region 102j
  • the depth of the first body region 103a from the surface of the first silicon carbide semiconductor layer 102 is Lp1
  • the depth of the second body region 103b from the bottom of the first body region 103a is Lp2.
  • the mobility in the JFET region 2j according to the conventional example is ⁇ j
  • the interval between two adjacent body regions 3 is a
  • the dopant concentration in the JFET region 2j is Nj
  • the JFET region 2j The length of the boundary line on the surface of the first silicon carbide semiconductor layer 2 in the body region 3 corresponding to the channel width of W is W
  • the depth of the body region 3 from the surface of the first silicon carbide semiconductor layer 2 is Lp. .
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in the direction perpendicular to the main surface of the semiconductor substrate 101, and The two body regions 103b are located inside the first body region 103a. Therefore, as shown in FIG. 1 (a), since the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a satisfy a2> a1, [value of expression (1)] ⁇ [Value of Expression (2)] is realized. That is, the on-resistance of the semiconductor element 100 according to the present embodiment can be reduced as compared with the conventional semiconductor element 50.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 ⁇ cm.
  • a high-resistance first silicon carbide semiconductor is formed on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as a chemical vapor deposition (CVD) method.
  • Layer 102 is grown epitaxially.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m. Subsequently, nitrogen (N) ions are implanted into the first silicon carbide semiconductor layer 102 to form an n-type implanted region 102i.
  • the impurity concentration of the implantation region 102i is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth is, for example, 0.5 ⁇ m.
  • a mask film 201 made of, for example, silicon oxide (SiO 2 ) and having the formation pattern of the first body region 103a in the opening on the implantation region 102i is used as a mask.
  • silicon oxide (SiO 2 ) For example, aluminum (Al) ions are implanted into the implantation region 102i to form the p + -type first body region 103a.
  • the JFET region 102j is formed from the implantation region 102i in a self-aligned manner with respect to the first body region 103a.
  • a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 201 by, eg, CVD.
  • Al ions are implanted into the implantation region 102 and the first silicon carbide semiconductor layer 102 thereunder through the sidewall formation film 202 to form the p-type second body region 103b.
  • the implanted Al ions are masked by the mask film 201 and the portion of the sidewall formation film 202 formed on the side surface of the opening of the mask film 201.
  • the second body region 103b It is formed so as to be located on the inner side from the periphery or the side of the region 103a.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 201 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 2D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming the impurity region 104 on the first body region 103a.
  • width of the sidewall 202a can be set as follows.
  • FIG. 12 shows that the sidewall width that can deplete the JFET region 102j before the avalanche breakdown occurs is the maximum sidewall width when the width of the JFET region 102j is 1 ⁇ m and 0.5 ⁇ m. Show.
  • the horizontal axis in FIG. 12 represents the impurity concentration of the first conductivity type in the JFET region 102j.
  • the solid line indicates the maximum sidewall width when the width of the JFET region 102j is 0.5 ⁇ m
  • the alternate long and short dash line indicates the maximum sidewall width when the width of the JFET region 102j is 1 ⁇ m.
  • the thick line indicates the width of the depletion layer at the time of avalanche breakdown.
  • the width of the sidewall 202a can be set so as to be a value equal to or smaller than the maximum sidewall width shown in FIG.
  • the thickness of the sidewall 202a is selected so as to have a sidewall width that can deplete the JFET region 102j, and, for example, Al ions are implanted to form the second body region 103b. Form.
  • the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
  • a mask film 205 made of SiO 2 having an opening at a portion of the first body region 103a where the contact region is formed is formed.
  • Al ions are implanted to form a p-type contact region 105 at substantially the center of the impurity region 104 and the first body region.
  • the contact region 105 may be formed so as to reach the second body implantation region 103b.
  • the mask film 205 is removed, and high-temperature heat treatment (activation annealing) is performed to activate the impurities implanted into the first silicon carbide semiconductor layer 102.
  • high-temperature heat treatment activation annealing
  • the first body region 103a, the second body region 103b, the impurity region 104, the contact region 105, and the JFET region 102j are formed.
  • the ion implantation profile is determined so that the depth of the first body region 103a is, for example, 300 nm and the average impurity concentration is about 1.6 ⁇ 10 19 cm ⁇ 3 .
  • the total depth of the body region 103 including the first body region 103a and the second body region 103b is, for example, 550 nm, and the average impurity concentration of the second body region 103b is about 2 ⁇ 10 18 cm ⁇ 3 .
  • the ion implantation profile is adjusted so that The depth of the impurity region 104 is, for example, 250 nm, and the ion implantation profile is adjusted so that the average impurity concentration is about 5 ⁇ 10 19 cm ⁇ 3 .
  • the depth of the first body region 103a is determined by the boundary shown in FIG. 11, and the depth of the second body region 103b is set to a depth at which, for example, an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
  • the depth of the impurity region 104 is set to a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained, for example.
  • the impurity concentration is calculated as follows, for example. As shown in FIG. 11, the relationship between the depth direction and the impurity concentration in a certain cross section is clarified using, for example, SIMS (secondary ion mass spectrometry), and then the region in the depth direction is defined. Since the depth of the first body region 103a is defined as the depth determined by the boundary shown in FIG. 11, the depth is 0.28 ⁇ m.
  • the impurity concentration is integrated in the depth direction and converted into a sheet dose (unit dimension is cm ⁇ 2 ). The impurity concentration is calculated by dividing the sheet dose calculated here by the depth of the region (here, 0.28 ⁇ m).
  • the depth of the contact region 105 is, for example, 400 nm, the average impurity concentration is about 1 ⁇ 10 20 cm ⁇ 3 , and the depth is, for example, a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
  • the surface layer of the first silicon carbide semiconductor layer 102 may be removed in order to clean the surface of the first silicon carbide semiconductor layer 102 after the activation annealing.
  • the depths of the first body region 103a, the impurity region 104, and the contact region 105 are all reduced by about 50 nm and become 250 nm, 200 nm, and 350 nm, respectively.
  • the second silicon carbide semiconductor layer is formed on the entire surface of the first silicon carbide semiconductor layer 102 including the JFET region 102j, the first body region 103a, the impurity region 104, and the contact region 105.
  • 106 is epitaxially grown.
  • second silicon carbide semiconductor layer 106 includes upper layer 106a and lower layer 106b.
  • the upper layer 106a is continuously formed on the lower layer 106b.
  • the dopant concentration of the lower layer 106b is, for example, about 2 ⁇ 10 18 cm ⁇ 3 and the film thickness is, for example, 24 nm.
  • the lower layer 106b is formed by doping nitrogen (N)
  • the introduction of the doping gas is stopped and the upper layer 106a is continuously formed so as to have a film thickness of about 26 nm.
  • the gate insulating film 107 is formed on the surface of the second silicon carbide semiconductor layer upper layer 106a by, eg, thermal oxidation.
  • a polycrystalline silicon film doped with phosphorus (P) at a concentration of about 7 ⁇ 10 20 cm ⁇ 3 is deposited on the gate insulating film 107.
  • the thickness of the polycrystalline silicon film is, for example, about 500 nm.
  • a resist pattern (not shown) having a gate electrode formation pattern is formed on the polycrystalline silicon film by lithography, and the polycrystalline silicon film is dry-etched using the formed resist pattern.
  • a plurality of gate electrodes 108 made of polycrystalline silicon are formed in a predetermined region.
  • an interlayer insulating film 111 containing, for example, SiO 2 is deposited by the CVD method so as to cover the surface of the gate electrode 108 and the surface of the first silicon carbide semiconductor layer 102.
  • the thickness of the interlayer insulating film 111 is, for example, 1.5 ⁇ m.
  • the upper part of the contact region 105 and the upper part of the impurity region 104 in the interlayer insulating film 111 are removed by dry etching using a mask (not shown). As a result, a contact hole 111 a is formed in the interlayer insulating film 111.
  • a nickel (Ni) film having a thickness of, for example, about 50 nm is formed on the interlayer insulating film 111 by vacuum deposition or sputtering. Subsequently, as shown in FIG. 4B, the nickel film is reacted with the exposed portion of the silicon carbide from the interlayer insulating film 111 by performing a heat treatment in an inert atmosphere, for example, at a temperature of 950 ° C. for 5 minutes. Then, the source electrode 109 made of nickel silicide (NiSi) is formed.
  • the unreacted nickel film on the interlayer insulating film 111 is removed by etching. Thereafter, as shown in FIG. 4C, a nickel film, for example, is deposited on the entire back surface of the semiconductor substrate 101 and reacted with silicon carbide by the same heat treatment to form the drain electrode 110.
  • an upper wiring 112 is formed by depositing an aluminum (Al) film having a thickness of about 4 ⁇ m on the interlayer insulating film 111 and inside the contact hole 111a, and etching it into a desired pattern.
  • Al aluminum
  • a gate wiring or a gate pad that contacts the gate electrode 108 is formed at the end of the chip.
  • titanium (Ti) / nickel (Ni) / silver (Ag) is deposited on the back surface of the drain electrode 110 as the back surface wiring 113 for die bonding from the drain electrode 110 side. In this way, the semiconductor element 100 shown in FIG. 1 is obtained.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the second body region 103b is disposed inside the first body region 103a in plan view.
  • the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlapping dimension of the body region 103 and the implantation region 102i. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
  • FIG. 15 shows a cross-sectional view of a semiconductor element having a conventional structure.
  • a semiconductor element 50 according to a conventional example includes an n-type semiconductor substrate 1 and an n-type first silicon carbide semiconductor layer 2 formed on the main surface of the semiconductor substrate 1.
  • a plurality of p-type body regions 3 are formed on top of first silicon carbide semiconductor layer 2, and n-type JFET region 2j is formed between body regions 3 included in adjacent unit cells 50u. Yes.
  • the body region 3 includes a first body region 3a and a second body region 3b below the first body region 3a.
  • the width of the first body region 3a and the width of the second body region 3b are formed to be equal, and the JFET region 2j is formed so as to overlap the body region 3.
  • An n-type impurity region 4 is formed above the first body region 3a, and a source electrode 9 is formed above the impurity region 4.
  • a source electrode 9 is formed above the impurity region 4.
  • a gate electrode 8 is formed on second silicon carbide semiconductor layer 6 with gate insulating film 7 interposed.
  • FIG. 13 shows the relationship between the amount of overlap between the JFET region 2j and the body region 3 and the threshold voltage in the conventional structure.
  • 3.2 V is obtained as a simulation value.
  • FIG. 14 shows the relationship between the ON resistance and the amount of overlap between the JFET region 2j and the body region 3 in the conventional structure.
  • 6.0 m ⁇ ⁇ cm 2 is obtained as a simulation value.
  • the conventional structure is formed by aligning the JFET region and the body region, the amount of overlap between the JFET region and the body region varies. Accordingly, since the amount of overlap between the JFET region and the body region varies, the threshold voltage and the on-resistance vary as shown in FIGS.
  • the semiconductor element 100 according to the present embodiment by forming the JFET region 102j in a self-aligning manner, it is possible to suppress fluctuations in threshold voltage and fluctuations in on-resistance while reducing on-resistance.
  • FIG. 5A schematically shows a cross-sectional configuration of the semiconductor element 300 according to the present embodiment.
  • FIG. 5A shows a cross section of two semiconductor elements 300 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 300u, and the semiconductor element 300 according to the present embodiment includes a plurality of unit cells 300u.
  • the same components as those in the first embodiment are denoted by the same reference numerals. Therefore, the description regarding the same content and the same component as 1st Embodiment may be abbreviate
  • Semiconductor element 300 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) 102 located on the main surface of semiconductor substrate 101. Also in this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type.
  • the semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC).
  • First silicon carbide semiconductor layer 102 is n ⁇ type.
  • a plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 300u, A one-conductivity type JFET region 102j is formed.
  • the impurity concentration is the same as that of the implantation layer 102i.
  • the depth of the implantation region 102i can be set to be deeper than at least the first body region 103a. Further, in the present embodiment, as shown in FIG. 5A, the depth of the implantation region 102i can be set to be deeper than the second body region 103b. In this embodiment, since the implantation region 102i is formed only in a region sandwiched between adjacent body regions 103, the depth of the implantation region 102i is set to be deeper than the second body region 103b. However, the JFET region 102j is not formed under the second body region 103b.
  • the on-resistance of the region sandwiched between the two adjacent first body regions 103a that is, the region serving as a current path that flows when the semiconductor element 300 is turned on, is further reduced while maintaining the withstand voltage.
  • the on-current can be further increased.
  • Each unit cell 300u constituting the semiconductor element 300 has, for example, a square shape when the semiconductor element 300 is viewed from the upper wiring 112 side.
  • Each unit cell 300u is not limited to a square shape but may be a rectangle or may have a polygonal shape other than a quadrangle.
  • FIG. 5B shows an arrangement of a plurality of unit cells 300u. As shown in FIG. 5B, the unit cells 300u are, for example, arranged two-dimensionally in the x and y directions, and the arrangement in the y direction is alternately shifted by a half in the x direction. Yes. When the unit cells 300u have a rectangular shape extending in one direction, the unit cells 300u may be arranged in parallel as shown in FIG.
  • the semiconductor element 300 is constituted by the plurality of unit cells 300u arranged in this way.
  • the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a have a relationship of a2> a1, and therefore, the semiconductor element 300 according to the present embodiment.
  • the on-resistance can be reduced as compared with the conventional semiconductor element 50.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low-resistance n-type 4H—SiC offcut substrate having a resistivity of about 0.02 ⁇ cm.
  • the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as CVD.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • a mask film 211 made of, for example, polysilicon and having a formation pattern of the first body region 103a in the opening on the first silicon carbide semiconductor layer 102 is used as a mask.
  • Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the p + -type first body region 103a.
  • FIG. 6C a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 211 by, eg, CVD. Thereafter, for example, Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b.
  • FIG. 11 shows an example of the ion implantation profile in the AB section of FIG.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 211 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 6D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form the sidewall 202a and the mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
  • the width of the sidewall 202a can be set to be a value equal to or smaller than the width of the sidewall described in FIG. 12, for example.
  • the thickness of the sidewall is selected so as to have a sidewall width that can deplete a JFET region formed in a later process, and Al ions are implanted, for example, to form the second body region. 103b is formed. Thereafter, the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
  • a mask formation film (not shown) made of SiO 2 is deposited so as to cover the impurity region 104 including the mask films 211 and 202b and the sidewalls 202a.
  • the upper surface of the deposited mask forming film is planarized by a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • the mask film 211 is selectively removed from the mask formation film by etching or the like, and a mask film 206 having a formation pattern of the JFET region 102j in the opening is formed.
  • N ions are implanted into the first silicon carbide semiconductor layer 102 using the mask film 206 as a mask to form a JFET region 102j.
  • the impurity concentration of the JFET region 102j is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth thereof is, for example, 0.5 ⁇ m.
  • the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a.
  • the high-density plasma non-doped silica glass (HDP-NSG) method or SOG (Spin On Glass) method and the CMP method are combined with the formation of the mask formation film and the mask film 206. Can do.
  • the mask film 206 is removed. Thereafter, the steps shown in FIGS. 7B to 9 are performed to obtain the semiconductor element 300 shown in FIG. Since the steps shown in FIGS. 7B to 9 are the same as the steps shown in FIGS. 3A to 4C in the first embodiment, description thereof will be omitted.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the second body region 103b is disposed inside the first body region 103a in plan view.
  • the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlap dimension between the body region 103 and the JFET region 102j. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 ⁇ cm.
  • the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by, for example, a deposition method capable of epitaxial growth such as a CVD method.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • a polysilicon film 216 and a silicon nitride film 207 are sequentially deposited on the first silicon carbide semiconductor layer 102. Thereafter, the deposited polysilicon film 216 and silicon nitride film 207 are selectively etched to form a mask film 206A having a formation pattern of the JFET region 102j in the opening. Thereafter, N ions are implanted into first silicon carbide semiconductor layer 102 using mask film 206A as a mask to form JFET region 102j.
  • the impurity concentration of the JFET region 102j is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth thereof is, for example, 0.5 ⁇ m.
  • a mask formation film (not shown) made of SiO 2 is deposited on the JFET region 102j including the mask film 206A by, for example, the CVD method. Thereafter, the surfaces of the mask formation film and the mask film 206A are planarized by a CMP method or the like. Subsequently, the mask film 206A is selectively removed to form a mask film 208 that is an inverted region of the mask film 206A from the mask formation film and has an opening in the formation pattern of the first body region. Thereafter, as shown in FIG. 10B, using the mask film 208 as a mask, for example, Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the first body region 103a. As a result, the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a.
  • the polysilicon film 216 is thermally oxidized using the silicon nitride film 207 as a mask to form the mask film 208 in a self-aligning manner.
  • a silicon oxide film grows laterally from the side surface of the polysilicon film 216 to cover the JFET region 102j.
  • a mask film 208 is formed by selectively removing the mask film 206A so as to leave the grown silicon oxide film.
  • the silicon nitride film 207 is not necessarily provided in the case where a deposited film by a CVD method is used for the mask film 208.
  • a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 208 by, eg, CVD.
  • Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b.
  • An example of the ion implantation profile in the cross section AB in FIG. 10C is shown in FIG.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 208 and the sidewall formation film 202 by lithography.
  • the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202.
  • the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is disposed inside the first body region 103a in plan view. With this configuration, the dimension corresponding to the distance a2 between the adjacent second body regions 103b can be increased, so that the on-resistance can be reduced.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced and current can be flowed stably, so that fluctuations in on-resistance and threshold voltage can be suppressed.
  • a JFET region 102j having a first conductivity type impurity having a concentration higher than that of the first silicon carbide semiconductor layer 102 is formed by ion implantation into the first silicon carbide semiconductor layer 102.
  • the present invention is not limited to this. That is, in the JFET region 102j in the semiconductor elements 100 and 300, ion implantation into the first silicon carbide semiconductor layer 102 is not performed, and the impurity concentration of the first conductivity type in the JFET region 102j is equal to that of the first silicon carbide semiconductor layer 102. It may be the same as the impurity concentration of one conductivity type.
  • FIG. 16 shows a modification of the semiconductor element in the case where the first conductivity type impurity concentration of the JFET region 102 j is the same as the first conductivity type impurity concentration of the first silicon carbide semiconductor layer 102.
  • the n-type MISFET has been described as the semiconductor elements 100 and 300.
  • a p-type MISFET can also be used.
  • the conductivity type of the semiconductor substrate, the first silicon carbide semiconductor layer (drift layer), and the source region may be p-type, and the conductivity type of the body region may be n-type.
  • the present invention is not limited to the MISFET, and various semiconductor elements in which electrodes are arranged on the semiconductor layer via an insulating film can be formed in the same manner.
  • an insulated gate bipolar transistor IGBT
  • the source electrode, drain electrode, and source region described in each embodiment are referred to as an emitter electrode, a collector electrode, and an emitter region, respectively.
  • an n-type IGBT can be obtained.
  • an n-type buffer layer may be disposed between the p-type semiconductor substrate and the n-type drift layer.
  • a p-type IGBT can be obtained.
  • a p-type buffer layer may be disposed between the n-type semiconductor substrate and the p-type drift layer.
  • the present invention can also be applied to semiconductor elements using other wide band gap semiconductors such as gallium nitride (GaN) or diamond (C).
  • GaN gallium nitride
  • C diamond
  • the configuration of the present disclosure can also be applied to a semiconductor element using silicon.
  • the semiconductor element and the manufacturing method thereof according to the present disclosure are useful as various semiconductor elements including a power device and the manufacturing method thereof.

Abstract

This semiconductor element has: a second conductivity-type body region in an upper portion of a first silicon carbide semiconductor layer; a first conductivity-type impurity region in an upper portion of the body region; and a first conductivity-type second silicon carbide semiconductor layer that is provided on the first silicon carbide semiconductor layer, said second silicon carbide semiconductor layer being in contact with at least a part of the body region and a part of the impurity region. The body region includes a first body region in contact with the front surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region. An impurity concentration of the first body region is higher than that of the second body region. The second body region is positioned on the inner side of the first body region in a planar view in the direction perpendicular to the main surface of a semiconductor substrate, and at least a part of the second body region is positioned below the impurity region.

Description

半導体素子及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体素子及びその製造方法に関し、特に、高耐圧用又は大電流用に使用される炭化珪素半導体素子及びその製造方法に関する。 The present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor element used for high withstand voltage or large current and a manufacturing method thereof.
　炭化珪素（シリコンカーバイド：ＳｉＣ）は、珪素（Ｓｉ）と比べてバンドギャップが大きい高硬度の半導体材料であり、パワー素子、耐環境素子、高温動作素子又は高周波素子等の種々の半導体素子に応用されている。なかでも、半導体素子及び整流素子等のパワー素子への応用が注目されている。ＳｉＣを用いたパワー素子は、Ｓｉパワー素子よりも電力損失を大幅に低減できる等の利点がある。また、ＳｉＣパワー素子は、そのような特性を活かして、Ｓｉパワー素子と比較して、より小型の半導体素子を実現することができる。 Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material having a larger band gap than silicon (Si), and is applied to various semiconductor elements such as power elements, environment-resistant elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power elements, such as a semiconductor element and a rectifier, attracts attention. A power element using SiC has advantages such as a significant reduction in power loss compared to a Si power element. Further, the SiC power element can realize a smaller semiconductor element as compared with the Si power element by utilizing such characteristics.
　ＳｉＣを用いたパワー素子のうち、代表的な半導体素子は、金属－絶縁体－半導体電界効果トランジスタ（Metal-Insulator-Semiconductor Field-Effect Transistor：ＭＩＳＦＥＴ）である（例えば、特許文献１を参照。）。以下、ＳｉＣにより構成されたＭＩＳＦＥＴを、単に「ＳｉＣ－ＦＥＴ」と称する場合がある。金属－酸化物－半導体電界効果トランジスタ（Metal-Oxide-Semiconductor Field-Effect Transistor：ＭＯＳＦＥＴ）は、ＭＩＳＦＥＴの一種である。 Among power elements using SiC, a typical semiconductor element is a metal-insulator-semiconductor field-effect transistor (MISFET) (see, for example, Patent Document 1). . Hereinafter, the MISFET composed of SiC may be simply referred to as “SiC-FET”. A metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor-Field-Effect-Transistor: MOSFET) is a kind of MISFET.
国際公開第２０１２／０５６７０４号International Publication No. 2012/0567704
　特許文献１に記載された半導体素子は、第１ボディ領域及び第２ボディ領域に分割されたボディ領域を備えている。特許文献１に記載された半導体素子によれば、第１ボディ領域及び第２ボディ領域の不純物濃度を制御することにより、閾値電圧及びオン抵抗等の電気特性を制御することができる。 The semiconductor element described in Patent Document 1 includes a body region divided into a first body region and a second body region. According to the semiconductor element described in Patent Document 1, electrical characteristics such as threshold voltage and on-resistance can be controlled by controlling the impurity concentrations of the first body region and the second body region.
　しかしながら、半導体素子において、オン抵抗の更なる低減が望まれている。 However, further reduction of on-resistance is desired in semiconductor devices.
　本明細書において開示される技術は、オン抵抗の低減が可能な半導体素子を実現することを目的とする。 The technology disclosed in this specification aims to realize a semiconductor element capable of reducing on-resistance.
　前記の目的を達成するため、本明細書において開示される半導体素子の一態様は、第１導電型の半導体基板と、半導体基板の主面上に設けられた第１導電型の第１炭化珪素半導体層と、第１炭化珪素半導体層の上部に設けられた第２導電型のボディ領域と、ボディ領域の上部に設けられた第１導電型の不純物領域と、第１炭化珪素半導体層の上であって、ボディ領域の少なくとも一部及び不純物領域の少なくとも一部とそれぞれ接して設けられた第１導電型の第２炭化珪素半導体層と、第２炭化珪素半導体層の上に設けられたゲート絶縁膜と、ゲート絶縁膜の上に設けられたゲート電極とを備え、ボディ領域は、第１炭化珪素半導体層の表面と接する第１ボディ領域と、第１ボディ領域の底面と接する第２ボディ領域とを含み、第１ボディ領域の不純物濃度は、第２ボディ領域の不純物濃度よりも高く、第２ボディ領域は、半導体基板の主面に対して垂直な方向の平面視において、第１ボディ領域の内側に位置し、第２ボディ領域のうち少なくとも一部は、不純物領域の下方に位置する。 In order to achieve the above object, one embodiment of a semiconductor element disclosed in this specification includes a first conductivity type semiconductor substrate, and a first conductivity type first silicon carbide provided on a main surface of the semiconductor substrate. A semiconductor layer, a second conductivity type body region provided on the first silicon carbide semiconductor layer, a first conductivity type impurity region provided on the body region, and the first silicon carbide semiconductor layer A second silicon carbide semiconductor layer of a first conductivity type provided in contact with at least a part of the body region and at least a part of the impurity region, and a gate provided on the second silicon carbide semiconductor layer The body region includes a first body region in contact with a surface of the first silicon carbide semiconductor layer, and a second body in contact with a bottom surface of the first body region. A first body including an area The impurity concentration of the region is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate. At least a part of the two body regions is located below the impurity region.
　本明細書において開示される半導体素子及びその製造方法によれば、オン抵抗を低減することができる。 According to the semiconductor element and the manufacturing method thereof disclosed in this specification, the on-resistance can be reduced.
図１（ａ）は第１の実施形態に係る半導体素子を示す断面図である。図１（ｂ）及び図１（ｃ）は第１の実施形態に係る半導体素子を構成する複数のユニットセルの配置を示す模式的な平面図である。FIG. 1A is a cross-sectional view showing the semiconductor element according to the first embodiment. FIG. 1B and FIG. 1C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the first embodiment. 図２（ａ）から図２（ｄ）は第１の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 2A to FIG. 2D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment. 図３（ａ）から図３（ｄ）は第１の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 3A to FIG. 3D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment. 図４（ａ）から図４（ｃ）は第１の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 4A to FIG. 4C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment. 図５（ａ）は第２の実施形態に係る半導体素子を示す断面図である。図５（ｂ）及び図５（ｃ）は第２の実施形態に係る半導体素子を構成する複数のユニットセルの配置を示す模式的な平面図である。FIG. 5A is a cross-sectional view showing a semiconductor element according to the second embodiment. FIGS. 5B and 5C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the second embodiment. 図６（ａ）から図６（ｄ）は第２の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 6A to FIG. 6D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment. 図７（ａ）から図７（ｄ）は第２の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 7A to FIG. 7D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment. 図８（ａ）から図８（ｃ）は第２の実施形態に係る半導体素子の製造方法の要部を示す工程順の断面図である。FIG. 8A to FIG. 8C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the second embodiment. 図９は第２の実施形態に係る半導体素子の製造方法の要部を示す一工程の断面図である。FIG. 9 is a cross-sectional view showing a main part of a method for manufacturing a semiconductor device according to the second embodiment. 図１０（ａ）から図１０（ｄ）は第２の実施形態に係る半導体素子の製造方法の一変形例の要部を示す工程順の断面図である。FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a main part of a modified example of the method for manufacturing a semiconductor device according to the second embodiment. 図１１は第１及び第２の実施形態に係る半導体素子におけるボディ領域の不純物プロファイルの一例を示すグラフである。FIG. 11 is a graph showing an example of the impurity profile of the body region in the semiconductor element according to the first and second embodiments. 図１２は第１及び第２の実施形態に係る半導体素子におけるＪＦＥＴ領域の濃度と、ＪＦＥＴ領域とボディ領域との間のブレイクダウン時の空乏層幅との関係を示すグラフ、及びＪＦＥＴ領域の濃度と最大サイドウォール幅との関係を示すグラフである。FIG. 12 is a graph showing the relationship between the concentration of the JFET region and the depletion layer width at the time of breakdown between the JFET region and the body region in the semiconductor device according to the first and second embodiments, and the concentration of the JFET region And a maximum sidewall width. 図１３は従来例に係る半導体素子におけるＪＦＥＴ領域とボディ領域との重なり量と閾値電圧との関係を示すグラフである。FIG. 13 is a graph showing the relationship between the amount of overlap between the JFET region and the body region and the threshold voltage in a conventional semiconductor device. 図１４は従来例に係る半導体素子におけるＪＦＥＴ領域とボディ領域との重なり量とオン抵抗との関係を示すグラフである。FIG. 14 is a graph showing the relationship between the on-resistance and the amount of overlap between the JFET region and the body region in the conventional semiconductor device. 図１５（ａ）は従来例に係る半導体素子を示す断面図である。図１５（ｂ）は従来例に係る半導体素子を構成する複数のユニットセルの配置を示す模式的な平面図である。FIG. 15A is a cross-sectional view showing a conventional semiconductor device. FIG. 15B is a schematic plan view showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the conventional example. 図１６（ａ）は第１の実施形態の一変形例に係る半導体素子を示す断面図である。図１６（ｂ）及び図１６（ｃ）は第１の実施形態の一変形例に係る半導体素子を構成する複数のユニットセルの配置を示す模式的な平面図である。FIG. 16A is a cross-sectional view showing a semiconductor element according to a modification of the first embodiment. FIGS. 16B and 16C are schematic plan views showing the arrangement of a plurality of unit cells constituting a semiconductor element according to a modification of the first embodiment.
　本明細書に開示される半導体素子は、第１炭化珪素半導体層の表面と接する第１ボディ領域と、第１ボディ領域の底面と接する第２ボディ領域とを含み、第１ボディ領域の不純物濃度は、第２ボディ領域の不純物濃度よりも高く、第２ボディ領域は、半導体基板の主面に対して垂直な方向の平面視において、第１ボディ領域の内側に位置し、第２ボディ領域のうち少なくとも一部は、不純物領域の下方に位置する。この構成により、電流が流れる領域が広がるため、ＪＦＥＴ（接合型電界効果トランジスタ：Junction Field-Effect Transistor）領域の抵抗を下げることができる。 The semiconductor element disclosed in this specification includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity concentration of the first body region Is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and the second body region At least some of them are located below the impurity regions. With this configuration, a region through which current flows is widened, so that the resistance of a JFET (junction field-effect transistor) region can be reduced.
　すなわち、一実施形態に係る半導体素子は、第１導電型の半導体基板と、半導体基板の主面上に設けられた第１導電型の第１炭化珪素半導体層と、第１炭化珪素半導体層の上部に設けられた第２導電型のボディ領域と、ボディ領域の上部に設けられた第１導電型の不純物領域と、第１炭化珪素半導体層の上であって、ボディ領域の少なくとも一部及び不純物領域の少なくとも一部とそれぞれ接して設けられた第１導電型の第２炭化珪素半導体層と、第２炭化珪素半導体層の上に設けられたゲート絶縁膜と、ゲート絶縁膜の上に設けられたゲート電極とを備え、ボディ領域は、第１炭化珪素半導体層の表面と接する第１ボディ領域と、第１ボディ領域の底面と接する第２ボディ領域とを含み、第１ボディ領域の不純物濃度は、第２ボディ領域の不純物濃度よりも高く、第２ボディ領域は、半導体基板の主面に対して垂直な方向の平面視において、第１ボディ領域の内側に位置し、第２ボディ領域のうち少なくとも一部は、不純物領域の下方に位置する。 That is, a semiconductor element according to an embodiment includes a first conductivity type semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer provided on a main surface of the semiconductor substrate, and a first silicon carbide semiconductor layer. A second conductivity type body region provided in the upper portion; a first conductivity type impurity region provided in the upper portion of the body region; and at least a part of the body region on the first silicon carbide semiconductor layer; A first conductivity type second silicon carbide semiconductor layer provided in contact with at least a part of the impurity region, a gate insulating film provided on the second silicon carbide semiconductor layer, and provided on the gate insulating film The body region includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity in the first body region Concentration is the second body region The second body region is higher than the impurity concentration and is located inside the first body region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate, and at least a part of the second body region is an impurity Located below the area.
　一実施形態の半導体素子は、第１炭化珪素半導体層におけるボディ領域の側方の領域に配置された第１導電型の注入領域をさらに備え、注入領域の下部は、ボディ領域よりも浅く形成され、ボディ領域は、注入領域の導電型を反転させるように第２導電型の不純物をドーピングすることにより形成されていてもよい。 The semiconductor device of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer at a side of the body region, and a lower portion of the injection region is formed shallower than the body region. The body region may be formed by doping a second conductivity type impurity so as to reverse the conductivity type of the implantation region.
　また、一実施形態の半導体素子は、第１炭化珪素半導体層におけるボディ領域の側方の領域に配置された第１導電型の注入領域をさらに備え、注入領域は、ボディ領域よりも深く形成されていてもよい。 The semiconductor element of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer on a side of the body region, and the injection region is formed deeper than the body region. It may be.
　一実施形態の半導体素子において、第１ボディ領域の不純物濃度は、１×１０１８ｃｍ－３以上且つ１×１０２０ｃｍ－３以下であり、第２ボディ領域の不純物濃度は、１×１０１７ｃｍ－３以上且つ１×１０１９ｃｍ－３以下であり、注入領域の不純物濃度は、５×１０１６ｃｍ－３以上且つ５×１０１７ｃｍ－３以下であってもよい。 In the semiconductor device of one embodiment, the impurity concentration of the first body region is 1 × 10 18 cm −3 or more and 1 × 10 20 cm −3 or less, and the impurity concentration of the second body region is 1 × 10 17. cm -3 or more and is 1 × 10 19 cm -3 or less, the impurity concentration of the implanted region, 5 × 10 16 cm -3 or more and 5 × 10 17 cm -3 may be less.
　一実施形態の半導体素子において、第２炭化珪素半導体層は、ゲート絶縁膜と接する上層と、第１炭化珪素半導体層と接する下層とを含み、上層の不純物濃度は、下層の不純物濃度よりも低くてもよい。 In the semiconductor element of one embodiment, the second silicon carbide semiconductor layer includes an upper layer in contact with the gate insulating film and a lower layer in contact with the first silicon carbide semiconductor layer, and the impurity concentration of the upper layer is lower than the impurity concentration of the lower layer. May be.
　一実施形態の半導体素子は、不純物領域と電気的に接続された第１オーミック電極と、半導体基板における第１炭化珪素半導体層と反対側の面上に設けられた第２オーミック電極とをさらに備えていてもよい。 The semiconductor device of one embodiment further includes a first ohmic electrode electrically connected to the impurity region, and a second ohmic electrode provided on a surface of the semiconductor substrate opposite to the first silicon carbide semiconductor layer. It may be.
　一実施形態の半導体素子において、第２ボディ領域は、半導体基板の主面に対して垂直な方向の平面視において、不純物領域と同一、又は不純物領域の外側に位置してもよい。 In the semiconductor element of one embodiment, the second body region may be located on the same side as the impurity region or outside the impurity region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate.
　他の実施形態に係る半導体素子の製造方法は、第１導電型の半導体基板の主面上に、第１導電型の第１炭化珪素半導体層を形成する工程と、第１炭化珪素半導体層の上部に、第１導電型の注入領域を形成する工程と、注入領域の上部に、第２導電型の第１ボディ領域を選択的に形成する工程と、注入領域における第１ボディ領域の下側に、第２導電型の第２ボディ領域を選択的に形成する工程と、第１ボディ領域の上部に、第１導電型の不純物領域を選択的に形成する工程とを備え、第２ボディ領域を形成する工程において、第２ボディ領域は、注入領域よりも深く形成すると共に、第２ボディ領域の不純物濃度は、第１ボディ領域の不純物濃度よりも低く、且つ、半導体基板の主面に対して垂直な方向の平面視において、第１ボディ領域の内側に位置し、第２ボディ領域のうち少なくとも一部が不純物領域の下方に位置するように形成する。 A method of manufacturing a semiconductor device according to another embodiment includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a step of forming the first silicon carbide semiconductor layer. A step of forming a first conductivity type implantation region on the upper portion; a step of selectively forming a second conductivity type first body region on the implantation region; and a lower side of the first body region in the implantation region A step of selectively forming a second body region of the second conductivity type, and a step of selectively forming an impurity region of the first conductivity type on the upper portion of the first body region. The second body region is formed deeper than the implantation region, and the impurity concentration of the second body region is lower than the impurity concentration of the first body region, and with respect to the main surface of the semiconductor substrate. The first body region in plan view in a vertical direction Located inside, at least a portion of the second body region is formed to be located below the impurity regions.
　他の実施形態に係る半導体素子の製造方法は、不純物領域を形成する工程よりも後に、第１炭化珪素半導体層の上に、第１ボディ領域の少なくとも一部及び不純物領域の少なくとも一部とそれぞれ接するように、第１導電型の第２炭化珪素半導体層を形成する工程と、第２炭化珪素半導体層の上に、ゲート絶縁膜及びゲート電極とを順次形成する工程とをさらに備えていてもよい。 In the method for manufacturing a semiconductor device according to another embodiment, at least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the impurity region. A step of forming a first conductivity type second silicon carbide semiconductor layer so as to be in contact; and a step of sequentially forming a gate insulating film and a gate electrode on the second silicon carbide semiconductor layer. Good.
　さらに他の実施形態に係る半導体素子の製造方法は、第１導電型の半導体基板の主面上に、第１導電型の第１炭化珪素半導体層を形成する工程と、第１炭化珪素半導体層の上部に、第２導電型の第１ボディ領域及び第１導電型の注入領域のうちの一方の領域を選択的に形成する工程と、第１炭化珪素半導体層における一方の領域の側方に、第１ボディ領域及び注入領域のうちの他方の領域を、一方の領域に対して自己整合的に形成する工程と、第１炭化珪素半導体層における第１ボディ領域の下側に、第２導電型の第２ボディ領域を選択的に形成する工程と、第１ボディ領域の上部に、第１導電型の不純物領域を選択的に形成する工程とを備え、注入領域を形成する工程において、注入領域は、第２ボディ領域よりも深く形成し、第２ボディ領域を形成する工程において、第２ボディ領域の不純物濃度は、第１ボディ領域の不純物濃度よりも低く、且つ、半導体基板の主面に対して垂直な方向の平面視において、第１ボディ領域の内側に位置し、第２ボディ領域のうち少なくとも一部が不純物領域の下方に位置するように形成する。 A method of manufacturing a semiconductor device according to still another embodiment includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a first silicon carbide semiconductor layer. And selectively forming one of the second conductivity type first body region and the first conductivity type implantation region on the side of the one region in the first silicon carbide semiconductor layer. And forming the other of the first body region and the implantation region in a self-aligned manner with respect to the one region, and forming a second conductive layer under the first body region in the first silicon carbide semiconductor layer. A step of selectively forming a second body region of the mold, and a step of selectively forming an impurity region of the first conductivity type on the first body region, and in the step of forming the implantation region, The region is formed deeper than the second body region, and the second body In the step of forming the region, the impurity concentration of the second body region is lower than the impurity concentration of the first body region and in a plan view in a direction perpendicular to the main surface of the semiconductor substrate, The second body region is formed on the inner side so that at least part of the second body region is located below the impurity region.
　他の実施形態に係る半導体素子の製造方法は、注入領域を形成する工程よりも後に、第１炭化珪素半導体層の上に、第１ボディ領域の少なくとも一部及び不純物領域の少なくとも一部とそれぞれ接するように、第１導電型の第２炭化珪素半導体層を形成する工程と、第２炭化珪素半導体層の上に、ゲート絶縁膜及びゲート電極とを順次形成する工程とをさらに備えていてもよい。 In the method for manufacturing a semiconductor device according to another embodiment, at least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the implantation region. A step of forming a first conductivity type second silicon carbide semiconductor layer so as to be in contact; and a step of sequentially forming a gate insulating film and a gate electrode on the second silicon carbide semiconductor layer. Good.
　（第１の実施形態）
　以下、第１の実施形態に係る半導体素子について図面を参照しながら説明する。図１（ａ）は本実施形態に係る半導体素子１００の断面構成を模式的に示している。図１（ａ）には、一点鎖線の右側及び左側にそれぞれ位置する２つの半導体素子１００の断面が示されている。これらは、ユニットセル１００ｕを構成しており、本実施形態に係る半導体素子１００は、複数のユニットセル１００ｕを含む。尚、本開示は、以下の実施形態等に限定されない。特に、以下の実施形態で示される数値、形状、材料、構成要素、該構成要素の配置位置及び接続形態、並びにプロセスのステップ及び該ステップの順序等は、いずれも一例である。また、以下の実施形態及び図面で示される構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、好ましい形態を構成する任意の構成要素として説明される。尚、各図は、模式図であり、必ずしも厳密に図示したものではない。これは、他の実施形態に係る半導体素子においても同様である。 (First embodiment)
The semiconductor element according to the first embodiment will be described below with reference to the drawings. FIG. 1A schematically shows a cross-sectional configuration of a semiconductor element 100 according to this embodiment. FIG. 1A shows a cross section of two semiconductor elements 100 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 100u, and the semiconductor element 100 according to the present embodiment includes a plurality of unit cells 100u. Note that the present disclosure is not limited to the following embodiments and the like. In particular, the numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, process steps, the order of the steps, and the like shown in the following embodiments are all examples. Among the constituent elements shown in the following embodiments and drawings, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements that constitute a preferred embodiment. . Each figure is a schematic diagram and is not necessarily illustrated strictly. The same applies to the semiconductor elements according to other embodiments.
　＜構成＞
　図１（ａ）に示すように、半導体素子１００は、第１導電型の半導体基板１０１と、半導体基板１０１の主面上に位置する第１導電型の第１炭化珪素半導体層（炭化珪素エピタキシャル層）１０２とを備える。本実施形態では、第１導電型がｎ型であり、第２導電型がｐ型である。但し、第１導電型がｐ型であり、第２導電型がｎ型であってもよい。半導体基板１０１は、ｎ＋型の導電性を有し、炭化珪素（ＳｉＣ）によって構成される。第１炭化珪素半導体層１０２は、ｎ－型である。ｎ又はｐの導電型の右肩の「＋」又は「－」は、不純物の相対的な濃度を表している。例えば、「ｎ＋」は「ｎ」よりもｎ型不純物濃度が高いことを意味し、「ｎ－」は「ｎ」よりもｎ型不純物濃度が低いことを意味している。ｐ型においても同様であり、また、他の実施形態においても同様である。 <Configuration>
As shown in FIG. 1A, a semiconductor element 100 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) located on the main surface of the semiconductor substrate 101. Layer) 102. In the present embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. The semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC). First silicon carbide semiconductor layer 102 is n − type. The “+” or “−” on the right shoulder of the n or p conductivity type represents the relative concentration of impurities. For example, “n + ” means that the n-type impurity concentration is higher than “n”, and “n − ” means that the n-type impurity concentration is lower than “n”. The same applies to the p-type, and the same applies to other embodiments.
　第１炭化珪素半導体層１０２の上部には、第２導電型の複数のボディ領域１０３が１ユニットセル当たり１個形成され、隣り合うユニットセル１００ｕに含まれるボディ領域１０３との間には、第１導電型のＪＦＥＴ領域１０２ｊが形成されている。ここで、ＪＦＥＴ領域１０２ｊとは、ボディ領域１０３と隣接する第１導電型の領域、すなわち、隣接する２つのユニットセル１００ｕのボディ領域１０３同士の間に挟まれる第１導電型の領域をいう。本実施形態においては、第２導電型のボディ領域１０３は、第１炭化珪素半導体層１０２の上部に形成された第１導電型の注入領域１０２ｉに第２導電型の不純物を導入することにより形成される。このため、ボディ領域１０３は、第１導電型の不純物及び第２導電型の不純物を共に含んでおり、第２導電型の不純物濃度の方が注入領域１０２ｉにおける第１導電型の不純物濃度よりも高くなっている領域として規定される。ボディ領域１０３の底面では、第１炭化珪素半導体層１０２におけるボディ領域１０３と接する領域の第１導電型の不純物濃度と、ボディ領域１０３における第２導電型の不純物濃度とが等しくなっている。 A plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 100u, A one-conductivity type JFET region 102j is formed. Here, the JFET region 102j refers to a first conductivity type region adjacent to the body region 103, that is, a first conductivity type region sandwiched between the body regions 103 of two adjacent unit cells 100u. In the present embodiment, the second conductivity type body region 103 is formed by introducing a second conductivity type impurity into the first conductivity type implantation region 102 i formed above the first silicon carbide semiconductor layer 102. Is done. For this reason, the body region 103 includes both the first conductivity type impurity and the second conductivity type impurity, and the second conductivity type impurity concentration is higher than the first conductivity type impurity concentration in the implantation region 102i. Defined as an area that is high. On the bottom surface of body region 103, the first conductivity type impurity concentration in the region in contact with body region 103 in first silicon carbide semiconductor layer 102 is equal to the second conductivity type impurity concentration in body region 103.
　ボディ領域１０３は、第２導電型の第１ボディ領域１０３ａと第２導電型の第２ボディ領域１０３ｂとを含む。第１ボディ領域１０３ａは、第１炭化珪素半導体層１０２の表面と接しており、第２ボディ領域１０３ｂの上面は、第１ボディ領域１０３ａの底面と接している。 The body region 103 includes a second conductivity type first body region 103a and a second conductivity type second body region 103b. First body region 103a is in contact with the surface of first silicon carbide semiconductor layer 102, and the upper surface of second body region 103b is in contact with the bottom surface of first body region 103a.
　第１ボディ領域１０３ａの厚さは、例えば、少なくとも１５ｎｍであり、第２ボディ領域１０３ｂの厚さは、例えば、少なくとも１００ｎｍである。ここでの各領域１０３ａ、１０３ｂの厚さとは、半導体基板１０１の主面と垂直な方向の厚さをいう。本実施形態では、第１ボディ領域１０３ａはｐ＋型であり、第２ボディ領域１０３ｂはｐ型である。以下において詳細に説明するように、第１ボディ領域１０３ａの平均不純物濃度は、第２ボディ領域１０３ｂの平均不純物濃度の２倍以上に設定することができる。また、半導体基板１０１の主面に垂直な方向から見た、いわゆる平面視では、第２ボディ領域１０３ｂは、第１ボディ領域１０３ａの内側に位置する。すなわち、第２ボディ領域１０３ｂは、該第２ボディ領域１０３ｂの幅が第１ボディ領域１０３ａの幅よりも小さくなるように設けられている。 The thickness of the first body region 103a is, for example, at least 15 nm, and the thickness of the second body region 103b is, for example, at least 100 nm. Here, the thickness of each of the regions 103a and 103b is a thickness in a direction perpendicular to the main surface of the semiconductor substrate 101. In the present embodiment, the first body region 103a is p + type, and the second body region 103b is p type. As will be described in detail below, the average impurity concentration of the first body region 103a can be set to be twice or more the average impurity concentration of the second body region 103b. Further, the second body region 103b is located inside the first body region 103a in a so-called planar view as seen from a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is provided such that the width of the second body region 103b is smaller than the width of the first body region 103a.
　第１ボディ領域１０３ａの上部には、第１導電型の不純物領域１０４が設けられている。不純物領域１０４の導電型はｎ＋型である。 A first conductivity type impurity region 104 is provided on the first body region 103a. The conductivity type of the impurity region 104 is n + type.
　第２ボディ領域１０３ｂは、半導体基板１０１の主面に対する平面視では、不純物領域１０４と同一となる位置、又は不純物領域１０４の外側に位置するように設けられている。従って、第２ボディ領域１０３ｂのうち少なくとも一部は、不純物領域１０４の下方に位置する。このように、本実施形態においては、第２ボディ領域１０３ｂのうち少なくとも一部が、ソース領域である不純物領域１０４の下方に設けられる。このため、不純物領域１０４、第１ボディ領域１０３ａ及び第１炭化珪素半導体層１０２を介したパンチスルーの発生を抑制することができる。 The second body region 103 b is provided so as to be located at the same position as the impurity region 104 or outside the impurity region 104 in a plan view with respect to the main surface of the semiconductor substrate 101. Accordingly, at least a part of the second body region 103 b is located below the impurity region 104. Thus, in the present embodiment, at least a part of the second body region 103b is provided below the impurity region 104 that is the source region. For this reason, generation | occurrence | production of the punch through through the impurity region 104, the 1st body region 103a, and the 1st silicon carbide semiconductor layer 102 can be suppressed.
　第１ボディ領域１０３ａには、第２導電型のコンタクト領域１０５を設けることができる。コンタクト領域１０５の導電型は、ｐ＋型であってもよい。コンタクト領域１０５は、第２ボディ領域１０３ｂと接している。 A second conductivity type contact region 105 can be provided in the first body region 103a. The conductivity type of contact region 105 may be p + type. Contact region 105 is in contact with second body region 103b.
　不純物領域１０４の上には、ソース電極（第１オーミック電極）１０９が設けられている。ソース電極１０９は、不純物領域１０４及びコンタクト領域１０５の表面に形成され、不純物領域１０４及びコンタクト領域１０５の両方と電気的に接触している。第１ボディ領域１０３ａの不純物濃度が十分に大きい場合には、コンタクト領域１０５を設けなくてもよい。この場合には、不純物領域１０４に第１ボディ領域１０３ａを露出するコンタクトトレンチを設け、設けたコンタクトトレンチの底部にソース電極１０９を形成することにより、第１ボディ領域１０３ａとソース電極１０９とを直接に接触させてもよい。また、不純物領域１０４を形成する際に、コンタクト領域１０５が形成される部分は非注入として第１ボディ領域１０３ａを露出させ、第１ボディ領域１０３ａとソース電極１０９とが直接に接する構造としてもよい。 A source electrode (first ohmic electrode) 109 is provided on the impurity region 104. The source electrode 109 is formed on the surfaces of the impurity region 104 and the contact region 105 and is in electrical contact with both the impurity region 104 and the contact region 105. When the impurity concentration of the first body region 103a is sufficiently high, the contact region 105 may not be provided. In this case, a contact trench exposing the first body region 103a is provided in the impurity region 104, and the source electrode 109 is formed at the bottom of the provided contact trench, whereby the first body region 103a and the source electrode 109 are directly connected. You may make it contact. Further, when the impurity region 104 is formed, the portion where the contact region 105 is formed may be non-implanted so that the first body region 103a is exposed and the first body region 103a and the source electrode 109 are in direct contact with each other. .
　上述したように、互いに隣接する２つのユニットセル１００ｕにおけるボディ領域１０３同士に挟まれる第１導電型の領域であるＪＦＥＴ領域１０２ｊは、注入領域１０２ｉに形成される。従って、ＪＦＥＴ領域１０２ｊにおける不純物濃度は、注入領域１０２ｉと同一である。注入領域１０２ｉの深さは、図１（ａ）に示すように、少なくとも第１ボディ領域１０３ａの下方までの深さに設定される。その理由は、隣り合う２つの第１ボディ領域１０３ａ同士に挟まれる領域、すなわち、半導体素子１００のオン時に流れる電流経路となる領域のオン抵抗を小さくして、半導体素子１００のオン電流を大きくするためである。尚、本実施形態においては、図１（ａ）に示すように、注入領域１０２ｉの深さは、第２ボディ領域１０３ｂの深さよりも浅く設定することができる。 As described above, the JFET region 102j which is the first conductivity type region sandwiched between the body regions 103 in the two unit cells 100u adjacent to each other is formed in the implantation region 102i. Therefore, the impurity concentration in the JFET region 102j is the same as that in the implantation region 102i. As shown in FIG. 1A, the depth of the implantation region 102i is set to a depth at least up to the lower side of the first body region 103a. The reason is that the on-resistance of the semiconductor element 100 is increased by reducing the on-resistance of a region sandwiched between two adjacent first body regions 103a, that is, a region serving as a current path that flows when the semiconductor element 100 is on. Because. In the present embodiment, as shown in FIG. 1A, the depth of the implantation region 102i can be set shallower than the depth of the second body region 103b.
　第１炭化珪素半導体層１０２の上には、ボディ領域１０３の少なくとも一部及び不純物領域１０４の少なくとも一部とそれぞれ接する第１導電型の第２炭化珪素半導体層１０６が設けられている。第２炭化珪素半導体層１０６は、不純物領域１０４及び第１炭化珪素半導体層１０２のうち、第１ボディ領域１０３ａと隣接するＪＦＥＴ領域１０２ｊと電気的に接続され、且つ、第１ボディ領域１０３ａの上に形成することができる。 On the first silicon carbide semiconductor layer 102, a second conductivity type second silicon carbide semiconductor layer 106 is provided in contact with at least part of the body region 103 and at least part of the impurity region 104, respectively. Second silicon carbide semiconductor layer 106 is electrically connected to JFET region 102j adjacent to first body region 103a in impurity region 104 and first silicon carbide semiconductor layer 102, and on top of first body region 103a. Can be formed.
　本実施形態では、第２炭化珪素半導体層１０６は、エピタキシャル成長によって形成されている。第２炭化珪素半導体層１０６は、第１ボディ領域１０３ａと接する領域にチャネル領域１０６ｃを含んでいる。チャネル領域１０６ｃの長さ（チャネル長Ｌ）は、図１（ａ）に示されている２つの双方向矢印で示される長さに相当する。すなわち、ＭＩＳＦＥＴの「チャネル長」は、第１ボディ領域１０３ａの上面、すなわち、第２炭化珪素半導体層１０６における第１ボディ領域１０３ａとの界面の長さで決定される。 In the present embodiment, the second silicon carbide semiconductor layer 106 is formed by epitaxial growth. Second silicon carbide semiconductor layer 106 includes a channel region 106c in a region in contact with first body region 103a. The length of the channel region 106c (channel length L) corresponds to the length indicated by the two bidirectional arrows shown in FIG. That is, the “channel length” of the MISFET is determined by the length of the upper surface of the first body region 103 a, that is, the length of the interface with the first body region 103 a in the second silicon carbide semiconductor layer 106.
　尚、ここでは、第２炭化珪素半導体層（チャネル層）１０６は、半導体基板１０１に対して垂直な方向にドーパント濃度の分布を有している。これを簡便に表現するため、例えば第２炭化珪素半導体層１０６を２層の積層構造で表現し、不純物領域１０４と接する側を下層１０６ｂとし、その下層１０６ｂの上方に位置する層を上層１０６ａとする。第２炭化珪素半導体層１０６の下層１０６ｂは、ｎ型のドーパントを有している。また、第２炭化珪素半導体層１０６の上層１０６ａは、例えばドーパント濃度が極めて小さいアンドープ状態である。 Here, the second silicon carbide semiconductor layer (channel layer) 106 has a dopant concentration distribution in a direction perpendicular to the semiconductor substrate 101. In order to express this simply, for example, the second silicon carbide semiconductor layer 106 is expressed by a two-layered structure, the side in contact with the impurity region 104 is the lower layer 106b, and the layer located above the lower layer 106b is the upper layer 106a. To do. Lower layer 106b of second silicon carbide semiconductor layer 106 has an n-type dopant. Further, the upper layer 106a of the second silicon carbide semiconductor layer 106 is in an undoped state, for example, having a very low dopant concentration.
　第２炭化珪素半導体層１０６の上には、ゲート絶縁膜１０７が設けられている。ゲート絶縁膜１０７の上には、ゲート電極１０８が設けられている。ゲート電極１０８は、少なくともチャネル領域１０６ｃの上方に位置している。 A gate insulating film 107 is provided on the second silicon carbide semiconductor layer 106. A gate electrode 108 is provided on the gate insulating film 107. The gate electrode 108 is located at least above the channel region 106c.
　ゲート電極１０８の上には、該ゲート電極１０８を覆うように層間絶縁膜１１１が設けられている。層間絶縁膜１１１の上には、上部配線１１２が設けられている。上部配線１１２は、層間絶縁膜１１１に設けられたコンタクトホール１１１ａを介してソース電極１０９と接続されている。半導体基板１０１における第１炭化珪素半導体層１０２と反対側の面である裏面には、ドレイン電極（第２オーミック電極）１１０が設けられている。ドレイン電極１１０には、更に裏面配線１１３が設けられている。 An interlayer insulating film 111 is provided on the gate electrode 108 so as to cover the gate electrode 108. An upper wiring 112 is provided on the interlayer insulating film 111. The upper wiring 112 is connected to the source electrode 109 through a contact hole 111 a provided in the interlayer insulating film 111. A drain electrode (second ohmic electrode) 110 is provided on the back surface of the semiconductor substrate 101 opposite to the first silicon carbide semiconductor layer 102. The drain electrode 110 is further provided with a back surface wiring 113.
　半導体素子１００を構成する各ユニットセル１００ｕは、上部配線１１２側から半導体素子１００を見た場合、例えば正方形状を有している。各ユニットセル１００ｕは、正方形状に限られず、長方形でもよく、また、四角形以外の多角形状を有していてもよい。図１（ｂ）は、複数のユニットセル１００ｕの配置を示している。図１（ｂ）に示すように、各ユニットセル１００ｕは、例えば、ｘ方向及びｙ方向に２次元状に配列され、且つ、ｙ方向の配列は交互にｘ方向の２分の１ずつシフトしている。ユニットセル１００ｕが一方向に長く延びた長方形状を有する場合は、図１（ｃ）に示すように、それぞれのユニットセル１００ｕを並列に配置してもよい。このように配置された複数のユニットセル１００ｕによって、半導体素子１００が構成される。 Each unit cell 100u constituting the semiconductor element 100 has, for example, a square shape when the semiconductor element 100 is viewed from the upper wiring 112 side. Each unit cell 100u is not limited to a square shape, and may be a rectangular shape or may have a polygonal shape other than a square shape. FIG. 1B shows an arrangement of a plurality of unit cells 100u. As shown in FIG. 1B, the unit cells 100u are, for example, two-dimensionally arranged in the x direction and the y direction, and the arrangement in the y direction is alternately shifted by half in the x direction. ing. When the unit cells 100u have a rectangular shape extending in one direction, the unit cells 100u may be arranged in parallel as shown in FIG. The semiconductor element 100 is configured by the plurality of unit cells 100u arranged in this way.
　＜動作＞
　次に、半導体素子１００の動作を説明する。 <Operation>
Next, the operation of the semiconductor element 100 will be described.
　半導体素子１００において、第２炭化珪素半導体層１０６と、第２炭化珪素半導体層１０６に流れる電流を制御するゲート電極１０８と、ゲート絶縁膜１０７と、第２炭化珪素半導体層１０６と電気的に接続されたソース電極１０９と、ドレイン電極１１０とによってＭＩＳＦＥＴが構成される。ソース電極１０９の電位を基準とするドレイン電極１１０の電位をＶｄｓ、ソース電極１０９の電位を基準とするゲート電極１０８の電位をＶｇｓ、及びＭＩＳＦＥＴの閾値電圧（順方向電流の閾値電圧）をＶｔｈとすると、ＭＩＳＦＥＴは、Ｖｇｓ≧Ｖｔｈの場合にオン状態となり、Ｖｄｓ＞０Ｖであれば、ドレイン電極１１０から、半導体基板１０１、第１炭化珪素半導体層（ドリフト層）１０２、ＪＦＥＴ領域１０２ｊ、第２炭化珪素半導体層（チャネル層）１０６及びソース領域である不純物領域１０４を介してソース電極１０９へ電流が流れる。 In semiconductor element 100, second silicon carbide semiconductor layer 106, gate electrode 108 that controls current flowing through second silicon carbide semiconductor layer 106, gate insulating film 107, and second silicon carbide semiconductor layer 106 are electrically connected. The source electrode 109 and the drain electrode 110 thus formed constitute a MISFET. The drain electrode 110 potential with reference to the source electrode 109 potential is Vds, the gate electrode 108 potential with reference to the source electrode 109 potential is Vgs, and the threshold voltage of the MISFET (threshold voltage of the forward current) is Vth. Then, the MISFET is turned on when Vgs ≧ Vth, and when Vds> 0 V, the semiconductor substrate 101, the first silicon carbide semiconductor layer (drift layer) 102, the JFET region 102j, the second carbonization are formed from the drain electrode 110. A current flows to the source electrode 109 through the silicon semiconductor layer (channel layer) 106 and the impurity region 104 which is a source region.
　この電流経路のうち、ＪＦＥＴ領域１０２ｊ付近の構造を接合型トランジスタとみれば、この領域におけるオン抵抗は、ＪＦＥＴ領域１０２ｊでの移動度をμｊ、隣り合う２つの第１ボディ領域１０３ａ同士の間隔をａ１、隣り合う２つの第２ボディ領域１０３ｂ同士の間隔をａ２、ＪＦＥＴ領域１０２ｊのドーパント濃度をＮｊ、ＪＦＥＴ領域１０２ｊとしてのチャネル幅に相当する、ボディ領域１０３の第１炭化珪素半導体層１０２の表面における境界線の長さをＷ、第１ボディ領域１０３ａの第１炭化珪素半導体層１０２の表面からの深さをＬｐ１、第２ボディ領域１０３ｂの第１ボディ領域１０３ａの底面からの深さをＬｐ２とすると、本実施形態においては、以下の式（１）に示す関係がある。 If the structure near the JFET region 102j in this current path is regarded as a junction transistor, the on-resistance in this region is the mobility in the JFET region 102j is μj, and the interval between two adjacent first body regions 103a is the same. a1, the distance between two adjacent second body regions 103b is a2, the dopant concentration of the JFET region 102j is Nj, and the surface of the first silicon carbide semiconductor layer 102 in the body region 103 corresponds to the channel width as the JFET region 102j , The depth of the first body region 103a from the surface of the first silicon carbide semiconductor layer 102 is Lp1, and the depth of the second body region 103b from the bottom of the first body region 103a is Lp2. Then, in this embodiment, there is a relationship represented by the following formula (1).
　ＪＦＥＴ領域のオン抵抗 ∝ Ｌｐ１／（μｊ × ａ１ × Ｎｊ × Ｗ）
　　　　　　　　　　　　 ＋ Ｌｐ２／（μｊ × ａ２ × Ｎｊ × Ｗ） … （１）
　ここで、ａ１、ａ２、Ｌｐ１及びＬｐ２は、従来例の半導体素子における隣り合う２つのボディ領域同士の間隔ａ、及びボディ領域の第１炭化珪素半導体層の表面からの深さＬｐの寸法と比較すると、以下の条件
　ａ２ ＞ ａ１ ＝ ａ、　Ｌｐ１ ＋ Ｌｐ２ ＝ Ｌｐ
となる。これを従来例に係るＪＦＥＴ領域のオン抵抗を表す式（２）に代入すると、
　従来例のＪＦＥＴ領域のオン抵抗 ∝ Ｌｐ／（μｊ × ａ × Ｎｊ × Ｗ）　
　　　　　　　　　　　　　　　 ＝ Ｌｐ１／（μｊ × ａ１ × Ｎｊ × Ｗ）
　　　　　　　　　　　　　　　 ＋ Ｌｐ２／（μｊ × ａ１ × Ｎｊ × Ｗ）…（２）
となる。ここで、図１５に示すように、従来例に係るＪＦＥＴ領域２ｊでの移動度をμｊ、隣り合う２つのボディ領域３同士の間隔をａ、ＪＦＥＴ領域２ｊのドーパント濃度をＮｊ、ＪＦＥＴ領域２ｊとしてのチャネル幅に相当する、ボディ領域３の第１炭化珪素半導体層２の表面における境界線の長さをＷ、ボディ領域３の第１炭化珪素半導体層２の表面からの深さをＬｐとする。 On-resistance of JFET region ∝ Lp1 / (μj × a1 × Nj × W)
+ Lp2 / (μj × a2 × Nj × W) (1)
Here, a1, a2, Lp1, and Lp2 are compared with the dimension of the distance a between two adjacent body regions and the depth Lp of the body region from the surface of the first silicon carbide semiconductor layer in the conventional semiconductor device. Then, the following conditions: a2> a1 = a, Lp1 + Lp2 = Lp
It becomes. Substituting this into equation (2) representing the on-resistance of the JFET region according to the conventional example,
On-resistance of JFET region of conventional example ∝ Lp / (μj × a × Nj × W)
= Lp1 / (μj × a1 × Nj × W)
+ Lp2 / (μj × a1 × Nj × W) (2)
It becomes. Here, as shown in FIG. 15, the mobility in the JFET region 2j according to the conventional example is μj, the interval between two adjacent body regions 3 is a, the dopant concentration in the JFET region 2j is Nj, and the JFET region 2j. The length of the boundary line on the surface of the first silicon carbide semiconductor layer 2 in the body region 3 corresponding to the channel width of W is W, and the depth of the body region 3 from the surface of the first silicon carbide semiconductor layer 2 is Lp. .
　本実施形態に係る半導体素子１００によれば、半導体基板１０１の主面に垂直な方向の平面視において、第２ボディ領域１０３ｂの幅は、第１ボディ領域１０３ａの幅よりも小さく、さらに、第２ボディ領域１０３ｂは第１ボディ領域１０３ａの内側に位置している。従って、図１（ａ）に示すように、第２ボディ領域１０３ｂ同士の間隔ａ２と第１ボディ領域１０３ａ同士の間隔ａ１とは、ａ２＞ａ１が成り立つので、［式（１）の値］＜［式（２）の値］が実現する。すなわち、本実施形態に係る半導体素子１００は従来の半導体素子５０と比べてそのオン抵抗を小さくすることができる。 According to the semiconductor device 100 according to the present embodiment, the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in the direction perpendicular to the main surface of the semiconductor substrate 101, and The two body regions 103b are located inside the first body region 103a. Therefore, as shown in FIG. 1 (a), since the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a satisfy a2> a1, [value of expression (1)] < [Value of Expression (2)] is realized. That is, the on-resistance of the semiconductor element 100 according to the present embodiment can be reduced as compared with the conventional semiconductor element 50.
　また、本実施形態に係る半導体素子１００においては、ＪＦＥＴ領域１０２ｊが自己整合的に形成されているため、電流経路の変動が小さくなる。その結果、電流を安定して流すことができ、オン抵抗及び閾値電圧の変動を抑えることができる。 Further, in the semiconductor device 100 according to the present embodiment, since the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
　＜製造方法＞
　以下、第１の実施形態に係る半導体素子の製造方法について、図２～図４を参照しながら説明する。 <Manufacturing method>
Hereinafter, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.
　まず、半導体基板１０１を準備する。半導体基板１０１は、例えば、抵抗率が０．０２Ωｃｍの低抵抗のｎ型４Ｈ－ＳｉＣオフカット基板である。 First, the semiconductor substrate 101 is prepared. The semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 Ωcm.
　図２（ａ）に示すように、例えば、化学気相堆積（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）法等のエピタキシャル成長が可能な堆積法により、半導体基板１０１の主面上に高抵抗の第１炭化珪素半導体層１０２をエピタキシャル成長する。第１炭化珪素半導体層１０２を形成する前に、半導体基板１０１の上に、高不純物濃度のＳｉＣによって構成されるバッファ層を堆積してもよい。バッファ層の不純物濃度は、例えば１×１０１８ｃｍ－３であり、その厚さは例えば１μｍである。第１炭化珪素半導体層１０２は、例えばｎ型４Ｈ－ＳｉＣによって構成され、不純物濃度は、例えば１×１０１６ｃｍ－３であり、その厚さは例えば１０μｍである。続いて、第１炭化珪素半導体層１０２に窒素（Ｎ）イオンを注入して、ｎ型の注入領域１０２ｉを形成する。注入領域１０２ｉの不純物濃度は、例えば１×１０１７ｃｍ－３であり、その深さは例えば０．５μｍである。 As shown in FIG. 2A, for example, a high-resistance first silicon carbide semiconductor is formed on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as a chemical vapor deposition (CVD) method. Layer 102 is grown epitaxially. Before forming the first silicon carbide semiconductor layer 102, a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101. The impurity concentration of the buffer layer is, for example, 1 × 10 18 cm −3 and the thickness thereof is, for example, 1 μm. The first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 × 10 16 cm −3 , and the thickness is, for example, 10 μm. Subsequently, nitrogen (N) ions are implanted into the first silicon carbide semiconductor layer 102 to form an n-type implanted region 102i. The impurity concentration of the implantation region 102i is, for example, 1 × 10 17 cm −3 and the depth is, for example, 0.5 μm.
　次に、図２（ｂ）に示すように、注入領域１０２ｉの上に、例えば酸化シリコン（ＳｉＯ２）からなり、第１ボディ領域１０３ａの形成パターンを開口部に持つマスク膜２０１をマスクとして、例えばアルミニウム（Ａｌ）イオンを注入領域１０２ｉに注入して、ｐ＋型の第１ボディ領域１０３ａを形成する。これにより、注入領域１０２ｉから、ＪＦＥＴ領域１０２ｊが第１ボディ領域１０３ａに対して自己整合的に形成される。 Next, as shown in FIG. 2B, a mask film 201 made of, for example, silicon oxide (SiO 2 ) and having the formation pattern of the first body region 103a in the opening on the implantation region 102i is used as a mask. For example, aluminum (Al) ions are implanted into the implantation region 102i to form the p + -type first body region 103a. As a result, the JFET region 102j is formed from the implantation region 102i in a self-aligned manner with respect to the first body region 103a.
　次に、図２（ｃ）に示すように、例えばＣＶＤ法により、マスク膜２０１を含め第１ボディ領域１０３ａの上に、ＳｉＯ２からなるサイドウォール形成膜２０２を形成する。その後、例えばＡｌイオンを注入領域１０２及びその下の第１炭化珪素半導体層１０２にサイドウォール形成膜２０２を介して注入し、ｐ型の第２ボディ領域１０３ｂを形成する。このとき、注入されるＡｌイオンは、マスク膜２０１とサイドウォール形成膜２０２におけるマスク膜２０１の開口部の側面に形成された部分とによってマスクされる結果、第２ボディ領域１０３ｂは、第１ボディ領域１０３ａの周囲又は側部から内側に位置するように形成される。図２（ｃ）のＡ－Ｂ断面におけるイオン注入プロファイルの一例を図１１に示す。例えば図１１に示すイオン注入プロファイルは、Ａｌイオンを以下の注入エネルギー及びドーズ量で４回に分けて注入することにより得られる。最初の２回で第１ボディ領域１０３ａにおけるイオン注入プロファイルが形成され、後の２回で第２ボディ領域１０３ｂにおけるイオン注入プロファイルが形成される。 Next, as shown in FIG. 2C, a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 201 by, eg, CVD. After that, for example, Al ions are implanted into the implantation region 102 and the first silicon carbide semiconductor layer 102 thereunder through the sidewall formation film 202 to form the p-type second body region 103b. At this time, the implanted Al ions are masked by the mask film 201 and the portion of the sidewall formation film 202 formed on the side surface of the opening of the mask film 201. As a result, the second body region 103b It is formed so as to be located on the inner side from the periphery or the side of the region 103a. FIG. 11 shows an example of the ion implantation profile in the cross section AB in FIG. For example, the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose. An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
　１）３０ｋｅＶ：３．０×１０１３ｃｍ－２
　２）７０ｋｅＶ：６．０×１０１３ｃｍ－２
　３）１５０ｋｅＶ：１．５×１０１４ｃｍ－２
　４）３５０ｋｅＶ：４．０×１０１３ｃｍ－２
　次に、マスク膜２０１及びサイドウォール形成膜２０２の上に、リソグラフィ法により、不純物領域１０４の形成パターンを開口部に持つレジストパターン（図示せず）を形成する。その後、図２（ｄ）に示すように、レジストパターンをマスクとして、サイドウォール形成膜２０２にドライエッチングを行って、サイドウォール形成膜２０２からサイドウォール２０２ａとマスク膜２０２ｂとを形成する。その後、レジストパターンを除去し、例えばＮイオンを、第１ボディ領域１０３ａに注入することにより、第１ボディ領域１０３ａの上部に不純物領域１０４を形成する。 1) 30 keV: 3.0 × 10 13 cm −2
2) 70 keV: 6.0 × 10 13 cm −2
3) 150 keV: 1.5 × 10 14 cm −2
4) 350 keV: 4.0 × 10 13 cm −2
Next, a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 201 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 2D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming the impurity region 104 on the first body region 103a.
　なお、サイドウォール２０２ａの幅は、下記の様に設定することができる。 Note that the width of the sidewall 202a can be set as follows.
　図１２に、アバランシェブレイクダウンが起きる前に、ＪＦＥＴ領域１０２ｊを空乏化することができるサイドウォール幅を、ＪＦＥＴ領域１０２ｊの幅が１μｍの場合と０．５μｍの場合とについて、最大サイドウォール幅として示す。図１２の横軸は、ＪＦＥＴ領域１０２ｊの第１導電型の不純物濃度である。図１２において、実線はＪＦＥＴ領域１０２ｊの幅が０．５μｍの場合の最大サイドウォール幅、一点鎖線はＪＦＥＴ領域１０２ｊの幅が１μｍの場合の最大サイドウォール幅を示す。なお、図１２において、太線はアバランシェブレイクダウン時の空乏層の幅を示す。図１２に示す最大サイドウォールの幅以下の値となるように、サイドウォール２０２ａの幅を設定することができる。このとき、製造方法の一変形例として、ＪＦＥＴ領域１０２ｊを空乏化することができるサイドウォール幅となるようにサイドウォール２０２ａの膜厚を選び、例えばＡｌイオンを注入して第２ボディ領域１０３ｂを形成する。その後、チャネル長を決める膜厚となるようにサイドウォール形成膜２０２をさらに堆積により大きくして、サイドウォール２０２ａを形成してもよい。 FIG. 12 shows that the sidewall width that can deplete the JFET region 102j before the avalanche breakdown occurs is the maximum sidewall width when the width of the JFET region 102j is 1 μm and 0.5 μm. Show. The horizontal axis in FIG. 12 represents the impurity concentration of the first conductivity type in the JFET region 102j. In FIG. 12, the solid line indicates the maximum sidewall width when the width of the JFET region 102j is 0.5 μm, and the alternate long and short dash line indicates the maximum sidewall width when the width of the JFET region 102j is 1 μm. In FIG. 12, the thick line indicates the width of the depletion layer at the time of avalanche breakdown. The width of the sidewall 202a can be set so as to be a value equal to or smaller than the maximum sidewall width shown in FIG. At this time, as a modified example of the manufacturing method, the thickness of the sidewall 202a is selected so as to have a sidewall width that can deplete the JFET region 102j, and, for example, Al ions are implanted to form the second body region 103b. Form. Thereafter, the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
　次に、マスク膜２０１、２０２ｂ及びサイドウォール２０２ａを除去する。その後、図３（ａ）に示すように、第１ボディ領域１０３ａにおけるコンタクト領域を形成する部分に開口部を持つ、ＳｉＯ２からなるマスク膜２０５を形成する。続いて、マスク膜２０５をマスクとして、Ａｌイオンを注入することにより、不純物領域１０４及び第１ボディ領域のほぼ中央部にｐ型のコンタクト領域１０５を形成する。ここで、コンタクト領域１０５は、第２ボディ注入領域１０３ｂに到達するように形成してもよい。 Next, the mask films 201 and 202b and the sidewalls 202a are removed. Thereafter, as shown in FIG. 3A, a mask film 205 made of SiO 2 having an opening at a portion of the first body region 103a where the contact region is formed is formed. Subsequently, by using the mask film 205 as a mask, Al ions are implanted to form a p-type contact region 105 at substantially the center of the impurity region 104 and the first body region. Here, the contact region 105 may be formed so as to reach the second body implantation region 103b.
　次に、マスク膜２０５を除去して、第１炭化珪素半導体層１０２に注入された不純物を活性化させる高温熱処理（活性化アニール）を行う。これにより、図３（ｂ）に示すように、第１ボディ領域１０３ａ、第２ボディ領域１０３ｂ、不純物領域１０４、コンタクト領域１０５及びＪＦＥＴ領域１０２ｊが形成される。第１ボディ領域１０３ａの深さは、例えば３００ｎｍで、平均的な不純物濃度は、約１．６×１０１９ｃｍ－３となるように、イオン注入プロファイルを決定する。 Next, the mask film 205 is removed, and high-temperature heat treatment (activation annealing) is performed to activate the impurities implanted into the first silicon carbide semiconductor layer 102. Thereby, as shown in FIG. 3B, the first body region 103a, the second body region 103b, the impurity region 104, the contact region 105, and the JFET region 102j are formed. The ion implantation profile is determined so that the depth of the first body region 103a is, for example, 300 nm and the average impurity concentration is about 1.6 × 10 19 cm −3 .
　第１ボディ領域１０３ａと第２ボディ領域１０３ｂとを併せたボディ領域１０３全体の深さは、例えば５５０ｎｍで、第２ボディ領域１０３ｂの平均的な不純物濃度は、約２×１０１８ｃｍ－３となるようにイオン注入プロファイルを調整する。不純物領域１０４の深さは、例えば２５０ｎｍで、平均的な不純物濃度は約５×１０１９ｃｍ－３となるようにイオン注入プロファイルを調整する。ここで、第１ボディ領域１０３ａの深さは、図１１に示す境界によって決定され、第２ボディ領域１０３ｂの深さは、例えば５×１０１７ｃｍ－３の不純物濃度が得られる深さとする。また、不純物領域１０４の深さは、例えば５×１０１７ｃｍ－３の不純物濃度が得られる深さとする。 The total depth of the body region 103 including the first body region 103a and the second body region 103b is, for example, 550 nm, and the average impurity concentration of the second body region 103b is about 2 × 10 18 cm −3 . The ion implantation profile is adjusted so that The depth of the impurity region 104 is, for example, 250 nm, and the ion implantation profile is adjusted so that the average impurity concentration is about 5 × 10 19 cm −3 . Here, the depth of the first body region 103a is determined by the boundary shown in FIG. 11, and the depth of the second body region 103b is set to a depth at which, for example, an impurity concentration of 5 × 10 17 cm −3 is obtained. The depth of the impurity region 104 is set to a depth at which an impurity concentration of 5 × 10 17 cm −3 is obtained, for example.
　不純物濃度は、例えば以下のように算出する。図１１のように、例えばＳＩＭＳ（二次イオン質量分析法）等を用いて、ある断面における深さ方向と不純物濃度との関係を明確にし、次に深さ方向の領域を定義する。第１ボディ領域１０３ａの深さは、図１１に示す境界によって決定される深さと定義したので、深さ０．２８μｍとする。ここで、不純物濃度を深さ方向に積分し、シートドーズ量（単位の次元はｃｍ－２）に換算する。ここで算出されたシートドーズ量を、その領域の深さ（ここでは０．２８μｍ）で除することにより、不純物濃度が算出される。 The impurity concentration is calculated as follows, for example. As shown in FIG. 11, the relationship between the depth direction and the impurity concentration in a certain cross section is clarified using, for example, SIMS (secondary ion mass spectrometry), and then the region in the depth direction is defined. Since the depth of the first body region 103a is defined as the depth determined by the boundary shown in FIG. 11, the depth is 0.28 μm. Here, the impurity concentration is integrated in the depth direction and converted into a sheet dose (unit dimension is cm −2 ). The impurity concentration is calculated by dividing the sheet dose calculated here by the depth of the region (here, 0.28 μm).
　コンタクト領域１０５の深さは、例えば４００ｎｍで、平均的な不純物濃度は約１×１０２０ｃｍ－３であり、その深さは、例えば５×１０１７ｃｍ－３の不純物濃度が得られる深さとする。尚、活性化アニール後の第１炭化珪素半導体層１０２の表面清浄化のために、第１炭化珪素半導体層１０２の表層を除去する場合がある。例えば第１炭化珪素半導体層１０２の表層を５０ｎｍ除去した場合、第１ボディ領域１０３ａ、不純物領域１０４及びコンタクト領域１０５の深さは、全て５０ｎｍほど小さくなり、それぞれ、２５０ｎｍ、２００ｎｍ及び３５０ｎｍとなる。 The depth of the contact region 105 is, for example, 400 nm, the average impurity concentration is about 1 × 10 20 cm −3 , and the depth is, for example, a depth at which an impurity concentration of 5 × 10 17 cm −3 is obtained. To do. Note that the surface layer of the first silicon carbide semiconductor layer 102 may be removed in order to clean the surface of the first silicon carbide semiconductor layer 102 after the activation annealing. For example, when the surface layer of the first silicon carbide semiconductor layer 102 is removed by 50 nm, the depths of the first body region 103a, the impurity region 104, and the contact region 105 are all reduced by about 50 nm and become 250 nm, 200 nm, and 350 nm, respectively.
　次に、図３（ｂ）に示すように、ＪＦＥＴ領域１０２ｊ、第１ボディ領域１０３ａ、不純物領域１０４及びコンタクト領域１０５を含む第１炭化珪素半導体層１０２の表面全体に、第２炭化珪素半導体層１０６をエピタキシャル成長する。第２炭化珪素半導体層１０６は、上述した通り、上層１０６ａ及び下層１０６ｂにより構成される。本実施形態においては、下層１０６ｂを形成した後に、下層１０６ｂの上に上層１０６ａを連続して形成する。下層１０６ｂのドーパント濃度は、例えば約２×１０１８ｃｍ－３であり、その膜厚は例えば２４ｎｍである。下層１０６ｂは、窒素（Ｎ）をドーピングして形成しているため、下層１０６ｂを形成した後に、ドーピングガスの導入を止めてアンドープ状態として、上層１０６ａをその膜厚が約２６ｎｍとなるように連続して形成する。その後、例えば熱酸化法により、第２炭化珪素半導体層上層１０６ａの表面にゲート絶縁膜１０７を形成する。 Next, as shown in FIG. 3B, the second silicon carbide semiconductor layer is formed on the entire surface of the first silicon carbide semiconductor layer 102 including the JFET region 102j, the first body region 103a, the impurity region 104, and the contact region 105. 106 is epitaxially grown. As described above, second silicon carbide semiconductor layer 106 includes upper layer 106a and lower layer 106b. In the present embodiment, after forming the lower layer 106b, the upper layer 106a is continuously formed on the lower layer 106b. The dopant concentration of the lower layer 106b is, for example, about 2 × 10 18 cm −3 and the film thickness is, for example, 24 nm. Since the lower layer 106b is formed by doping nitrogen (N), after the formation of the lower layer 106b, the introduction of the doping gas is stopped and the upper layer 106a is continuously formed so as to have a film thickness of about 26 nm. To form. Thereafter, the gate insulating film 107 is formed on the surface of the second silicon carbide semiconductor layer upper layer 106a by, eg, thermal oxidation.
　次に、図３（ｃ）に示すように、ゲート絶縁膜１０７の上に、リン（Ｐ）を７×１０２０ｃｍ－３程度の濃度にドーピングした多結晶シリコン膜を堆積する。多結晶シリコン膜の厚さは、例えば５００ｎｍ程度である。続いて、リソグラフィ法により、多結晶シリコン膜の上に、ゲート電極形成パターンを有するレジストパターン（図示せず）を形成し、形成したレジストパターンを用いて、多結晶シリコン膜をドライエッチングすることにより、所定の領域に多結晶シリコンからなる複数のゲート電極１０８を形成する。 Next, as shown in FIG. 3C, a polycrystalline silicon film doped with phosphorus (P) at a concentration of about 7 × 10 20 cm −3 is deposited on the gate insulating film 107. The thickness of the polycrystalline silicon film is, for example, about 500 nm. Subsequently, a resist pattern (not shown) having a gate electrode formation pattern is formed on the polycrystalline silicon film by lithography, and the polycrystalline silicon film is dry-etched using the formed resist pattern. A plurality of gate electrodes 108 made of polycrystalline silicon are formed in a predetermined region.
　次に、図３（ｄ）に示すように、ＣＶＤ法により、ゲート電極１０８の表面及び第１炭化珪素半導体層１０２の表面を覆うように、例えばＳｉＯ２を含む層間絶縁膜１１１を堆積する。層間絶縁膜１１１の厚さは、例えば１．５μｍである。 Next, as shown in FIG. 3D, an interlayer insulating film 111 containing, for example, SiO 2 is deposited by the CVD method so as to cover the surface of the gate electrode 108 and the surface of the first silicon carbide semiconductor layer 102. The thickness of the interlayer insulating film 111 is, for example, 1.5 μm.
　次に、図４（ａ）に示すように、マスク（図示せず）を用いて、ドライエッチングにより、層間絶縁膜１１１におけるコンタクト領域１０５の上側部分及び不純物領域１０４の一部の上側部分を除去することにより、層間絶縁膜１１１にコンタクトホール１１１ａを形成する。 Next, as shown in FIG. 4A, the upper part of the contact region 105 and the upper part of the impurity region 104 in the interlayer insulating film 111 are removed by dry etching using a mask (not shown). As a result, a contact hole 111 a is formed in the interlayer insulating film 111.
　次に、真空蒸着法又はスパッタ法等により、層間絶縁膜１１１の上に、例えば厚さが５０ｎｍ程度のニッケル（Ｎｉ）膜を形成する。続いて、図４（ｂ）に示すように、不活性雰囲気の、例えば９５０℃の温度で５分間の熱処理を行うことにより、ニッケル膜を炭化珪素における層間絶縁膜１１１からの露出部分と反応させて、ニッケルシリサイド（ＮｉＳｉ）からなるソース電極１０９を形成する。 Next, a nickel (Ni) film having a thickness of, for example, about 50 nm is formed on the interlayer insulating film 111 by vacuum deposition or sputtering. Subsequently, as shown in FIG. 4B, the nickel film is reacted with the exposed portion of the silicon carbide from the interlayer insulating film 111 by performing a heat treatment in an inert atmosphere, for example, at a temperature of 950 ° C. for 5 minutes. Then, the source electrode 109 made of nickel silicide (NiSi) is formed.
　次に、層間絶縁膜１１１の上の未反応のニッケル膜をエッチングにより除去する。その後、図４（ｃ）に示すように、半導体基板１０１の裏面にも、例えばニッケル膜を全面に堆積し、同様の熱処理によって炭化珪素と反応させて、ドレイン電極１１０を形成する。 Next, the unreacted nickel film on the interlayer insulating film 111 is removed by etching. Thereafter, as shown in FIG. 4C, a nickel film, for example, is deposited on the entire back surface of the semiconductor substrate 101 and reacted with silicon carbide by the same heat treatment to form the drain electrode 110.
　続いて、層間絶縁膜１１１の上及びコンタクトホール１１１ａの内部に、厚さが４μｍ程度のアルミニウム（Ａｌ）膜を堆積し、所望のパターンにエッチングすることにより、上部配線１１２を形成する。尚、図示はしないが、チップの端部にゲート電極１０８と接触するゲート配線又はゲートパッドを形成する。更に、ドレイン電極１１０の裏面に、ダイボンド用の裏面配線１１３として、ドレイン電極１１０側から、例えばチタン（Ｔｉ）／ニッケル（Ｎｉ）／銀（Ａｇ）を堆積する。このようにして、図１に示した半導体素子１００が得られる。 Subsequently, an upper wiring 112 is formed by depositing an aluminum (Al) film having a thickness of about 4 μm on the interlayer insulating film 111 and inside the contact hole 111a, and etching it into a desired pattern. Although not shown, a gate wiring or a gate pad that contacts the gate electrode 108 is formed at the end of the chip. Further, for example, titanium (Ti) / nickel (Ni) / silver (Ag) is deposited on the back surface of the drain electrode 110 as the back surface wiring 113 for die bonding from the drain electrode 110 side. In this way, the semiconductor element 100 shown in FIG. 1 is obtained.
　＜効果＞
　本実施形態に係る半導体素子１００によれば、半導体基板１０１の主面に垂直な方向の平面視において、第２ボディ領域１０３ｂの幅が第１ボディ領域１０３ａの幅よりも小さい。言い換えれば、平面視において、第２ボディ領域１０３ｂは第１ボディ領域１０３ａの内側に配置される。この構成により、上掲の式（１）の左辺における「ａ２」に相当する寸法を大きくできることにより、オン抵抗を小さくすることができる。 <Effect>
According to the semiconductor element 100 according to the present embodiment, the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101. In other words, the second body region 103b is disposed inside the first body region 103a in plan view. With this configuration, the dimension corresponding to “a2” on the left side of the above formula (1) can be increased, so that the on-resistance can be reduced.
　また、本実施形態に係る半導体素子１００は、ＪＦＥＴ領域１０２ｊが自己整合的に形成されている。このため、ボディ領域１０３と注入領域１０２ｉとの重なり寸法にばらつきが生じない。その結果、電流経路の変動が小さくなって、電流を安定して流すことができるので、オン抵抗及び閾値電圧の変動を抑えることができる。 In the semiconductor device 100 according to the present embodiment, the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlapping dimension of the body region 103 and the implantation region 102i. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
　従来構造を持つ半導体素子の断面図を図１５に示す。従来例に係る半導体素子５０は、ｎ型の半導体基板１と、半導体基板１の主面上に形成されたｎ型の第１炭化珪素半導体層２とを備える。第１炭化珪素半導体層２の上部には、ｐ型の複数のボディ領域３が形成され、隣り合うユニットセル５０ｕに含まれるボディ領域３との間に、ｎ型のＪＦＥＴ領域２ｊが形成されている。ボディ領域３は、第１ボディ領域３ａとその下の第２ボディ領域３ｂとから構成される。第１ボディ領域３ａの幅と第２ボディ領域３ｂの幅とは同等に形成され、ＪＦＥＴ領域２ｊがボディ領域３と重ねて形成されている。 FIG. 15 shows a cross-sectional view of a semiconductor element having a conventional structure. A semiconductor element 50 according to a conventional example includes an n-type semiconductor substrate 1 and an n-type first silicon carbide semiconductor layer 2 formed on the main surface of the semiconductor substrate 1. A plurality of p-type body regions 3 are formed on top of first silicon carbide semiconductor layer 2, and n-type JFET region 2j is formed between body regions 3 included in adjacent unit cells 50u. Yes. The body region 3 includes a first body region 3a and a second body region 3b below the first body region 3a. The width of the first body region 3a and the width of the second body region 3b are formed to be equal, and the JFET region 2j is formed so as to overlap the body region 3.
　第１ボディ領域３ａの上部には、ｎ型の不純物領域４が形成され、不純物領域４の上部には、ソース電極９が形成されている。第１炭化珪素半導体層２の上には、ボディ領域３及び不純物領域４と接するｎ型の第２炭化珪素半導体層６が形成されている。第２炭化珪素半導体層６の上には、ゲート絶縁膜７を介在させてゲート電極８が形成されている。 An n-type impurity region 4 is formed above the first body region 3a, and a source electrode 9 is formed above the impurity region 4. On the first silicon carbide semiconductor layer 2, an n-type second silicon carbide semiconductor layer 6 in contact with the body region 3 and the impurity region 4 is formed. A gate electrode 8 is formed on second silicon carbide semiconductor layer 6 with gate insulating film 7 interposed.
　従来構造におけるＪＦＥＴ領域２ｊとボディ領域３との重なり量と閾値電圧との関係を図１３に示す。本実施形態に係る半導体素子１００の場合は、シミュレーション値として、３．２Ｖを得ている。また、従来構造におけるＪＦＥＴ領域２ｊとボディ領域３との重なり量とオン抵抗との関係を図１４に示す。本実施形態に係る半導体素子１００の場合は、シミュレーション値として、６．０ｍΩ・ｃｍ２を得ている。 FIG. 13 shows the relationship between the amount of overlap between the JFET region 2j and the body region 3 and the threshold voltage in the conventional structure. In the case of the semiconductor element 100 according to the present embodiment, 3.2 V is obtained as a simulation value. FIG. 14 shows the relationship between the ON resistance and the amount of overlap between the JFET region 2j and the body region 3 in the conventional structure. In the case of the semiconductor element 100 according to the present embodiment, 6.0 mΩ · cm 2 is obtained as a simulation value.
　従来構造では、ＪＦＥＴ領域とボディ領域とを位置合わせすることにより形成しているため、ＪＦＥＴ領域とボディ領域との重なり量にばらつきが生じる。従って、ＪＦＥＴ領域とボディ領域との重なり量に変動があることから、図１３及び図１４に示すように、閾値電圧及びオン抵抗が変動する。しかしながら、本実施形態に係る半導体素子１００においては、ＪＦＥＴ領域１０２ｊを自己整合的に形成することにより、オン抵抗を低減しつつ、閾値電圧の変動及びオン抵抗の変動をも抑えることができる。 Since the conventional structure is formed by aligning the JFET region and the body region, the amount of overlap between the JFET region and the body region varies. Accordingly, since the amount of overlap between the JFET region and the body region varies, the threshold voltage and the on-resistance vary as shown in FIGS. However, in the semiconductor element 100 according to the present embodiment, by forming the JFET region 102j in a self-aligning manner, it is possible to suppress fluctuations in threshold voltage and fluctuations in on-resistance while reducing on-resistance.
　（第２の実施形態）
　以下、第２の実施形態に係る半導体素子について図面を参照しながら説明する。図５（ａ）は本実施形態に係る半導体素子３００の断面構成を模式的に示している。図５（ａ）には、一点鎖線の右側及び左側にそれぞれ位置する２つの半導体素子３００の断面が示されている。これらは、ユニットセル３００ｕを構成しており、本実施形態に係る半導体素子３００は、複数のユニットセル３００ｕを含む。第２の実施形態においては、第１の実施形態と同一の構成部材には同一の符号を付している。従って、第１の実施形態と同一の内容及び同一の構成部材に関する説明を省略又は簡略化する場合がある。 (Second Embodiment)
The semiconductor element according to the second embodiment will be described below with reference to the drawings. FIG. 5A schematically shows a cross-sectional configuration of the semiconductor element 300 according to the present embodiment. FIG. 5A shows a cross section of two semiconductor elements 300 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 300u, and the semiconductor element 300 according to the present embodiment includes a plurality of unit cells 300u. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. Therefore, the description regarding the same content and the same component as 1st Embodiment may be abbreviate | omitted or simplified.
　＜構成＞
　半導体素子３００は、第１導電型の半導体基板１０１と、半導体基板１０１の主面上に位置する第１導電型の第１炭化珪素半導体層（炭化珪素エピタキシャル層）１０２とを備える。本実施形態においても、第１導電型がｎ型であり、第２導電型がｐ型である。第１導電型がｐ型であり第２導電型がｎ型であってもよい。半導体基板１０１は、ｎ＋型の導電性を有し、炭化珪素（ＳｉＣ）によって構成される。第１炭化珪素半導体層１０２は、ｎ－型である。 <Configuration>
Semiconductor element 300 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) 102 located on the main surface of semiconductor substrate 101. Also in this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type. The semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC). First silicon carbide semiconductor layer 102 is n − type.
　第１炭化珪素半導体層１０２の上部には、第２導電型の複数のボディ領域１０３が１ユニットセル当たり１個形成され、隣り合うユニットセル３００ｕに含まれるボディ領域１０３との間には、第１導電型のＪＦＥＴ領域１０２ｊが形成されている。 A plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 300u, A one-conductivity type JFET region 102j is formed.
　ボディ領域１０３と隣接するＪＦＥＴ領域１０２ｊは、注入領域１０２ｉにより構成されるため、不純物濃度は注入層１０２ｉと同一である。注入領域１０２ｉの深さは、少なくとも第１ボディ領域１０３ａよりも深くなるように設定することができる。さらに、本実施形態においては、図５（ａ）に示すように、注入領域１０２ｉの深さは、第２ボディ領域１０３ｂよりも深くなるように設定することができる。本実施形態においては、隣り合うボディ領域１０３同士に挟まれた領域にのみ注入領域１０２ｉを形成しているため、注入領域１０２ｉの深さを第２ボディ領域１０３ｂよりも深くなるように設定しても、第２ボディ領域１０３ｂの下にはＪＦＥＴ領域１０２ｊが形成されない。従って、耐圧を維持しつつ、隣り合う２つの第１ボディ領域１０３ａ同士に挟まれる領域、すなわち、半導体素子３００のオン時に流れる電流経路となる領域のオン抵抗をさらに小さくして、半導体素子３００のオン電流をさらに大きくすることができる。 Since the JFET region 102j adjacent to the body region 103 is constituted by the implantation region 102i, the impurity concentration is the same as that of the implantation layer 102i. The depth of the implantation region 102i can be set to be deeper than at least the first body region 103a. Further, in the present embodiment, as shown in FIG. 5A, the depth of the implantation region 102i can be set to be deeper than the second body region 103b. In this embodiment, since the implantation region 102i is formed only in a region sandwiched between adjacent body regions 103, the depth of the implantation region 102i is set to be deeper than the second body region 103b. However, the JFET region 102j is not formed under the second body region 103b. Therefore, the on-resistance of the region sandwiched between the two adjacent first body regions 103a, that is, the region serving as a current path that flows when the semiconductor element 300 is turned on, is further reduced while maintaining the withstand voltage. The on-current can be further increased.
　半導体素子３００を構成する各ユニットセル３００ｕは、上部配線１１２側から半導体素子３００を見た場合、例えば正方形状を有している。各ユニットセル３００ｕは、正方形状に限られず、長方形でもよく、また、四角形以外の多角形状を有していてもよい。図５（ｂ）は、複数のユニットセル３００ｕの配置を示している。図５（ｂ）に示すように、各ユニットセル３００ｕは、例えば、ｘ及びｙ方向に２次元状に配列され、且つ、ｙ方向の配列は交互にｘ方向の２分の１ずつシフトしている。ユニットセル３００ｕが一方向に長く延びた長方形状を有する場合は、図５（ｃ）に示すように、それぞれのユニットセル３００ｕを並列に配置してもよい。このように配置された複数のユニットセル３００ｕによって、半導体素子３００が構成される。 Each unit cell 300u constituting the semiconductor element 300 has, for example, a square shape when the semiconductor element 300 is viewed from the upper wiring 112 side. Each unit cell 300u is not limited to a square shape but may be a rectangle or may have a polygonal shape other than a quadrangle. FIG. 5B shows an arrangement of a plurality of unit cells 300u. As shown in FIG. 5B, the unit cells 300u are, for example, arranged two-dimensionally in the x and y directions, and the arrangement in the y direction is alternately shifted by a half in the x direction. Yes. When the unit cells 300u have a rectangular shape extending in one direction, the unit cells 300u may be arranged in parallel as shown in FIG. The semiconductor element 300 is constituted by the plurality of unit cells 300u arranged in this way.
　図５（ａ）に示すように、第２ボディ領域１０３ｂ同士の間隔ａ２と第１ボディ領域１０３ａ同士の間隔ａ１とは、ａ２＞ａ１の関係があることから、本実施形態に係る半導体素子３００は、第１の実施形態に係る半導体素子１００と同様に、従来の半導体素子５０と比べてそのオン抵抗を小さくすることができる。 As shown in FIG. 5A, the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a have a relationship of a2> a1, and therefore, the semiconductor element 300 according to the present embodiment. As in the semiconductor element 100 according to the first embodiment, the on-resistance can be reduced as compared with the conventional semiconductor element 50.
　また、本実施形態に係る半導体素子３００においては、ＪＦＥＴ領域１０２ｊが自己整合的に形成されているため、電流経路の変動が小さくなる。その結果、電流を安定して流すことができ、オン抵抗及び閾値電圧の変動を抑えることができる。 Further, in the semiconductor element 300 according to the present embodiment, since the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
　＜製造方法＞
　以下、第２の実施形態に係る半導体素子の製造方法について、図６～図９を参照しながら説明する。 <Manufacturing method>
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS.
　まず、半導体基板１０１を準備する。半導体基板１０１は、例えば、抵抗率が０．０２Ωｃｍ程度の低抵抗のｎ型４Ｈ－ＳｉＣオフカット基板である。 First, the semiconductor substrate 101 is prepared. The semiconductor substrate 101 is, for example, a low-resistance n-type 4H—SiC offcut substrate having a resistivity of about 0.02 Ωcm.
　図６（ａ）に示すように、例えば、ＣＶＤ法等のエピタキシャル成長が可能な堆積法により、半導体基板１０１の主面上に高抵抗の第１炭化珪素半導体層１０２をエピタキシャル成長する。第１炭化珪素半導体層１０２を形成する前に、半導体基板１０１の上に、高不純物濃度のＳｉＣによって構成されるバッファ層を堆積してもよい。バッファ層の不純物濃度は、例えば１×１０１８ｃｍ－３であり、その厚さは例えば１μｍである。第１炭化珪素半導体層１０２は、例えばｎ型４Ｈ－ＳｉＣによって構成され、不純物濃度は、例えば１×１０１６ｃｍ－３であり、その厚さは例えば１０μｍである。 As shown in FIG. 6A, the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as CVD. Before forming the first silicon carbide semiconductor layer 102, a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101. The impurity concentration of the buffer layer is, for example, 1 × 10 18 cm −3 and the thickness thereof is, for example, 1 μm. The first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 × 10 16 cm −3 , and the thickness is, for example, 10 μm.
　次に、図６（ｂ）に示すように、第１炭化珪素半導体層１０２の上に、例えばポリシリコンからなり、第１ボディ領域１０３ａの形成パターンを開口部に持つマスク膜２１１をマスクとして、例えばＡｌイオンを第１炭化珪素半導体層１０２に注入して、ｐ＋型の第１ボディ領域１０３ａを形成する。 Next, as shown in FIG. 6B, a mask film 211 made of, for example, polysilicon and having a formation pattern of the first body region 103a in the opening on the first silicon carbide semiconductor layer 102 is used as a mask. For example, Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the p + -type first body region 103a.
　次に、図６（ｃ）に示すように、例えばＣＶＤ法により、マスク膜２１１を含め第１ボディ領域１０３ａの上に、ＳｉＯ２からなるサイドウォール形成膜２０２を形成する。その後、例えばＡｌイオンを第１炭化珪素半導体層１０２のサイドウォール形成膜２０２を介して注入し、第２ボディ領域１０３ｂを形成する。図６（ｃ）のＡ－Ｂ断面におけるイオン注入プロファイルの一例を図１１に示す。例えば図１１に示すイオン注入プロファイルは、Ａｌイオンを以下の注入エネルギー及びドーズ量で４回に分けて注入することにより得られる。最初の２回で第１ボディ領域１０３ａにおけるイオン注入プロファイルが形成され、後の２回で第２ボディ領域１０３ｂにおけるイオン注入プロファイルが形成される。 Next, as shown in FIG. 6C, a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 211 by, eg, CVD. Thereafter, for example, Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b. FIG. 11 shows an example of the ion implantation profile in the AB section of FIG. For example, the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose. An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
　１）３０ｋｅＶ：３．０×１０１３ｃｍ－２
　２）７０ｋｅＶ：６．０×１０１３ｃｍ－２
　３）１５０ｋｅＶ：１．５×１０１４ｃｍ－２
　４）３５０ｋｅＶ：４．０×１０１３ｃｍ－２
　次に、マスク膜２１１及びサイドウォール形成膜２０２の上に、リソグラフィ法により、不純物領域１０４の形成パターンを開口部に持つレジストパターン（図示せず）を形成する。その後、図６（ｄ）に示すように、レジストパターンをマスクとして、サイドウォール形成膜２０２にドライエッチングを行って、サイドウォール形成膜２０２からサイドウォール２０２ａとマスク膜２０２ｂとを形成する。その後、レジストパターンを除去し、例えばＮイオンを第１ボディ領域１０３ａに注入することにより、第１ボディ領域１０３ａの上部に不純物領域１０４を形成する。 1) 30 keV: 3.0 × 10 13 cm −2
2) 70 keV: 6.0 × 10 13 cm −2
3) 150 keV: 1.5 × 10 14 cm −2
4) 350 keV: 4.0 × 10 13 cm −2
Next, a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 211 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 6D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form the sidewall 202a and the mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
　なお、サイドウォール２０２ａの幅は、例えば、図１２で説明したサイドウォールの幅以下の値となるように設定することができる。このとき、製造方法の変形例として、後工程で形成するＪＦＥＴ領域を空乏化することができるサイドウォール幅となるようにサイドウォールの膜厚を選び、例えばＡｌイオンを注入して第２ボディ領域１０３ｂを形成する。その後、チャネル長を決める膜厚となるようにサイドウォール形成膜２０２をさらに堆積により大きくして、サイドウォール２０２ａを形成してもよい。 Note that the width of the sidewall 202a can be set to be a value equal to or smaller than the width of the sidewall described in FIG. 12, for example. At this time, as a modification of the manufacturing method, the thickness of the sidewall is selected so as to have a sidewall width that can deplete a JFET region formed in a later process, and Al ions are implanted, for example, to form the second body region. 103b is formed. Thereafter, the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
　次に、マスク膜２１１、２０２ｂ及びサイドウォール２０２ａを含め不純物領域１０４を覆うように、ＳｉＯ２からなるマスク形成膜（図示せず）を堆積する。続いて、堆積したマスク形成膜の上面を化学機械研磨（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ：ＣＭＰ）法等により平坦化する。その後、エッチング等により、マスク形成膜に対してマスク膜２１１を選択的に除去して、ＪＦＥＴ領域１０２ｊの形成パターンを開口部に持つマスク膜２０６を形成する。その後、図７（ａ）に示すように、マスク膜２０６をマスクとして、Ｎイオンを第１炭化珪素半導体層１０２に注入して、ＪＦＥＴ領域１０２ｊを形成する。ＪＦＥＴ領域１０２ｊの不純物濃度は、例えば１×１０１７ｃｍ－３であり、その深さは例えば０．５μｍである。これにより、ＪＦＥＴ領域１０２ｊは、第１ボディ領域１０３ａに対して自己整合的に形成される。なお、マスク形成膜及びマスク膜２０６の形成には、高密度プラズマノンドープシリカガラス（Ｈｉｇｈ Ｄｅｎｓｉｔｙ Ｐｌａｓｍａ Ｎｏｎ ｄｏｐｅｄ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ：ＨＤＰ－ＮＳＧ）法又はＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ）法と、ＣＭＰ法とを組み合わせることができる。 Next, a mask formation film (not shown) made of SiO 2 is deposited so as to cover the impurity region 104 including the mask films 211 and 202b and the sidewalls 202a. Subsequently, the upper surface of the deposited mask forming film is planarized by a chemical mechanical polishing (CMP) method or the like. Thereafter, the mask film 211 is selectively removed from the mask formation film by etching or the like, and a mask film 206 having a formation pattern of the JFET region 102j in the opening is formed. Thereafter, as shown in FIG. 7A, N ions are implanted into the first silicon carbide semiconductor layer 102 using the mask film 206 as a mask to form a JFET region 102j. The impurity concentration of the JFET region 102j is, for example, 1 × 10 17 cm −3 and the depth thereof is, for example, 0.5 μm. As a result, the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a. Note that the high-density plasma non-doped silica glass (HDP-NSG) method or SOG (Spin On Glass) method and the CMP method are combined with the formation of the mask formation film and the mask film 206. Can do.
　次に、マスク膜２０６を除去する。その後、図７（ｂ）から図９に示す工程を行うことにより、図５に示した半導体素子３００が得られる。図７（ｂ）から図９に示す工程は、第１の実施形態における図３（ａ）から図４（ｃ）に示す工程と同様であるので説明を省略する。 Next, the mask film 206 is removed. Thereafter, the steps shown in FIGS. 7B to 9 are performed to obtain the semiconductor element 300 shown in FIG. Since the steps shown in FIGS. 7B to 9 are the same as the steps shown in FIGS. 3A to 4C in the first embodiment, description thereof will be omitted.
　＜効果＞
　本実施形態に係る半導体素子３００によれば、半導体基板１０１の主面に垂直な方向の平面視において、第２ボディ領域１０３ｂの幅が第１ボディ領域１０３ａの幅よりも小さい。言い換えれば、平面視において、第２ボディ領域１０３ｂは第１ボディ領域１０３ａの内側に配置される。この構成により、隣り合う第２ボディ領域１０３ｂ同士の間隔ａ２に相当する寸法を大きくできることにより、オン抵抗を小さくすることができる。 <Effect>
According to the semiconductor element 300 according to the present embodiment, the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101. In other words, the second body region 103b is disposed inside the first body region 103a in plan view. With this configuration, the dimension corresponding to the distance a2 between the adjacent second body regions 103b can be increased, so that the on-resistance can be reduced.
　また、本実施形態に係る半導体素子３００は、ＪＦＥＴ領域１０２ｊが自己整合的に形成されている。このため、ボディ領域１０３とＪＦＥＴ領域１０２ｊとの重なり寸法にばらつきが生じない。その結果、電流経路の変動が小さくなって、電流を安定して流すことができるので、オン抵抗及び閾値電圧の変動を抑えることができる。 Also, in the semiconductor element 300 according to the present embodiment, the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlap dimension between the body region 103 and the JFET region 102j. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
　（第２の実施形態の製造方法の一変形例）
　以下、第２の実施形態の製造方法の一変形例について図１０を参照しながら説明する。　　　 (One Modification of Manufacturing Method of Second Embodiment)
Hereinafter, a modification of the manufacturing method of the second embodiment will be described with reference to FIG.
　まず、半導体基板１０１を準備する。半導体基板１０１は、例えば、抵抗率が０．０２Ωｃｍの低抵抗のｎ型４Ｈ－ＳｉＣオフカット基板である。 First, the semiconductor substrate 101 is prepared. The semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 Ωcm.
　図１０（ａ）に示すように、例えば、ＣＶＤ法等のエピタキシャル成長が可能な堆積法により、半導体基板１０１の主面上に高抵抗の第１炭化珪素半導体層１０２をエピタキシャル成長する。第１炭化珪素半導体層１０２を形成する前に、半導体基板１０１の上に、高不純物濃度のＳｉＣによって構成されるバッファ層を堆積してもよい。バッファ層の不純物濃度は、例えば１×１０１８ｃｍ－３であり、その厚さは例えば１μｍである。第１炭化珪素半導体層１０２は、例えばｎ型４Ｈ－ＳｉＣによって構成され、不純物濃度は、例えば１×１０１６ｃｍ－３であり、その厚さは例えば１０μｍである。第１炭化珪素半導体層１０２は、例えばｎ型４Ｈ－ＳｉＣによって構成され、不純物濃度は、例えば１×１０１６ｃｍ－３であり、その厚さは例えば１０μｍである。 As shown in FIG. 10A, the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by, for example, a deposition method capable of epitaxial growth such as a CVD method. Before forming the first silicon carbide semiconductor layer 102, a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101. The impurity concentration of the buffer layer is, for example, 1 × 10 18 cm −3 and the thickness thereof is, for example, 1 μm. The first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 × 10 16 cm −3 , and the thickness is, for example, 10 μm. The first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 × 10 16 cm −3 , and the thickness is, for example, 10 μm.
　続いて、第１炭化珪素半導体層１０２の上に、ポリシリコン膜２１６とシリコン窒化膜２０７とを順次堆積する。その後、堆積したポリシリコン膜２１６とシリコン窒化膜２０７とに対して選択的にエッチングを行って、ＪＦＥＴ領域１０２ｊの形成パターンを開口部に持つマスク膜２０６Ａを形成する。その後、マスク膜２０６Ａをマスクとして、Ｎイオンを第１炭化珪素半導体層１０２に注入して、ＪＦＥＴ領域１０２ｊを形成する。ＪＦＥＴ領域１０２ｊの不純物濃度は、例えば１×１０１７ｃｍ－３であり、その深さは例えば０．５μｍである。 Subsequently, a polysilicon film 216 and a silicon nitride film 207 are sequentially deposited on the first silicon carbide semiconductor layer 102. Thereafter, the deposited polysilicon film 216 and silicon nitride film 207 are selectively etched to form a mask film 206A having a formation pattern of the JFET region 102j in the opening. Thereafter, N ions are implanted into first silicon carbide semiconductor layer 102 using mask film 206A as a mask to form JFET region 102j. The impurity concentration of the JFET region 102j is, for example, 1 × 10 17 cm −3 and the depth thereof is, for example, 0.5 μm.
　次に、例えばＣＶＤ法により、マスク膜２０６Ａを含めＪＦＥＴ領域１０２ｊの上に、ＳｉＯ２からなるマスク形成膜（図示せず）を堆積する。その後、ＣＭＰ法等により、マスク形成膜とマスク膜２０６Ａとの表面を平坦化する。続いて、マスク膜２０６Ａを選択的に除去して、マスク形成膜からマスク膜２０６Ａの反転領域であり、第１ボディ領域の形成パターンに開口部を持つマスク膜２０８を形成する。その後、図１０（ｂ）に示すように、マスク膜２０８をマスクとして、例えばＡｌイオンを第１炭化珪素半導体層１０２に注入して、第１ボディ領域１０３ａを形成する。これにより、ＪＦＥＴ領域１０２ｊは、第１ボディ領域１０３ａに対して自己整合的に形成される。 Next, a mask formation film (not shown) made of SiO 2 is deposited on the JFET region 102j including the mask film 206A by, for example, the CVD method. Thereafter, the surfaces of the mask formation film and the mask film 206A are planarized by a CMP method or the like. Subsequently, the mask film 206A is selectively removed to form a mask film 208 that is an inverted region of the mask film 206A from the mask formation film and has an opening in the formation pattern of the first body region. Thereafter, as shown in FIG. 10B, using the mask film 208 as a mask, for example, Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the first body region 103a. As a result, the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a.
　ここで、マスク膜２０８の形成方法の一変形例を説明する。すなわち、マスク膜２０８としてＣＶＤ法による堆積膜に代えて、ポリシリコン膜２１６をシリコン窒化膜２０７をマスクとして熱酸化し、マスク膜２０８を自己整合的に形成する。このとき、ポリシリコン膜２１６の側面から酸化シリコン膜が横方向に成長して、ＪＦＥＴ領域１０２ｊを覆う。次に、この成長した酸化シリコン膜を残すように、マスク膜２０６Ａを選択的に除去することにより、マスク膜２０８が形成される。なお、マスク膜２０８にＣＶＤ法による堆積膜を用いる場合は、シリコン窒化膜２０７は設けなくてもよい。 Here, a modification of the method for forming the mask film 208 will be described. That is, in place of the deposited film by the CVD method as the mask film 208, the polysilicon film 216 is thermally oxidized using the silicon nitride film 207 as a mask to form the mask film 208 in a self-aligning manner. At this time, a silicon oxide film grows laterally from the side surface of the polysilicon film 216 to cover the JFET region 102j. Next, a mask film 208 is formed by selectively removing the mask film 206A so as to leave the grown silicon oxide film. Note that the silicon nitride film 207 is not necessarily provided in the case where a deposited film by a CVD method is used for the mask film 208.
　次に、図１０（ｃ）に示すように、例えばＣＶＤ法により、マスク膜２０８を含め第１ボディ領域１０３ａの上に、ＳｉＯ２からなるサイドウォール形成膜２０２を形成する。その後、例えばＡｌイオンを第１炭化珪素半導体層１０２のサイドウォール形成膜２０２を介して注入し、第２ボディ領域１０３ｂを形成する。図１０（ｃ）のＡ－Ｂ断面におけるイオン注入プロファイルの一例を図１１に示す。例えば図１１に示すイオン注入プロファイルは、Ａｌイオンを以下の注入エネルギー及びドーズ量で４回に分けて注入することにより得られる。最初の２回で第１ボディ領域１０３ａにおけるイオン注入プロファイルが形成され、後の２回で第２ボディ領域１０３ｂにおけるイオン注入プロファイルが形成される。 Next, as shown in FIG. 10C, a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 208 by, eg, CVD. Thereafter, for example, Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b. An example of the ion implantation profile in the cross section AB in FIG. 10C is shown in FIG. For example, the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose. An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
　１）３０ｋｅＶ：３．０×１０１３ｃｍ－２
　２）７０ｋｅＶ：６．０×１０１３ｃｍ－２
　３）１５０ｋｅＶ：１．５×１０１４ｃｍ－２
　４）３５０ｋｅＶ：４．０×１０１３ｃｍ－２
　次に、マスク膜２０８及びサイドウォール形成膜２０２の上に、リソグラフィ法により、不純物領域１０４の形成パターンを開口部に持つレジストパターン（図示せず）を形成する。その後、図１０（ｄ）に示すように、レジストパターンをマスクとして、サイドウォール形成膜２０２にドライエッチングを行って、サイドウォール形成膜２０２からサイドウォール２０２ａとマスク膜２０２ｂとを形成する。その後、レジストパターンを除去し、例えばＮイオンを第１ボディ領域１０３ａに注入することにより、第１ボディ領域１０３ａの上部に不純物領域１０４を形成する。 1) 30 keV: 3.0 × 10 13 cm −2
2) 70 keV: 6.0 × 10 13 cm −2
3) 150 keV: 1.5 × 10 14 cm −2
4) 350 keV: 4.0 × 10 13 cm −2
Next, a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 208 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 10D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
　この工程以降は、図７（ｂ）から図９に示したように、前述の第２の実施形態の製造方法と同様の方法により形成することができる。 After this step, as shown in FIGS. 7B to 9, it can be formed by a method similar to the manufacturing method of the second embodiment described above.
　＜効果＞
　本実施形態に係る半導体素子３００によれば、半導体基板１０１の主面に垂直な方向の平面視において、第２ボディ領域１０３ｂの幅が第１ボディ領域１０３ａの幅よりも小さい。すなわち、平面視において、第２ボディ領域１０３ｂは第１ボディ領域１０３ａの内側に配置される。この構成により、隣り合う第２ボディ領域１０３ｂ同士の間隔ａ２に相当する寸法を大きくできることにより、オン抵抗を小さくすることができる。 <Effect>
According to the semiconductor element 300 according to the present embodiment, the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is disposed inside the first body region 103a in plan view. With this configuration, the dimension corresponding to the distance a2 between the adjacent second body regions 103b can be increased, so that the on-resistance can be reduced.
　また、ＪＦＥＴ領域１０２ｊが自己整合的に形成されているため、電流経路の変動が小さくなって、電流を安定して流すことができるので、オン抵抗及び閾値電圧の変動を抑えることができる。 In addition, since the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced and current can be flowed stably, so that fluctuations in on-resistance and threshold voltage can be suppressed.
　尚、以上の各実施形態においては、第１炭化珪素半導体層１０２にイオン注入することにより、第１炭化珪素半導体層１０２よりも高濃度の第１導電型の不純物を有するＪＦＥＴ領域１０２ｊを形成する例について説明したが、これに限定されない。すなわち、半導体素子１００、３００におけるＪＦＥＴ領域１０２ｊにおいて、第１炭化珪素半導体層１０２へのイオン注入は行わず、ＪＦＥＴ領域１０２ｊの第１導電型の不純物濃度は、第１炭化珪素半導体層１０２の第１導電型の不純物濃度と同じであってもよい。例えば、ＪＦＥＴ領域１０２ｊの第１導電型の不純物濃度が、第１炭化珪素半導体層１０２の第１導電型の不純物濃度と同じである場合の半導体素子の一変形例を図１６に示す。 In each of the above embodiments, a JFET region 102j having a first conductivity type impurity having a concentration higher than that of the first silicon carbide semiconductor layer 102 is formed by ion implantation into the first silicon carbide semiconductor layer 102. Although an example has been described, the present invention is not limited to this. That is, in the JFET region 102j in the semiconductor elements 100 and 300, ion implantation into the first silicon carbide semiconductor layer 102 is not performed, and the impurity concentration of the first conductivity type in the JFET region 102j is equal to that of the first silicon carbide semiconductor layer 102. It may be the same as the impurity concentration of one conductivity type. For example, FIG. 16 shows a modification of the semiconductor element in the case where the first conductivity type impurity concentration of the JFET region 102 j is the same as the first conductivity type impurity concentration of the first silicon carbide semiconductor layer 102.
　また、各実施形態において、半導体素子１００、３００としてｎ型のＭＩＳＦＥＴについて説明した。しかしながら、ｐ型のＭＩＳＦＥＴとすることも可能である。この場合、半導体基板、第１炭化珪素半導体層（ドリフト層）及びソース領域の導電型をｐ型とし、ボディ領域の導電型をｎ型とすればよい。 In each embodiment, the n-type MISFET has been described as the semiconductor elements 100 and 300. However, a p-type MISFET can also be used. In this case, the conductivity type of the semiconductor substrate, the first silicon carbide semiconductor layer (drift layer), and the source region may be p-type, and the conductivity type of the body region may be n-type.
　更に、ＭＩＳＦＥＴに限られず、半導体層の上に絶縁膜を介して電極が配置されている種々の半導体素子を同様にして形成することができる。例えば、基板とその直上に形成する半導体層とを互いに異なる導電型とすることにより、絶縁ゲートバイポーラトランジスタ（Insulated Gate Bipolar Transistor：ＩＧＢＴ）を形成することができる。ＩＧＢＴの場合、各実施形態で説明したソース電極、ドレイン電極及びソース領域は、それぞれエミッタ電極、コレクタ電極及びエミッタ領域と呼ばれる。 Furthermore, the present invention is not limited to the MISFET, and various semiconductor elements in which electrodes are arranged on the semiconductor layer via an insulating film can be formed in the same manner. For example, an insulated gate bipolar transistor (IGBT) can be formed by making the substrate and the semiconductor layer formed immediately above have different conductivity types. In the case of an IGBT, the source electrode, drain electrode, and source region described in each embodiment are referred to as an emitter electrode, a collector electrode, and an emitter region, respectively.
　従って、以上に説明した半導体素子について、ドリフト層及びエミッタ領域の導電型をｎ型とし、半導体基板及びボディ領域の導電型をｐ型とすると、ｎ型のＩＧＢＴを得ることができる。このとき、ｐ型の半導体基板とｎ型のドリフト層との間に、ｎ型のバッファ層を配置してもよい。また、ドリフト層及びエミッタ領域の導電型をｐ型とし、半導体基板及びボディ領域の導電型をｎ型とすると、ｐ型のＩＧＢＴを得ることができる。このとき、ｎ型の半導体基板とｐ型のドリフト層との間に、ｐ型のバッファ層を配置してもよい。 Therefore, for the semiconductor element described above, if the conductivity type of the drift layer and the emitter region is n-type and the conductivity type of the semiconductor substrate and the body region is p-type, an n-type IGBT can be obtained. At this time, an n-type buffer layer may be disposed between the p-type semiconductor substrate and the n-type drift layer. Further, when the conductivity type of the drift layer and the emitter region is p-type and the conductivity type of the semiconductor substrate and the body region is n-type, a p-type IGBT can be obtained. At this time, a p-type buffer layer may be disposed between the n-type semiconductor substrate and the p-type drift layer.
　更に、ＳｉＣ基板の他に、窒化ガリウム（ＧａＮ）又はダイヤモンド（Ｃ）等の他のワイドバンドギャップ半導体を用いた半導体素子に適用することも可能である。また、本開示の構成を、シリコンを用いた半導体素子に適用することも可能である。 Furthermore, in addition to the SiC substrate, the present invention can also be applied to semiconductor elements using other wide band gap semiconductors such as gallium nitride (GaN) or diamond (C). The configuration of the present disclosure can also be applied to a semiconductor element using silicon.
　この他にも、以上に説明した半導体素子及びその変形例における部材の形状、大きさ、不純物濃度、及び構成材料等の種々の構成要素は、本開示の趣旨を逸脱しない範囲において適宜変更可能である。 In addition to the above, various constituent elements such as the shape, size, impurity concentration, and constituent material of the members in the semiconductor element described above and its modifications can be appropriately changed without departing from the spirit of the present disclosure. is there.
　本開示に係る半導体素子及びその製造方法は、パワーデバイス等を含む種々の半導体素子及びその製造方法として有用である。 The semiconductor element and the manufacturing method thereof according to the present disclosure are useful as various semiconductor elements including a power device and the manufacturing method thereof.
１００、３００　　　半導体素子
１００ｕ、３００ｕ　ユニットセル
１０１　　半導体基板
１０２　　第１炭化珪素半導体層（ドリフト層）
１０２ｉ　注入領域
１０２ｊ　ＪＦＥＴ領域
１０３　　ボディ領域
１０３ａ　第１ボディ領域
１０３ｂ　第２ボディ領域
１０３ｕ　底面
１０４　　不純物領域
１０５　　コンタクト領域
１０６　　第２炭化珪素半導体層
１０６ａ　上層
１０６ｂ　下層
１０６ｃ　チャネル領域
１０７　　ゲート絶縁膜
１０８　　ゲート電極
１０９　　ソース電極（第１オーミック電極）
１１０　　ドレイン電極（第２オーミック電極）
１１１　　層間絶縁膜
１１１ａ　コンタクトホール
１１２　　上部配線
１１３　　裏面配線
２０１、２０２ｂ、２０５、２０６、２０６Ａ、２０８、２１１　　マスク膜
２０２　　サイドウォール形成膜
２０２ａ　サイドウォール
２０７　　シリコン窒化膜
２１６　　ポリシリコン膜 100, 300 Semiconductor element 100u, 300u Unit cell 101 Semiconductor substrate 102 First silicon carbide semiconductor layer (drift layer)
102i implantation region 102j JFET region 103 body region 103a first body region 103b second body region 103u bottom surface 104 impurity region 105 contact region 106 second silicon carbide semiconductor layer 106a upper layer 106b lower layer 106c channel region 107 gate insulating film 108 gate electrode 109 source Electrode (first ohmic electrode)
110 Drain electrode (second ohmic electrode)
111 Interlayer insulating film 111a Contact hole 112 Upper wiring 113 Back wiring 201, 202b, 205, 206, 206A, 208, 211 Mask film 202 Side wall forming film 202a Side wall 207 Silicon nitride film 216 Polysilicon film

Claims (11)

  1. 　第１導電型の半導体基板と、
    　前記半導体基板の主面上に設けられた第１導電型の第１炭化珪素半導体層と、
    　前記第１炭化珪素半導体層の上部に設けられた第２導電型のボディ領域と、
    　前記ボディ領域の上部に設けられた第１導電型の不純物領域と、
    　前記第１炭化珪素半導体層の上であって、前記ボディ領域の少なくとも一部及び前記不純物領域の少なくとも一部とそれぞれ接して設けられた第１導電型の第２炭化珪素半導体層と、
    　前記第２炭化珪素半導体層の上に設けられたゲート絶縁膜と、
    　前記ゲート絶縁膜の上に設けられたゲート電極とを備え、
    　前記ボディ領域は、前記第１炭化珪素半導体層の表面と接する第１ボディ領域と、前記第１ボディ領域の底面と接する第２ボディ領域とを含み、
    　前記第１ボディ領域の不純物濃度は、前記第２ボディ領域の不純物濃度よりも高く、
    　前記第２ボディ領域は、前記半導体基板の主面に対して垂直な方向の平面視において、前記第１ボディ領域の内側に位置し、
    　前記第２ボディ領域のうち少なくとも一部は、前記不純物領域の下方に位置する半導体素子。     A first conductivity type semiconductor substrate;
    A first conductivity type first silicon carbide semiconductor layer provided on a main surface of the semiconductor substrate;
    A second conductivity type body region provided on top of the first silicon carbide semiconductor layer;
    An impurity region of a first conductivity type provided on the body region;
    A second silicon carbide semiconductor layer of a first conductivity type provided on the first silicon carbide semiconductor layer and in contact with at least a part of the body region and at least a part of the impurity region;
    A gate insulating film provided on the second silicon carbide semiconductor layer;
    A gate electrode provided on the gate insulating film,
    The body region includes a first body region in contact with a surface of the first silicon carbide semiconductor layer, and a second body region in contact with a bottom surface of the first body region,
    The impurity concentration of the first body region is higher than the impurity concentration of the second body region,
    The second body region is located inside the first body region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate;
    A semiconductor element, wherein at least a part of the second body region is located below the impurity region.
  2. 　前記第１炭化珪素半導体層における前記ボディ領域の側方の領域に配置された第１導電型の注入領域をさらに備え、
    　前記注入領域の下部は、前記ボディ領域よりも浅く形成され、
    　前記ボディ領域は、前記注入領域の導電型を反転させるように第２導電型の不純物をドーピングすることにより形成された、請求項１に記載の半導体素子。     A first conductivity type implantation region disposed in a region lateral to the body region in the first silicon carbide semiconductor layer;
    The lower portion of the implantation region is formed shallower than the body region,
    The semiconductor element according to claim 1, wherein the body region is formed by doping an impurity of a second conductivity type so as to reverse a conductivity type of the implantation region.
  3. 　前記第１炭化珪素半導体層における前記ボディ領域の側方の領域に配置された第１導電型の注入領域をさらに備え、
    　前記注入領域は、前記ボディ領域よりも深く形成された、請求項１に記載の半導体素子。     A first conductivity type implantation region disposed in a region lateral to the body region in the first silicon carbide semiconductor layer;
    The semiconductor device according to claim 1, wherein the implantation region is formed deeper than the body region.
  4. 　前記第１ボディ領域の不純物濃度は、１×１０１８ｃｍ－３以上且つ１×１０２０ｃｍ－３以下であり、前記第２ボディ領域の不純物濃度は、１×１０１７ｃｍ－３以上且つ１×１０１９ｃｍ－３以下であり、前記注入領域の不純物濃度は、５×１０１６ｃｍ－３以上且つ５×１０１７ｃｍ－３以下である、請求項２又は３に記載の半導体素子。 The impurity concentration of the first body region is 1 × 10 18 cm −3 or more and 1 × 10 20 cm −3 or less, and the impurity concentration of the second body region is 1 × 10 17 cm −3 or more and 1 × is the 10 19 cm -3 or less, the impurity concentration of the implanted region, 5 × is 10 16 cm -3 or more and 5 × 10 17 cm -3 or less, the semiconductor device according to claim 2 or 3.
  5. 　前記第２炭化珪素半導体層は、前記ゲート絶縁膜と接する上層と、前記第１炭化珪素半導体層と接する下層とを含み、
    　前記上層の不純物濃度は、前記下層の不純物濃度よりも低い、請求項１から４のいずれか１項に記載の半導体素子。     The second silicon carbide semiconductor layer includes an upper layer in contact with the gate insulating film and a lower layer in contact with the first silicon carbide semiconductor layer,
    The semiconductor element according to claim 1, wherein an impurity concentration of the upper layer is lower than an impurity concentration of the lower layer.
  6. 　前記不純物領域と電気的に接続された第１オーミック電極と、
    　前記半導体基板における前記第１炭化珪素半導体層と反対側の面上に設けられた第２オーミック電極とをさらに備えた、請求項１から５のいずれか１項に記載の半導体素子。     A first ohmic electrode electrically connected to the impurity region;
    6. The semiconductor device according to claim 1, further comprising a second ohmic electrode provided on a surface of the semiconductor substrate opposite to the first silicon carbide semiconductor layer.
  7. 　前記第２ボディ領域は、前記半導体基板の主面に対して垂直な方向の平面視において、前記不純物領域と同一、又は前記不純物領域の外側に位置する、請求項１から６のいずれか１項に記載の半導体素子。 7. The first body region according to claim 1, wherein the second body region is the same as the impurity region or located outside the impurity region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate. The semiconductor element as described in.
  8. 　第１導電型の半導体基板の主面上に、第１導電型の第１炭化珪素半導体層を形成する工程と、
    　前記第１炭化珪素半導体層の上部に、第１導電型の注入領域を形成する工程と、
    　前記注入領域の上部に、第２導電型の第１ボディ領域を選択的に形成する工程と、
    　前記注入領域における前記第１ボディ領域の下側に、第２導電型の第２ボディ領域を選択的に形成する工程と、
    　前記第１ボディ領域の上部に、第１導電型の不純物領域を選択的に形成する工程とを備え、
    　前記第２ボディ領域を形成する工程において、
    　前記第２ボディ領域は、前記注入領域よりも深く形成すると共に、前記第２ボディ領域の不純物濃度は、前記第１ボディ領域の不純物濃度よりも低く、且つ、前記半導体基板の主面に対して垂直な方向の平面視において、前記第１ボディ領域の内側に位置し、前記第２ボディ領域のうち少なくとも一部が前記不純物領域の下方に位置するように形成する半導体素子の製造方法。     Forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate;
    Forming a first conductivity type implantation region on the first silicon carbide semiconductor layer;
    Selectively forming a second conductivity type first body region on the implantation region;
    Selectively forming a second body region of a second conductivity type below the first body region in the implantation region;
    A step of selectively forming an impurity region of a first conductivity type on the first body region;
    In the step of forming the second body region,
    The second body region is formed deeper than the implantation region, and the impurity concentration of the second body region is lower than the impurity concentration of the first body region, and with respect to the main surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the semiconductor element is formed so as to be positioned inside the first body region and at least a portion of the second body region is positioned below the impurity region in plan view in a vertical direction.
  9. 　前記不純物領域を形成する工程よりも後に、
    　前記第１炭化珪素半導体層の上に、前記第１ボディ領域の少なくとも一部及び前記不純物領域の少なくとも一部とそれぞれ接するように、第１導電型の第２炭化珪素半導体層を形成する工程と、
    　前記第２炭化珪素半導体層の上に、ゲート絶縁膜及びゲート電極とを順次形成する工程とをさらに備えた、請求項８に記載の半導体素子の製造方法。     After the step of forming the impurity region,
    Forming a first conductivity type second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer so as to be in contact with at least part of the first body region and at least part of the impurity region; ,
    The method for manufacturing a semiconductor device according to claim 8, further comprising a step of sequentially forming a gate insulating film and a gate electrode on the second silicon carbide semiconductor layer.
  10. 　第１導電型の半導体基板の主面上に、第１導電型の第１炭化珪素半導体層を形成する工程と、
    　前記第１炭化珪素半導体層の上部に、第２導電型の第１ボディ領域及び第１導電型の注入領域のうちの一方の領域を選択的に形成する工程と、
    　前記第１炭化珪素半導体層における前記一方の領域の側方に、前記第１ボディ領域及び前記注入領域のうちの他方の領域を、前記一方の領域に対して自己整合的に形成する工程と、
    　前記第１炭化珪素半導体層における前記第１ボディ領域の下側に、第２導電型の第２ボディ領域を選択的に形成する工程と、
    　前記第１ボディ領域の上部に、第１導電型の不純物領域を選択的に形成する工程とを備え、
    　前記注入領域を形成する工程において、前記注入領域は、前記第２ボディ領域よりも深く形成し、
    　前記第２ボディ領域を形成する工程において、
    　前記第２ボディ領域の不純物濃度は、前記第１ボディ領域の不純物濃度よりも低く、且つ、前記半導体基板の主面に対して垂直な方向の平面視において、前記第１ボディ領域の内側に位置し、前記第２ボディ領域のうち少なくとも一部が前記不純物領域の下方に位置するように形成する半導体素子の製造方法。     Forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate;
    Selectively forming one of a second conductivity type first body region and a first conductivity type implantation region on the first silicon carbide semiconductor layer;
    Forming the other of the first body region and the implantation region in a self-aligned manner with respect to the one region on a side of the one region in the first silicon carbide semiconductor layer;
    Selectively forming a second body region of a second conductivity type below the first body region in the first silicon carbide semiconductor layer;
    A step of selectively forming an impurity region of a first conductivity type on the first body region;
    In the step of forming the implantation region, the implantation region is formed deeper than the second body region,
    In the step of forming the second body region,
    The impurity concentration of the second body region is lower than the impurity concentration of the first body region and is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate. And a method of manufacturing a semiconductor device, wherein at least a part of the second body region is located below the impurity region.
  11. 　前記注入領域を形成する工程よりも後に、
    　前記第１炭化珪素半導体層の上に、前記第１ボディ領域の少なくとも一部及び前記不純物領域の少なくとも一部とそれぞれ接するように、第１導電型の第２炭化珪素半導体層を形成する工程と、
    　前記第２炭化珪素半導体層の上に、ゲート絶縁膜及びゲート電極とを順次形成する工程とをさらに備えた、請求項１０に記載の半導体素子の製造方法。     After the step of forming the implantation region,
    Forming a first conductivity type second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer so as to be in contact with at least part of the first body region and at least part of the impurity region; ,
    The method for manufacturing a semiconductor element according to claim 10, further comprising: sequentially forming a gate insulating film and a gate electrode on the second silicon carbide semiconductor layer.
PCT/JP2013/006471 2012-11-28 2013-10-31 Semiconductor element and method for manufacturing same WO2014083771A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012259358 2012-11-28
JP2012-259358 2012-11-28

Publications (1)

Publication Number Publication Date
WO2014083771A1 true WO2014083771A1 (en) 2014-06-05

Family

ID=50827435

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/006471 WO2014083771A1 (en) 2012-11-28 2013-10-31 Semiconductor element and method for manufacturing same

Country Status (1)

Country Link
WO (1) WO2014083771A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016013182A1 (en) * 2014-07-24 2016-01-28 パナソニックＩｐマネジメント株式会社 Silicon carbide semiconductor element and method for manufacturing same
WO2016143099A1 (en) * 2015-03-11 2016-09-15 株式会社日立製作所 Semiconductor device, method for manufacturing same, and power conversion device
WO2017081935A1 (en) * 2015-11-12 2017-05-18 三菱電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
CN111430449A (en) * 2020-04-01 2020-07-17 张清纯 MOSFET device and preparation process thereof
US11862687B2 (en) 2019-10-03 2024-01-02 Fuji Electric Co., Ltd. Nitride semiconductor device and method for fabricating nitride semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213939A (en) * 1996-01-30 1997-08-15 Nec Corp Semiconductor device
JP2000183348A (en) * 1998-12-09 2000-06-30 Stmicroelectronics Srl Mos gate power device
JP2002270839A (en) * 2001-03-12 2002-09-20 Denso Corp Silicon carbide semiconductor device and method of manufacturing the same
JP2010027833A (en) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp Silicon carbide semiconductor device and its manufacturing method
WO2012056705A1 (en) * 2010-10-29 2012-05-03 パナソニック株式会社 Semiconductor element and manufacturing method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213939A (en) * 1996-01-30 1997-08-15 Nec Corp Semiconductor device
JP2000183348A (en) * 1998-12-09 2000-06-30 Stmicroelectronics Srl Mos gate power device
JP2002270839A (en) * 2001-03-12 2002-09-20 Denso Corp Silicon carbide semiconductor device and method of manufacturing the same
JP2010027833A (en) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp Silicon carbide semiconductor device and its manufacturing method
WO2012056705A1 (en) * 2010-10-29 2012-05-03 パナソニック株式会社 Semiconductor element and manufacturing method therefor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9923090B2 (en) 2014-07-24 2018-03-20 Panasonic Intellectual Property Management Co., Ltd. Silicon carbide semiconductor element and method for manufacturing the same
WO2016013182A1 (en) * 2014-07-24 2016-01-28 パナソニックＩｐマネジメント株式会社 Silicon carbide semiconductor element and method for manufacturing same
JPWO2016013182A1 (en) * 2014-07-24 2017-06-15 パナソニックＩｐマネジメント株式会社 Silicon carbide semiconductor device and manufacturing method thereof
WO2016143099A1 (en) * 2015-03-11 2016-09-15 株式会社日立製作所 Semiconductor device, method for manufacturing same, and power conversion device
JPWO2016143099A1 (en) * 2015-03-11 2017-07-13 株式会社日立製作所 Semiconductor device, method of manufacturing the same, and power conversion device
JPWO2017081935A1 (en) * 2015-11-12 2018-04-26 三菱電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
WO2017081935A1 (en) * 2015-11-12 2017-05-18 三菱電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
CN108352407A (en) * 2015-11-12 2018-07-31 三菱电机株式会社 The manufacturing method of manufacturing silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device
US10374075B2 (en) 2015-11-12 2019-08-06 Mitsubishi Electric Corporation Silicon carbide semiconductor device and manufacturing method for the same
US11862687B2 (en) 2019-10-03 2024-01-02 Fuji Electric Co., Ltd. Nitride semiconductor device and method for fabricating nitride semiconductor device
JP7413701B2 (en) 2019-10-03 2024-01-16 富士電機株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
CN111430449A (en) * 2020-04-01 2020-07-17 张清纯 MOSFET device and preparation process thereof
CN111430449B (en) * 2020-04-01 2023-06-02 清纯半导体(宁波)有限公司 MOSFET device and preparation process thereof

Similar Documents

Publication Publication Date Title
JP5433352B2 (en) Manufacturing method of semiconductor device
CN102403356B (en) Semiconductor device
JP5586887B2 (en) Semiconductor device and manufacturing method thereof
JP5693851B2 (en) Semiconductor device
WO2011027540A1 (en) Semiconductor element and method for manufacturing same
US20120012929A1 (en) Semiconductor device
JP2017092368A (en) Semiconductor device and semiconductor device manufacturing method
JP7176239B2 (en) semiconductor equipment
JP6073719B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6802454B2 (en) Semiconductor devices and their manufacturing methods
WO2017064887A1 (en) Semiconductor device
JP2023060154A (en) Semiconductor device
CN110291620B (en) Semiconductor device and method for manufacturing semiconductor device
JP4990458B2 (en) Self-aligned silicon carbide LMOSFET
WO2012131768A1 (en) Silicon carbide semiconductor device and method for producing same
WO2014083771A1 (en) Semiconductor element and method for manufacturing same
JP2011228643A (en) Semiconductor device and manufacturing method thereof
JP4948784B2 (en) Semiconductor device and manufacturing method thereof
JP2020136416A (en) Semiconductor device and semiconductor device manufacturing method
JP2010027833A (en) Silicon carbide semiconductor device and its manufacturing method
WO2016013182A1 (en) Silicon carbide semiconductor element and method for manufacturing same
CA3025767C (en) Semiconductor device
JP2005019494A (en) Semiconductor device and its manufacturing method
WO2021260853A1 (en) Silicon carbide semiconductor device
JP2019033140A (en) Semiconductor device and semiconductor device thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13859359

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13859359

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP