JP4802378B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a silicon carbide semiconductor device.SetThe present invention relates to a manufacturing method, and more particularly to an insulated gate field effect transistor, particularly to a vertical power MOSFET for high power.
[0002]
[Prior art]
Conventionally, as a storage type silicon carbide semiconductor device, for example, a vertical power MOSFET disclosed in JP-A-10-308510 is cited. FIG. 17 shows a cross-sectional configuration of this silicon carbide semiconductor device.
[0003]
This vertical power MOSFET is made of silicon carbide having a main surface and a back surface.⁺Mold substrate 1 and n⁺N epitaxially grown on the mold substrate 1^-Type epi layer 2 and n^-P-type base region 3 and n formed in the surface layer portion of the epitaxial layer 2⁺Type source region 4 and n adjacent to each other on the surface of p-type base region 3⁺N formed so as to connect the type source regions 4^-A surface channel layer 5 made of a mold layer, a gate electrode 7 formed on the surface channel layer 5 via a gate oxide film 6, and n via an interlayer insulating film 8⁺Source electrode 9 electrically connected to type source region 4 and p type base region 3, n⁺The drain electrode 10 is electrically connected to the back surface of the mold substrate 1.
[0004]
And the vertical power MOSFET of such a structure is manufactured by the following processes. FIG. 18 shows a manufacturing process of the vertical power MOSFET, and a conventional manufacturing method of the vertical power MOSFET will be described with reference to FIG.
[0005]
First, as shown in FIG.⁺N on the mold substrate 1^-The epitaxial epitaxial layer 2 is epitaxially grown, and then n is implanted by ion implantation or the like.^-A p-type base region 3 is formed in the surface layer portion of the type epi layer 2. Subsequently, n including the p-type base region 3 as shown in FIG.^-N on the surface of the epitaxial layer 2^-After the surface channel layer 5 made of the mold layer is formed, n is implanted by ion implantation as shown in FIG.⁺A mold source region 4 is formed. Then, after forming the gate oxide film 6 by thermal oxidation (gate oxidation) as shown in FIG. 18 (d), a gate electrode 7 is formed on the gate oxide film 6, and an interlayer is formed on the gate electrode 7. A source electrode 9 is formed through the insulating film 8 and n⁺By forming the drain electrode 10 on the back side of the mold substrate 1, the vertical power MOSFET shown in FIG. 17 is completed.
[0006]
[Problems to be solved by the invention]
However, when a vertical power MOSFET is manufactured by the conventional manufacturing method, n⁺Since ion implantation damage remains in the source region 4, n⁺The mold source region 4 is oxidized at a high speed, causing the following problems.
[0007]
That is, n⁺Since the end portion of the surface channel layer 5 adjacent to the mold source region 4 has an inclined shape, the gate oxide film 6 becomes thick in that portion, and a storage channel is not sufficiently formed by the voltage applied to the gate electrode 7. This causes a problem that the channel resistance becomes high. N⁺As the mold source region 4 becomes thinner, the problem of increased source resistance occurs. And n⁺The overlap amount of the type source region 4 and the surface channel layer 5 is reduced, and n⁺This causes a problem that the contact resistance between the type source region 4 and the surface channel layer 5 increases.
[0008]
Here, the storage type power MOSFET is exemplified, but the inversion type power MOSFET also has n⁺Due to the accelerated oxidation of the type source region, there arises a problem that the channel resistance is increased and the source resistance is increased.
[0009]
In view of the above points, the first object of the present invention is to prevent channel resistance from becoming higher due to accelerated oxidation of the source region. Another object of the present invention is to prevent the source resistance from being increased due to accelerated oxidation of the source region. A third object is to prevent the contact resistance between the source region and the surface channel layer from increasing.
[0014]
[Means for Solving the Problems]
  Claim1In the invention described in the above, over the source regionBy epitaxial growthThe surface channel layer is formed, and when the surface channel layer is partially removed, the end of the surface channel layer is projected outward from the end of the gate electrode. By doing so, a gate oxide film having a uniform thickness can be formed on the surface channel layer having a good surface state, and an overlap between the surface channel layer and the source region can be ensured. ThisIt is possible to prevent the channel resistance from being increased due to the accelerated oxidation of the source region, to prevent the source resistance from being increased, and to increase the contact resistance between the source region and the surface channel layer. Prevention can be achieved.
[0015]
  Claim2In the invention described in (1), by performing ion implantation from the upper part of the surface channel layer, in a lower layer than the surface channel layer, a predetermined region of the surface layer portion of the base region is shallower than the depth of the base region. A source region (4) of the first conductivity type is formed. Thus, after forming the surface channel layer, the source region may be formed below the surface channel layer.1The same effect can be obtained.
[0016]
  Claim3In the invention described in (1), the surface of the semiconductor layer including the base region and a part of the surface of the source region is epitaxially grown in a state where the predetermined region on the source region is covered with the first mask layer (21). A step of forming a first conductivity type surface channel layer (5) made of silicon carbide, and epitaxial growth is performed with the surface channel layer covered with a second mask layer, and a first mask of the source region is formed. Forming a contact layer (22) on the portion covered with the layer. As described above, if a contact layer that contacts the surface channel layer and the source region is formed by selective epitaxial growth, a gate oxide film can be formed on the epitaxial layer having a good surface state. Therefore, the claim1The same effect can be obtained.
[0022]
  Claim4In the invention described in (1), the first thermal oxidation is performed with the source region covered with a mask to form a gate oxide film (6) on the surface channel layer, and after the mask is removed, the second And a step of forming a gate oxide film over the source region by performing heat treatment. Thus, if the gate oxide film is formed in a state where the source region is covered with the mask, a gate oxide film having a uniform film thickness can be formed. As a result, the claim1The same effect can be obtained.
[0023]
  In this case, the claim6As shown in FIG. 2, the second heat treatment temperature is set lower than the first heat treatment temperature. Claims5As shown in FIG. 5, for example, silicon nitride is used as the mask.
[0024]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a cross-sectional configuration of a vertical power MOSFET according to the first embodiment of the present invention. Hereinafter, the configuration of the vertical power MOSFET according to the present embodiment will be described with reference to this figure. However, the description of the same parts as those of the conventional vertical power MOSFET shown in FIG. Only will be described.
[0026]
First, in this embodiment, n is different from the conventional one.⁺The surface channel layer 5 is formed on the upper surface of the type source region 4, and n⁺The difference is that the distance A is secured as an overlap between the mold source region 4 and the surface channel layer 5.
[0027]
Further, the present embodiment is different from the prior art in that the end portion of the surface channel layer 5 projects to the outside of the end portion of the gate electrode 7. Specifically, the end portion of the surface channel layer 5 protrudes outward from the end portion of the gate electrode 7 by a distance L. Therefore, the gate oxide film 6 is entirely formed on the surface channel layer 5.
[0028]
Furthermore, in this embodiment, the width of the gate electrode 7 in the channel length direction is n adjacent to the conventional one.⁺The difference is that the distance is set to be sufficiently longer than the distance between the mold source regions 4. Specifically, n⁺In the type source region 4, the distance from the end on the J-FET side to the end of the gate electrode 7 can be expected.
[0029]
With such a configuration, n⁺The type source region 4 and the surface channel layer 5 are sufficiently overlapped so that the gate oxide film 6 between the gate electrode 7 and the surface channel layer 5 has a uniform thickness.
[0030]
Next, the manufacturing process of the vertical power MOSFET shown in FIG. 1 is shown in FIGS. 2 to 3, and the manufacturing method of the vertical power MOSFET will be described with reference to these drawings.
[0031]
[Step shown in FIG. 2 (a)]
First, n provided with a drain electrode 10 on the back side⁺After preparing the mold substrate 1, n⁺N by epitaxial growth on the mold substrate 1^-A type epi layer 2 is formed. N^-After forming the p-type base region 3 in the surface layer portion of the p-type epi layer 2, n⁺A mold source region 4 is formed.
[0032]
[Step shown in FIG. 2 (b)]
n⁺Including the surfaces of the type source region 4 and the p-type base region 3, and n^-N on the surface of the epitaxial layer 2^-A surface channel layer 5 made of a mold layer is epitaxially grown. The surface channel layer 5 thus formed is a film having a good surface state in which the surface is not damaged by ion implantation or the like.
[0033]
[Step shown in FIG. 2 (c)]
A gate oxide film 6 is formed on the surface of the surface channel layer 5 by thermal oxidation. At this time, as described above, since the surface channel layer 5 is a film having a good surface state, the gate oxide film 6 has a uniform film thickness and is not partially oxidized at a speed.
[0034]
[Step shown in FIG. 3 (a)]
After depositing polysilicon doped with impurities on the surface of the gate oxide film 6, the polysilicon is patterned to form the gate electrode. Then, after forming an interlayer insulating film 8 made of an LTO film or the like so as to cover the gate electrode 7, the interlayer insulating film 8 and the gate oxide film 6 are selectively etched to form a contact hole to be a source contact.
[0035]
[Step shown in FIG. 3B]
N of the surface channel layers 5⁺A portion formed on the mold source region 4 is selectively etched. At this time, a photomask for etching the surface channel layer 5 is used so that the end of the surface channel layer 5 protrudes beyond the end of the gate electrode 7. Then, after forming an electrode layer on the interlayer insulating film 8, the electrode layer is patterned to form n⁺A source electrode 9 in contact with the type source region 4 and the p type base region 3 is formed, and the vertical power MOSFET shown in FIG. 1 is completed.
[0036]
In the vertical power MOSFET described above, n⁺Since the gate oxide film 6 is formed by preventing the surface of the mold source region 4 from being thermally oxidized and only the surface channel layer 5 is thermally oxidized, the thickness of the gate oxide film 6 can be made uniform. For this reason, n⁺It is possible to prevent the channel resistance from being increased due to accelerated oxidation of the source region 4. N⁺It is also possible to prevent the source resistance from being increased due to accelerated oxidation of the type source region.
[0037]
In the vertical power MOSFET, n⁺By forming the surface channel layer 5 on the type source region 4, n⁺A contact area between the mold source region 4 and the surface channel layer 5 is ensured. For this reason, n⁺It is also possible to prevent the contact resistance between the mold source region 4 and the surface channel layer 5 from increasing.
[0038]
(Second Embodiment)
In the present embodiment, the vertical power MOSFET shown in the first embodiment is formed by another manufacturing method. Therefore, only different parts of the manufacturing method from the first embodiment will be described. FIG. 4 shows a manufacturing process of the vertical power MOSFET in this embodiment.
[0039]
First, in the process shown in FIG. 4A, the formation of the p-type base region 3 is performed in the process of FIG. 2A shown in the first embodiment. Subsequently, as a step shown in FIG. 4B, the surface of the p-type base region 3 is included, and n^-After the surface channel layer 5 is formed on the surface of the type epi layer 2, as shown in FIG. 4 (c), n-type impurities are ion-implanted into the p-type base region 3 from the upper part of the surface channel layer 5. N⁺A mold source region 4 is formed. At this time, by adjusting the ion implantation range, the ion implantation amount with respect to the ion implantation depth is made to have the relationship of the box profile shown on the right side of FIG. 4C. Thereafter, the vertical power MOSFET is completed by performing the steps shown in FIG. 2C and thereafter in the first embodiment.
[0040]
Thus, after the surface channel layer 5 is formed, n is implanted by ion implantation.⁺Even if the type source region 4 is formed, n is formed below the surface channel layer 5.⁺By forming the type source region 4, the gate oxide film 6 can be formed only by the surface channel layer 5. Thereby, the effect similar to 1st Embodiment can be acquired.
[0041]
(Third embodiment)
In the present embodiment, substantially the same configuration as the vertical power MOSFET shown in the first embodiment is formed by another manufacturing method. Therefore, only different parts of the manufacturing method from the first embodiment will be described. 5 and 6 show the manufacturing process of the vertical power MOSFET in this embodiment.
[0042]
First, in the step shown in FIG. 5A, the same step as that in FIG. 2A shown in the first embodiment is performed. Subsequently, the following steps shown in FIG.
[0043]
[Step shown in FIG. 5B]
n⁺Including the surfaces of the type source region 4 and the p-type base region 3, and n^-A first mask layer 20 is formed on the surface of the mold epilayer 2. For example, the first mask layer 20 is formed from a graphite film or the like. And by photoetching, n⁺The first mask layer 20 is left only in the part of the mold source region 4 where the contact with the source electrode 9 is taken, and the other part is removed. Then, epitaxial growth is performed with the first mask layer 20 as a mask. As a result, epitaxial growth is selectively performed in a region not covered with the first mask layer 20, and n^-A surface channel layer 5 made of a mold layer is formed.
[0044]
[Step shown in FIG. 5 (c)]
After removing the first mask layer 20, the surface channel layer 5 and n⁺A second mask layer 21 is formed on the surface of the mold source region 4. For example, the second mask layer 21 is formed from a graphite film or the like. And by photoetching, n⁺After the second mask layer 21 on the mold source region 4 is removed, epitaxial growth is performed with the second mask layer 21 as a mask. Thereby, epitaxial growth is selectively performed in a region not covered with the second mask layer 21, and n⁺A contact layer 22 made of a mold layer is formed. This contact layer 22 is not formed in the vertical power MOSFET in the first embodiment, but n⁺This is used for contact between the mold source region 4 and the source electrode 9.
[0045]
Thereafter, in the steps shown in FIGS. 6A to 6C, the same steps as those in FIGS. 2C, 3A, and 3B in the first embodiment are performed. 1, a vertical power MOSFET in which the contact layer 22 is formed is completed. Thus, by performing selective epitaxial growth, the surface channel layer 5 and n⁺If the contact layer 22 that makes contact with the type source region 4 is formed, the surface channel layer 5 and the contact layer 22 are formed of an epitaxial layer having good crystallinity, so that the thickness of the gate oxide film 6 is made uniform. And the same effects as those of the first embodiment can be obtained.
[0046]
(Fourth embodiment)
FIG. 7 shows a cross-sectional configuration of a vertical power MOSFET in the fourth embodiment of the present invention. Hereinafter, the configuration of the vertical power MOSFET according to the present embodiment will be described with reference to this figure. However, the description of the same parts as those of the vertical power MOSFET according to the first embodiment shown in FIG. Only the part will be described.
[0047]
In the present embodiment shown in FIG. 7, n is different from FIG.⁺Type source region 4, p type base region 3 and n^-A recess is formed in a region of the type epilayer 2 where the surface channel layer 5 is formed, and the surface channel layer 5 is embedded in the recess. It is different that it is in an inclined state.
[0048]
The manufacturing process of the vertical power MOSFET configured as described above is shown in FIGS. 8 and 9, and the manufacturing method of the vertical power MOSFET of this embodiment will be described based on these drawings.
[0049]
First, in the process shown in FIG. 8A, the same process as in FIG. 2A shown in the first embodiment is performed. Subsequently, the following steps shown in FIG.
[0050]
[Step shown in FIG. 8B]
n⁺N including the surfaces of the source region 4 and the p-type base region 3^-A mask layer 30 is formed on the surface of the mold epilayer 2. For example, the mask layer 30 is formed from a graphite film or the like. Then, after selectively removing the mask layer 30, n masks 30 are used as masks.⁺Type source region 4, p type base region 3 and n^-A recess is formed in the region of the type epi layer 2 where the surface channel layer 5 is to be formed.
[0051]
[Step shown in FIG. 8C]
Epitaxial growth is performed using the mask layer 30 as a mask. As a result, the epitaxial growth is selectively performed in a region not covered with the mask layer 30, and n^-A surface channel layer 5 made of a mold layer is formed.
[0052]
[Step shown in FIG. 9A]
After removing the mask layer 30, a gate oxide film 6 is formed by thermal oxidation. At this time, n formed by ion implantation⁺Since the mold source region 4 is exposed, n⁺Enhanced oxidation is performed on the surface of the mold source region 4. However, n⁺Type source region 4, p type base region 3 and n^-Since the surface channel layer 5 is embedded in the recess formed in the type epi layer 2, the surface channel layer 5 can remain thicker after thermal oxidation. Also, by adjusting the width of the recess, n⁺An overlap portion between the type source region 4 and the surface channel layer 5 can be expected, and n⁺The contact resistance between the mold source region 4 and the surface channel layer 5 can also be reduced.
[0053]
Thereafter, in the steps shown in FIGS. 9B and 9C, the same steps as in FIGS. 3A and 3B in the first embodiment are performed, and the vertical power MOSFET shown in FIG. 7 is completed.
[0054]
The vertical power MOSFET configured in this way has n⁺Since sufficient overlap between the type source region 4 and the surface channel layer 5 can be taken, n⁺The contact resistance between the mold source region 4 and the surface channel layer 5 can be prevented from increasing. Further, by adjusting the width of the recess for embedding the surface channel layer 5, even if the end portion of the surface channel layer 5 has an inclined shape, the gate electrode 7 can be arranged inside the portion. . For this reason, the gate oxide film 6 between the gate electrode 7 and the surface channel layer 5 can have a uniform film thickness, and it is also possible to prevent the channel resistance from being increased.
[0055]
(Fifth embodiment)
FIG. 10 shows a cross-sectional configuration of a vertical power MOSFET in the fifth embodiment of the present invention. Hereinafter, the configuration of the vertical power MOSFET according to the present embodiment will be described with reference to this figure, but the description of the same parts as those of the vertical power MOSFET according to the fourth embodiment shown in FIG. Only the part will be described.
[0056]
In this embodiment shown in FIG. 10, n is different from FIG.⁺The type source region 4 is divided into two parts, an n-type region 4a as a first region constituted by the first concentration, and a second region constituted by a second concentration higher than the first concentration. N⁺N by mold region 4b⁺A mold source region 4 is formed. Specifically, n-type region 4a is arranged in contact with surface channel layer 5, and n-type region 4a has n⁺The mold region 4 b is arranged so as to be separated from the surface channel layer 5.
[0057]
The manufacturing process of the vertical power MOSFET configured as described above is shown in FIGS. 11 and 12, and the manufacturing method of the vertical power MOSFET of this embodiment will be described based on these drawings.
[0058]
First, in the steps shown in FIGS. 11A and 11B, the same steps as in FIGS. 4A and 4B shown in the second embodiment are performed. Subsequently, as shown in FIG. 11C, after the n-type region 4a is formed by selectively ion-implanting the n-type impurity from the upper surface of the surface channel layer 5, the n-type impurity is selectively removed. N by ion implantation⁺A mold region 4b is formed. Then, in the steps shown in FIGS. 12A to 12C, the same steps as in FIGS. 8A to 8C are performed to complete the vertical power MOSFET shown in FIG.
[0059]
In such a vertical power MOSFET, n⁺Since the region in contact with the surface channel layer 5 in the type source region 4 is constituted by the n-type region 4a having a relatively low impurity concentration, the n-type region 4a is increased during the thermal oxidation when the gate oxide film 6 is formed. Fast oxidation is not achieved, n⁺Only the mold region 4b is subjected to accelerated oxidation. Therefore, the thickness of the gate oxide film 6 between the surface channel layer 5 and the gate electrode 7 can be made uniform, and the surface channel layer 5 and n⁺Sufficient contact area with the source region 4 and n⁺A sufficient thickness of the mold source region 4 can be obtained. For this reason, the effect similar to 1st Embodiment can be acquired.
[0060]
(Sixth embodiment)
FIG. 13 shows a cross-sectional configuration of a vertical power MOSFET in the sixth embodiment of the present invention. In this embodiment, the surface channel layer 5 in the vertical power MOSFET of the fifth embodiment shown in FIG. 10 is eliminated, and an inverted vertical power MOSFET is formed.
[0061]
Thus, even in the inverted vertical power MOSFET, n⁺The configuration of the type source region 4 is different from that of the fifth embodiment in two parts (n-type regions 4a and n⁺By forming the type region 4b), the accelerated oxidation can be prevented from being performed on the n-type region 4a side, so that the thickness of the gate oxide film 6 can be made uniform, and the channel resistance can be increased. Can be prevented, and the source resistance can be prevented from being increased.
[0062]
The vertical power MOSFET having such a configuration is the surface channel layer 5 shown in FIG. 11B in the manufacturing process of the storage type vertical power MOSFET in the fifth embodiment shown in FIGS. It is only necessary if the forming step is not performed, and the other manufacturing methods are exactly the same.
[0063]
(Seventh embodiment)
In each of the above embodiments, n⁺The gate oxide film 6 is formed after the formation of the source region 4, and n is formed after the gate oxide film 6 is formed.⁺By forming the mold source region 4, it is possible to obtain the same effect as that of the first embodiment. The manufacturing process of such a vertical power MOSFET is shown in FIGS. 14 and 15, and the manufacturing method of the vertical power MOSFET in this embodiment will be described.
[0064]
First, in the steps shown in FIGS. 14A and 14B, the same steps as in FIGS. 4A and 4B shown in the second embodiment are performed. Subsequently, as shown in FIG. 14C, a gate oxide film 6 is formed on the surface of the surface channel layer 5 by thermal oxidation. That is, n⁺Prior to the formation of the mold source region 4, a gate oxide film 6 is formed. Then, after selectively forming a gate electrode 7 on the gate oxide film 6 as shown in FIG. 15A, ion implantation using the gate electrode 7 as a mask is performed as shown in FIG. 15B. Then, the implanted ions are activated by RTA (short-time heat treatment) at 1000 ° C. or lower to make n⁺A mold source region 4 is formed. Thereafter, in the step shown in FIG. 15C, the same steps as those shown in FIGS. 2A and 2B shown in the first embodiment are performed to complete the vertical power MOSFET.
[0065]
In this way, the step of forming the gate oxide film 6 is n⁺By applying before the step of forming the mold source region 4, n⁺The problem of accelerated oxidation in the mold source region 4 is also eliminated, and the same effect as in the first embodiment can be obtained.
[0066]
Although the gate electrode 7 is used as a mask here, the same effect as described above can be obtained even when the gate electrode 7 and the interlayer insulating film 8 are used as a mask.
[0067]
(Eighth embodiment)
In this embodiment, n⁺In view of the accelerated oxidation of the source region 4, a region formed on the surface channel layer 5 in the gate oxide film 6 and n⁺The region formed on the mold source region 4 and the thickness of each region are controlled to be substantially uniform. The manufacturing process of such a vertical power MOSFET is shown in FIG. 16, and the manufacturing method of the vertical power MOSFET in this embodiment will be described.
[0068]
First, in the process shown in FIG. 16A, by performing FIGS. 18A to 18C shown as the manufacturing process of the conventional vertical power MOSFET, and performing ion implantation from the surface of the surface channel layer 5, n⁺A mold source region 5 is formed. Subsequently, as shown in FIG.⁺After forming the mask layer 40 on the mold source region 4, the mask layer 40 forms n⁺Thermal oxidation is performed while covering the mold source region 4 to form a gate oxide film 6 on the surface channel layer 5. Then, after removing the mask layer 40, low-temperature re-oxidation is performed, so that the gate oxide film 6 is n.⁺It is also formed on the mold source region 4. Thereafter, the vertical power MOSFET shown in this embodiment is completed by performing the same steps as those shown in FIGS. 3A and 3B shown in the first embodiment.
[0069]
Thus, once the gate oxide film 6 is formed, n⁺The gate oxide film 6 is made to cover the n-type source region 4 and then the low-temperature reoxidation is performed to form the gate oxide film 6⁺By forming also on the type source region 4, n⁺The accelerated oxidation in the mold source region 4 can be prevented. Even if it does in this way, the effect similar to 1st Embodiment can be acquired.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross-sectional configuration of a vertical power MOSFET according to a first embodiment of the present invention.
2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG.
3 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 2. FIG.
FIG. 4 is a diagram showing a manufacturing process of the vertical power MOSFET shown in the second embodiment of the present invention.
FIG. 5 is a diagram showing a manufacturing process of the vertical power MOSFET shown in the third embodiment of the present invention.
6 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 5. FIG.
FIG. 7 is a diagram showing a cross-sectional configuration of a vertical power MOSFET according to a fourth embodiment of the present invention.
8 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 7;
FIG. 9 is a diagram illustrating manufacturing steps of the vertical power MOSFET subsequent to FIG. 8;
FIG. 10 is a diagram showing a cross-sectional configuration of a vertical power MOSFET shown in a fifth embodiment of the present invention.
11 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 10; FIG.
12 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 11. FIG.
FIG. 13 is a diagram showing a cross-sectional configuration of a vertical power MOSFET shown in a sixth embodiment of the present invention.
FIG. 14 is a diagram showing manufacturing steps of the vertical power MOSFET shown in the seventh embodiment of the present invention.
15 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 14. FIG.
FIG. 16 is a diagram showing manufacturing processes for the vertical power MOSFET shown in the eighth embodiment of the present invention;
FIG. 17 is a diagram showing a cross-sectional configuration of a conventional vertical power MOSFET.
FIG. 18 is a diagram showing a manufacturing process of a conventional vertical power MOSFET.
[Explanation of symbols]
1 ... n⁺Mold substrate, 2 ... n^-Type epi layer, 3... P type base region,
4 ... n⁺Type source region, 5... Surface channel layer, 6... Gate oxide film,
7 ... Gate electrode, 9 ... Source electrode, 10 ... Drain electrode.

Claims (6)

Providing a first conductive type semiconductor substrate (1) having a main surface and a back surface and made of silicon carbide;
Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the semiconductor substrate;
Forming a second conductive type base region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a first conductivity type source region (4) shallower than a depth of the base region in a predetermined region of a surface layer portion of the base region;
Forming a first conductivity type surface channel layer (5) made of silicon carbide on the surface of the semiconductor layer including the surface of the base region and the source region by epitaxial growth ;
Forming a gate oxide film (6) on the surface of the surface channel layer by thermal oxidation;
Forming a gate electrode (7) on the gate oxide film;
Forming a source electrode (9) in contact with the base region and the source region;
Forming a drain electrode (10) on the back surface of the semiconductor substrate,
In the step of forming the source electrode, the surface channel layer is partially removed on the source region so that an end portion of the surface channel layer protrudes outside an end portion of the gate electrode. A method for manufacturing a semiconductor device. Providing a first conductive type semiconductor substrate (1) having a main surface and a back surface and made of silicon carbide;
Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the semiconductor substrate;
Forming a second conductive type base region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a first conductivity type surface channel layer (5) made of silicon carbide on the surface of the semiconductor layer including the surface of the base region by epitaxial growth ;
By performing ion implantation from the upper part of the surface channel layer, a first conductive layer shallower than the depth of the base region is formed in a predetermined region of the surface layer portion of the base region below the surface channel layer. Forming a source region (4) of the mold;
Forming a gate oxide film (6) on the surface of the surface channel layer by thermal oxidation;
Forming a gate electrode (7) on the gate oxide film;
Forming a source electrode (9) in contact with the base region and the source region;
Forming a drain electrode (10) on the back surface of the semiconductor substrate,
In the step of forming the source electrode, the surface channel layer is partially removed on the source region so that an end portion of the surface channel layer protrudes outside an end portion of the gate electrode. A method for manufacturing a semiconductor device. Providing a first conductive type semiconductor substrate (1) having a main surface and a back surface and made of silicon carbide;
Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the semiconductor substrate;
Forming a second conductive type base region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a first conductivity type source region (4) shallower than a depth of the base region in a predetermined region of a surface layer portion of the base region;
Epitaxial growth is performed in a state in which a predetermined region on the source region is covered with a first mask layer (20), and on the surface of the semiconductor layer including the base region and a part of the surface of the source region. Forming a first conductivity type surface channel layer (5) made of silicon carbide;
Performing epitaxial growth in a state where the surface channel layer is covered with a second mask layer (21), and forming a contact layer (22) on a portion of the source region covered with the first mask layer. When,
Forming a gate oxide film (6) on the surface of the surface channel layer by thermal oxidation;
Forming a gate electrode (7) on the gate oxide film;
Forming a source electrode (9) in contact with the base region and the source region;
Forming a drain electrode (10) on the back surface of the semiconductor substrate,
In the step of forming the surface channel layer, the first mask layer is set so that an end portion of the surface channel layer projects outward from an end portion of the gate electrode. Production method. Providing a first conductive type semiconductor substrate (1) having a main surface and a back surface and made of silicon carbide;
Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the semiconductor substrate;
Forming a second conductive type base region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a first conductivity type surface channel layer (5) made of silicon carbide on the surface of the semiconductor layer including the surface of the base region;
A step of forming a first conductivity type source region (4) shallower than the base region in a predetermined region of the surface channel layer and the base region by performing ion implantation from above the surface channel layer. When,
Performing a first thermal oxidation with the source region covered with a mask to form a gate oxide film (6) on the surface channel layer;
Forming the gate oxide film on the source region by performing a second heat treatment after removing the mask;
Forming a gate electrode (7) on the gate oxide film;
Forming a source electrode (9) in contact with the base region and the source region;
Forming a drain electrode (10) on the back surface of the semiconductor substrate. A method for manufacturing a silicon carbide semiconductor device, comprising: The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein silicon nitride is used as the mask. The method for manufacturing the silicon carbide semiconductor device according to claim 4 or 5, characterized in that the second heat treatment temperature to a low temperature than the first annealing temperature.

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