JPS62229880A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS62229880A
JPS62229880A JP7076686A JP7076686A JPS62229880A JP S62229880 A JPS62229880 A JP S62229880A JP 7076686 A JP7076686 A JP 7076686A JP 7076686 A JP7076686 A JP 7076686A JP S62229880 A JPS62229880 A JP S62229880A
Authority
JP
Japan
Prior art keywords
region
impurity
conductivity type
oxide film
high concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7076686A
Other languages
Japanese (ja)
Inventor
Yoshinori Asahi
朝日 良典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7076686A priority Critical patent/JPS62229880A/en
Publication of JPS62229880A publication Critical patent/JPS62229880A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To alleviate the increase in electric field intensity, to improve withstanding voltage and to decrease adverse effects due to yield of hot carriers, by a structure, wherein impurity regions, which are to become a source and a drain, are positively isolated from a fieldinversion preventing impurity region. CONSTITUTION:On a p-type semiconductor substrate 11, an element isolating regions comprising a field oxide film 12 and a high-concentration impurity p<+> region 13 is formed. A gate oxide film is formed by thermal oxidation. A polycrystalline silicon film is formed on the entire surface by CVD. Selective etching is performed, and a gate electrode 16 is formed. A polycrystalline silicon layer is extended to a boundary part between an element region and the element isolating region. With the polycrystalline silicon film 16 as a mask, highconcentration impurity n<+> regions 14 and 15 are formed by ion implantation or diffusion. The high-concentration u<+> region 15 for a drain is isolated from the high-concentration p<+> region 13 beneath the field oxide film 12. An insulator 18 of a CVD-silicon oxide film is deposited. Contact holes are formed, and an Al evaporated pattern 19 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMO8半導体装置及びその製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an MO8 semiconductor device and a method for manufacturing the same.

〔従来技術〕[Prior art]

従来のMOa型半導体装置の構造を第5図に示す、第5
図aは、平面図であり、A−A’  の断面図を第5図
すに、B−「の断面図1−@5図Cに示す9図において
P型半導体基板1の表面上には絶縁体2からなる素子分
離領域が選択的に設けられている、この素子分離領域以
外の素子領域表面には互いに電気的に分離された高濃度
のn型のソース領域4とドレイン領域5が設けられ、こ
れらソース領域4.ドレイン領域5の間の基板1上には
The structure of a conventional MOa type semiconductor device is shown in FIG.
FIG. An element isolation region made of an insulator 2 is selectively provided, and a highly doped n-type source region 4 and drain region 5 electrically isolated from each other are provided on the surface of the element region other than this isolation region. and on the substrate 1 between the source region 4 and drain region 5.

ゲート絶#を膜7を介してゲート電極6が設けられてい
る。ソース領域4とドレイン領域5とゲート電極6上に
はこれらに接続される配線9が設けられ、全面は絶縁膜
8が堆積されている。また素子分離領域のフィールド酸
化膜2の下の基板lにはn型のソース・ドレイン領域4
,5に隣接してP型高濃度不純物(P+)領域3がフィ
ールド反転防止のために設けられている。
A gate electrode 6 is provided with a film 7 in between. Wires 9 are provided on the source region 4, drain region 5, and gate electrode 6 to be connected thereto, and an insulating film 8 is deposited on the entire surface. Also, in the substrate l below the field oxide film 2 in the element isolation region, there is an n-type source/drain region 4.
, 5, a P-type high concentration impurity (P+) region 3 is provided to prevent field inversion.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

半導体装置の微細化が進むにつれて、ゲート酸化膜の薄
膜化、基板濃度の上昇などによって接合耐圧が低下する
傾向にある。従来のMO8半導体装置は、第5図に示し
友ように高不純物濃度上領域とドレイ/領域を形成する
n中領域が接している念めにゲート電圧が印加されると
空乏層が伸びにくくなり、接触部分でとくに電界強度が
強くなる。これによシ、耐圧値が低下したp、ホットキ
ャリアが生成され信頼性が低下する。この問題は特にチ
ャネル巾が小さいトランジスタにおいて顕著に現われる
。電界の増大を緩和させるために複数の拡散速度の異な
る不純物でソース・ドレイン領域を構成するGDD構造
や2回のイオン注入によりソース・ドレイン領域全形成
し、不純物濃度のプロ7マイルを滑らかにしたLDD構
造が知られているが、これらの構造においても、高不純
物濃度n中領域と上領域との接触は避けられない。
As the miniaturization of semiconductor devices progresses, the junction breakdown voltage tends to decrease due to thinning of gate oxide films, increase in substrate concentration, etc. In the conventional MO8 semiconductor device, as shown in Fig. 5, the high impurity concentration upper region and the n middle region forming the drain/region are in contact with each other.When a gate voltage is applied, the depletion layer becomes difficult to grow. , the electric field strength becomes particularly strong at the contact area. As a result, the breakdown voltage value decreases, hot carriers are generated, and reliability decreases. This problem is particularly noticeable in transistors with small channel widths. In order to alleviate the increase in electric field, the source/drain region is constructed with a GDD structure consisting of multiple impurities with different diffusion rates, and the entire source/drain region is formed by two ion implantations to smooth the impurity concentration. LDD structures are known, but even in these structures, contact between the high impurity concentration n middle region and the upper region is unavoidable.

また、この不純物拡散領域nとフィールド反転防止用の
不純物拡散領域p+の接触は空乏層が伸びにくいことか
ら寄生キャパシタンスの容量が増大し、回路の速度が低
下するという問題もある。
Furthermore, since the depletion layer is difficult to extend in the contact between the impurity diffusion region n and the impurity diffusion region p+ for preventing field inversion, there is a problem that the parasitic capacitance increases and the speed of the circuit decreases.

本発明はこのような耐圧性、信頼性、速度の低下を改善
すること?目的とする。
Does the present invention improve such deterioration in pressure resistance, reliability, and speed? purpose.

〔問題点ヲ屏決するための手段〕[Means for determining issues]

以上述べ念耐圧性、信頼性、速度の低下は、ソース・ド
レインとなる不純物領域n+と、フィールド反転防止用
の不純物領域p+とが接触していることに帰因する。そ
こで本発明は、ゲート電極管形成する念めの第1層目の
導電層を素子領域と素子分離領域との境界部分にも形成
し、この導電層管マスクとして不純物を注入し、ソース
・ドレイン領域を形成した1本発明はこのように従来の
第1層目の導電層をゲー)1[に形成するのと同時に素
子領域と素子分離領域の境界部分に形成することによっ
てソース・ドレインとなる不純物領域n+とフィールド
反転防止用の不純物領域p+とを積極的に分離し次構造
を提供する。
The above-mentioned reductions in voltage resistance, reliability, and speed are attributable to the fact that the impurity region n+ serving as the source/drain is in contact with the impurity region p+ for preventing field inversion. Therefore, in the present invention, a first conductive layer for forming a gate electrode tube is also formed at the boundary between the element region and the element isolation region, and impurities are implanted as a mask for the source and drain layers. In this way, the present invention forms the conventional first conductive layer at the boundary between the element region and the element isolation region, thereby forming the source and drain. The impurity region n+ and the impurity region p+ for preventing field inversion are actively separated to provide the next structure.

〔作用〕[Effect]

以上のように構成された半導体装置は、ソース・ドレイ
ンとなる不純物領域n+とフィールド反転防止用の不純
物領域とが接していないため、ゲート電極に電圧が印加
されると高濃度不純物n中領域の基板との境界部分に加
えて、従来高濃度不純物p+領領域接触していた部分に
おいても空乏層が充分大がり、電界強度の増大をおさえ
ることができる。
In the semiconductor device configured as described above, since the impurity region n+ that becomes the source/drain and the impurity region for preventing field reversal are not in contact with each other, when a voltage is applied to the gate electrode, the high concentration impurity region n+ In addition to the boundary portion with the substrate, the depletion layer is sufficiently enlarged in the portion conventionally in contact with the high-concentration impurity p+ region, and an increase in electric field strength can be suppressed.

〔実施例〕〔Example〕

以下2本発明の一実施例t−第1図a〜gに示す製造方
法を併記して説明する。
Hereinafter, two embodiments of the present invention - manufacturing methods shown in FIGS. 1a to 1g will be described together.

まず、p型半導体基板11に酸化膜101f:形成し、
その表面にさらにシリコン窒化膜102t−形成し、素
子分離領域の選択酸化用パターンを形成する。選択的に
形成されたシリコン窒化膜102をマスクにして不純物
(例えばボロン)を注入する。
First, an oxide film 101f is formed on the p-type semiconductor substrate 11,
A silicon nitride film 102t- is further formed on the surface, and a pattern for selective oxidation of an element isolation region is formed. Impurities (for example, boron) are implanted using the selectively formed silicon nitride film 102 as a mask.

(第1図aに図示)次にフィールド酸化膜12t−形成
した後酸化[101と窒化膜102t−除去し、第1図
すに示すようなp型基板11にフィールド酸化膜12と
高濃度不純物p中領域13とからなる素子分離領域が形
成される。つづいて熱酸化を行ないゲート酸化膜を形成
した後、ゲート電極となる多結晶シリコン膜t−CVD
により全面に形成する。
(Illustrated in FIG. 1A) Next, after forming a field oxide film 12t, oxidation film 101 and nitride film 102t are removed, and a field oxide film 12 and high concentration impurity are formed on the p-type substrate 11 as shown in FIG. An element isolation region consisting of p medium region 13 is formed. Next, thermal oxidation is performed to form a gate oxide film, and then a polycrystalline silicon film that will become the gate electrode is deposited by t-CVD.
Form on the entire surface.

つづいて多結晶シリーン膜を選択的にエツチングして、
ゲート電極16!形成するとともに第1図Cに示すよう
に素子領域と素子分離領域との境界部分にもこの多結晶
シリコン層を延在させる。次にパターン形成し九多結晶
シリコン膜16をマスクとしてイオン注入または拡散を
行ない(第1図dに図示)、第1図Cに示すような高濃
度不純物n中領域14.15が形成さ、れ、ドレインの
高濃度不純物n十領域15とフィールド酸化膜下の高濃
度不純物p十領域13とは分離される。つづいて第1図
fに示すようにCVD−シリコン酸化膜のような絶縁物
18を堆積し、ソース・ドレイン電極用のコンタクトホ
ールを形成し友後、Atf蒸着してAtパターン19t
−形成し、第1図gに示す半導体を得る。第1図gは@
1図りのA−ににおける断面図である。このように本発
明の第1の実施例ではゲート電極のマスクパターンfn
+のドレイン領域色素子分離酸化膜下のp+の不純物領
域との境界部分にも延在させこれをマスクとして両領域
を形成することにより両領域の接触を避けることができ
Next, the polycrystalline silicon film is selectively etched,
Gate electrode 16! At the same time, this polycrystalline silicon layer is also extended to the boundary between the element region and the element isolation region as shown in FIG. 1C. Next, a pattern is formed, and ion implantation or diffusion is performed using the nine-polycrystalline silicon film 16 as a mask (as shown in FIG. 1D), to form high concentration impurity n medium regions 14 and 15 as shown in FIG. 1C. As a result, the high concentration impurity n+ region 15 of the drain is separated from the high concentration impurity p+ region 13 under the field oxide film. Subsequently, as shown in FIG. 1f, an insulator 18 such as a CVD silicon oxide film is deposited, contact holes for source and drain electrodes are formed, and then Atf is deposited to form an At pattern 19t.
- forming the semiconductor shown in FIG. 1g. Figure 1 g is @
FIG. 1 is a sectional view taken along line A- in Figure 1; In this way, in the first embodiment of the present invention, the gate electrode mask pattern fn
Contact between the two regions can be avoided by extending the + drain region to the boundary with the p+ impurity region under the dye element isolation oxide film and using this as a mask to form both regions.

電界強度を緩和できる。Can reduce electric field strength.

次に他の実施例について説明する。Next, other embodiments will be described.

第2図はGDD講造の半導体装置に本発明を適用した実
施例である。第1の実施例で説明した工程(第1図az
d)に従い、p型半導体基板21上にフィールド酸化膜
22とその下の半導体領域に形成されたP十型高濃度不
純物領域23からなる素子分離領域を形成し、この素子
分離領域に領接する素子領域にゲート酸化膜27を形成
し、このゲート酸化膜27上のゲート電極を形成する部
分及び素子領域と素子分離領域の境界部分上に多結晶シ
リコン層26を形成する。この多結晶シリコン層をマス
クにしてn型の拡散速度の速い不純物。
FIG. 2 shows an embodiment in which the present invention is applied to a semiconductor device manufactured by GDD Kozo. The process explained in the first example (Fig. 1 az
d), an element isolation region consisting of a field oxide film 22 and a P-type high-concentration impurity region 23 formed in the semiconductor region below is formed on the p-type semiconductor substrate 21, and an element adjacent to this element isolation region is formed. A gate oxide film 27 is formed in the region, and a polycrystalline silicon layer 26 is formed on the gate oxide film 27 at a portion where a gate electrode is to be formed and on the boundary portion between the element region and the element isolation region. Using this polycrystalline silicon layer as a mask, an n-type impurity with a fast diffusion rate is added.

例えばリンを比較的深く注入した後、この不純物に比べ
て拡散速度の遅いn型の不純物1例えばヒ素を注入して
、ソース・ドレイン領域24 、25 ?形成する。そ
の稜CVDシリコン酸化膜28を堆積し食後、コンタク
トホールを形成し、アルミ電極29t−蒸着する。この
ように製造された半導体装置は、ドレイン領域25とフ
ィールド反転防止用不純物23が分離されているので空
乏層を充分に拡げることができる上に、ソース・ドレイ
ン領域が第1の高不純物濃度領域と2重の注入で更に高
濃度の第2の高不純物濃度領域によシ構成され。
For example, after implanting phosphorus relatively deeply, an n-type impurity 1 such as arsenic, which has a slower diffusion rate than this impurity, is implanted into the source/drain regions 24, 25? Form. After depositing and eating the edge CVD silicon oxide film 28, a contact hole is formed and an aluminum electrode 29t is deposited. In the semiconductor device manufactured in this way, since the drain region 25 and the field inversion prevention impurity 23 are separated, the depletion layer can be sufficiently expanded. A second high impurity concentration region with an even higher concentration is formed by double implantation.

第3図に示すように不純物濃度のプロアサイルが滑らか
であり、電界強度を緩和することができる。
As shown in FIG. 3, the impurity concentration profile is smooth, and the electric field strength can be relaxed.

第3図はLDD構造の半導体装置を本発明によシ製造し
た実施例である。第1図、第2図の実施と同様にp型半
導体基板31上にゲート絶縁膜37を介してゲート電極
の多結晶シリコンのパターン36を形成する。(第1図
a〜Cに図示)その後、多結晶シリコンをマスクとして
ソース・ドレイン不純物として拡散速度の速い不純物、
例えばリンを注入する0次いで多結晶シリコンの側壁に
、CVD51Oz40f堆1aさJt、第2のソース・
ドレイン不純物として1例えばヒ素とイオン注入する。
FIG. 3 shows an example in which a semiconductor device having an LDD structure is manufactured according to the present invention. Similar to the embodiments shown in FIGS. 1 and 2, a polycrystalline silicon pattern 36 for a gate electrode is formed on a p-type semiconductor substrate 31 with a gate insulating film 37 interposed therebetween. (Illustrated in Figures 1a to 1C) Then, using polycrystalline silicon as a mask, impurities with a fast diffusion rate are added as source/drain impurities.
For example, implant phosphorous into the sidewalls of the polycrystalline silicon, CVD 51Oz40f deposited Jt, and a second source layer.
For example, ions of arsenic are implanted as a drain impurity.

この結果ソース・ドレイン領域にn領域とn十領域が設
けられる。多結晶シリコンの側壁にCVD8i02=i
堆積させる代シにレジストでパターニングしたのち、第
2のイオン注入を行ないその後レジストヲ除去してもよ
い。つづいてこの全面に絶縁膜38を堆積する。次にコ
ンタクトホールを形成した後アルミ蒸着を行ない、アル
ミパターン39を形成して第3図dに示す半導体装置を
得る。このようにして製造され7jLDD構造の半導体
装置は、ドレインのn十領域35と素子分離領域のフィ
ールド酸化膜32下のフィールド反転防止用高濃度不純
物p十領域33とが接触しない構造が得られるのでこの
部分においても空乏層が伸び、電界強度の増加をおさえ
ることができる。
As a result, an n region and an n+ region are provided in the source/drain region. CVD8i02=i on the sidewall of polycrystalline silicon
Instead of deposition, a resist may be patterned, followed by second ion implantation, and then the resist may be removed. Subsequently, an insulating film 38 is deposited on this entire surface. Next, after forming contact holes, aluminum evaporation is performed to form an aluminum pattern 39 to obtain the semiconductor device shown in FIG. 3d. In the semiconductor device manufactured in this manner and having the 7jLDD structure, a structure is obtained in which the n+ region 35 of the drain does not come into contact with the high concentration impurity p+ region 33 for preventing field inversion under the field oxide film 32 of the element isolation region. The depletion layer also extends in this portion, making it possible to suppress an increase in electric field strength.

更に不純物濃度のプロファイルが滑らかな構造であるの
′でよシミ界強度の低減に効果的である。
Furthermore, since the structure has a smooth impurity concentration profile, it is effective in reducing the strength of the stain field.

第4図はゲート電極16,26,36tドレイン領域上
の基板表面と素子分離領域との境界部分の一部のみに延
在させ念実施例である。製造方法は第1の実施例と同様
であ夛、第1図の実施例よりは多少効果が劣るが信頼性
は充分得られる。
FIG. 4 shows an example in which the gate electrodes 16, 26, and 36t are extended only to a part of the boundary between the substrate surface and the element isolation region on the drain region. The manufacturing method is the same as that of the first embodiment, and although the effect is somewhat inferior to that of the embodiment shown in FIG. 1, sufficient reliability can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば電界強度の増加が
緩和されるため、耐圧性が向上し、″またホットキャリ
アの発生による悪影響も低減し、信頼性が向上する。更
に空乏層が充分に伸びる之め寄生容量の増加がおさえら
れ1回路のスピードの低下を防ぐことができる。
As explained above, according to the present invention, since the increase in electric field strength is alleviated, voltage resistance is improved, and the adverse effects caused by the generation of hot carriers are also reduced, improving reliability.Furthermore, the depletion layer is sufficiently As a result, the increase in parasitic capacitance is suppressed, and a decrease in the speed of one circuit can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明による一実施例の製造方法及び半導体
装置の断面図、第2図は他の実施例の半導体装置の断面
図、第3図は他の実施例の製造方法及び半導体装置の断
面図%第4図は他の実施例の平面図、第5図は従来の半
導体装置の平面図と断面図である。 11・・・半導体基板、12・・・素子分離領域13・
・・p中不純物領域   14・・・ソースn領域15
・・・ドレインn領域  16・・・ゲート電極↓ 1
 番 ↓ 番 ↓ ↓ 茅 j 凹 (b) (C) % 5 図
1 is a sectional view of a manufacturing method and a semiconductor device according to one embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device of another embodiment, and FIG. 3 is a sectional view of a manufacturing method and a semiconductor device of another embodiment. 4 is a plan view of another embodiment, and FIG. 5 is a plan view and a sectional view of a conventional semiconductor device. 11... Semiconductor substrate, 12... Element isolation region 13.
...P impurity region 14...Source n region 15
...Drain n region 16...Gate electrode↓ 1
Number ↓ Number ↓ ↓ Kaya j Concave (b) (C) % 5 Figure

Claims (1)

【特許請求の範囲】 1)一導電型の半導体基板と、この基板表面に選択的に
設けられた絶縁体からなる素子分離領域と、この素子分
離領域に隣接する素子領域の基板表面に設けられた他導
電型の第1高濃度不純物領域と、前記素子領域の基板表
面に前記第1高濃度不純物領域から所定距離をへだてて
設けられた他導電型の第2高濃度不純物領域と、前記素
子分離領域の下に設けられた一導電型の高濃度不純物領
域と、前記他導電型の第1及び第2高不純物領域の間の
基板表面上に絶縁膜を介して設けられた導電層とからな
り、前記導電層は素子分離領域と素子領域との境界部分
上に延在し、この境界部分で前記一導電型の高濃度不純
物領域は前記他導電型の第1高濃度不純物領域と接触し
ていないことを特徴とする半導体装置。 2)一導電型の半導体基板表面に選択的に一導電型の高
不純物領域を形成する工程と、この一導電型の高濃度不
純物領域上に絶縁体からなる素子分離領域を形成する工
程と、素子分離領域に隣接した素子領域の露出した基板
表面上に薄い絶縁層を形成する工程と、この絶縁層上の
前記素子領域と素子分離領域との境界部分を含む選択さ
れた部分に導電層を形成する工程と、この導電層をマス
クとして不純物を注入し、他導電型の第1及び第2高不
純物領域を形成する工程とを具備したことを特徴とする
半導体装置の製造方法。
[Claims] 1) A semiconductor substrate of one conductivity type, an element isolation region made of an insulator selectively provided on the surface of this substrate, and an element isolation region provided on the substrate surface of an element region adjacent to this element isolation region. a first high concentration impurity region of a different conductivity type; a second high concentration impurity region of a different conductivity type provided on a substrate surface of the element region at a predetermined distance from the first high concentration impurity region; a conductive layer provided on the substrate surface between the first and second highly impurity regions of the other conductivity type with an insulating film interposed therebetween; The conductive layer extends over a boundary between the element isolation region and the element region, and the high concentration impurity region of one conductivity type contacts the first high concentration impurity region of the other conductivity type at this boundary. A semiconductor device characterized by: 2) selectively forming a high impurity region of one conductivity type on the surface of a semiconductor substrate of one conductivity type; forming an element isolation region made of an insulator on the high concentration impurity region of one conductivity type; forming a thin insulating layer on the exposed substrate surface of the device region adjacent to the device isolation region; and forming a conductive layer on the insulating layer at selected portions including the boundary between the device region and the device isolation region. 1. A method of manufacturing a semiconductor device, comprising the steps of forming first and second highly impurity regions of different conductivity types by implanting impurities using the conductive layer as a mask.
JP7076686A 1986-03-31 1986-03-31 Semiconductor device and manufacture thereof Pending JPS62229880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7076686A JPS62229880A (en) 1986-03-31 1986-03-31 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7076686A JPS62229880A (en) 1986-03-31 1986-03-31 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS62229880A true JPS62229880A (en) 1987-10-08

Family

ID=13440964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7076686A Pending JPS62229880A (en) 1986-03-31 1986-03-31 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS62229880A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185974A (en) * 1988-01-21 1989-07-25 Pioneer Electron Corp Mis-fet
JPH0521791A (en) * 1991-07-17 1993-01-29 Nec Kansai Ltd High-voltage field-effect transistor and ic
JPH08130308A (en) * 1994-10-31 1996-05-21 Nec Corp Semiconductor device
EP1043778A1 (en) * 1999-04-06 2000-10-11 STMicroelectronics S.r.l. Method of fabrication of a high voltage MOS transistor
JP2001156268A (en) * 1999-11-25 2001-06-08 Hitachi Ltd Semiconductor integrated-circuit device
US6818915B1 (en) 1998-03-23 2004-11-16 Matsushita Electric Industrial Co., Ltd. Field-emission electron source

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185974A (en) * 1988-01-21 1989-07-25 Pioneer Electron Corp Mis-fet
JPH0521791A (en) * 1991-07-17 1993-01-29 Nec Kansai Ltd High-voltage field-effect transistor and ic
JPH08130308A (en) * 1994-10-31 1996-05-21 Nec Corp Semiconductor device
JP2800702B2 (en) * 1994-10-31 1998-09-21 日本電気株式会社 Semiconductor device
US6818915B1 (en) 1998-03-23 2004-11-16 Matsushita Electric Industrial Co., Ltd. Field-emission electron source
EP1043778A1 (en) * 1999-04-06 2000-10-11 STMicroelectronics S.r.l. Method of fabrication of a high voltage MOS transistor
US6350637B1 (en) 1999-04-06 2002-02-26 Stmicroelectronics S.R.L. Method of fabrication of a no-field MOS transistor
JP2001156268A (en) * 1999-11-25 2001-06-08 Hitachi Ltd Semiconductor integrated-circuit device

Similar Documents

Publication Publication Date Title
US6188104B1 (en) Trench DMOS device having an amorphous silicon and polysilicon gate
KR940006702B1 (en) Manufacturing method of mosfet
US6518623B1 (en) Semiconductor device having a buried-channel MOS structure
JP2663402B2 (en) Method for manufacturing CMOS integrated circuit device
JPH0355984B2 (en)
US4396930A (en) Compact MOSFET device with reduced plurality of wire contacts
JPH04225529A (en) Improved method for manufacture of integrated-circuit structure body provided with lightly doped drain (ldd)
US5612242A (en) Trench isolation method for CMOS transistor
JP2587444B2 (en) Bipolar transistor using CMOS technology and method of manufacturing the same
JPH03178159A (en) Formation of integrated circuit electrode
JPS62229880A (en) Semiconductor device and manufacture thereof
KR100488099B1 (en) A mos transistor having short channel and a manufacturing method thereof
JPS5978576A (en) Semiconductor device and manufacture thereof
JPH1064898A (en) Manufacturing method of semiconductor device
KR100408000B1 (en) Method for Forming Semiconductor Device
JPH11191624A (en) Fabrication of high voltage power element
JPH0491481A (en) Mis field effect transistor
JP3703427B2 (en) MOS field effect transistor
KR940004258B1 (en) Manufacturing method of soi structure device
KR0128024B1 (en) Fabrication method of cateral bipolar transistor device
JPS6376481A (en) Semiconductor device and manufacture thereof
KR0166506B1 (en) Manufacture of a semiconductor device
KR0124634B1 (en) Method of forming the isolation layer on the semiconductor device
JPH06151842A (en) Semiconductor device and its manufacture
JP2532694B2 (en) Method for manufacturing semiconductor device