KR0166506B1 - Manufacture of a semiconductor device - Google Patents
Manufacture of a semiconductor device Download PDFInfo
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- KR0166506B1 KR0166506B1 KR1019950016023A KR19950016023A KR0166506B1 KR 0166506 B1 KR0166506 B1 KR 0166506B1 KR 1019950016023 A KR1019950016023 A KR 1019950016023A KR 19950016023 A KR19950016023 A KR 19950016023A KR 0166506 B1 KR0166506 B1 KR 0166506B1
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- forming
- contact hole
- polycrystalline silicon
- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 210000003323 beak Anatomy 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 소오스, 드레인 및 채널영역으로 구비되는 활성영역을 반도체 기판에 구비하지 않고, 게이트 전극의 상부에 다결정 실리콘 패턴으로 구비함으로써, 소자분리막으로 사용되는 절연막에는 버즈비크가 거의 없고, 단차가 거의 발생되지 않는다. 그로 인하여 후속 공정이 용이한 효과가 있다. 또한, 상기 다결정 실리콘 패턴 상부에 절연층을 형성한 후, 제1콘택홀을 형성하고 노출된 다결정 실리콘 패턴에 이온주입공정으로 소오스 및 게이트 전극과의 간격유지 및 소자분리막과의 간격유지가 필요없이 공정 여유도가 증가하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. The present invention relates to an insulating film used as an element isolation film by providing a polycrystalline silicon pattern on a gate electrode without having an active region formed of a source, a drain, and a channel region on a semiconductor substrate. There is little Burj beak, and little step occurs. Thereby, the subsequent process is easy to effect. In addition, after the insulating layer is formed on the polycrystalline silicon pattern, a first contact hole is formed and an ion implantation process is performed on the exposed polycrystalline silicon pattern, thereby eliminating the need to maintain the gap between the source and gate electrodes and the gap between the device isolation layer. It is a technology that increases the process margin.
Description
제1도 및 제2도는 종래의 기술로 형성된 디램의 구조를 나타낸 단면도.1 and 2 are cross-sectional views showing the structure of the DRAM formed by the prior art.
제3a도 및 제3f도는 본 발명의 실시예에 따른 반도체 소자를 형성하는 단계를 도시한 단면도.3A and 3F are cross-sectional views illustrating steps of forming a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 소자분리막 2,34 : 게이트 산화막1: device isolation film 2,34: gate oxide film
3,32 : 게이트 전극 4,38 : 드레인 영역3,32 gate electrode 4,38 drain region
5,42 : 소오스 영역 6,31 : 제1절연막5,42 source region 6,31 first insulating film
7,37 : 제1콘택홀 8,39 : 비트라인7,37: 1st contact hole 8,39: bit line
9,33 : 제2절연막 10,41 : 제2콘택홀9,33: second insulating film 10,41: second contact hole
20,50 : 실리콘 기판 35 : 다결정 실리콘20,50 silicon substrate 35 polycrystalline silicon
36 : 제3절연막 40 : 제4절연막36: third insulating film 40: fourth insulating film
본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, 게이트 전극의 상부에 소오스, 드레인 및 채널영역을 형성하여 소자 분리막을 이상적으로 형성하고 콘택홀의 공정 여유도를 크게 하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a source, drain, and channel region is formed on an upper portion of a gate electrode to ideally form an isolation layer and increase a process margin of contact holes. .
최근에 디램을 비롯한 반도체 소자의 집적도가 증가함에 따라 상하의 배선구조, 소자분리막 및 콘택홀 등의 크기가 감소함에 따라 각 요소들을 형성하기 위한 공정조건이 복잡해지고 장치의 기능이 감소를 가져와 고집적화에 제한을 주는 요인이 되었고 이를 억제하기 위한 여러 가지 방법들도 복잡한 공정조건으로 수율향상에 어려움이 있다.Recently, as the integration of semiconductor devices including DRAMs increases, the size of upper and lower wiring structures, device isolation layers, and contact holes decreases, which increases the complexity of the process conditions for forming each element and reduces the function of the device. In addition, various methods to suppress this have difficulty in improving yield due to complicated process conditions.
특히, LOCOS나 PBL(Poly Buffered LOCOS) 방식의 소자분리막은 초기에는 단순한 공정과 충분한 소자분리 효과로 큰 성과를 얻었으나, 소자가 고집적화됨에 따라 내제되어 있던 활성영역을 감소시키는 버즈비크(Bird's Beak)와 단차발생 그리고 좁은 분리영역(Field Area)에서 막의 두께가 얇아지는 현상(Field Thinning Effect) 등이 소자의 기능감소와 고집적화에 제한을 주는 요인이 되었고 이를 억제하기 위한 여러 가지 방법들도 복잡한 공정조건으로 수율향상에 어려움이 있다.In particular, LOCOS or PBL (Poly Buffered LOCOS) device isolation films have achieved great results in the early stages by a simple process and sufficient device isolation effect, but as the devices are highly integrated, Bird's Beak reduces the intrinsic active area. And the step difference and the thinning of the film in the narrow field area (Field Thinning Effect) are the factors that limit the functional reduction and integration of the device, and the various methods to suppress them are complicated process conditions. As a result, there is a difficulty in improving yield.
한편 상하의 배선구조를 연결시키는 콘택홀은 배선구조 및 소자분리막과의 일정한 간격을 요구하고 또, 콘택홀 자체의 크기를 어느 정도 이상을 요구한다. 더욱이, 장치 제작시의 공정 여유도를 고려하게 되면 보다 더 큰 간격과 크기가 필요함으로 종래의 기술로는 소자의 고집적화가 어려워진다. 따라서 충분한 공정 여유도를 가지면서 공정이 단순한 콘택홀 형성방법이 요구된다.On the other hand, contact holes connecting the upper and lower wiring structures require a constant distance from the wiring structure and the device isolation film, and the contact holes themselves require a certain size or more. Furthermore, considering the process margin in manufacturing the device, larger spacing and size are required, which makes it difficult to integrate the device with the conventional technology. Therefore, there is a need for a method of forming a contact hole having a sufficient process margin and a simple process.
종래의 반도체 소자의 제조방법에 대하여 설명하면 다음과 같다.The manufacturing method of the conventional semiconductor device is as follows.
제1도는 종래의 반도체 소자의 디램 구조를 도시한 단면도로서, 실리콘 기판(20)상에 LOCOS나 PBL 방식으로 성장한 소자분리막(1)을 형성하고, 게이트 산화막(2)을 성장시키고, 게이트 전극(3)을 형성한 후 소오스 영역(5)과 드레인 영역(4)을 형성하고, 제1절연막(6)을 증착하고, 상기 드레인 영역(4)이 노출되는 비트라인 콘택용 제1콘택홀(7)을 형성하고, 제1콘택홀(7)에 도전층이 채워진 비트라인(8)을 형성하고, 제2절연막(9)을 증착하고, 소오스 영역(5)이 노출되는 저장전극 콘택용 제2콘택홀(10)을 형성한 것이다.FIG. 1 is a cross-sectional view showing a DRAM structure of a conventional semiconductor device. The device isolation film 1 grown on the silicon substrate 20 by LOCOS or PBL is formed, the gate oxide film 2 is grown, and the gate electrode ( 3) and then the source region 5 and the drain region 4 are formed, the first insulating layer 6 is deposited, and the first contact hole 7 for the bit line contact in which the drain region 4 is exposed. ), A bit line 8 filled with a conductive layer in the first contact hole 7, a second insulating layer 9 is deposited, and a second storage electrode contact for exposing the source region 5. The contact hole 10 is formed.
참고로 상기 제2콘택홀(10)에 채워져서 형성되는 저장전극과 그 상부에 유전체막, 플레이트 전극을 후속공정에서 형성할 수 있다.For reference, a storage electrode formed by filling the second contact hole 10 and a dielectric film and a plate electrode formed thereon may be formed in a subsequent process.
제2도는 제1도에 도시된 반도체 소자의 디램 구조에서 상기 제2콘택홀을 중심으로 수직방향이 단면도를 도시한 것이다.FIG. 2 is a cross-sectional view in a vertical direction about the second contact hole in the DRAM structure of the semiconductor device illustrated in FIG. 1.
그러나, 상기와 같은 LOCOS나 PBL 방식으로 성장한 소자분리막은 버즈비크의 발생으로 마스크상의 활성영역(a)이 제1도에서는 a'로, 제2도에서는 a로 감소되고 제2도에서는 소자분리영역(b)에서의 소자분리막(1)의 두께는 제1도에서의 소자분리막(1)의 두께보다 작아지는 현상이 발생하여 소자 격리 기능을 감소시키며 또, 소자분리막에 의한 단차의 발생은 후속공정에 악영향을 주는 문제점이 발생한다. 또, 종래의 디램구조에서 드레인 영역(4)에 비트라인(8)을 콘택하기 위한 제1콘택홀(7)은 게이트 전극(3)과의 간격유지 및 콘택홀의 자체 크기와 콘택홀과 소자분리막과의 간격유지를 위한 공정 여유도가 추가되어 소자의 고집적화에 더욱 큰 제한요인이 되는 또 다른 문제점이 발생한다.However, in the device isolation layer grown by the LOCOS or PBL method as described above, the active region a on the mask is reduced to a 'in FIG. 1 and a in FIG. 2 due to the occurrence of Buzzbee, and the device isolation region in FIG. The thickness of the device isolation film 1 in (b) becomes smaller than the thickness of the device isolation film 1 in FIG. 1, thereby reducing the device isolation function. Problems that adversely affect the problem occurs. In addition, in the conventional DRAM structure, the first contact hole 7 for contacting the bit line 8 to the drain region 4 has a gap between the gate electrode 3 and the size of the contact hole, the contact hole and the isolation layer. Another problem arises in that the process margin for maintaining the gap between and is further limited to the high integration of the device.
결국, 상기와 같은 반도체 소자의 디램구조는 소자가 고집적화됨에 따라 공정 여유도가 급격히 감소하여 수율이 나빠지는 문제점이 발생하여 수율의 향상을 기대하기 어렵게 되며 이러한 문제점을 해소하는 여러 가지 새로운 방법도 공정이 복잡해짐에 따라 제조단가의 상승을 일으키게 된다.As a result, the DRAM structure of the semiconductor device as described above has a problem that the yield margin decreases rapidly due to the high integration of the device, so that it is difficult to expect an improvement in yield, and various new methods for solving such problems are also processed. This complexity leads to an increase in manufacturing cost.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위한 것으로, 게이트 전극 상부면에 다결정 실리콘 패턴을 형성하고, 그 상부에 콘택홀을 형성한 후 이온주입공정으로 노출된 다결정 실리콘 패턴에 선택적으로 소오스, 드레인을 형성하는 반도체 소자 제조 방법을 제공하는데 있다.Accordingly, an object of the present invention is to solve the above problems, by forming a polycrystalline silicon pattern on the upper surface of the gate electrode, and forming a contact hole thereon, and then selectively selecting a source, the polycrystalline silicon pattern exposed by the ion implantation process, A semiconductor device manufacturing method for forming a drain is provided.
상기 목적을 달성하기 위하여 본 발명의 반도체 소자의 제조 방법은 반도체 기판상에 제1절연막을 형성하고, 게이트 전극 마스크를 이용하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측면에 제2절연막을 형성하는 단계와, 상기 게이트 전극의 상부에 게이트 산화막을 형성하는 단계와, 전체 구조의 상부에 제1타입의 불순물이 도프된 제1다결정 실리콘을 증착한 후 소자분리 마스크를 이용하여 예정된 활성영역에 제1다결정 실리콘 패턴을 형성하는 단계와, 전체 구조의 상부에 제3절연막을 증착하고, 제1콘택홀 마스크를 이용한 식각 공정으로 상기 제1다결정 실리콘 패턴의 일측단부가 노출되는 제1콘택홀을 형성하는 단계와, 제2타입의 불순물을 이온주입하여 노출된 제1다결정 실리콘 패턴을 드레인으로 형성하는 단계와, 상기 드레인에 콘택되는 제1도전배선을 형성하는 단계와, 전체 구조 상부에 제4절연막을 증착하고, 제2콘택홀 마스크를 이용한 식각공정으로 다결정 실리콘 패턴의 타측단부가 도출된 제2콘택홀을 형성하는 단계와, 제2타입의 불순물을 이온주입하여 노출된 제1다결정 실리콘 패턴을 소오스로 형성하는 단계와, 상기 소오스에 콘택되는 제2도전배선을 형성하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes forming a first insulating film on a semiconductor substrate, forming a gate electrode using a gate electrode mask, and forming a second insulating film on a side surface of the gate electrode. Forming a gate oxide film on the gate electrode, depositing first polycrystalline silicon doped with a first type of impurity on the entire structure, and then depositing a first polycrystalline silicon on a predetermined active region using a device isolation mask. Forming a first polycrystalline silicon pattern, depositing a third insulating layer on the entire structure, and etching the first contact hole to expose one end of the first polycrystalline silicon pattern by an etching process using a first contact hole mask. Forming a drained first polycrystalline silicon pattern by implanting an impurity of a second type into the drain; Forming a selected first conductive wiring, depositing a fourth insulating layer over the entire structure, and forming a second contact hole from which the other end of the polycrystalline silicon pattern is derived by an etching process using a second contact hole mask. And forming a first polycrystalline silicon pattern exposed by ion implantation of a second type of impurity into a source, and forming a second conductive wiring contacted to the source.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3a도 내지 제3f도는 본 발명의 제1실시예에 따라 반도체 소자를 제조하는 제조 공정도이다.3A to 3F are manufacturing process diagrams for manufacturing a semiconductor device according to the first embodiment of the present invention.
제3a도는 실리콘 기판(50)상에 제1절연막(31)을 형성하고, 다결정 실리콘막을 증착하고, 게이트 마스크를 이용한 식각공정으로 다결정 실리콘막을 상기 제1절연막(31)이 들어날 때까지 식각하여 게이트 전극(32)을 형성하고, 제2절연막(33)을 증착하여 평탄화시킨 상태를 도시한 단면도이다.3A illustrates the formation of the first insulating film 31 on the silicon substrate 50, the deposition of the polycrystalline silicon film, and the etching of the polycrystalline silicon film until the first insulating film 31 enters by an etching process using a gate mask. It is sectional drawing which shows the state in which the gate electrode 32 was formed and the 2nd insulating film 33 was deposited and planarized.
제3b도는 전체 구조 상부에 상기 제2절연막(33)을 게이트 전극(32)의 상부가 들어날 때까지 식각하고, 게이트 전극(32)의 상부에 게이트 산화막(34)을 형성하고, 전체 구조 상부에 N MOSFET(P MOSFET)의 경우 P형(N형)의 불순물이 도핑된 다결정 실리콘(35)을 증착한 상태를 나타낸 단면도이다.3B illustrates that the second insulating layer 33 is etched on the entire structure until the upper portion of the gate electrode 32 enters, and the gate oxide layer 34 is formed on the gate electrode 32. In the case of N MOSFET (P MOSFET), a cross-sectional view showing a state in which polycrystalline silicon 35 doped with an impurity of P type (N type) is deposited.
제3c도는 전체 구조 상부에 소자분리 마스크를 이용하여 상기 다결정 실리콘(35)을 식각하여 게이트 산화막(34) 및 제2절연막(33)이 들어날 때까지 식각하여 소오스와 드레인 그리고 채널 영역이 형성될 활성영역에만 다결정 실리콘 패턴(35')을 남기고, 전체 구조의 상부에 제3절연막(36)을 형성한 상태를 나타낸 단면도이다. 상기와 같은 활성영역에 다결정 실리콘 패턴(35')을 남기면 자연적으로 소자분리 영역에는 버즈비크가 없고 단차가 거의 없는 상태가 된다.In FIG. 3C, the polycrystalline silicon 35 is etched using the device isolation mask on the entire structure to etch until the gate oxide layer 34 and the second insulating layer 33 enter the source, drain, and channel regions. A cross-sectional view showing a state in which a third insulating film 36 is formed on the entire structure while leaving the polycrystalline silicon pattern 35 'only in the active region. When the polycrystalline silicon pattern 35 ′ is left in the active region as described above, the device isolation region is naturally free of bleeding bezels and has little step difference.
제3d도는 제1콘택홀 마스크를 이용한 식각 공정으로 제3절연막(36)을 다결정 실리콘 패턴(35')이 들어날 때까지 식각하여 드레인 영역(37)의 제1콘택홀(38)을 형성하고, 노출된 다결정 실리콘 패턴(35')에 NMOSFET(PMOSFET)의 경우 N 형(P 형)의 불순물을 이온주입하여 드레인 영역(38)을 형성한 상태를 나타낸 단면도이다.In FIG. 3D, in the etching process using the first contact hole mask, the third insulating layer 36 is etched until the polycrystalline silicon pattern 35 ′ enters to form the first contact hole 38 of the drain region 37. In the case of an NMOSFET (PMOSFET), an N-type (P-type) impurity is ion-implanted into the exposed polycrystalline silicon pattern 35 'to form a drain region 38.
이때 상기 제1콘택홀(37)은 게이트 전극(32)과 간격유지가 필요없어 공정 여유도가 크게 증가한다.In this case, the first contact hole 37 does not need to be spaced apart from the gate electrode 32, thereby greatly increasing the process margin.
제3e도에 전체 구조의 상부에 다결정 실리콘을 증착하고, 비트라인 마스크를 이용하여 제3절연막(36)이 들어날 때까지 식각하여 상기 제1콘택홀(37) 상부에 다결정 실리콘이 채워진 비트라인(39)을 형성한 후에 전체 상부에 제4절연막(40)을 증착한 상태를 나타낸 단면도이다.In FIG. 3E, polycrystalline silicon is deposited on the entire structure, and is etched by using a bit line mask until the third insulating layer 36 enters the bit line, in which the polycrystalline silicon is filled on the first contact hole 37. After the 39 is formed, the cross-sectional view showing a state in which the fourth insulating film 40 is deposited on the entire upper portion.
제3f도는 제2콘택홀 마스크를 이용하여 제4절연막(40)과 제3절연막(36)을 식각하되, 다결정 실리콘 패턴(35')이 들어날 때까지 식각하여 제2콘택홀(41)을 형성한 후에 노출된 다결정 실리콘 패턴(35')에 N MOSFET(P MOSFET)의 경우 N형(P형)의 불순물을 이온주입하여 소오스 영역(42)을 형성한 상태를 나타낸 단면도이다.In FIG. 3F, the fourth insulating layer 40 and the third insulating layer 36 are etched using the second contact hole mask, and the second contact hole 41 is etched until the polysilicon pattern 35 ′ is formed. In the case of N MOSFET (P MOSFET), the source region 42 is formed by ion implantation of an N type (P type) impurity in the exposed polycrystalline silicon pattern 35 'after formation.
참고로 상기 제2콘택홀(41)에 채워져서 형성되는 저장전극과 그 상부에 유전체막, 플레이트 전극을 후속공정에서 형성할 수 있다.For reference, a storage electrode formed by filling the second contact hole 41 and a dielectric film and a plate electrode formed thereon may be formed in a subsequent process.
상술한 바와 같이 본 발명의 반도체 소자 및 그 제조 방법에 의하면 소오스, 드레인 및 채널영역으로 구비되는 활성영역을 반도체 기판에 구비하지 않고, 게이트 전극의 상부에 다결정 실리콘 패턴으로 구비함으로써, 소자분리막으로 사용되는 절연막에는 버즈비크가 거의 없고, 단차가 거의 발생되지 않는다. 그로 인하여 후속 공정이 용이한 효과가 있다. 또한, 상기 다결정 실리콘 패턴 상부에 절연층을 형성한 후, 제1콘택홀을 형성하고 노출된 다결정 실리콘 패턴에 이온주입공정으로 소오스 및 게이트 전극과의 간격유지 및 소자분리막과의 간격유지가 필요없이 공정 여유도가 증가하는 효과가 있다.As described above, according to the semiconductor device of the present invention and a method of manufacturing the same, a semiconductor device does not include an active region formed of a source, a drain, and a channel region, and is used as an isolation layer by providing a polycrystalline silicon pattern on the gate electrode. The insulating film thus formed has almost no buzz beak, and hardly any step is generated. Thereby, the subsequent process is easy to effect. In addition, after the insulating layer is formed on the polycrystalline silicon pattern, a first contact hole is formed and an ion implantation process is performed on the exposed polycrystalline silicon pattern, thereby eliminating the need to maintain the gap between the source and gate electrodes and the gap between the device isolation layer. The process margin increases.
Claims (5)
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