JP4265890B2 - Method for manufacturing insulated gate field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an insulated gate field effect transistor.
[0002]
[Prior art]
Conventionally, in order to increase the breakdown voltage by reducing the electric field in the drain portion while miniaturizing the insulated gate field effect transistor, the following method has been employed.
[0003]
A conventional method for manufacturing an insulated gate field effect transistor will be described with reference to cross-sectional views in the order of steps in FIGS.
[0004]
Here, as an example, a case where an NchMOS transistor is formed on an SOI substrate will be described. However, even when the substrate is bulk silicon, the same process is performed except that a well is formed.
[0005]
FIG. 6A shows an SOI substrate in which a silicon oxide film 2 is formed on a support substrate 1 and a silicon active layer 3 is formed on the silicon oxide film 2. This structure includes SIMOX, which forms an oxide film and a silicon active layer by high-temperature heat treatment after ion implantation of oxygen into the silicon substrate, and a silicon oxide film formed on the support substrate, and then silicon is bonded together, and then the silicon is polished to form a thin film This is realized by a bonding method for forming a silicon active layer.
[0006]
FIG. 6B shows a process of forming the field oxide film 6, the element region 5, and the gate oxide film 13. In this step, the element region 5 is doped into P-type by ion implantation, and the P-type impurity concentration in a portion that becomes a body region of the transistor is determined in a later step. Accordingly, the P-type impurity concentration is set in consideration of the threshold value.
[0007]
FIG. 6C shows a step of forming a gate electrode 14 on the gate oxide film 13.
[0008]
FIG. 6D shows a step of forming an N-type LDD region (low concentration drain region) 12 in a self-aligning manner using the gate electrode 14 as a mask. When the LDD region 12 is formed, the portion immediately below the gate electrode 14 becomes the body region 11. Here, in order to reduce the drain electric field, the N-type impurity concentration of the LDD region 12 is desirably as low as possible. However, it is difficult from the viewpoint of controllability to form the element region 5 formed lower than the P-type impurity concentration in the step of FIG. 6B. Therefore, the N-type impurity concentration of the LDD region 12 must be formed higher than the P-type impurity concentration of the body region 11.
[0009]
FIG. 7A shows a process of forming the N-type source region 7 and drain region 8.
The N-type source region 7 and drain region 8 are usually formed by ion implantation after forming a sidewall on the side surface of the gate electrode 14, but may be formed by ion implantation using a resist as a mask.
[0010]
FIG. 7B shows a step of depositing the interlayer insulating film 15.
[0011]
FIG. 7C shows a step of forming a contact hole in a part of the interlayer insulating film 15 and further forming a metal wiring 16.
[0012]
Through the above steps, an insulated gate field effect transistor as shown in FIG. 7C is completed.
[0013]
[Problems to be solved by the invention]
However, the conventional method for manufacturing an insulated gate field effect transistor having an LDD structure has the following problems.
[0014]
Since doping for forming the LDD region is performed in addition to doping for forming the body region, it is difficult in terms of controllability to form the impurity concentration of the LDD region lower than the impurity concentration of the body region. Therefore, the impurity concentration of the LDD region must be formed higher than the impurity concentration of the body region. Accordingly, in the completed insulated gate field effect transistor, the withstand voltage decreases because the electric field between the body and the drain is high. In addition, since the depletion layer extends to the body side longer than the drain side, channel length modulation increases, and analog characteristics using saturation characteristics deteriorate.
[0015]
[Means for Solving the Problems]
Therefore, the present invention uses the following means in order to solve the above problems.
[0016]
In a method of manufacturing an insulated gate field effect transistor, a first step of forming a silicon oxide film and a silicon active layer having a desired impurity concentration on the silicon oxide film on a support substrate, and a source of a first conductivity type A second step of forming a region and a drain region of the first conductivity type, and forming a body region by doping a part of the silicon active layer to the second conductivity type at a desired distance from the drain region The method includes a third step, a fourth step of forming a gate oxide film on the surface of the body region, and a fifth step of forming a gate electrode on the gate oxide film.
[0017]
【Example】
Hereinafter, a preferred first embodiment of the present invention will be described with reference to cross-sectional views in the order of steps in FIGS. Here, the case of an NchMOS transistor will be described as an example.
[0018]
FIG. 1A shows an SOI in which a silicon oxide film 2 is formed on a support substrate 1 with a thickness of 100 nm, for example, and a silicon active layer 3 is formed on the silicon oxide film 2 with a thickness of 50 nm, for example. The substrate is shown. Here, the impurity of the silicon active layer 3 may be either P-type or N-type, but the impurity concentration is formed to be sufficiently lower than the impurity concentration of the element region 5 formed in the step of FIG. There must be.
[0019]
FIG. 1B shows a step of forming the sacrificial oxide film 4 after forming the field oxide film 6 to perform element isolation and forming the element region 5. In the case of forming an NchMOS transistor, the element region 5 is doped N-type by ion implantation, and an N-type impurity concentration of a portion that becomes an LDD region is determined in a later process. Although not described here, in the case of forming a PchMOS transistor, the element region 5 is doped P-type. The impurity conductivity type (P-type or N-type) and impurity concentration of the element region 5 formed in this step become the conductivity type and impurity concentration of the LDD region 12 formed in FIG. By forming the body region 11 so as to be lower than the P-type impurity concentration, the depletion layer on the drain side extends to the drain side more than the channel side.
[0020]
For example, if the P-type impurity concentration of the body region 11 is formed to be 1E16 cm-3, naturally, the N-type impurity field concentration of the element region 5 must be lower than 1E16 cm-3. Further, if the entire LDD region 12 is not depleted only by the built-in potential, the parasitic resistance increases and the driving capability of the transistor decreases. Therefore, the concentration of the LDD region 12 must be 1E15 cm −3 or less. When As is ion-implanted at an acceleration energy of 80 keV and a dose of about 5E9 cm-2, the N-type impurity concentration of the silicon active layer 3 having a thickness of 50 nm is 1E15 cm-3.
[0021]
FIG. 1C shows a step of forming a source region 7 and a drain region 8 by performing ion implantation of N-type impurities through the sacrificial oxide film 4 using a photolithography process. For example, when As is ion-implanted at an acceleration energy of 80 keV and a dose of about 5E14 cm-2, the N-type impurity concentration in the source region 7 and the drain region 8 is 1E20 cm-3.
[0022]
FIG. 1D shows a process of forming a P-type body region 11 by ion implantation of P-type impurities through the sacrificial oxide film 4 using a photolithography process. Here, the channel length of the transistor is determined, and the distance between the P-type body region 11 and the drain region 8 is the length of the LDD region. In a transistor in which the source and drain voltages are switched, a desired interval is provided between both the source region 7 and the drain region 8 and the channel region 11.
[0023]
Here, the impurity concentration of the P-type body region 11 is set so as to obtain a desired threshold value (Vth) of the NchMOS transistor. The impurity concentration of the P-type body region 11 formed here must be sufficiently higher than the impurity concentration of the element region 5 formed in FIG. 1B in order to improve controllability. For example, when BF2 is ion-implanted at an acceleration energy of 30 keV and a dose of about 5E10 cm-2, the impurity concentration of the P-type body region 11 is 1E16 cm-3. After the ion implantation for forming the body region, the sacrificial oxide film is removed.
[0024]
FIG. 2A shows a process of forming a gate oxide film 13 on the surface of the P-type body region 11. FIG. 2B shows a step of forming the gate electrode 14 on the gate oxide film 13. FIG. 2C shows a step of depositing the interlayer insulating film 15. FIG. 2D shows a process of forming a contact hole in a part of the interlayer insulating film 15 and further forming a metal wiring 16.
[0025]
Through the steps as described above, an insulated gate field effect transistor as shown in FIG. 2 (d) is completed. Since the doping of the LDD region is before the doping of the body region, the impurity concentration of the LDD region can be made lower than the impurity concentration of the body region and with good controllability.
[0026]
In this embodiment, the impurity concentration of the LDD region can be made lower than the impurity concentration of the body region. In an insulated gate field effect transistor in which the impurity concentration in the LDD region is lower than the impurity concentration in the body region, the channel length modulation is small because the depletion layer due to the drain voltage extends to the drain side rather than the channel side. . In addition, since the electric field in the LDD region is uniform because the impurity concentration in the LDD region is low, the maximum value of the electric field becomes small and the breakdown voltage can be increased if the drain potential is constant. In order to realize the above effect, it is necessary to set the product of the LDD region concentration and the LDD region length to be smaller than half of the product of the body region concentration and the body region length.
[0027]
In this embodiment, since the impurity concentration of the LDD region can be made very small compared to the impurity concentration of the body region, the impurity concentration of the LDD region is sufficiently low compared to the impurity concentration of the body region. In this case, it is possible to reduce the N-type or P-type doping step in the step of FIG. 1 (b). When the impurity concentration of the silicon active layer 3 is sufficiently low, the LDD region is completely depleted only by the built-in potential even when no voltage is applied between the drain and the source. This is because there is no difference in the maximum electric field or leakage current even in the N type.
[0028]
As described above, a low impurity concentration silicon layer in which the LDD region is completely depleted only by the built-in potential is not possible with, for example, an epitaxial substrate other than the SOI substrate. Therefore, the effect is great when combined with an SOI substrate as in this embodiment.
[0029]
In the present embodiment, the manufacturing method of the NchMOS transistor has been described, but the same applies to the case of the PchMos transistor. However, since the decrease in breakdown voltage due to the impact ion effect is significant in the Nch MOS transistor, the effect of this embodiment is great in the case of the Nch MOS transistor.
[0030]
In the following, a second preferred embodiment of the present invention will be described with reference to the cross-sectional views in the order of the steps in FIGS. Here, the case of an NchMOS transistor will be described as an example.
[0031]
FIG. 3A shows an SOI in which a silicon oxide film 2 is formed on a support substrate 1 with a thickness of 100 nm, for example, and a silicon active layer 3 is formed on the silicon oxide film 2 with a thickness of 50 nm, for example. The substrate is shown. Here, the impurity of the silicon active layer 3 may be either P-type or N-type, but the impurity concentration is formed to be sufficiently lower than the impurity concentration of the element region 5 formed in the step of FIG. There must be.
[0032]
FIG. 3B shows a process of forming the sacrificial oxide film 4 after forming the field oxide film 6 to perform element isolation and forming the element region 5. In the case of forming an NchMOS transistor, the element region 5 is doped N-type by ion implantation, and an N-type impurity concentration of a portion that becomes an LDD region is determined in a later process. Although not described here, in the case of forming a PchMOS transistor, the element region 5 is doped P-type. The drain-side depletion layer is formed by forming the N-type impurity concentration of the element region 5 formed here to be sufficiently lower than the P-type impurity concentration of the body region 11 formed in FIG. Extends more to the drain side than to the channel side.
[0033]
For example, if the P-type impurity concentration of the body region 11 is formed to be 1E16 cm-3, naturally, the N-type impurity field concentration of the element region 5 must be lower than 1E16 cm-3. In addition, if the entire LDD region is not depleted with only the built-in potential, the parasitic resistance increases and the transistor driving capability decreases. For example, if the LDD region length is 1 micron, the concentration of the LDD region is 1E15 cm- Must be 3 or less. When As is ion-implanted at an acceleration energy of 80 keV and a dose of about 5E9 cm-2, the N-type impurity concentration of the silicon active layer 3 having a thickness of 50 nm is 1E15 cm-3.
[0034]
FIG. 3C shows a step of forming a source region 7 and a drain region 8 by performing ion implantation of N-type impurities through the sacrificial oxide film 4 using a photolithography process. For example, when As is ion-implanted at an acceleration energy of 80 keV and a dose of about 5E14 cm-2, the N-type impurity concentration in the source region 7 and the drain region 8 is 1E20 cm-3.
[0035]
FIG. 3D shows a step of depositing the oxide film 9. The oxide film 9 deposited here needs to be a somewhat dense oxide film in order to increase the accuracy of the window opening in the process of FIG. 4 (a). Therefore, the LPCVD is performed at a temperature of 600 to 800 ° C. Oxide film formation is desirable.
[0036]
FIG. 4A shows a process of opening a window by etching a part of the oxide film 9. Here, the opened portion becomes the gate portion of the MOS transistor, the channel length is determined, and the distance between the opened portion and the drain region 8 becomes the length of the LDD region. In a transistor in which the source and drain voltages are switched, a desired interval is provided between both the source region 7 and the drain region 8 and the window opening portion.
[0037]
FIG. 4B shows a step of forming the P-type body region 11 by performing ion implantation into the window portion of the oxide film 9. Here, the impurity concentration of the P-type body region 11 is set so as to obtain a desired threshold value (Vth) of the NchMOS transistor. The impurity concentration of the P-type body region 11 formed here must be sufficiently higher than the impurity concentration of the element region 5 formed in FIG. 3B in order to improve controllability. For example, when BF2 is ion-implanted at an acceleration energy of 30 keV and a dose of about 5E10 cm-2, the impurity concentration of the P-type body region 11 is 1E16 cm-3. In this process, although not shown in the figure, a sacrificial oxide film is newly formed before ion implantation, and ion implantation is performed from the viewpoint of suppressing damage to the body region 11 and preventing channeling during ion implantation. desirable. When the sacrificial oxide film is formed, the sacrificial oxide film is removed after ion implantation for forming the body region.
[0038]
FIG. 4C shows a step of forming a gate oxide film 13 on the surface of the P-type body region 11. FIG. 5A shows a process of forming the gate electrode 14 on the gate oxide film 13. Since the window of the oxide film 9 is formed and the body region 11 is doped in the steps of FIG. 3D and FIG. 4A, the gate electrode 14 is formed without shifting from the P-type body region 11. Therefore, due to mask misalignment or the like, there is no defect such as a portion where the gate electrode 14 is not formed on the P-type body region 11 and the current value is reduced.
[0039]
FIG. 5B shows a step of depositing the interlayer insulating film 15. FIG. 5C shows a step of forming a contact hole in a part of the interlayer insulating film 15 and further forming a metal wiring 16.
[0040]
Through the above steps, an insulated gate field effect transistor as shown in FIG. 5C is completed. Since the doping of the LDD region is before the doping of the body region, the impurity concentration of the LDD region can be made lower than the impurity concentration of the body region and with good controllability.
[0041]
In this embodiment, the impurity concentration of the LDD region can be made lower than the impurity concentration of the body region. In an insulated gate field effect transistor in which the impurity concentration in the LDD region is lower than the impurity concentration in the body region, the channel length modulation is small because the depletion layer due to the drain voltage extends to the drain side rather than the channel side. . In addition, since the electric field in the LDD region is uniform because the impurity concentration in the LDD region is low, the maximum value of the electric field becomes small and the breakdown voltage can be increased if the drain potential is constant. In order to realize the above effect, it is necessary to set the product of the LDD region concentration and the LDD region length to be smaller than half of the product of the body region concentration and the body region length.
[0042]
In this embodiment, since the impurity concentration of the LDD region can be made very small compared to the impurity concentration of the body region, the impurity concentration of the LDD region is sufficiently low compared to the impurity concentration of the body region. In this case, it is possible to reduce the N-type or P-type doping step in the step of FIG. 1 (b). When the impurity concentration of the silicon active layer 3 is sufficiently low, the LDD region is completely depleted only by the built-in potential even when no voltage is applied between the drain and the source. This is because there is no difference in the maximum electric field or leakage current even in the N type.
[0043]
As described above, a low impurity concentration silicon layer in which the LDD region is completely depleted only by the built-in potential is not possible with, for example, an epitaxial substrate other than the SOI substrate. Therefore, the effect is great when combined with an SOI substrate as in this embodiment.
[0044]
In the present embodiment, the manufacturing method of the NchMOS transistor has been described, but the same applies to the case of the PchMos transistor. However, since the decrease in breakdown voltage due to the impact ion effect is significant in the Nch MOS transistor, the effect of this embodiment is great in the case of the Nch MOS transistor.
[0045]
A preferred third embodiment of the present invention will be described below with reference to FIG. Here, the case of an NchMOS transistor will be described as an example.
[0046]
FIG. 8 (a) is a plan view corresponding to the step of FIG. 4 (a) described in the second embodiment. In this step, a part of the oxide film 9 formed in the step of FIG. 3D is etched to open a window. At this time, a window 17 for forming a body region is formed larger than the width of the silicon active layer 3. . Further, the oxide film is etched in this step so that the bird's beak at the end of the body region 11 is completely removed.
[0047]
FIG. 8B is a plan view corresponding to the step of FIG. 4B described in the second embodiment. A process of forming a P-type body region 11 by ion implantation of BF2 into the window 17 for forming the body region is shown. Here, the body region end 18 is formed with a higher impurity concentration than the body region 11. Specifically, in addition to ion implantation for forming the body region 11, a photolithography process is added once to perform ion implantation to the body region end portion. This step increases the boron concentration at the end of the body region and reduces off-leakage.
[0048]
Further, a gate oxide film is formed by a process corresponding to the process of FIG. 4C described in the second embodiment. In this process, when the bird's beak at the end of the body region 11 is completely removed in the process of FIG. 8A, the silicon oxide film 3 between the support substrate 1 and the body region end 18 is removed. This has the effect of reducing the risk of insulation failure. Except as described above, NchMOS transistors are formed in the same manner as in the second embodiment.
[0049]
Thus, according to the third embodiment, an NchMOS transistor can be obtained in which off-leakage is reduced at the end of the body region and the risk of insulation failure between the end of the body region and the support substrate is low. In order to reduce off-leakage at the end of the body region, there is a method in which field doping is performed on a portion other than the device region before field oxidation. The effect of reducing off-leakage is low. Therefore, this embodiment has a greater effect of reducing off-leakage.
[0050]
【The invention's effect】
According to the present invention, the impurity concentration of the LDD region can be formed lower than the impurity concentration of the body region and with good controllability. Therefore, the drain breakdown voltage of the manufactured insulated gate field effect transistor is increased. It is particularly effective in preventing pressure drop due to impact ions. Further, the depletion layer between the drain and the body extends to the drain side and does not extend much to the body side. Therefore, when compared with the same L length, the channel length modulation is smaller than that of the conventional transistor, and the analog characteristics using the saturation characteristics are improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view in order of manufacturing steps of a method for manufacturing a semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a schematic cross-sectional view in order of manufacturing steps of a conventional method for manufacturing a semiconductor device.
FIG. 7 is a schematic cross-sectional view in the order of the manufacturing steps of a conventional method for manufacturing a semiconductor device. FIG. 8 is a schematic plan view in the order of the manufacturing steps of the manufacturing method of the present invention.
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Silicon oxide film 3 Silicon active layer 4 Sacrificial oxide film 5 Element region 6 Field oxide film 7 Source region 8 Drain region 9 Oxide film 11 Body region 12 LDD region (low concentration drain region)
13 Gate oxide film 14 Gate electrode 15 Interlayer insulating film 16 Metal wiring 17 Window for body region formation 18 End of body region

Claims (5)

A first step of forming a silicon oxide film on the support substrate and a silicon active layer having a first conductivity type low impurity concentration on the silicon oxide film;
A second step of forming a first conductivity type source region and a first conductivity type drain region in the silicon active layer ;
An interval of the drain region and Nozomu Tokoro, to form a body region part by doping the second conductivity type of the silicon active layer, between the said drain region body region and the lightly doped drain region A third step to
A fourth step of forming a gate oxide film on the surface of the body region;
A fifth step of forming a gate electrode on the gate oxide film;
In a method of manufacturing an insulated gate field effect transistor having
The lightly doped drain length of the product of the impurity concentration and the channel length direction of the region, an insulated gate field effect transistor, wherein said less than half the product of the length of the impurity concentration and the channel length direction of the body region Manufacturing method. The method for manufacturing an insulated gate field effect transistor according to claim 1, wherein the impurity concentration of the silicon active layer formed in the first step is lower than the impurity concentration of the body region formed in the third step. A first step of forming a silicon oxide film on the support substrate and a silicon active layer having a first conductivity type low impurity concentration on the silicon oxide film;
A second step of forming a first conductivity type source region and a first conductivity type drain region in the silicon active layer ;
A third step of forming a silicon oxide film on the silicon active layer;
A fourth step of opening a window by etching a part of the silicon oxide film at a desired distance from the drain region;
A body region is formed by doping the silicon active layer immediately below the window opened in the third step to a second conductivity type, and a low-concentration drain region is formed between the drain region and the body region . With five processes,
A sixth step of forming a gate oxide film on the surface of the body region;
A seventh step of forming a gate electrode on the gate oxide film , and a method of manufacturing an insulated gate field effect transistor,
The lightly doped drain length of the product of the impurity concentration and the channel length direction of the region, an insulated gate field effect transistor, wherein said less than half the product of the length of the impurity concentration and the channel length direction of the body region Manufacturing method. The impurity concentration of the silicon active layer formed in the first step, the manufacturing method of an insulated gate field effect transistor according than the impurity concentration of the body region formed in said fifth step to a low I請 Motomeko 3 . In the fourth step, the window opening region is larger than the width of the silicon active layer , and in the fifth step, the body region end is doped with a second conductivity type impurity, and the body region end The method of manufacturing an insulated gate field effect transistor according to claim 2, wherein the impurity concentration of the gate region is higher than the impurity concentration of the body region .

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