JPH11191559A - Manufacture of mosfet - Google Patents

Manufacture of mosfet

Info

Publication number
JPH11191559A
JPH11191559A JP9358817A JP35881797A JPH11191559A JP H11191559 A JPH11191559 A JP H11191559A JP 9358817 A JP9358817 A JP 9358817A JP 35881797 A JP35881797 A JP 35881797A JP H11191559 A JPH11191559 A JP H11191559A
Authority
JP
Japan
Prior art keywords
region
semiconductor
semiconductor layer
channel region
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9358817A
Other languages
Japanese (ja)
Inventor
Hiroshi Okada
洋 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP9358817A priority Critical patent/JPH11191559A/en
Publication of JPH11191559A publication Critical patent/JPH11191559A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a MOSFET, having low on-resistance in a channel region, without lowering the specific resistance in the vicinity of the surface of the channel region from a prescribed value. SOLUTION: This MOSFET is provided with a semiconductor layer 2 of a first conductivity type, a semiconductor region 9 of a second conductivity type provided along the main surface of the semiconductor layer 2, a source region 10 provided on the semiconductor region 9 along the main surface of the semiconductor layer 2, and a channel region 12 of the first conductivity type, which is changed from the point located along one main surface between the semiconductor layer 2 and the source region 10 in the semiconductor region 9. In this case, a recess for the channel region is formed along the main surface by removing and etching the place between the semiconductor layer 2 and the surface region 10 in the semiconductor region 9, the recess for the channel region is embedded by epitaxial growth, and the semiconductor region 9 is changed into a channel region 12.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、DMOSFETの
製造方法に関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a DMOSFET.

【0002】[0002]

【従来の技術】従来、この種のMOSFETとして図8
に示す構成のものが存在する。このものは、図9乃至図
11に示した製造方法により製造される。
2. Description of the Related Art Conventionally, as a MOSFET of this type, FIG.
There exists a thing of a structure shown in FIG. This is shown in FIGS.
It is manufactured by the manufacturing method shown in FIG.

【0003】まず、図9(a) に示すように、第1の導電
型(n+ 型)の第1の半導体層1 及びその第1の半導体
層1 よりも比抵抗の大きい第1の導電型(n- 型)の第
2の半導体層2 が形成された基板3 のその第2の半導体
層2 の一主面に、所定の膜厚を有した第1の酸化膜4 を
形成する。次に、図9(b) に示すように、第1の酸化膜
4 の一部を除去して、第1の凹部5 を形成してから、矢
示するように、高濃度のホウ素イオンを注入する。次
に、図9(c) に示すように、注入したホウ素イオンを拡
散させて、比抵抗の小さい第2の導電型(p+ 型)の第
1の半導体領域6を所定の深さで一主面に沿って形成す
るのと同時に、その第1の半導体領域6 上に第2の酸化
膜7 を形成する。次に、図9(d) に示すように、エッチ
ングでもって、第2の酸化膜7 の一部を除去して、第2
の半導体層2 及び第1の半導体領域5 に達するよう第2
の凹部8 を形成する。次に、図9(e) に矢示するよう
に、ホウ素イオンを注入する。
First, as shown in FIG. 9A, a first semiconductor layer 1 of a first conductivity type (n + type) and a first conductive layer having a higher specific resistance than the first semiconductor layer 1. A first oxide film 4 having a predetermined thickness is formed on one main surface of a second semiconductor layer 2 of a substrate 3 on which a second semiconductor layer 2 of the type (n type) is formed. Next, as shown in FIG.
After removing a part of 4 to form the first concave portion 5, high concentration boron ions are implanted as shown by arrows. Next, as shown in FIG. 9 (c), the implanted boron ions are diffused so that the first semiconductor region 6 of the second conductivity type (p + type) having a small specific resistance has a predetermined depth. At the same time as forming along the main surface, a second oxide film 7 is formed on the first semiconductor region 6. Next, as shown in FIG. 9D, a part of the second oxide film 7 is removed by etching,
The second semiconductor layer 2 and the first semiconductor region 5
Is formed. Next, as shown by an arrow in FIG. 9E, boron ions are implanted.

【0004】次に、図10(a) に示すように、注入したホ
ウ素イオンを拡散させて、第2の導電型(p型)の第2
の半導体領域9 を形成する。次に、図10(b) に矢示する
ように、リンイオンを注入する。次に、図2(c) に示す
ように、注入したリンイオンを拡散させて、第1の導電
型(n+ 型)のソース領域10を一主面に沿って形成して
後に、第3の酸化膜11を形成する。次に、図2(d) に示
すように、エッチングでもって、第3の酸化膜11を除去
する。次に、図10(e) に示すように、リンイオンを注入
されることにより、ディプレッション化する。このと
き、第1の半導体領域6 であって第2の半導体層2 とソ
ース領域10とにより挟まれた箇所が、一主面に沿って第
1の導電型(n+ 型)を有したチャネル領域12に変換さ
れる。
Next, as shown in FIG. 10A, the implanted boron ions are diffused to form a second conductive type (p-type).
The semiconductor region 9 is formed. Next, as shown in FIG. 10B, phosphorus ions are implanted. Next, as shown in FIG. 2C, the implanted phosphorus ions are diffused to form a source region 10 of the first conductivity type (n + type) along one main surface, and thereafter, a third region is formed. An oxide film 11 is formed. Next, as shown in FIG. 2D, the third oxide film 11 is removed by etching. Next, as shown in FIG. 10E, depletion is performed by implanting phosphorus ions. At this time, the portion of the first semiconductor region 6 sandwiched between the second semiconductor layer 2 and the source region 10 is a channel having the first conductivity type (n + type) along one main surface. Converted to area 12.

【0005】次に、図11(a) に示すように、ゲート絶縁
膜となる第4の酸化膜13を形成する。次に、図11(b) に
示すように、ゲート電極となるポリシリコン製の第1の
導電膜14を形成する。次に、図11(c) に示すように、第
1の半導体領域6 及び第2の半導体層2 に達するよう、
エッチングでもって、第4の酸化膜13及び第1の導電膜
14のそれぞれの一部を除去して第3の凹部15を形成す
る。次に、図11(d) に示すように、第5の絶縁膜16を形
成して後に、第4の凹部17を形成し、さらに、第1の半
導体領域5 及びソース領域10にコンタクトしてソース電
極となる第2の導電膜18を形成し、さらに、第1の半導
体層1 の表面に、ドレイン電極となる第3の導電膜19を
形成して、図9に示したディプレッション型のDMOS
FETが製造される。
Next, as shown in FIG. 11A, a fourth oxide film 13 serving as a gate insulating film is formed. Next, as shown in FIG. 11B, a first conductive film 14 made of polysilicon to be a gate electrode is formed. Next, as shown in FIG. 11C, the first semiconductor region 6 and the second semiconductor layer 2 are reached.
By etching, the fourth oxide film 13 and the first conductive film
A portion of each of the 14 is removed to form a third recess 15. Next, as shown in FIG. 11 (d), after forming a fifth insulating film 16, a fourth concave portion 17 is formed, and further, a contact is made with the first semiconductor region 5 and the source region 10. A second conductive film 18 serving as a source electrode is formed, and a third conductive film 19 serving as a drain electrode is formed on the surface of the first semiconductor layer 1 to form a depletion type DMOS shown in FIG.
An FET is manufactured.

【0006】[0006]

【発明が解決しようとする課題】上記した従来のMOS
FETにあっては、第1の導電型(n+ 型)を有したチ
ャネル領域12は、リンイオンを注入されることにより第
2の半導体層2 とソース領域10とにより挟まれた第1の
半導体領域5 を変換することにより形成されているか
ら、図12(a) に示すように、注入されたリンイオンの濃
度が、一主面の表面付近では高いものの、深くなるにつ
れて、急激に小さくなってしまう。
SUMMARY OF THE INVENTION The conventional MOS described above
In the FET, a channel region 12 having a first conductivity type (n + type) is formed by implanting phosphorus ions into a first semiconductor layer sandwiched between a second semiconductor layer 2 and a source region 10. Since the region 5 is formed by converting the region 5, as shown in FIG. 12 (a), the concentration of the implanted phosphorus ions is high near the surface of one main surface, but rapidly decreases as the depth increases. I will.

【0007】一方、このMOSFETは、ディプレッシ
ョン型であるから、ドレインソース間をオフさせるため
には、ゲートに印加される電圧によって、一主面の表面
付近のチャネル領域12を第2の導電型(p型)に反転さ
せなければならないので、一主面の表面付近の比抵抗を
所定値以下にすることができず、深い部分のリンイオン
の濃度を高くするために、表面付近のリンイオン濃度ま
でも高くして、表面付近の比抵抗を所定値よりも低くす
るわけにはいかなくなっている。
On the other hand, since this MOSFET is a depletion type, in order to turn off between the drain and the source, the channel region 12 near the surface of one main surface is changed to the second conductivity type ( (p-type), the specific resistance in the vicinity of the surface of one main surface cannot be reduced to a predetermined value or less. It is impossible to make the specific resistance near the surface lower than a predetermined value by making it higher.

【0008】そうなると、チャネル領域12における深い
部分では、リンイオンの濃度が極めて低くなってしまっ
て、図12(b) に示すように、その深い部分での比抵抗の
値が高くなり、図13に示すように、表面付近における浅
抵抗r1と深い部分における深抵抗r2との並列接続された
抵抗r と考えられるチャネル領域12全体のオン抵抗の値
が高くなってしまう。
As a result, the concentration of phosphorus ions in the deep portion of the channel region 12 becomes extremely low, and as shown in FIG. 12 (b), the value of the specific resistance in the deep portion becomes high. as shown, parallel-connected value of the on resistance of the entire channel region 12 which is considered the resistance r was the deep resistance r 2 in shallow resistors r 1 and the deep portion in the vicinity of the surface becomes high.

【0009】本発明は、上記の点に着目してなされたも
ので、その目的とするところは、チャネル領域の表面付
近の比抵抗を所定値よりも低くすることなく、チャネル
領域のオン抵抗の値の低いMOSFETの製造方法を提
供することにある。
The present invention has been made in view of the above points, and an object thereof is to reduce the on-resistance of the channel region without lowering the specific resistance near the surface of the channel region below a predetermined value. An object of the present invention is to provide a method for manufacturing a MOSFET having a low value.

【0010】[0010]

【課題を解決するための手段】上記した課題を解決する
ために、請求項1記載の発明の製造方法は、第1の導電
型を有する半導体層と、第2の導電型を有して半導体層
の一主面に沿って設けられた半導体領域と、第1の導電
型を有して前記一主面に沿って半導体領域に設けられた
ソース領域と、半導体領域における半導体層とソース領
域との間で前記一主面に沿って位置した箇所から変換さ
れてなる第1の導電型を有したチャネル領域と、を備え
たMOSFETを製造する製造方法であって、前記半導
体領域における前記半導体層と前記ソース領域との間の
箇所をエッチングにより除去して一主面に沿ってチャネ
ル領域用凹部を形成し、エピタキシャル成長によりチャ
ネル領域用凹部を埋めて前記半導体領域から前記チャネ
ル領域に変換するようにしている。
According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor layer having a first conductivity type and a semiconductor layer having a second conductivity type. A semiconductor region provided along one main surface of the layer, a source region having a first conductivity type and provided in the semiconductor region along the one main surface, and a semiconductor layer and a source region in the semiconductor region. And a channel region having a first conductivity type converted from a portion located along the one main surface between the semiconductor layers. A portion between the semiconductor region and the source region is removed by etching to form a channel region recess along one main surface, and the channel region is filled by epitaxial growth to convert the semiconductor region to the channel region. Unishi to have.

【0011】[0011]

【発明の実施の形態】本発明の一実施形態のMOSFE
Tを図1乃至図6に基づいて以下に説明する。このMO
SFETは、デプレッション型であって、図3乃至図6
に示す製造方法により製造される。なお、従来例と実質
的に同一の箇所には、同一の符号を付し、図3及び図4
に示す工程については、従来例と同一であるので、簡略
に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS MOSFE according to one embodiment of the present invention
T will be described below with reference to FIGS. This MO
The SFET is a depletion type and is shown in FIGS.
The manufacturing method shown in FIG. The same reference numerals are given to substantially the same portions as in the conventional example, and FIGS.
Are the same as those in the conventional example, and thus will be briefly described.

【0012】まず、図3(a) に示すように、第1の半導
体層1 及第2の半導体層2 が形成された基板3 のその第
2の半導体層2 の一主面に、第1の酸化膜4 を形成す
る。次に、図3(b) に示すように、第1の絶縁膜4 の一
部を除去して、第1の凹部5 を形成してから、矢示する
ように、高濃度のホウ素イオンを注入する。次に、図3
(c) に示すように、第1の半導体領域6 を形成するのと
同時に、その第1の半導体領域6 上に第2の酸化膜7 を
形成する。次に、図3(d) に示すように、エッチングで
もって、第2の酸化膜7 の一部を除去して、第2の凹部
8 を形成する。次に、図4(a) に矢示するように、ホウ
素イオンを注入する。次に、図4(b) に示すように、第
2の半導体領域9 を形成する。次に、図4(c) に矢示す
るように、リンイオンを注入する。次に、図4(d) に示
すように、ソース領域10を形成して後に、第3の酸化膜
11を形成する。
First, as shown in FIG. 3 (a), a first main surface of a second semiconductor layer 2 of a substrate 3 on which a first semiconductor layer 1 and a second semiconductor layer 2 are formed is provided. An oxide film 4 is formed. Next, as shown in FIG. 3B, a part of the first insulating film 4 is removed to form a first concave portion 5, and then, as shown by an arrow, a high-concentration boron ion is formed. inject. Next, FIG.
As shown in (c), a second oxide film 7 is formed on the first semiconductor region 6 at the same time as the first semiconductor region 6 is formed. Next, as shown in FIG. 3D, a part of the second oxide film 7 is removed by etching to form a second concave portion.
Form 8. Next, as shown in FIG. 4A, boron ions are implanted. Next, as shown in FIG. 4B, a second semiconductor region 9 is formed. Next, as shown in FIG. 4C, phosphorus ions are implanted. Next, as shown in FIG. 4D, after forming the source region 10, a third oxide film is formed.
Form 11.

【0013】次に、図5(a) に示すように、エッチング
でもって、第3の酸化膜11の一部を除去して、第2の半
導体領域9 における第2の半導体層2 とソース領域10と
の間の箇所、詳しくは、第2の半導体領域9 を含んで第
2の半導体層2 からソース領域10にかけての箇所を露出
させる。次に、図5(b) に示すように、露出された第2
の半導体領域9 をエッチングして、チャネル領域用凹部
20を形成する。次に、図5(c) に示すように、エピタキ
シャル成長により、所定の比抵抗を有した第1の導電型
(n型)のシリコン層21を堆積して、チャネル領域用凹
部20を埋めることにより、第2の半導体領域9 からチャ
ネル領域12に変換する。次に、図5(d)に示すように、
リフトオフでもって、第3の酸化膜11と共に、エピタキ
シャル成長による余分なシリコン層21を除去する。
Next, as shown in FIG. 5A, a part of the third oxide film 11 is removed by etching, and the second semiconductor layer 2 and the source region in the second semiconductor region 9 are removed. The portion between the second semiconductor layer 9 and the source region 10 including the second semiconductor region 9 is exposed. Next, as shown in FIG.
The semiconductor region 9 is etched to form a recess for the channel region.
Form 20. Next, as shown in FIG. 5 (c), a first conductivity type (n-type) silicon layer 21 having a predetermined specific resistance is deposited by epitaxial growth to fill the channel region recess 20. , From the second semiconductor region 9 to the channel region 12. Next, as shown in FIG.
By lift-off, the excess silicon layer 21 by epitaxial growth is removed together with the third oxide film 11.

【0014】次に、図6(a) に示すように、ゲート絶縁
膜となる第4の酸化膜13を形成する。次に、図6(b) に
示すように、ゲート電極となるポリシリコン製の第1の
導電膜14を形成する。次に、図6(c) に示すように、第
1の半導体領域6 及び第2の半導体層2 に達するよう、
エッチングでもって、第4の酸化膜13及び第1の導電膜
14のそれぞれの一部を除去して第3の凹部15を形成す
る。次に、図6(d) に示すように、第5の酸化膜16を形
成して後に、第4の凹部17を形成し、さらに、第1の半
導体領域6 及びソース領域10にコンタクトしてソース電
極となる第2の導電膜18を形成し、さらに、第1の半導
体層1 の表面に、ドレイン電極となる第3の導電膜19を
形成して、図1に示したデプレッション型のDMOSF
ETが製造される。
Next, as shown in FIG. 6A, a fourth oxide film 13 serving as a gate insulating film is formed. Next, as shown in FIG. 6B, a first conductive film 14 made of polysilicon to be a gate electrode is formed. Next, as shown in FIG. 6C, the first semiconductor region 6 and the second semiconductor layer 2 are reached.
By etching, the fourth oxide film 13 and the first conductive film
A portion of each of the 14 is removed to form a third recess 15. Next, as shown in FIG. 6 (d), after forming a fifth oxide film 16, a fourth concave portion 17 is formed, and further, a contact is made with the first semiconductor region 6 and the source region 10. A second conductive film 18 serving as a source electrode is formed, and a third conductive film 19 serving as a drain electrode is formed on the surface of the first semiconductor layer 1, thereby forming a depletion type DMMOS shown in FIG.
An ET is manufactured.

【0015】かかるMOSFETの製造方法にあって
は、第2の半導体領域9 における第2の半導体層2 とソ
ース領域10との間の箇所をエッチングにより除去して形
成されたチャネル領域用凹部20が、エピタキシャル成長
により埋められて変換されてなるチャネル領域12は、従
来例のように、深さ方向に沿った濃度分布を殆ど有して
いないから、比抵抗が深さ方向に沿って略同一となり、
表面付近の比抵抗の値が所定値以下ではないR1 である
とき、深い部分での比抵抗の値が、R1 と略等しいR2
となる。従って、図7に示すように、表面付近における
浅抵抗r1と深い部分における深抵抗r2との並列接続され
た抵抗r と考えられるチャネル領域12全体のオン抵抗の
値R3 は、(1) 式に示されるようになる。
In this method of manufacturing a MOSFET, a channel region recess 20 formed by etching away a portion of the second semiconductor region 9 between the second semiconductor layer 2 and the source region 10 is formed. Since the channel region 12 buried and converted by epitaxial growth has almost no concentration distribution along the depth direction as in the conventional example, the specific resistance becomes substantially the same along the depth direction,
When the value of the specific resistance in the vicinity of the surface is R 1 is not equal to or less than the predetermined value, the value of the specific resistance of the deep portion is substantially equal to R 1 R 2
Becomes Accordingly, as shown in FIG. 7, the shallow resistance r 1 and deep resistor r 2 value R 3 of the on resistance of the entire parallel-connected resistor r and is considered a channel region 12 between the deeper portion in the vicinity of the surface (1 ) Expression.

【0016】 R3 =R1 ×R2 /(R1 +R2 ) (1) 一方、従来例では、深い部分での比抵抗の値は、表面付
近の比抵抗の値R1 よりも大きいR4 となるので、図13
に示すように、表面付近における浅抵抗r1と深い部分に
おける深抵抗r2との並列接続された抵抗r と考えられる
チャネル領域12全体のオン抵抗の値R5 は、(2) 式に示
されるようになる。
R 3 = R 1 × R 2 / (R 1 + R 2 ) (1) On the other hand, in the conventional example, the value of the specific resistance in the deep portion is larger than the specific resistance R 1 in the vicinity of the surface. 4
As shown, the value R 5 of the shallow resistance r 1 and parallel connected channel region 12 is believed resistance r was the overall on-resistance of the deep resistance r 2 in the deep portion near the surface are shown in (2) Will be able to

【0017】 R5 =R1 ×R4 /(R1 +R4 ) (2) ここで、R3 とR5 との大小関係を考察するために、
(1) 式から(2) 式を減算する。
R 5 = R 1 × R 4 / (R 1 + R 4 ) (2) Here, in order to consider the magnitude relationship between R 3 and R 5 ,
Subtract equation (2) from equation (1).

【0018】R3 −R5 =(R1 2×(R2 −R4 ))/
((R1 +R4 )×(R1 +R2 )) なお、R2 <R4 であるから、R3 −R5 <0となっ
て、R3 <R5 、すなわち、チャネル領域12全体のオン
抵抗の値を、従来例よりも低くすることができる。
[0018] R 3 -R 5 = (R 1 2 × (R 2 -R 4)) /
((R 1 + R 4 ) × (R 1 + R 2 )) Since R 2 <R 4 , R 3 −R 5 <0, and R 3 <R 5 , that is, the entire channel region 12. The value of the on-resistance can be made lower than in the conventional example.

【0019】このように、オン抵抗の値を低くすること
ができるから、オン抵抗を低減するために、チャネル幅
を増大させなくてもよくなり、半導体素子面積を小さく
でき、ひいては、半導体ウエハー上に作り込む半導体素
子数を増加させることができる。
As described above, since the value of the on-resistance can be reduced, the channel width does not need to be increased in order to reduce the on-resistance, and the area of the semiconductor element can be reduced. The number of semiconductor elements to be manufactured can be increased.

【0020】また、チャネル領域12は、その深さ方向に
沿って、比抵抗が略一定となるので、比抵抗の深さ方向
の分布を特に配慮せずに、その深さを決定でき、設計の
自由度を上げることができる。
Further, since the resistivity of the channel region 12 is substantially constant along the depth direction, the depth can be determined without particular consideration of the distribution of the resistivity in the depth direction. Degree of freedom can be increased.

【0021】[0021]

【発明の効果】請求項1記載の発明の製造方法による
と、半導体領域における半導体層 とソース領域との間
の箇所をエッチングにより除去して形成されたチャネル
領域用凹部が、エピタキシャル成長により埋められて変
換されてなるチャネル領域は、従来例のように、深さ方
向に沿った濃度分布を殆ど有していないから、比抵抗が
深さ方向に沿って略同一となり、一主面の表面付近の比
抵抗を所定値以下にすることなく、その表面付近の比抵
抗が従来例と同一である場合、深い部分での比抵抗が、
従来例よりも小さくなるので、表面付近における浅抵抗
と深い部分における深抵抗との並列接続された抵抗と考
えられるチャネル領域全体のオン抵抗の値を、従来例よ
りも低くすることができる。
According to the manufacturing method of the present invention, the recess for the channel region formed by removing the portion between the semiconductor layer and the source region in the semiconductor region by etching is filled by epitaxial growth. Since the converted channel region has almost no concentration distribution along the depth direction as in the conventional example, the specific resistance becomes substantially the same along the depth direction, and the vicinity of the surface of one main surface is reduced. If the specific resistance near the surface is the same as that of the conventional example without making the specific resistance equal to or less than a predetermined value, the specific resistance in a deep part is
Since the resistance is smaller than in the conventional example, the value of the on-resistance of the entire channel region, which is considered to be a resistance connected in parallel with the shallow resistance near the surface and the deep resistance in the deep portion, can be lower than in the conventional example.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の断面図である。FIG. 1 is a cross-sectional view of one embodiment of the present invention.

【図2】同上のチャネル領域におけるリンイオン濃度及
び抵抗率の深さ方向の分布を示す説明図である。
FIG. 2 is an explanatory diagram showing a distribution in the depth direction of a phosphorus ion concentration and a resistivity in a channel region of the above.

【図3】同上の製造方法を示す基板の断面図である。FIG. 3 is a cross-sectional view of the substrate, illustrating the manufacturing method according to the first embodiment.

【図4】同上の図3に続く製造方法を示す基板の断面図
である。
FIG. 4 is a cross-sectional view of the substrate showing a manufacturing method following FIG. 3 in the same.

【図5】同上の図4に続く製造方法を示す基板の断面図
である。
FIG. 5 is a cross-sectional view of the substrate showing the manufacturing method following FIG. 4 in the above.

【図6】同上の図5に続く製造方法を示す基板の断面図
である。
FIG. 6 is a cross-sectional view of the substrate, showing a manufacturing method following FIG. 5 in the above.

【図7】同上のチャネル部の抵抗値を説明する断面図で
ある。
FIG. 7 is a cross-sectional view illustrating a resistance value of a channel part of the above power supply system.

【図8】従来例の断面図である。FIG. 8 is a sectional view of a conventional example.

【図9】従来例の製造方法を示す基板の断面図である。FIG. 9 is a cross-sectional view of a substrate showing a conventional manufacturing method.

【図10】同上の図9に続く製造方法を示す基板の断面
図である。
FIG. 10 is a cross-sectional view of the substrate showing the manufacturing method following FIG. 9 in the above.

【図11】同上の図10に続く製造方法を示す基板の断
面図である。
FIG. 11 is a sectional view of the substrate, showing a manufacturing method following FIG. 10 in the above.

【図12】同上のチャネル領域におけるリンイオン濃度
及び抵抗率の深さ方向の分布を示す説明図である。
FIG. 12 is an explanatory diagram showing the distribution of the concentration of phosphorus ions and the resistivity in the channel region in the depth direction in the depth direction.

【図13】同上のチャネル部の抵抗値を説明する断面図
である。
FIG. 13 is a cross-sectional view for explaining a resistance value of a channel portion of the above.

【符号の説明】[Explanation of symbols]

2 第2の半導体層 9 第2の半導体領域 10 ソース領域 12 チャネル領域 20 チャネル領域用凹部 2 Second semiconductor layer 9 Second semiconductor region 10 Source region 12 Channel region 20 Channel region recess

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1の導電型を有する半導体層と、第2
の導電型を有して半導体層の一主面に沿って設けられた
半導体領域と、第1の導電型を有して前記一主面に沿っ
て半導体領域に設けられたソース領域と、半導体領域に
おける半導体層とソース領域との間で前記一主面に沿っ
て位置した箇所から変換されてなる第1の導電型を有し
たチャネル領域と、を備えたMOSFETを製造する製
造方法であって、 前記半導体領域における前記半導体層と前記ソース領域
との間の箇所をエッチングにより除去して一主面に沿っ
てチャネル領域用凹部を形成し、エピタキシャル成長に
よりチャネル領域用凹部を埋めて前記半導体領域から前
記チャネル領域に変換することを特徴とするMOSFE
Tの製造方法。
A semiconductor layer having a first conductivity type;
A semiconductor region having a first conductivity type provided along one main surface of the semiconductor layer, a source region having a first conductivity type provided in the semiconductor region along the one main surface, and a semiconductor And a channel region having a first conductivity type converted from a portion located along the one main surface between the semiconductor layer and the source region in the region. A portion between the semiconductor layer and the source region in the semiconductor region is removed by etching to form a channel region concave portion along one main surface, and the channel region concave portion is filled by epitaxial growth. MOSFE for converting to the channel region
Manufacturing method of T.
JP9358817A 1997-12-26 1997-12-26 Manufacture of mosfet Pending JPH11191559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9358817A JPH11191559A (en) 1997-12-26 1997-12-26 Manufacture of mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9358817A JPH11191559A (en) 1997-12-26 1997-12-26 Manufacture of mosfet

Publications (1)

Publication Number Publication Date
JPH11191559A true JPH11191559A (en) 1999-07-13

Family

ID=18461266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9358817A Pending JPH11191559A (en) 1997-12-26 1997-12-26 Manufacture of mosfet

Country Status (1)

Country Link
JP (1) JPH11191559A (en)

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