WO2022190269A1

WO2022190269A1 - Silicon carbide semiconductor device, method for manufacturing same, and power conversion device

Info

Publication number: WO2022190269A1
Application number: PCT/JP2021/009567
Authority: WO
Inventors: 基吉田; 梨菜田中; 裕福井; 英之八田
Original assignee: 三菱電機株式会社
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2022-09-15
Also published as: JPWO2022190269A1

Abstract

A silicon carbide semiconductor device according to the present disclosure comprises: an n-type drift layer (20) on an n-type semiconductor substrate (10); a p-type body region (30) on the drift layer (20); an n-type source region (40) on the body region (30); a gate trench (91) penetrating the source region (40) and the body region (30); a gate electrode (50) formed in the gate trench (91) so as to face the body region (30) via a gate insulating film (60); a Schottky trench (20) formed so as to have a lower end in the drift layer (92); a Schottky electrode (81) which is formed within the Schottky trench (81) and which has Ti as the main component; and a reaction layer (92) which is formed between the Schottky electrode (20) and the drift layer (20) in contact with the side surface of the Schottky trench (92), and which is composed of TiSi having an atomic composition ratio of Ti to Si of at least 0.5. According to the present disclosure, a highly reliable silicon carbide semiconductor device can be obtained.

Description

SILICON CARBIDE SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND POWER CONVERTER

The present disclosure relates to a silicon carbide semiconductor device having a trench gate, a manufacturing method thereof, and a power conversion device using the silicon carbide semiconductor device having a trench gate.

A unipolar switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) and a unipolar freewheeling diode such as a Schottky Barrier Diode (SBD) are incorporated. Power semiconductor devices are known. Such a semiconductor device can be realized by arranging a MOSFET cell and an SBD cell in parallel on the same chip. It can be realized by making

By incorporating a freewheeling diode into the switching element chip, the cost can be reduced compared to attaching a freewheeling diode to the switching element externally. In particular, in a MOSFET using silicon carbide (SiC) as a base material, it is one of the merits that a bipolar operation due to a parasitic pn diode can be suppressed by incorporating an SBD. This is because, in a silicon carbide semiconductor device, the reliability of the device may be impaired due to expansion of crystal defects caused by recombination energy of carriers due to parasitic pn diode operation.

In addition, in a trench-gate MOSFET having a structure in which a gate electrode is embedded in a trench formed in a semiconductor layer, compared to a planar-type MOSFET having a structure in which a gate electrode is formed on the surface of a semiconductor layer, the side wall of the trench Since the channel can be formed in the region, the channel width density can be improved and the on-resistance can be reduced. Therefore, a structure is known in which an SBD is incorporated in a trench gate type MOSFET (for example, Patent Document 1).

JP 2019-218224 A

In such an SBD-embedded trench type MOSFET, a Schottky interface is formed on the sidewall of the trench, but in some cases the Schottky interface cannot be formed uniformly. If the Schottky interface cannot be formed uniformly, the height of the Schottky barrier will be uneven, resulting in uneven flow of leakage current during reverse bias and occurrence of locations where the adhesion between the Schottky electrode and the semiconductor layer is reduced. In some cases, the Schottky electrode was partially peeled off.

The present disclosure has been made to solve the above-described problems, and aims to uniformize the leakage current at the Schottky interface and suppress the separation of the Schottky electrode at the Schottky interface by forming the Schottky interface uniformly. An object of the present invention is to provide a highly reliable silicon carbide semiconductor device.

A silicon carbide semiconductor device of the present disclosure includes a drift layer made of first conductivity type silicon carbide formed on a first main surface of a semiconductor substrate made of first conductivity type silicon carbide, and a drift layer formed on the drift layer. a body region made of silicon carbide of the second conductivity type, a source region made of silicon carbide of the first conductivity type formed on at least a part of the body region, and drift through the source region and the body region a gate trench reaching a layer; a gate electrode formed in the gate trench so as to face the body region with a gate insulating film interposed therebetween; A reaction layer formed between the formed Schottky electrode containing Ti as a main component and a drift layer in contact with the Schottky electrode and the side surface of the Schottky trench and made of TiSi having an atomic composition ratio of Ti to Si of 0.5 or more. and

According to the silicon carbide semiconductor device according to the present disclosure, a highly reliable silicon carbide semiconductor device can be obtained.

1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment; FIG. 1 is a plan view of a silicon carbide semiconductor device according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a first embodiment; FIG. 3 is a cross-sectional SEM view of the Schottky interface of the silicon carbide semiconductor device according to Embodiment 1; FIG. 3 is a reference cross-sectional SEM view of the Schottky interface of the silicon carbide semiconductor device related to the first embodiment; FIG. FIG. 9 is a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a second embodiment; FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device under manufacture according to a second embodiment; FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device according to a third embodiment; FIG. 11 is a cross-sectional view of a silicon carbide semiconductor device according to a fourth embodiment; FIG. 11 is a schematic diagram showing the configuration of a power converter diagram according to Embodiment 5;

Embodiments will be described below with reference to the accompanying drawings. It should be noted that the drawings are shown schematically, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily described accurately and may be changed as appropriate. Moreover, in the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.
In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the conductivity types may be reversed.

Embodiment 1.
First, a silicon carbide semiconductor device according to a first embodiment of the present disclosure will be described.
FIG. 1 is a cross-sectional view of a part of an active region of a trench type silicon carbide MOSFET with built-in Schottky barrier diode (SiC trench MOSFET with built-in SBD), which is a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a plan view of the SBD-embedded SiC trench MOSFET shown in FIG. 1, and is a plan view at a certain depth where the trench is formed.

As shown in FIG. 1, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistance silicon carbide. Body region 30 made of p-type silicon carbide is provided on drift layer 20 .
Gate trenches 91 and Schottky trenches 92 are arranged alternately and in parallel in drift layer 20 in which body region 30 is formed. A source region 40 made of n-type silicon carbide is provided in a surface layer portion of body region 30 adjacent to gate trench 91 . A low-resistance p-type contact region 35 is formed in the surface layer portion of the body region 30 between the gate trench 91 and the Schottky trench 92 .

Gate trench 91 is formed to reach drift layer 20 from the surface of source region 40 through source region 40 and body region 30 . Schottky trench 92 is formed to extend from the surface of body region 30 through body region 30 to reach drift layer 20 . A gate electrode 60 is formed in the gate trench 91 with a gate insulating film 50 made of silicon oxide interposed therebetween. The gate electrode 60 is made of low resistance polycrystalline silicon with a high impurity concentration. An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60 .

A Schottky electrode 81 containing Ti is formed in Schottky trench 92 , and a reaction layer 71 made of TiSi is formed at the interface between Schottky trench 92 and drift layer 20 and body region 30 . The reaction layer 71 and the Schottky electrode 81 are in Schottky contact with the drift layer 20 as a whole.
A p-type first protection region 31 is formed in the drift layer 20 at the bottom of the gate trench 91 . A p-type second protection region 32 is formed in the drift layer 20 at the bottom of the Schottky trench 92 . The first protection region 31 and the second protection region 32 have the same depth and the same impurity concentration. A drain electrode 82 is formed on the back surface side of the semiconductor substrate 10 .
Ohmic electrode 70 is formed on contact region 35 and source region 40 , and source electrode 80 is formed on ohmic electrode 70 and Schottky electrode 81 .

As shown in FIG. 2, in plan view, p-type connection regions are formed at regular intervals along the longitudinal direction of the striped gate trenches 91 and Schottky trenches 92 . A p-type connection region formed for the gate trench 91 is the first connection region 33 , and the first connection region 33 is formed on the drift layer 20 so as to connect the first protection region 31 and the body region 30 . formed within. A p-type connection region formed for the Schottky trench 92 is the second connection region 34 , and the second connection region 34 connects the second protection region 32 and the body region 30 to the drift layer 20 . formed within.

Here, the reaction layer 71 is a layer formed by reaction of Ti and Si, and the atomic composition ratio of Ti to Si is 0.5 or more and 2.0 or less. Also, the thickness of the reaction layer 71 is 1 nm or more and 50 nm or less. Also, the reaction layer 71 between the drift layer 20 and the Schottky electrode 81 is formed uniformly.

In addition, the Schottky electrode 81 may be made of Ti, but at least the part closest to the semiconductor layer is made of Ti, and may have a laminated structure of Ti and other metals.

Next, a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to cross-sectional views of FIGS. 3 to 10 corresponding to the cross-section shown in FIG.
explain.

First, on a semiconductor substrate 10 made of n-type low-resistance silicon carbide having a 4H polytype and a (0001) plane whose first main surface is inclined by 1° or more in the <11-20> direction, Silicon carbide having an impurity concentration of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less and an n-type silicon carbide thickness of 5 μm or more and 50 μm or less by chemical vapor deposition (CVD method). A drift layer 20 made of is epitaxially grown. The surface of the drift layer 20 is also the (0001) plane inclined by 1° or more in the <11-20> direction.

Subsequently, ions of Al (aluminum), which is a p-type impurity, are implanted into the surface of the drift layer 20 . At this time, the depth of the Al ion implantation is about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20 . The impurity concentration of ion-implanted Al is in the range of 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, which is higher than the impurity concentration of the drift layer 20 . A region implanted with Al ions in this step becomes the body region 30 .

Next, an implantation mask is formed with a photoresist or the like so that a predetermined portion of the body region 30 on the surface of the drift layer 20 is opened, and an n-type impurity N (nitrogen) is ion-implanted. The N ion implantation depth is assumed to be shallower than the thickness of the body region 30 . The impurity concentration of ion-implanted N is in the range of 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ and exceeds the p-type impurity concentration of the body region 30 . Of the regions into which N is implanted in this step, the region exhibiting the n-type becomes the source region 40 . After that, the implantation mask is removed.
Further, by the same method, impurities in a range of 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ⁻³ higher than the impurity concentration of the body region 30 are added to a predetermined region of the body region 30 adjacent to the source region 40 . A contact region 35 is formed by ion-implanting Al so as to obtain a concentration. Through these steps, the structure of the cross-sectional view shown in FIG. 3 is obtained.

Subsequently, a resist mask is formed to partially open the region where the source region 40 is formed, and a gate trench 91 is formed by dry etching to reach the drift layer 20 through the source region 40 and the body region 30 . Similarly, a resist mask is formed to partially open a region where the source region 40 is not formed, and a Schottky trench 92 that penetrates the body region 30 and reaches the drift layer 20 is formed by dry etching.
At this time, the gate trench 91 and the Schottky trench 92 are formed so that their longitudinal directions are along the <11-20> direction. When the trench sidewalls of the gate trench 91 and the Schottky trench 92 are formed perpendicular to the surface of the drift layer 20, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 are aligned with the (1-100) plane. (−1100) plane. In practice, the longitudinal sidewalls of the gate trench 91 and the Schottky trench 92 face the first main surface, which is the surface of the drift layer 20 or the surface of the semiconductor substrate 10 . The angle forms an angle in the range of 80 degrees or more and 90 degrees or less. Therefore, the side walls of the gate trench 91 and the Schottky trench 92 in the longitudinal direction are inclined within 10 degrees from the (1-100) plane and the (-1100) plane.
Here, the gate trench 91 and the Schottky trench 92 may be formed to the same depth by the same dry etching process. Through these steps, the structure of the cross-sectional view shown in FIG. 4 is obtained.

Subsequently, as shown in the schematic cross-sectional view of FIG. 5, p-type impurity ions are implanted into the drift layer 20 at the bottom of the gate trench 91 and the Schottky trench 92 to form a first protection region 31 and a second protection region, respectively. form 32; The p-type impurity concentration of the first protection region 31 and the second protection region 32 may be in the range of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. After ion implantation, the resist mask is removed. In addition, a resist mask is formed with openings at locations where the first connection region 33 and the second connection region 34 are to be formed, and p-type impurities are obliquely ion-implanted to form the first connection region 33 and the second connection region 34 . Form. The p-type impurity concentration of the first connection region 33 and the second connection region 34 may be in the range of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. After ion implantation, the resist mask is removed.
Next, annealing is performed in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour using a heat treatment apparatus. This annealing electrically activates the implanted N and Al ions.

Subsequently, with the Schottky trench 92 covered with a protective insulating film, the gate insulating film 50 made of silicon oxide is formed in the gate trench 91 with a thickness of 10 nm or more and 300 nm or less. Next, a gate electrode 60 is formed by forming a conductive polycrystalline silicon film having a thickness of 300 nm or more and 2000 nm or less in the gate insulating film 50 by low pressure CVD and patterning. After removing the protective insulating film, the cross-sectional view shown in FIG. 6 is formed.

Subsequently, an interlayer insulating film 55 made of silicon oxide and having a thickness of 500 nm or more and 3000 nm or less is formed by low pressure CVD.
Next, the interlayer insulating film 55 is etched so as to open above the region where the source region 40 and the contact region 35 are formed, and a metal such as Ni is deposited inside and annealed. 2, an ohmic electrode 70 made of a NiSi alloy layer (silicide) is formed on the source region 40 and the contact region 35. As shown in FIG.

Subsequently, as shown in the cross-sectional view of FIG. 8, after removing the interlayer insulating film 55 in the Schottky trench 92, a Schottky electrode 81 made of Ti is formed in the Schottky trench 92, on the ohmic electrode 70 and on the interlayer insulating film 55. Then, as shown in FIG. is formed by sputtering. Further, a source electrode 80 containing Al is formed thereon by a sputtering method. The source electrode 80 may have a laminated structure of Al/Ti. A cross-sectional view of this state is shown in FIG.
Thereafter, with the Schottky electrode 81 formed in the Schottky trench 92, the temperature is raised from room temperature to 400° C. or more and 600° C. or less at a rate of 10° C./sec in an inert gas such as Ar. to heat. The heating time for annealing at a temperature of 400° C. or more and 600° C. or less may be 5 minutes or more and 30 minutes or less.

By heating under such conditions, a reaction layer 71 made of TiSi is formed at the interface between the drift layer 20 and the Schottky electrode 81, as shown in the sectional view of FIG. As described above, the atomic composition ratio of Ti to Si in the reaction layer 71 is 0.5 or more and 2.0 or less. Also, the thickness of the reaction layer 71 is 5 nm or more and 50 nm or less. Further, the reaction layer 71 is formed uniformly in the region where the reaction layer 71 is formed. Since the reaction layer 71 is heated in the inert gas, the oxygen concentration in the reaction layer 71 is low, and the atomic composition concentration of oxygen in the reaction layer 71 is 5% or less. Since the reaction layer 71 is formed in a state with less oxygen, it is possible to prevent unevenness from being formed on the interface, and the reaction layer 71 is formed uniformly.
Further, the longitudinal side walls of the gate trench 91 and the Schottky trench 92 are not affected by the off direction of the semiconductor substrate 10 (1-100) plane and (−1100) plane, or are inclined within 10 degrees from these planes. Therefore, the reaction layer 71 can be uniformly formed on both side wall surfaces of the Schottky trench 92 in the longitudinal direction regardless of the off-angle of the semiconductor substrate 10 .

Here, FIG. 11 shows a cross-sectional SEM (Scanning Electron Microscope) view from source electrode 80 to drift layer 20 of the silicon carbide semiconductor device of the present embodiment. In FIG. 11, after the Schottky electrode 81 was formed in the Schottky trench 92, the temperature was raised at a rate of temperature rise of 10° C./sec and annealed in Ar gas at a temperature of 450° C. for 10 minutes. On the other hand, FIG. 12 is a cross-sectional SEM view ( Reference diagram).
In the silicon carbide semiconductor device of the present embodiment annealed at 450° C., the reaction layer 71 is uniformly formed with substantially the same thickness at the Schottky interface. , the interface was not formed uniformly.

Subsequently, by forming a back surface ohmic electrode (not shown) and a drain electrode 82 on the back surface side, the SBD-embedded SiC trench MOSFET whose cross-sectional view is shown in FIG. 1 can be manufactured.

Although the example in which the silicon carbide layer in contact with the upper end of Schottky trench 92 is p-type body region 30 has been described, an n-type low resistance region may be formed here.

According to the silicon carbide semiconductor device of the present embodiment, not only is the Schottky barrier height of the SBD formed between Schottky electrode 81 and drift layer 20 constant within each Schottky trench 92, but also Variations in the Schottky barrier heights of the SBDs of the other Schottky trenches 92 are also reduced. Therefore, it is possible to suppress leakage current from flowing from a portion where the Schottky barrier height is partially reduced in the off state. In addition, the adhesion between Schottky electrode 81 and drift layer 20 on the side wall of Schottky trench 92 is improved, and partial separation of Schottky electrode 81 can be prevented, so that a highly reliable silicon carbide semiconductor device can be obtained. can.
In addition, since the longitudinal direction of the stripe-shaped Schottky trenches 92 is formed parallel to the off-direction of the semiconductor substrate 10 , that is, along the off-direction, the Schottky trenches 92 are not affected by the off-angle of the semiconductor substrate 10 . A reaction layer 71 having the same properties and thickness can be formed on both longitudinal side walls of the .

Embodiment 2.
FIG. 13 is a cross-sectional view of part of the active region in the silicon carbide semiconductor device of the second embodiment. Unlike the silicon carbide semiconductor device of the first embodiment, the silicon carbide semiconductor device of the present embodiment further includes an ohmic electrode 70 between Schottky trench 92 and body region 30 in contact with Schottky trench 92 . That is, ohmic electrode 70 formed on contact region 35 and source region 40 extends to the upper portion of the sidewall of Schottky trench 92 . Since other points are the same as those of the first embodiment, detailed description thereof will be omitted.

In the silicon carbide semiconductor device of the present disclosure, the Schottky interface of SBD formed between Schottky electrode 81 and drift layer 20 may be homogeneously formed, and between body region 30 and Schottky electrode 81 The reaction layer 71 may be omitted. In FIG. 13, Schottky trench 92 is formed through contact region 35 and body region 30 . Within the Schottky trench 92, the ohmic electrode 70 is formed in the entire region where the contact region 35 faces the Schottky trench 92 and part of the region where the body region 30 faces the Schottky trench 92. . Reactive layer 71 is formed in a region of Schottky trench 92 facing below body region 30 and drift layer 20 .

Next, a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described.
The first half of the manufacturing method is the same as in FIGS. 3 to 6 of the first embodiment. 6, interlayer insulating film 55 is patterned so that interlayer insulating film 55 remains only on gate trench 91 and on the bottom of Schottky trench 92, as shown in the cross-sectional view of FIG.
Subsequently, as shown in the cross-sectional view of FIG. 15, the ohmic electrode 70 is formed in a portion where the interlayer insulating film 55 is not formed, and the interlayer insulating film at the bottom of the Schottky trench 92 is removed in the same manner as in the first embodiment. .
After that, a Schottky electrode 81 is formed, and annealing is performed in the same manner as in the first embodiment. After that, a drain electrode 82 is formed on the back surface side of semiconductor substrate 10, thereby forming the structure of the present embodiment having the cross-sectional view of FIG. A silicon carbide semiconductor device can be manufactured.

According to silicon carbide semiconductor device of the present embodiment, the contact area between contact region 35 and ohmic electrode 70 can be increased. Contact resistance can be reduced. Further, since it is not necessary to form a region between the contact region 35 and the Schottky trench 92, it is possible to reduce the width of the contact region 35 between the end of the source region 40 and the Schottky trench 92 in the lateral direction of the cross section. can. Therefore, the width of the unit cell shown in FIG. 13 can be reduced, and as a result, the amount of current flowing per unit area can be increased. That is, the on-resistance of the chip can be reduced.

Also, since the ohmic electrode 70 formed by reacting a layer of silicon carbide and a metal such as Ni is formed on the upper end of the Schottky trench 92, the corners of the upper end of the Schottky trench 92 are rounded. Therefore, the embedding property when embedding the Schottky electrode 81 in the Schottky trench 92 is improved, and the manufacturing yield can be further increased.

Embodiment 3.
FIG. 16 is a cross-sectional view of part of the active region in the silicon carbide semiconductor device of the third embodiment. The silicon carbide semiconductor device of the present embodiment of FIG. 16 differs from the silicon carbide semiconductor device of the first embodiment in that reaction layer 71 is not uniformly formed within Schottky trench 92 . Since other points are the same as those of the first embodiment, detailed description thereof will be omitted.

In the silicon carbide semiconductor device of the present disclosure, the Schottky interface of SBD formed between Schottky electrode 81 and drift layer 20 only needs to be homogeneously formed, and the reaction between body region 30 and Schottky electrode 81 Layer 71 need not be the same thickness as reaction layer 71 formed between Schottky electrode 81 and drift layer 20 . Also, the reaction layer 71 between the body region 30 and the Schottky electrode 81 may be omitted.

As shown in FIG. 16 , in the silicon carbide semiconductor device of the present embodiment, Schottky electrode 81 does not have to be buried in the entire region where body region 30 is in contact with Schottky trench 92 . When Schottky electrode 81 is buried in Schottky trench 92, the silicon carbide semiconductor device of the present embodiment can be manufactured by not filling Schottky trench 92 entirely, or by removing the upper portion after filling Schottky trench 92 . The upper portion of the Schottky trench 92, which is not filled with the Schottky electrode 81, may be filled with the source electrode 80 to be formed later.

According to silicon carbide semiconductor device of the present embodiment, homogeneous reaction layer 71 is formed between drift layer 20 and Schottky electrode 81 even when Schottky electrode 81 is not embedded up to the upper portion of Schottky trench 92 . and can be manufactured more easily.

Embodiment 4.
FIG. 17 is a cross-sectional view of part of the active region in the silicon carbide semiconductor device of the fourth embodiment. In the silicon carbide semiconductor device of the present embodiment in FIG. 17 , an inclined surface 92T is formed on the side wall at the lower portion of Schottky trench 92 . Since other points are the same as those of the first embodiment, detailed description thereof will be omitted.

As shown in FIG. 17, in the silicon carbide semiconductor device of the present embodiment, in the region where Schottky electrode 81 and drift layer 20 under Schottky trench 92 face each other, inclined surface 92T is inclined at an angle of 45 degrees with respect to the silicon carbide layer surface. is inclined at an angle of A reaction layer 71 having a constant thickness is formed between the Schottky electrode 81 and the drift layer 20 .
The boundary between body region 30 and Schottky electrode 81 is a plane perpendicular to the surface of the silicon carbide layer, and reaction layer 71 is also formed at that interface.
The silicon carbide semiconductor device of the present embodiment can be manufactured by etching Schottky trench 92 in two stages.

According to the silicon carbide semiconductor device of the present embodiment, the area of the Schottky interface can be increased for trenches of the same depth, and the unipolar current density that can be flowed per unit area can be increased. .
In addition, since the angle formed by the corners at both ends of the bottom of the Schottky trench 92 is obtuse, the filling property of the Schottky electrode 81 into the Schottky trench 92 is improved, and the probability of forming a void-like space in the Schottky trench 92 is increased. can be reduced.
Furthermore, according to the silicon carbide semiconductor device of the present embodiment, since the corner portion of the bottom of Schottky trench 92 is covered with second protection region 32 of the second conductivity type, the voltage is applied to gate insulating film 50 near the bottom of Schottky trench 92 . The applied electric field can be reduced, and a more reliable silicon carbide silicon carbide semiconductor device can be obtained.

Thus, the silicon carbide semiconductor device of the present embodiment includes an SBD with a large area and uniform Schottky barrier height, and is a highly reliable silicon carbide semiconductor device.

In the silicon carbide silicon carbide semiconductor device of the present embodiment, the inclined surface 92T of the Schottky trench 92 has been described as inclined at an angle of 45 degrees with respect to the surface of the silicon carbide layer, but this angle is not necessarily 45 degrees. The angle need not be equal, and may be 35 degrees or more and 60 degrees or less.
Furthermore, in the silicon carbide silicon carbide semiconductor device of the present embodiment, the case where the Schottky interface where the reaction layer 71 is formed is entirely the inclined surface 92T has been described. Even if it is formed on a plane substantially perpendicular to the surface of the silicon carbide layer, the same effect can be obtained as long as the reaction layer 71 is formed uniformly on both.

In Embodiments 1 to 4, an example in which the Schottky electrode 81 and the source electrode 80 are separately formed has been described. may be the same electrode in one piece. At this time, it may be a laminated structure as a whole.

Moreover, in the first to fourth embodiments, the method of forming the body region 30 and the source region 40 by ion implantation has been described, but the body region 30 and the source region 40 may be formed by other methods. For example, it may be formed by an epitaxial method. Furthermore, although the example in which the body region 30 is formed over the entire surface has been described, the body region 30 may be formed in part of the upper layer portion of the drift layer 20 . At that time, the Schottky trench 92 may be provided directly from the surface of the drift layer 20 instead of penetrating the body region 30 .

Furthermore, in Embodiments 1 to 4, examples in which the first protection region 31 and the second protection region 32 are provided under the trench have been described, but the first protection region 31 and the second protection region 32 may be may be omitted. At this time, neither the first connection region 33 nor the second connection region 34 may be provided.
Moreover, the gate trenches 91 and the Schottky trenches 92 may be provided in a grid pattern instead of in a stripe pattern.

Furthermore, although aluminum (Al) is used as the p-type impurity in the first to fourth embodiments, the p-type impurity may be boron (B) or gallium (Ga). The n-type impurity may be phosphorus (P) instead of nitrogen (N). In the MOSFETs described in the first and second embodiments, the gate insulating film does not necessarily have to be an oxide film such as SiO ₂ . may be a combination of Further, in the above-described embodiments, the crystal structure, the plane orientation of the main surface, the off-angle, the implantation conditions, and the like have been described using specific examples, but the scope of application is not limited to these numerical ranges.

Further, in the above embodiment, the SBD is incorporated in a so-called vertical MOSFET silicon carbide semiconductor device in which the drain electrode 85 is formed on the back surface of the semiconductor substrate 10 . It can also be used for a so-called lateral MOSFET such as a RESURF (REduced SURface Field) type MOSFET formed on the surface, in which an SBD is built. Furthermore, the silicon carbide semiconductor device may be an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) with an SBD built therein. It can also be applied to MOSFETs and IGBTs having a superjunction structure with built-in SBDs.

Embodiment 5.
The present embodiment applies the silicon carbide semiconductor devices according to the first to fourth embodiments described above to a power converter. Although the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a fifth embodiment.

FIG. 18 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

The power conversion system shown in FIG. 18 is composed of a power supply 100, a power converter 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power converter 200 . The power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too. Also, the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

Power converter 200 is a three-phase inverter connected between power supply 100 and load 300 , converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300 . As shown in FIG. 30, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201. , and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 .
The drive circuit 202 turns off each normally-off switching element by setting the voltage of the gate electrode and the voltage of the source electrode to the same potential.

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 . Note that the load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for air conditioning equipment.

The details of the power converter 200 will be described below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 . Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel. A silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to any one of the first to third embodiments described above is applied to each switching element of main conversion circuit 201 . Six switching elements are connected in series every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .

The drive circuit 202 generates a drive signal for driving the switching element of the main converter circuit 201 and supplies it to the control electrode of the switching element of the main converter circuit 201 . Specifically, in accordance with a control signal from the control circuit 203, which will be described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When maintaining the switching element in the ON state, the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).

The control circuit 203 controls the switching elements of the main converter circuit 201 so that desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
In the power conversion device according to the present embodiment, since the silicon carbide semiconductor device according to the first to fourth embodiments is applied as the switching element of the main conversion circuit 201, low loss and high-speed switching reliability are improved. A conversion device can be implemented.

Although an example in which the present disclosure is applied to a two-level three-phase inverter has been described in the present embodiment, the present disclosure is not limited to this, and can be applied to various power converters. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it. In addition, the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.

In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.

10 Semiconductor substrate 20 Drift layer 30 Body region 31 First protection region 32 Second protection region 33 First connection region 34 Second connection region 35 Contact region 40 Source region 50 Gate insulating film 55 Interlayer insulating film, 60 Gate electrode, 70 Ohmic electrode, 71 Reaction layer, 80 Source electrode, 81 Schottky electrode, 82 Drain electrode, 91 Gate trench, 92 Schottky trench, 100 Power source, 200 Power conversion device, 201 Main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

a drift layer made of first conductivity type silicon carbide formed on a first main surface of a semiconductor substrate made of first conductivity type silicon carbide;
a body region made of silicon carbide of a second conductivity type formed on the drift layer;
a source region made of silicon carbide of a first conductivity type formed on at least part of the body region;
a gate trench penetrating through the source region and the body region and reaching the drift layer;
a gate electrode formed in the gate trench so as to face the body region with a gate insulating film interposed therebetween;
a Schottky trench formed to have a lower end in at least the drift layer;
a Schottky electrode mainly composed of Ti formed in the Schottky trench;
and a reaction layer formed between the Schottky electrode and the drift layer in contact with the side surface of the Schottky trench and made of TiSi in which the atomic composition ratio of Ti to Si is 0.5 or more. Silicon semiconductor device.
The silicon carbide semiconductor device according to claim 1, wherein the reaction layer has a thickness of 1 nm or more.
The silicon carbide semiconductor device according to claim 1 , wherein the reaction layer has an oxygen atomic composition concentration of 5% or less.
the semiconductor substrate is silicon carbide having a 4H polytype in which the first main surface is inclined by 1° or more in the <11-20> direction from the (0001) plane;
The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the Schottky trenches are formed in stripes along the <11-20> direction.
The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein an angle formed between a longitudinal side wall of said Schottky trench and said first main surface is in the range of 80 degrees or more and 90 degrees or less.
the Schottky trench is formed through the body region;
The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein an ohmic electrode made of NiSi is formed in a region where said Schottky trench contacts said body region.
forming a drift layer made of silicon carbide of the first conductivity type on the first main surface of a semiconductor substrate made of silicon carbide of the first conductivity type;
forming a body region made of second conductivity type silicon carbide on the drift layer;
forming a source region made of silicon carbide of the first conductivity type on at least part of the body region;
forming a gate trench through the source region and the body region to reach the drift layer;
forming a gate electrode in the gate trench so as to face the body region with a gate insulating film interposed therebetween;
forming a Schottky trench with a lower end in at least the drift layer;
depositing a Ti-based Schottky electrode in the Schottky trench;
and a step of increasing the temperature at a rate of 10° C./sec while depositing the Schottky electrode, and then performing a heat treatment at a temperature of 400° C. or more and 600° C. or less to form a TiSi reaction layer. A method for manufacturing a silicon carbide semiconductor device.
a main conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 6 and converting input electric power for output;
a drive circuit that turns off the silicon carbide semiconductor device by making the voltage of the gate electrode of the silicon carbide semiconductor device equal to the voltage of the source electrode, and outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device;
a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit;
A power converter with