JP2010068008A - Method of manufacturing silicon carbide schottky barrier diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing silicon carbide Schottky barrier diodes having uniform characteristics by reducing variations in their forward characteristics. <P>SOLUTION: The silicon carbide Schottky barrier diode is manufactured in the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on one principal surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on another principal surface of the silicon carbide substrate; (e) heat-treating the silicon carbide substrate at a prescribed temperature to form ohmic bonding between the first metal layer and the another principal surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a Ti layer on the epitaxial layer; (h) and heat-treating the silicon carbide substrate at 400-600°C to reduce variations in barrier height of a Schottky junction between the Ti layer and the epitaxial layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide Schottky barrier diode.

  In the manufacture of a silicon carbide Schottky barrier diode (hereinafter referred to as SiC-SBD), selection of a Schottky metal material and stabilization of its forward characteristics are important factors. Schottky metal materials are generally Ti, Ni, Mo, W, and the like. For example, when manufacturing a Ti Schottky diode using a Ni ohmic junction on the back surface, the following process characteristics and problems are involved.

  Since kV class high voltage SiC Schottky diodes usually have an electric field peak (electric field concentration) near the outer edge (edge) of the Schottky electrode, a p-type termination structure is required to alleviate electric field concentration. . This termination structure is generally formed by ion implantation of p-type impurities such as Al (aluminum) and B (boron) into the n-type epitaxial layer and activation annealing at a high temperature of about 1500 ° C. or higher.

  In order to form a Ti Schottky junction with good characteristics, it is desirable to form a surface Schottky junction as early as possible in the wafer process. However, the Ni ohmic junction on the back surface requires high-temperature annealing at about 1000 ° C., and the Ti Schottky junction cannot maintain a good condition at that temperature. It is common to form the bond later.

  A manufacturing method for simultaneously forming a front surface Schottky junction and a back surface ohmic junction is disclosed in Patent Document 1, for example. In addition, techniques related to the present invention are disclosed in Patent Documents 2, 3, and 4.

Japanese Patent No. 3890311 Japanese Patent No. 3884070 JP 2004-172400 A JP 2000-164528 A

  In the fabrication and evaluation of SiC-SBD, the reverse leakage current and reverse breakdown voltage characteristics among device characteristics are greatly affected by defects in wafers and epilayers and process defects. On the other hand, the forward characteristics, especially the barrier height φB and n value, are the pretreatment conditions at the time of Schottky junction formation, Schottky metal film formation conditions, Schottky metal patterning method, and baking heating conditions after applying the sealing material represented by polyimide. It is greatly influenced by. Even in the case of a Ti Schottky diode, it was necessary to make the above-described process so as not to affect the forward characteristics. However, the SiC-SBD manufactured by the conventional manufacturing method has a problem that the forward characteristics, in particular, the barrier height φB varies over about 1.05 to 1.25 eV, and the characteristics are not stable.

  Moreover, as in the manufacturing method described in Patent Document 1, it is ideal if the same kind of metal is used for the front surface Schottky material and the back surface ohmic material, and good bonding can be achieved by one annealing firing. However, since the process margin is actually very narrow, it is not suitable for a mass production process from the viewpoint of increasing the yield rate of the entire wafer and stably producing devices with good reproducibility.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to obtain a method for manufacturing a silicon carbide Schottky barrier diode having uniform characteristics by reducing variations in forward characteristics.

  The method for manufacturing a silicon carbide Schottky barrier diode according to the present invention includes: (a) a step of preparing a silicon carbide substrate; (b) a step of forming an epitaxial layer on one main surface of the silicon carbide substrate; A step of forming a protective film on the epitaxial layer, (d) a step of forming a first metal layer on the other main surface of the silicon carbide substrate after the step (c), and (e) the step (D) After the heat treatment of the silicon carbide substrate at a predetermined temperature, forming an ohmic junction between the first metal layer and the other main surface of the silicon carbide substrate; After the step (e), the step of removing the protective film, (g) the step of forming a Ti layer on the epitaxial layer after the step (f), and (h) after the step (g) The silicon carbide substrate is heat-treated at 400 ° C. or higher and 600 ° C. or lower, and the Ti layer and the epitaxial layer are heat-treated. And a step of reducing variations in barrier height of the Schottky junction between the catcher Le layer.

  According to the method for manufacturing a silicon carbide Schottky barrier diode of the present invention, a silicon carbide substrate is covered with a protective film until Schottky metal is formed, and after the Schottky metal is formed, sintering heating is performed at 400 ° C. to 600 ° C. By annealing, it is possible to reduce the forward characteristics, particularly the variation in the barrier height φB. This makes it possible to produce and provide a device chip with uniform forward characteristics.

It is sectional drawing which showed the manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which showed the conventional silicon carbide semiconductor device. It is the figure which showed the barrier height (phi) B characteristic of the silicon carbide semiconductor device in Embodiment 1 of this invention.

<Embodiment 1>
1 (a) to 1 (d) are cross-sectional views showing manufacturing steps of a silicon carbide semiconductor device (silicon carbide Schottky diode, hereinafter referred to as SiC-SBD) in the first embodiment of the present invention. This manufacturing process includes the following processes 1 to 4.

Step 1: First, with reference to FIG. 1A, the steps up to forming an ohmic junction will be described. First, an n-type silicon carbide substrate is prepared. In the present embodiment, description will be made using an n ⁺ substrate 1 made of (0001) silicon surface 4H—SiC. The resistivity of the n ⁺ substrate 1 is about 0.02 Ω · cm.

Next, a low-concentration n-type epitaxial layer 2 having an impurity concentration of about 5 × 10 ¹⁵ / cm ³ is formed on the surface of the n ⁺ substrate 1. Next, the surface of the n-type epitaxial layer 2 is sacrificial oxidized to form a protective film such as the SiO ₂ thermal oxide film 10 on the opposite side of the n ⁺ substrate 1. The thermal oxide film 10 formed on this surface functions as a process protective film. Further, as will be described later, by removing the thermal oxide film 10 immediately before the formation of the metal layer 5 (FIG. 1B), the surface of the n-type epitaxial layer 2 after the removal is chemically stable with good reproducibility. This makes it possible to form a good Schottky junction. Here, the thermal oxide film 10 is an SiO ₂ thermal oxide film having a thickness of 10 nm to 50 nm, for example.

  Next, a termination structure is formed in the n-type epitaxial layer 2. Electric field concentration is likely to occur at the end of the Schottky electrode, and the termination structure is formed in order to relax the electric field concentration and stably secure a breakdown voltage of kV or higher. For example, in this termination structure, Al ions are implanted to form a GR (Guard Ring) implantation layer 3 as an electric field concentration relaxation structure at the end of the Schottky electrode. Further, Al ions having a slightly lower concentration than that of the GR implantation layer 3 are continuously implanted to the outside, thereby forming a JTE (Junction Termination Extension) implantation layer 4 for the purpose of reducing the surface electric field.

Next, annealing (heat treatment) is performed in order to activate Al ions in the GR implanted layer 3 and the JTE implanted layer 4. For example, this annealing is performed for about 15 minutes at 1350 ° C. in a reduced pressure H ₂ & C ₃ H ₈ atmosphere using a furnace type SiC-CVD apparatus. By performing this annealing, it is possible for C ₃ H ₈ to suppress sublimation of carbon atoms from silicon carbide, and to suppress surface irregularities after annealing represented by a bunching step to less than 1 nm. By suppressing the surface unevenness to less than 1 nm, it is possible to avoid the problem of residual oxidation when the SiO ₂ thermal oxide film is removed.

This annealing may be performed in a normal pressure Ar atmosphere using an RTA type annealing furnace without using a high vacuum specification or a special gas such as H ₂ or C ₃ H ₈ .

  In the case of annealing in an atmospheric pressure Ar atmosphere using an RTA type annealing furnace, it is effective to mount a graphite cap (G-cap) during annealing as a technique for suppressing the occurrence of bunching steps. For example, when using a wafer structure with a graphite cap and a single wafer RTA furnace is annealed at a temperature range of at least 1500-1700 ° C. for 10 minutes, the p-type implanted layer has an activation rate of 50% or more and is terminated. It functions sufficiently as a structure and does not generate a bunching step of 1 nm or more.

In the case of no G-cap, a bunching step of about 20 nm occurs, and the uneven shape increases the leakage current. Furthermore, on the SiC surface where a bunching step of about 20 nm has occurred, surface orientations other than the (0001) silicon surface also appear. As is apparent from the fact that the SiO ₂ thermal oxide film 10 whose (000-1) carbon surface is about 10 times thicker than the (0001) silicon surface is formed by thermal oxidation, the SiO ₂ thermal oxide film 10 in the wafer surface is clear. Variation in the thickness of the material increases dramatically. This causes a residual defect in the thermal oxide film 10 even after the oxide film is removed by fluorine etching, and increases the leakage current.

  In SiC-SBD, Ti is used for the Schottky bonding material on the front (0001) silicon surface, and Ni is used for the ohmic bonding material on the back (000-1) carbon surface. The (0001) silicon surface is used as the Schottky junction formation surface when the high-quality n-type drift layer is epitaxially grown on the n-type 4H-SiC substrate. Is one of the main reasons why it is generally considered difficult. Further, since the (0001) silicon surface can control the thickness of the sacrificial oxide film to be relatively thin, the oxide film remaining problem can be avoided as a result.

  Here, in the SiC-SBD, since the junction location that most affects the device characteristics is the Ti / SiC interface, the Ti metal layer 5 that forms the Schottky junction on the front surface is formed first, and the ohmic junction on the back surface is formed later. It is desirable to form the Ni metal layer 6 that forms However, in order to form a good Ni ohmic junction, annealing of about 1000 ° C. is required, and the Ti Schottky junction is destroyed by this high temperature process. First, the method of forming the Ti Schottky junction later is used.

  Moreover, as in the invention described in Patent Document 1 shown in FIG. 2, it is ideal if the same kind of metal is used for the Schottky material on the front surface and the ohmic material on the back surface, and both can be bonded satisfactorily by one annealing firing. From the viewpoint of manufacturing a device with a very narrow process margin and stable and good reproducibility, it is not preferable.

  Next, a process of forming an ohmic junction on the back surface of the substrate 1 (surface opposite to the n-type epitaxial layer 2) will be described. A Ni metal layer 6 as a first metal layer is deposited on the back surface of the SiC substrate 1 and is subjected to heat treatment (annealing) to form an ohmic junction. Here, the conditions such as the flattening of the back SiC carbon surface, the formation of the ohmic Ni metal layer 6 and the ohmic annealing conditions are such that Ni silicide is applied to the interface between SiC and Ni so that excess carbon does not adversely affect segregation. Set to form well.

  For example, a sacrificial oxide film 10 is formed as a process protective film on the surface to be kept clean when annealing is performed at about 1000 ° C. after forming a Ni film with a thickness of 100 nm in order to form a backside Ni ohmic junction. This prevents the surface of the n-type epitaxial layer 2 of the SiC wafer forming the Ti Schottky junction from being contaminated with Ni on the back surface of the wafer or metal impurities generated from the annealing apparatus during back surface Ni annealing.

  In this way, when the formation of the back-side Ni ohmic junction is performed before the formation of the Ti Schottky junction, the surface of the Ti Schottky junction to be formed is protected by the thermal oxide film 10, whereby the characteristics of the Ti sinter 12 to be described later can It is possible to further increase the variation reducing effect.

  Step 2: Next, with reference to FIG. 1B, a process until a Schottky junction is formed on the surface will be described. On the surface of the n-type 4H-SiC substrate 1 on which the n-type drift layer (n-type epitaxial layer 2) is epitaxially grown on the (0001) silicon surface, a Ti film as a second metal layer is deposited to form the metal layer 5. The metal layer 5 is patterned, and heat treatment (Ti sintering 12) is performed at 400 ° C. or more and 600 ° C. or less to form a Schottky junction with desired characteristics. By using Ti as the Schottky bonding material, desired forward characteristics can be obtained, and a processing process such as wet etching described later can be facilitated.

  Here, in order to form a Ti Schottky junction with stable characteristics, it is necessary to carefully control the interface state. That is, in order to form the termination structure of the GR implanted layer 3 and the JTE implanted layer 4, it is important to control the heat treatment after the annealing step in which Al ions are implanted into the n-type epitaxial layer 2 and activated. .

  In the Ti / n-type SiC Schottky junction, by applying the Ti sinter 12, the barrier height φB is increased to about 1.25 eV and the variation is reduced. The timing of the Ti sinter 12 is good after the patterning of the metal layer 5. This is to prevent a transition layer such as a silicide layer from being formed at the Ti / n-type SiC interface by the Ti sinter 12 and causing a problem in patterning the Ti metal layer 5 by wet etching, for example. The Ti sinter 12 has a maximum temperature holding time of 10 seconds to 30 minutes and a temperature increase rate of 5 ° C./second to 25 ° C./second. Under this Ti sintering 12 condition, wafer breakage due to rapid thermal distortion can be eliminated and heating can be performed well in a short time.

  Step 3: Next, with reference to FIG. 1C, the process until the surface electrode 7 is formed on the metal layer 5 will be described. After patterning the metal layer 5 and performing Ti sintering 12, Al having a thickness of 3 μm, for example, is deposited. The resist opening is patterned by wet etching such as hot phosphoric acid by photolithography.

  On the other hand, more preferably, the Ti sinter 12 is formed after an Al electrode pad (surface electrode 7) of about 3 μm, for example, is formed on the Ti metal layer 5. By forming the electrode pad and then patterning and Ti sintering 12, it is effective to improve the adhesion of the Al / Ti interface. Moreover, it becomes possible to perform wet etching patterning simultaneously on the Schottky metal (Ti metal layer 5) and the electrode pad (surface electrode 7), and the photolithography process can be reduced once.

  Step 4: Finally, with reference to FIG. 1 (d), the process up to the formation of the polyimide 8 and the formation of the back electrode 9 will be described. After the surface is Al metallized, a surface sealing material such as polyimide 8 is applied and fired on the n-type epitaxial layer 2 and the surface electrode 7. At this time, the curing temperature is set to 50 ° C. or more lower than the Ti sinter 12 heat treatment temperature at the time of forming the Schottky junction. This is for the purpose of preventing the interface state of the stable Schottky junction by the Ti sinter 12 from becoming unstable again.

Next, after polyimide curing, a back electrode 9 is formed on the back surface of the n ⁺ substrate 1 at the end of the wafer process. For example, by performing Ni & Au metallization, solder wettability can be improved when die-bonding the back surface to the chip. Here, the back electrode 9 is formed after polyimide curing. If, after the backside Ni & Au metallization, polyimide 8 formation & cure is performed at the end, the lower layer Ni diffuses to the Au surface in the polyimide cure process at 350 ° C, and as a result of forming Ni oxide, solder wettability The problem that it deteriorates extremely arises.

  FIG. 3 is a diagram in which the characteristic of the barrier height φB of the SiC-SBD prepared by the above-described manufacturing method is measured. As shown in FIG. 3, the barrier height φB ranges from about 1.24 to 1.27 eV. Since the barrier height φB of the conventional SiC-SBD is 1.05 to 1.25 eV, it can be seen that the variation can be reduced as compared with this.

  As described above, according to the SiC-SBD manufacturing method of the present embodiment, the silicon carbide substrate is covered with the protective film until the Schottky metal is formed, and after the Schottky metal is formed, the temperature is 400 ° C. or higher and 600 ° C. or lower. In this case, the Ti sinter 12 is annealed to reduce the forward characteristics, particularly the variation in the barrier height φB. This makes it possible to produce and provide a device chip with uniform forward characteristics.

<Embodiment 2>
The SiC-SBD manufacturing method in the present embodiment is characterized in that sacrificial oxidation is performed a plurality of times. Hereinafter, a method for manufacturing SiC-SBD in the present embodiment will be described. The thermal oxide film 10 formed to protect the surface of the n-type epitaxial layer 2 is removed after Al ion implantation for forming a termination structure and before activation annealing. This is because the thermal oxide film 10 disappears irregularly at an activation annealing temperature of about 1400 ° C. or higher, so that the entire surface is removed in advance to prevent the remaining thermal oxide film 10 from being defective. From around the viewpoint of suppressing surface unevenness occurs typified mentioned bunching steps in the first embodiment, in the temperature conditions exceeding the heat-resistant limit of the SiO ₂ thermal oxide film 10, entirely removed the SiO ₂ thermal oxide film 10 This is effective for reducing variations in the forward characteristics of the device chip.

  Since the outermost surface of the n-type epitaxial layer 2 after activation annealing for forming the termination structure is generally considered to be an unstable surface rich in carbon, it may be removed by about 0.1 μm by dry etching such as RIE. . Thereafter, for the purpose of further removing surface damage due to dry etching, a second sacrificial oxidation is performed, and the thermal oxide film 10 is formed again. Here, repeating the sacrificial oxidation twice is also effective for reducing process defects.

  As described above, performing sacrificial oxidation at least twice depending on the detailed process status is effective in reducing process defects caused by particles or inactivating crystal defects.

<Embodiment 3>
In the first embodiment, the case where Ti is used as the Schottky electrode has been described. However, other metals, for example, metals such as Ni, Mo, and W may be used. Depending on the metal material, the forward barrier height φB obtained as a diode characteristic naturally varies depending on the work function and the binning effect with SiC.

<Embodiment 4>
In the first embodiment, the case where the SiO ₂ thermal oxide film 10 is used as the protective film has been described. However, another CVD oxide film, or a SiN nitride film, a SiON oxynitride film, or the like may be used.

1 n ⁺ substrate, 2 n type epitaxial layer, 3 GR (Guard Ring) injection layer, 4 JTE (Junction Termination Extension) injection layer, 5 metal layer, 6 metal layer, 7 surface electrode, 8 polyimide, 9 back electrode, 10 Thermal oxide film, 11 Ohmic annealing, 12 Ti sinter.

Claims (6)

(A) preparing a silicon carbide substrate;
(B) forming an epitaxial layer on one main surface of the silicon carbide substrate;
(C) forming a protective film on the epitaxial layer;
(D) after the step (c), forming a first metal layer on the other main surface of the silicon carbide substrate;
(E) after the step (d), heat-treating the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and another main surface of the silicon carbide substrate; ,
(F) After the step (e), removing the protective film;
(G) after the step (f), forming a Ti layer on the epitaxial layer;
(H) After the step (g), the silicon carbide substrate is heat-treated at 400 ° C. or more and 600 ° C. or less to reduce variations in the Schottky junction barrier height between the Ti layer and the epitaxial layer; A method for manufacturing a silicon carbide Schottky barrier diode comprising:   Between the steps (c) and (d), (i) a step of implanting impurity ions into the epitaxial layer, and (j) activating the impurity ions implanted into the silicon carbide substrate after the step (i). The manufacturing method of the silicon carbide Schottky barrier diode of Claim 1 provided with the process of performing the annealing to convert.   3. The method of manufacturing a silicon carbide Schottky barrier diode according to claim 2, wherein the step (j) is performed by covering the silicon carbide substrate on which the epitaxial layer is formed with a graphite cap.   3. The method of manufacturing a silicon carbide Schottky barrier diode according to claim 2, wherein the step (j) is performed such that surface irregularities of the epitaxial layer into which the impurity ions are implanted are less than 1 nm. In the step (j), annealing is performed after removing the protective film,
The method for manufacturing a silicon carbide Schottky barrier diode according to any one of claims 2 to 4, further comprising a step of forming a protective film again on the epitaxial layer between the steps (j) and (d).   The method for manufacturing a silicon carbide Schottky barrier diode according to claim 5, further comprising a step of removing a surface of the epitaxial layer by dry etching between the step (j) and the step of forming the protective film again.

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