JP5207939B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Method for manufacturing silicon carbide semiconductor device Download PDF

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JP5207939B2
JP5207939B2 JP2008313043A JP2008313043A JP5207939B2 JP 5207939 B2 JP5207939 B2 JP 5207939B2 JP 2008313043 A JP2008313043 A JP 2008313043A JP 2008313043 A JP2008313043 A JP 2008313043A JP 5207939 B2 JP5207939 B2 JP 5207939B2
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silicon carbide
oxide film
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研一 黒田
寛 渡邊
吉徳 松野
健一 大塚
直毅 油谷
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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Description

本発明は、炭化珪素半導体装置の製造方法に関し、特に炭化珪素ショットキダイオードの製造に好適な炭化珪素半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device suitable for manufacturing a silicon carbide Schottky diode.

ｋＶ級高耐圧の炭化珪素（以下、ＳｉＣと呼ぶ）ショットキダイオードは、ＳｉＣからなるｎ型のエピタキシャル層上にショットキ電極が形成されて構成されている。この構造では、エピタキシャル層とショットキ電極との接合面の周縁に電界が集中し易くなるので、その接合面（ショットキ接合面）の周縁の表層に電界集中緩和のためのｐ型終端構造を形成する必要がある。   A kV class high breakdown voltage silicon carbide (hereinafter referred to as SiC) Schottky diode is configured by forming a Schottky electrode on an n-type epitaxial layer made of SiC. In this structure, the electric field tends to concentrate on the periphery of the junction surface between the epitaxial layer and the Schottky electrode, so that a p-type termination structure for reducing the electric field concentration is formed on the surface layer of the periphery of the junction surface (Schottky junction surface). There is a need.

ｐ型終端構造の形成には、一般にＡｌ（アルミ），Ｂ（ボロン）等のｐ型不純物をｎ型エピタキシャル層にイオン注入し、１５００℃程度以上の高温熱処理で活性化アニールする方法が用いられる。良好な特性のショットキ接合を形成するためには、この高温熱処理によるＳｉＣ表面の変質層を除去する必要がある。この変質層を除去する技術としては、例えば特許文献１〜３に記載された技術が知られている。   In order to form the p-type termination structure, a method is generally used in which p-type impurities such as Al (aluminum) and B (boron) are ion-implanted into the n-type epitaxial layer, and activation annealing is performed by high-temperature heat treatment at about 1500 ° C. or higher. . In order to form a Schottky junction with good characteristics, it is necessary to remove the altered layer on the SiC surface by this high-temperature heat treatment. For example, techniques described in Patent Documents 1 to 3 are known as techniques for removing the deteriorated layer.

特開２００８−５３４１８号公報JP 2008-53418 A 特開２００１−３５８３８号公報JP 2001-35838 A 特開２００４−３６３３２６号公報JP 2004-363326 A

特許文献１では、上記の変質層を除去する方法として、活性化アニール後にＳｉＣ表層に４０ｎｍ以上の犠牲酸化膜を形成し、その犠牲酸化膜と共に変質層を除去する方法を提唱している。   In Patent Document 1, as a method for removing the above-described deteriorated layer, a method is proposed in which a sacrificial oxide film having a thickness of 40 nm or more is formed on the SiC surface layer after activation annealing, and the deteriorated layer is removed together with the sacrificial oxide film.

活性化アニールによる変質層の厚さは１００ｎｍ以上であり、特許文献１の方法でその変質層を除去するには、変質層の厚さに合わせて犠牲酸化膜を厚くする必要があり、余剰残留Ｃの挙動等のＳｉＣ特有の問題点や、犠牲酸化膜を形成するのに時間が掛かるという問題点が発生する。そればかりか、犠牲酸化膜はＳｉＣ表層全面に形成されるため、ｐ型イオン注入層の表面も１００ｎｍ以上除去されることになる。   The thickness of the altered layer by activation annealing is 100 nm or more, and in order to remove the altered layer by the method of Patent Document 1, it is necessary to increase the sacrificial oxide film in accordance with the thickness of the altered layer. There are problems peculiar to SiC, such as the behavior of C, and that it takes time to form a sacrificial oxide film. In addition, since the sacrificial oxide film is formed on the entire surface of the SiC surface, the surface of the p-type ion implantation layer is also removed by 100 nm or more.

その結果、その除去量を見込んであらかじめｐ型イオン注入量を増加するか、より深く注入する必要があり、注入に要する時間とエネルギーが増大するという問題点がある。   As a result, it is necessary to increase the p-type ion implantation amount in advance in anticipation of the removal amount or to perform deeper implantation, which increases the time and energy required for implantation.

特許文献２では、プラズマによる表面エッチングあるいは高温溶融塩中における表面エッチングにより変質層を除去する方法を提案している。しかしこの方法でも、特許文献１の場合と同様にｐ型イオン注入層の表面も１００ｎｍ以上除去され、注入層の厚みが薄くなるという問題点がある。   Patent Document 2 proposes a method of removing the altered layer by surface etching with plasma or surface etching in a high-temperature molten salt. However, this method also has a problem that the surface of the p-type ion implantation layer is removed by 100 nm or more as in the case of Patent Document 1, and the thickness of the implantation layer is reduced.

特許文献３では、水素エッチングで変質層を除去する方法を提案しているが、水素エッチングは危険で高価な高温プロセス装置が必要となるという問題点があるばかりでなく、特許文献１の場合と同様にｐ型イオン注入層の表面も１００ｎｍ以上除去され、注入層の膜厚が薄くなるという問題点がある。   Patent Document 3 proposes a method of removing a deteriorated layer by hydrogen etching. However, hydrogen etching is not only dangerous and requires an expensive high-temperature process apparatus. Similarly, the surface of the p-type ion implantation layer is also removed by 100 nm or more, and there is a problem that the thickness of the implantation layer becomes thin.

以上のように、活性化アニール後の変質層を除去するにあたって、イオン注入層の表面も同時に除去されるが、その除去量が少ない方法が望ましい。   As described above, when removing the altered layer after the activation annealing, the surface of the ion implantation layer is also removed at the same time, but a method with a small removal amount is desirable.

本発明は、上述のような問題点を解決するためになされたものであり、イオンを注入された領域であるイオン注入層の厚みの除去量を低減できる炭化珪素半導体装置の製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and provides a method for manufacturing a silicon carbide semiconductor device capable of reducing the amount of removal of the thickness of an ion-implanted layer that is an ion-implanted region. For the purpose.

この発明の第１の態様にかかる炭化珪素半導体装置の製造方法は、（ａ）炭化珪素層に選択的にイオン注入した後、前記炭化珪素層を活性化アニールする工程と、（ｂ）前記イオン注入された領域上にフォトレジストを形成する工程と、（ｃ）前記フォトレジストをマスクとして、前記活性化アニール後に前記炭化珪素層の表層を１００ｎｍ以上ドライエッチングにより除去する工程と、（ｄ）前記フォトレジストを除去する工程と、（ｅ）前記工程（ｄ）後、前記炭化珪素層の表層全体に犠牲酸化膜を形成する工程と、（ｆ）前記犠牲酸化膜をウエットエッチングにより除去する工程とを備える。 A method for manufacturing a silicon carbide semiconductor device according to a first aspect of the present invention includes: (a) a step of selectively annealing ions in a silicon carbide layer and then activating annealing the silicon carbide layer; and (b) the ions. forming a photoresist implanted region, removing by (c) said photoresist as a mask, 100 nm or more dry etching of the surface layer of the silicon carbide layer after the activation annealing, (d) the Removing the photoresist; (e) after the step (d), forming a sacrificial oxide film over the entire surface of the silicon carbide layer; and (f) removing the sacrificial oxide film by wet etching. Is provided.

この発明の第１の態様によれば、炭化珪素半導体装置の製造方法において、（ａ）炭化珪素層に選択的にイオン注入した後、前記炭化珪素層を活性化アニールする工程と、（ｂ）前記イオン注入された領域上にフォトレジストを形成する工程と、（ｃ）前記フォトレジストをマスクとして、前記活性化アニール後に前記炭化珪素層の表層を１００ｎｍ以上ドライエッチングにより除去する工程と、（ｄ）前記フォトレジストを除去する工程と、（ｅ）前記工程（ｄ）後、前記炭化珪素層の表層全体に犠牲酸化膜を形成する工程と、（ｆ）前記犠牲酸化膜をウエットエッチングにより除去する工程とを備えることにより、フォトレジストをマスクとして、炭化珪素層の表層をドライエッチングした後、犠牲酸化膜をウエットエッチングするので、ウエットエッチングする際のイオン注入した領域の厚みの除去量を低減することが可能となる。 According to a first aspect of the present invention, in the method for manufacturing a silicon carbide semiconductor device, (a) a step of selectively annealing the silicon carbide layer and then activating annealing the silicon carbide layer; wherein the step of forming a photoresist on the ion implanted region, a step of removing by (c) said photoresist as a mask, 100 nm or more dry etching of the surface layer of the silicon carbide layer after the activation annealing, (d ) Removing the photoresist; (e) after the step (d), forming a sacrificial oxide film over the entire surface of the silicon carbide layer; and (f) removing the sacrificial oxide film by wet etching. And the step of dry etching the surface layer of the silicon carbide layer using the photoresist as a mask, and then wet etching the sacrificial oxide film. It is possible to reduce the removal of the ion implanted region of the thickness at the time of wet etching.

＜Ａ．実施の形態１＞
以下、本実施の形態１に係る炭化珪素半導体装置の製造方法の一例として、炭化珪素ショットキダイオード（ＳｉＣ−ＳＢＤ）の製造工程を、図１〜図７に基づき説明する。 <A. Embodiment 1>
Hereinafter, as an example of a method for manufacturing a silicon carbide semiconductor device according to the first embodiment, a manufacturing process of a silicon carbide Schottky diode (SiC-SBD) will be described with reference to FIGS.

＜Ａ−１．ｐ型終端構造の形成方法＞
まず図１の様に、（０００１）シリコン面を有する４Ｈ−ＳｉＣからなる例えば高濃度のｎ型の炭化珪素（ＳｉＣ）基板１を準備する。炭化珪素基板１の抵抗率は、例えば０．０２Ω・ｃｍ程度である。 <A-1. Method for forming p-type termination structure>
First, as shown in FIG. 1, a high-concentration n-type silicon carbide (SiC) substrate 1 made of 4H—SiC having a (0001) silicon surface is prepared. The resistivity of silicon carbide substrate 1 is, for example, about 0.02 Ω · cm.

次に炭化珪素基板１の（０００１）シリコン面において、炭化珪素層である不純物濃度が５×１０15／ｃｍ3程度の低濃度ｎ型のエピタキシャル層（以後、エピ層と呼ぶ）２を成長させる。尚、エピ層２の形成後、そのエピ層２の表面に、加熱処理により熱酸化膜（ＳｉＯ2熱酸化膜）を形成しても良い。その場合は、その熱酸化膜がプロセス保護膜として機能する。 Next, on the (0001) silicon surface of the silicon carbide substrate 1, a low-concentration n-type epitaxial layer (hereinafter referred to as an epi layer) 2 having an impurity concentration of about 5 × 10 15 / cm 3 as a silicon carbide layer is grown. . Note that after the formation of the epi layer 2, a thermal oxide film (SiO 2 thermal oxide film) may be formed on the surface of the epi layer 2 by heat treatment. In that case, the thermal oxide film functions as a process protective film.

次にｋＶ超級の耐圧を確保するｐ型終端構造を作成するために、エピ層２の表層に、ｐ型ドーパントである例えばＡｌ（アルミニウム）イオンを注入して、イオン注入された領域であるｐ型イオン注入層３を０．８μｍ程度の深さで選択的に形成する。この形成には、写真製版によりフォトレジストで注入パターンを形成して行えば良い。   Next, in order to create a p-type termination structure that secures a breakdown voltage exceeding kV, for example, Al (aluminum) ions, which are p-type dopants, are implanted into the surface layer of the epi layer 2, and p is a region where ions are implanted. The type ion implantation layer 3 is selectively formed at a depth of about 0.8 μm. This formation may be performed by forming an implantation pattern with a photoresist by photolithography.

尚ここでは、ｐ型イオン注入層３は、ｐ型終端構造となる環状のＧＲ（Ｇｕａｒｄ Ｒｉｎｇ）と、そのＧＲの外側に連続して形成され、表面電界を低減するためのＪＴＥ（Ｊｕｎｃｔｉｏｎ Ｔｅｒｍｉｎａｔｉｏｎ Ｅｘｔｅｎｓｉｏｎ）とから構成される。ＪＴＥのＡｌイオン濃度は、ＧＲのそれよりも若干薄く設定されている。   Here, the p-type ion implantation layer 3 is formed continuously from an annular GR (Guard Ring) serving as a p-type termination structure and the outside of the GR, and JTE (Junction Termination Extension) for reducing the surface electric field. ). The Al ion concentration of JTE is set slightly lower than that of GR.

ｐ型終端構造として完成させるためには、ｐ型イオン注入層３を活性化する必要がある。そのため、例えばＲＴＡ（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ａｎｎｅａｌ）タイプのアニール炉を用いて、エピ層２全体を、常圧Ａｒ（アルゴン）雰囲気で１６００℃、１０分程度、高温熱処理（活性化アニール）する。   In order to complete the p-type termination structure, it is necessary to activate the p-type ion implantation layer 3. Therefore, for example, using an RTA (Rapid Thermal Anneal) type annealing furnace, the entire epi layer 2 is subjected to high-temperature heat treatment (activation annealing) at 1600 ° C. for about 10 minutes in an atmospheric pressure Ar (argon) atmosphere.

そして、活性化アニールされたエピ層２の表層には、活性化アニールによる変質層（活性化アニール後最表面変質層）４が発生する。変質層４の厚みは、１００〜２００ｎｍ程度であると考えられる。良好なショットキ接合を形成するには、この変質層４を除去する必要がある。   Then, in the surface layer of the epi layer 2 that has been subjected to the activation annealing, a modified layer (an outermost surface modified layer after the activation annealing) 4 is generated by the activation annealing. The thickness of the altered layer 4 is considered to be about 100 to 200 nm. In order to form a good Schottky junction, it is necessary to remove the altered layer 4.

＜Ａ−２．変質層の除去方法＞
次にこの変質層４を除去する方法を説明する。以下では、説明の便宜上、変質層４の厚さが１５０ｎｍの場合を想定する。 <A-2. Removal method of altered layer>
Next, a method for removing the deteriorated layer 4 will be described. In the following, for convenience of explanation, it is assumed that the altered layer 4 has a thickness of 150 nm.

まず図２の様に、ｐ型イオン注入層３上に写真製版によりフォトレジスト５でパターンを形成しマスクすることで、ｐ型イオン注入層を保護する。   First, as shown in FIG. 2, the p-type ion implantation layer 3 is protected by forming a pattern with a photoresist 5 on the p-type ion implantation layer 3 by photolithography and masking.

次に図３の様に、変質層４が生じたエピ層２の表層を、ドライエッチング（ここではＲＩＥ（Ｒｅａｃｔｉｖｅ ｉｏｎ ｅｔｉｎｇ））により、例えば約１５０ｎｍ程度の厚さを除去し変質層４を除去する。この時のエッチング条件は、例えば、ＳＦ6ガス流量３０ｓｃｃｍ、処置室圧力０．５Ｐａ、エッチング時間２０秒、エッチング速度７．５ｎｍ／秒程度とする。なお、ｐ型イオン注入層３はフォトレジスト５で保護されているのでエッチングされることはない。 Next, as shown in FIG. 3, the surface layer of the epi layer 2 where the altered layer 4 is generated is removed by dry etching (here, RIE (Reactive ion etching)), for example, to a thickness of about 150 nm to remove the altered layer 4. To do. The etching conditions at this time are, for example, an SF 6 gas flow rate of 30 sccm, a treatment chamber pressure of 0.5 Pa, an etching time of 20 seconds, and an etching rate of about 7.5 nm / second. The p-type ion implantation layer 3 is not etched because it is protected by the photoresist 5.

表層６ａを除去後のエピ層２の新たな表面には、このドライエッチングにより、例えば約２０ｎｍ程度未満の厚さの新たな変質層６ｂが発生する。   On the new surface of the epi layer 2 after removing the surface layer 6a, a new altered layer 6b having a thickness of, for example, less than about 20 nm is generated by this dry etching.

次にこの新たな変質層６ｂを除去する。尚、変質層４がドライエッチングによって完全に除去されず、その下層部分が残っていたとしても、その部分は新たな変質層６ｂに含まれた状態になっているので、新たな変質層６ｂを除去すれば、変質層４の残りの下層部分も除去される。   Next, the new altered layer 6b is removed. Even if the deteriorated layer 4 is not completely removed by dry etching and the lower layer portion remains, the portion is included in the new deteriorated layer 6b. If removed, the remaining lower layer portion of the altered layer 4 is also removed.

変質層６ｂの除去について図４の様に、プラズマ・アッシング装置またはアセトン溶液でフォトレジスト５を除去し、表面を硫酸で洗浄する。   Regarding the removal of the altered layer 6b, as shown in FIG. 4, the photoresist 5 is removed with a plasma ashing apparatus or an acetone solution, and the surface is washed with sulfuric acid.

次に、図５の様に、エピ層２の新たな表面の表層を犠牲酸化して、その表層に厚さ２０ｎｍ程度の犠牲酸化膜（ＳｉＯ2酸化膜）７を形成する。犠牲酸化膜７はエピ層２の表面の全面に形成されるので、ｐ型イオン注入層３の表面にも形成される。この時の犠牲酸化の条件は、乾式酸化で、１１５０℃で、酸化時間２時間とする。この犠牲酸化により、エピ層２の表層には、新たな変質層６ｂを取り込む様にして犠牲酸化膜７が形成される。 Next, as shown in FIG. 5, the surface layer of the new surface of the epi layer 2 is sacrificial oxidized, and a sacrificial oxide film (SiO 2 oxide film) 7 having a thickness of about 20 nm is formed on the surface layer. Since the sacrificial oxide film 7 is formed on the entire surface of the epi layer 2, it is also formed on the surface of the p-type ion implantation layer 3. The conditions for the sacrificial oxidation at this time are dry oxidation, 1150 ° C., and oxidation time of 2 hours. By this sacrificial oxidation, a sacrificial oxide film 7 is formed on the surface layer of the epi layer 2 so as to incorporate a new altered layer 6b.

次に図６の様に、この犠牲酸化膜７を例えば１０倍希釈のフッ酸中で例えば５分間ウエットエッチングして除去することで、その犠牲酸化膜７と共に新たな変質層６ｂを除去する。ただしこの時、ｐ型イオン注入層３の表面もまた除去される。   Next, as shown in FIG. 6, the sacrificial oxide film 7 is removed by wet etching, for example, in a 10-fold diluted hydrofluoric acid for 5 minutes, for example, thereby removing the new altered layer 6b together with the sacrificial oxide film 7. However, at this time, the surface of the p-type ion implantation layer 3 is also removed.

この様に、ドライエッチングによって変質層４を除去し、その後ドライエッチングによって新たに発生した変質層６ｂを、犠牲酸化膜７の形成およびウエットエッチングによって除去することにより、エピ層２の表面は変質層の無い状態にされる。   In this way, the altered layer 4 is removed by dry etching, and then the altered layer 6b newly generated by dry etching is removed by formation of the sacrificial oxide film 7 and wet etching, whereby the surface of the epi layer 2 is altered. There is no state.

なお、図１の工程においてイオン注入層３に活性化アニールにより形成される図示しないダメージ層（変質層）は、図５から図６の工程において完全に除去されないかもしれないが、その除去が結果的に少なくてもよいのは、イオン注入層３が低抵抗なので、ダメージが部分的に残存していても実質的に問題ないからである。   Note that a damage layer (modified layer) (not shown) formed in the ion implantation layer 3 by activation annealing in the step of FIG. 1 may not be completely removed in the steps of FIGS. 5 to 6, but the removal results. The reason why it may be reduced is that the ion-implanted layer 3 has a low resistance, so that even if some damage remains, there is substantially no problem.

＜Ａ−３．電極等の形成方法＞
次に図７の様に、炭化珪素（ＳｉＣ）基板１の裏面の全面に、例えばＮｉシリサイドによるオーミック電極８を形成すると共に、変質層４の除去されたエピ層２の表面に、例えばＴｉメタルによるショットキ電極９を選択的に形成する。 <A-3. Method for forming electrodes, etc.>
Next, as shown in FIG. 7, an ohmic electrode 8 made of, for example, Ni silicide is formed on the entire back surface of the silicon carbide (SiC) substrate 1, and, for example, Ti metal is formed on the surface of the epi layer 2 from which the altered layer 4 has been removed. The Schottky electrode 9 is selectively formed.

尚、オーミック電極８の形成時のプロセス温度が、ショットキ接合（ショットキ電極９とエピ層２との接合部分）に損傷を与える１０００℃程度になる場合は、オーミック電極８をショットキ電極９よりも先に形成する必要がある。この場合は、犠牲酸化膜７の除去は、オーミック電極８の形成後が望ましい。   If the process temperature during the formation of the ohmic electrode 8 is about 1000 ° C. that damages the Schottky junction (the junction between the Schottky electrode 9 and the epi layer 2), the ohmic electrode 8 is placed before the Schottky electrode 9. Need to be formed. In this case, the sacrificial oxide film 7 is preferably removed after the ohmic electrode 8 is formed.

そして更に図示を省略するが、エピ層２の表面にＡｌ等の金属によりワイヤボンディング用の金属膜を形成し、その金属膜上にワイヤボンディングのための開口部を有する様にポリイミド等の樹脂層を形成する。そしてエピ層２の裏面には、Ｎｉ，Ａｕ等の金属によりダイボンド用の金属膜を形成する。この様にして炭化珪素半導体装置を製造する。   Further, although not shown in the drawing, a metal film for wire bonding is formed on the surface of the epi layer 2 with a metal such as Al, and a resin layer such as polyimide so as to have an opening for wire bonding on the metal film. Form. On the back surface of the epi layer 2, a metal film for die bonding is formed from a metal such as Ni or Au. In this way, a silicon carbide semiconductor device is manufactured.

なお、本実施の形態１においては、ｐ型終端構造の形成に関して記載したが、この発明は導電型が限定されるものではない。   In the first embodiment, the formation of the p-type termination structure has been described. However, the present invention is not limited to the conductivity type.

＜Ａ−４．効果＞
この発明にかかる実施の形態１によれば、炭化珪素半導体装置の製造方法において、（ａ）エピタキシャル層（炭化珪素層）２に選択的にイオン注入した後、エピ層２を活性化アニールする工程と、（ｂ）前記イオン注入された領域上であるｐ型イオン注入層３上にフォトレジスト５を形成する工程と、（ｃ）前記フォトレジスト５をマスクとして、前記エピ層２の表層をドライエッチングする工程と、（ｄ）前記フォトレジスト５を除去する工程と、（ｅ）前記工程（ｄ）後、前記エピ層２の表層全体に犠牲酸化膜７を形成する工程と、（ｆ）前記犠牲酸化膜７をウエットエッチングにより除去する工程とを備えることにより、ｐ型イオン注入層３上に写真製版によりフォトレジスト５でパターンを形成し、ｐ型イオン注入層３を保護しているので、活性化アニールにより変質したエピ層（炭化珪素層）２の表層の変質層４をドライエッチングにより除去したとき、ｐ型イオン注入層３の表面はエッチングされず、ｐ型イオン注入層３の厚みの減少は発生しないという効果がある。 <A-4. Effect>
According to the first embodiment of the present invention, in the method for manufacturing a silicon carbide semiconductor device, (a) a step of selectively annealing the epitaxial layer (silicon carbide layer) 2 and then activating annealing the epi layer 2 (B) a step of forming a photoresist 5 on the p-type ion implantation layer 3 which is on the ion-implanted region; and (c) a surface layer of the epi layer 2 is dried using the photoresist 5 as a mask. An etching step; (d) a step of removing the photoresist 5; (e) a step of forming a sacrificial oxide film 7 over the entire surface of the epilayer 2 after the step (d); And a step of removing the sacrificial oxide film 7 by wet etching, thereby forming a pattern on the p-type ion implantation layer 3 by photolithography and protecting the p-type ion implantation layer 3. Therefore, when the altered layer 4 on the surface layer of the epi layer (silicon carbide layer) 2 altered by the activation annealing is removed by dry etching, the surface of the p-type ion implanted layer 3 is not etched, and the p-type ion implanted layer 3 There is an effect that the thickness of the film does not decrease.

ただしドライエッチングによって発生した表面の新たな変質層６ｂを犠牲酸化してウエットエッチングで除去する時、ｐ型イオン注入層３の表面も除去される。この時の犠牲酸化膜７の厚さは２０ｎｍ程度であり、ｐ型イオン注入層３の表面も除去量も２０ｎｍ程度となる。ｐ型イオン注入層３の厚みは０．８μｍであり、したがってその減少割合は３％以下となるので、実質的な厚みは変わらない。したがってあらかじめｐ型イオン注入層３の厚みの減少を見込んでｐ型イオン注入量を増加したり深く注入したりする必要がなく、注入に要する時間とエネルギーが増大するという問題点を回避し、エッチング量に対する制約も小さくすることができる。   However, when the new altered layer 6b on the surface generated by the dry etching is sacrificed and removed by wet etching, the surface of the p-type ion implantation layer 3 is also removed. At this time, the thickness of the sacrificial oxide film 7 is about 20 nm, and the surface of the p-type ion implantation layer 3 and the removal amount are about 20 nm. The thickness of the p-type ion implantation layer 3 is 0.8 μm, and therefore the reduction rate is 3% or less, so that the substantial thickness is not changed. Therefore, it is not necessary to increase or deeply implant the p-type ion implantation in anticipation of a decrease in the thickness of the p-type ion implantation layer 3 in advance, avoiding the problem of increasing the time and energy required for implantation, and etching. Limits on quantity can also be reduced.

＜Ｂ．実施の形態２＞
＜Ｂ−１．変質層の除去方法＞
実施の形態１では図５において、ドライエッチングによって新たに発生した表面変質層６ｂを除去するために犠牲酸化膜７を形成し除去した。この新たな表面変質層６ｂを除去するための方法は実施の形態１に示す方法に限らない。 <B. Second Embodiment>
<B-1. Removal method of altered layer>
In Embodiment 1, the sacrificial oxide film 7 is formed and removed in FIG. 5 in order to remove the surface alteration layer 6b newly generated by dry etching. The method for removing the new surface-affected layer 6b is not limited to the method shown in the first embodiment.

図１〜図４のような工程を経てフォトレジスト５を除去した後、図８の様にエピ層２の表面全体を研磨して新たな表面変質層６ｂを除去してもよい。   After removing the photoresist 5 through the steps as shown in FIGS. 1 to 4, the entire surface of the epi layer 2 may be polished as shown in FIG. 8 to remove the new surface-modified layer 6b.

なお、図１〜図４における工程については実施の形態１に記載するものと同様であるので、説明は省略する。   The steps in FIGS. 1 to 4 are the same as those described in the first embodiment, and a description thereof will be omitted.

＜Ｂ−２．効果＞
この発明にかかる本実施の形態２によれば、炭化珪素半導体装置の製造方法において、（ａ）エピタキシャル層（炭化珪素層）２に選択的にイオン注入した後、エピ層２を活性化アニールする工程と、（ｂ）前記イオン注入された領域上であるｐ型イオン注入層３上にフォトレジスト５を形成する工程と、（ｃ）前記フォトレジスト５をマスクとして、前記エピ層２の表層をドライエッチングする工程と、（ｄ）前記フォトレジスト５を除去する工程と、（ｅ）前記工程（ｄ）の後、前記エピ層２の表層全体を研磨する工程とを備えることにより、実施の形態１と同様に、ｐ型イオン注入層３上に写真製版によりフォトレジスト５でパターンを形成し、ｐ型イオン注入層３を保護しているので、活性化アニールにより変質したエピ層（炭化珪素層）２の表層の変質層４をドライエッチングにより除去したとき、ｐ型イオン注入層３の表面はエッチングされず、さらに本実施の形態２においては、犠牲酸化膜７を形成する替わりに研磨するが、その際に、ｐ型イオン注入層３の厚みの減少は小さく、実質的には実施の形態１と同様に発生しないという効果がある。 <B-2. Effect>
According to the second embodiment of the present invention, in the method for manufacturing a silicon carbide semiconductor device, (a) after selectively implanting ions into epitaxial layer (silicon carbide layer) 2, epi layer 2 is activated and annealed. A step, (b) a step of forming a photoresist 5 on the p-type ion implantation layer 3 that is on the ion-implanted region, and (c) a surface layer of the epilayer 2 using the photoresist 5 as a mask. Embodiments comprising: a step of dry etching; (d) a step of removing the photoresist 5; and (e) a step of polishing the entire surface layer of the epilayer 2 after the step (d). 1, a pattern is formed with a photoresist 5 on the p-type ion implantation layer 3 by photoengraving, and the p-type ion implantation layer 3 is protected. Therefore, an epitaxial layer (silicon carbide) altered by activation annealing is used. When the altered layer 4 of the surface layer 2 is removed by dry etching, the surface of the p-type ion implantation layer 3 is not etched, and in the second embodiment, polishing is performed instead of forming the sacrificial oxide film 7. However, at this time, the decrease in the thickness of the p-type ion implantation layer 3 is small, and there is an effect that the p-type ion implantation layer 3 does not substantially occur as in the first embodiment.

実施の形態１に係る炭化珪素半導体装置の製造工程（炭化珪素層２に活性化アニールを実施する工程）を説明する図である。FIG. 6 is a diagram for describing a process for manufacturing a silicon carbide semiconductor device according to the first embodiment (a process for performing activation annealing on silicon carbide layer 2). 実施の形態１に係る炭化珪素半導体装置の製造工程（ｐ型イオン注入層３の表層をフォトレジスト５で保護する工程）を説明する図である。It is a figure explaining the manufacturing process (The process of protecting the surface layer of the p-type ion implantation layer 3 with the photoresist 5) of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造工程（炭化珪素層２の変質層をドライエッチングで除去する工程）を説明する図である。It is a figure explaining the manufacturing process (process which removes the altered layer of the silicon carbide layer 2 by dry etching) of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造工程（フォトレジスト５除去する工程）を説明する図である。It is a figure explaining the manufacturing process (process of removing photoresist 5) of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造工程（炭化珪素層２の表層に犠牲酸化を行って犠牲酸化膜７を形成する工程）を説明する図である。FIG. 6 is a diagram illustrating a manufacturing process of the silicon carbide semiconductor device according to the first embodiment (a process of forming sacrificial oxide film 7 by performing sacrificial oxidation on the surface layer of silicon carbide layer 2). 実施の形態１に係る炭化珪素半導体装置の製造工程（犠牲酸化膜７をウエットエッチングで除去する工程）を説明する図である。It is a figure explaining the manufacturing process (The process of removing the sacrificial oxide film 7 by wet etching) of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造工程（ショットキ電極９を形成する工程）を説明する図である。It is a figure explaining the manufacturing process (process which forms the Schottky electrode 9) of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態２に係る炭化珪素半導体装置の製造工程（新たな変質層６ｂを表面研磨で除去する工程）を説明する図である。It is a figure explaining the manufacturing process (The process of removing the new alteration layer 6b by surface polishing) of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG.

符号の説明Explanation of symbols

１ 炭化珪素（ＳｉＣ）基板、２ ｎ型エピタキシャル層（炭化珪素層）、３ ｐ型イオン注入層、４ 活性化アニールによる変質層、５ フォトレジスト、６ａ ドライエッチングによる除去部分、６ｂ ドライエッチングによる新たな変質層、７ 犠牲酸化膜、８ オーミック電極、９ ショットキ電極。   1 silicon carbide (SiC) substrate, 2 n-type epitaxial layer (silicon carbide layer), 3 p-type ion implantation layer, 4 altered layer by activation annealing, 5 photoresist, 6a removed portion by dry etching, 6b new by dry etching Altered layer, 7 sacrificial oxide film, 8 ohmic electrode, 9 Schottky electrode.

Claims (1)

（ａ）炭化珪素層に選択的にイオン注入した後、前記炭化珪素層を活性化アニールする工程と、
（ｂ）前記イオン注入された領域上にフォトレジストを形成する工程と、
（ｃ）前記フォトレジストをマスクとして、前記活性化アニール後に前記炭化珪素層の表層を１００ｎｍ以上ドライエッチングにより除去する工程と、
（ｄ）前記フォトレジストを除去する工程と、
（ｅ）前記工程（ｄ）後、前記炭化珪素層の表層全体に犠牲酸化膜を形成する工程と、
（ｆ）前記犠牲酸化膜をウエットエッチングにより除去する工程と、
を備える、炭化珪素半導体装置の製造方法。 (A) after selectively implanting ions into the silicon carbide layer, activation annealing the silicon carbide layer;
(B) forming a photoresist on the ion-implanted region;
(C) the photoresist as a mask, removing the surface layer of 100nm or more dry etching of the silicon carbide layer after the activation annealing,
(D) removing the photoresist;
(E) after the step (d), forming a sacrificial oxide film over the entire surface layer of the silicon carbide layer;
(F) removing the sacrificial oxide film by wet etching;
A method for manufacturing a silicon carbide semiconductor device comprising:
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