JPWO2013145022A1 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

In order to provide a SiC-MOSFET manufacturing method capable of increasing Vth without reducing channel mobility, (a) a silicon carbide substrate is represented by plasma oxidation before forming a gate insulating film. A silicon oxide film is formed by oxidation by a low temperature oxidation method. Next, (b) the silicon oxide film is removed. After the steps (a) and (b) are repeated one or more times, (c) a gate insulating film is formed.

Description

  The present invention relates to a sacrificial oxide film used in a method for manufacturing a silicon carbide semiconductor device.

  A general manufacturing method of this SiC-MOSFET will be described. First, an SiC epitaxial layer is formed on a SiC substrate, and an impurity serving as a dopant is ion-implanted into a drain region, a base region, and a source region. Next, activation annealing is performed on the implanted impurities. At the time of annealing, for example, a carbon film having excellent heat resistance is deposited as a cap material so that Si of the SiC substrate does not sublime, and heat treatment is performed at a temperature of 1600 ° C. or higher. Thereafter, the carbon layer of the cap material is removed by oxygen plasma ashing or heat treatment at, for example, about 900 ° C., in which the SiC substrate is hardly oxidized in an oxygen atmosphere. However, the cap material and the substrate react and the formed carbon compound cannot be completely removed. This carbon compound causes deterioration of the reliability of the gate insulating film. Therefore, the interface that forms the gate insulating film is thermally oxidized at a high temperature to form a silicon oxide film (sacrificial oxide film), and then the silicon oxide film is removed with diluted hydrofluoric acid, so-called sacrificial oxidation is performed. A method for removing the carbon compound is generally used. Thereafter, a SiC-MOSFET is completed through a gate insulating film process, a silicide electrode process, and an interlayer insulating film forming process.

Many of the SiC-MOSFETs formed in this way have a low _{Vth and} are _normally on. However, the threshold voltage (V _th ) of the current Si-IGBT is about 5 to 5.5 V, and a threshold voltage (V _th ) of 5 V or more is required to replace this with SiC-MOSFET. As a means for increasing _Vth , for example, there is a method of increasing the dopant concentration in the base region where the channel is formed.

  On the other hand, in order to realize a low-loss device, it is important to improve mobility and lower on-resistance. However, the current SiC-MOSFET has a low channel mobility because there are many interface states at the so-called MOS interface of silicon oxide film / silicon carbide. Therefore, it is necessary to improve the MOS interface characteristics and increase the channel mobility. As a means for increasing the channel mobility, for example, there is a method in which a deposited oxide film is applied to a gate oxide film to perform an oxynitriding process (Non-Patent Document 1).

M. Noborio, J. Suda, S. Beljakowa, M. Krieger, and T. Kimoto, phys.stat.sol. (A) 206, 2374 (2009)

However, when V _th and channel mobility are increased by the above method, there are technical problems described below.

In the method of increasing the dopant concentration in the base region where the channel is formed in order to increase V _th , V _th can be increased, but the channel mobility decreases due to the influence of the high impurity concentration.

In the method of applying the deposited oxide film to the gate oxide film and performing the oxynitriding treatment in order to improve the channel mobility, the channel mobility is improved, but _Vth is lowered.

An object of the present invention is to provide a SiC-MOSFET that achieves both high channel mobility and high _Vth .

As a result of various examinations of the sacrificial oxidation process before forming the gate insulating film, we have found that _Vth is increased by performing plasma oxidation instead of high-temperature thermal oxidation. That is, by replacing the conventional sacrificial oxidation by thermal oxidation with plasma oxidation, _Vth of 5 V or more can be obtained without reducing the channel mobility of the SiC-MOSFET.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the method of manufacturing a semiconductor device according to the present invention, before forming the gate insulating film, (a) a silicon carbide substrate is oxidized by a low-temperature oxidation method typified by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After the steps (a) and (b) are repeated one or more times, (c) a gate insulating film is formed.

According to the present invention, there is provided an SiC-MOSFET that achieves both high channel mobility and high _Vth .

1 is a cross sectional view of a silicon carbide semiconductor device in Example 1. FIG. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. FIG. 6 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 1. It is a figure which shows the gate voltage dependence of the drain current of the silicon carbide semiconductor device in Example 1 with a comparative example. It is a figure which shows the gate voltage dependence of the channel mobility of the silicon carbide semiconductor device in Example 1 with a comparative example. 5 is a table showing a relationship between a peak value of channel mobility and a gate threshold voltage of the silicon carbide semiconductor device in Example 1 together with a comparative example. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2. FIG. 10 is a cross sectional view showing a part of the process for manufacturing the silicon carbide semiconductor device in Example 2.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In all the drawings for explaining the embodiments, the same reference numerals are given to the same members in principle, and the repeated explanation thereof is omitted. In particular, for functions corresponding to different embodiments, the same reference numerals are given even if there are differences in shape, impurity concentration, crystallinity, and the like.

  Hereinafter, the process of forming a silicon oxide film by oxidizing the interface that forms the gate insulating film, removing the silicon oxide film with diluted hydrofluoric acid, and repeating the above process one or more times is referred to as “sacrificial oxidation”. Call it.

  In the first and second embodiments, a silicon carbide semiconductor device having a so-called MOS (Metal-Oxide-Semiconductor) structure as shown in FIGS. 1 and 6 will be described.

  1 and 6 show application examples to a semiconductor device having a MOS structure. FIG. 1 shows a structure in which a source 23 and a drain 24 are arranged in a direction parallel to the substrate surface (hereinafter referred to as a lateral MOS), and FIG. 6 shows a source 23 and a drain 26 arranged in a direction perpendicular to the substrate surface (hereinafter referred to as a vertical MOS). Structure.

[Horizontal MOS structure]
In FIG. 1, a silicon carbide MOSFET which is a silicon carbide semiconductor device includes a silicon carbide substrate 10, a silicon carbide layer 20 formed on silicon carbide substrate 10, an insulating film 32 formed on silicon carbide layer 20, Gate electrode 42 formed on insulating film 32, and source electrode 51, drain electrode 52, and base contact electrode 53 formed on silicon carbide layer 20 are included.

  Silicon carbide layer 20 is formed of a silicon carbide epitaxial layer 21, a base region 22 that is an ion implantation region or an epitaxial layer, a source region 23 that is an ion implantation region, a drain region 24, and a base contact region 25.

Here, for example, nitrogen (N) ions are used as the impurity implanted into the region desired to be n-type, and boron (B) or aluminum (Al) ions are used as the impurity implanted into the region desired to be p-type. In FIG. 1 (a), an n ⁺ region and a p ⁺ type base contact region 25 to be a source region 23 and a drain region 24 of a transistor are formed inside a p type base region 22.

  A gate insulating film 32, a source electrode 51, a drain electrode 52, and a base contact electrode 53 are formed on the surface of the silicon carbide layer 20.

  The source electrode 51, the drain electrode 52, and the base contact electrode 53 are connected to the source region 23, the drain region 24, and the base contact region 25, respectively.

  A gate electrode 42 is formed so as to cover a part of the source region 23 and the drain region 24 via the gate insulating film 32 on the silicon carbide layer 20.

[Manufacturing method of lateral MOS structure]
Next, a method for manufacturing the lateral MOS structure will be described.

FIG. 2A to FIG. 2K are cross-sectional views at each step when manufacturing the lateral MOS transistor of the first embodiment. In addition, in order to avoid complexity, the cross-sectional view shows only the configuration of the main part in the process, and does not correspond to an accurate cross-sectional view.
First, as shown in FIG. 2A, a silicon carbide epitaxial layer 21 was laminated on n-type silicon carbide substrate 10.

  Next, as shown in FIG. 2B, Al ions were implanted into the surface layer portion of the silicon carbide epitaxial layer 21 to form a p-type base region 22. The ions implanted into base contact region 25 may be B ions, or a p-type silicon carbide epitaxial layer may be further formed on silicon carbide epitaxial layer 21 to form p-type base region 22.

  Next, a mask for implanting ions into the source region 23 and the drain region 24 was used, and N ions were implanted into the source region 23 and the drain region 24 as shown in FIG. Thereafter, the mask was removed.

  Next, a mask was used to implant ions into the base contact region 25, and Al ions were implanted into the base contact region 25 as shown in FIG. The ions implanted into the base contact region 25 may be B ions. Thereafter, the mask was removed.

  Subsequently, as shown in FIG. 2E, a carbon film 60 was deposited as a cap material for impurity activation annealing around the silicon carbide substrate 10 and the silicon carbide layer 20. Thereafter, impurity activation annealing is performed at a temperature of 1600 to 1800 ° C., for example. In this example, impurity activation annealing was performed at 1700 ° C. for 60 seconds.

  Next, as shown in FIG. 2 (f), the carbon layer of the cap material was removed by oxygen plasma ashing. At this time, since the carbon compound formed by the reaction between the carbon of the cap material and the substrate could not be completely removed, sacrificial oxidation by plasma oxidation was performed. Specifically, after performing predetermined cleaning, as shown in FIG. 2G, the surface of the silicon carbide layer 20 is plasma-oxidized to form an oxide film 31. Then, the oxide film 31 is removed with diluted hydrofluoric acid. The above process, so-called sacrificial oxidation process, is repeated one or more times. In the sacrificial oxidation step, if the removal thickness of the silicon carbide layer 20 is thin, the carbon compound cannot be removed, and if it is thick, the impurity concentration in the ion implantation region is affected. In the conventional sacrificial oxidation process using thermal oxidation, the source region 23, the drain region 24, the base contact region 25, and the silicon carbide epitaxial layer 21 which are ion implantation regions have different oxidation rates. A step is generated at the interface of 32. This level difference leads to device characteristic deterioration such as electric field concentration on the gate insulating film. According to the method using plasma oxidation of the present invention, a uniform interface without a step can be formed, and good device characteristics can be obtained. In this embodiment, plasma oxidation by ICP (Inductive Coupled Plasma) method is used for forming the oxide film 31 at a temperature of 500 ° C. or less. In this example, the above-described process, so-called sacrificial oxidation, was repeatedly performed so that the thickness of the silicon carbide layer 20 removed by sacrificial oxidation was, for example, 10 nm.

  Next, as shown in FIG. 2H, a gate oxide film 32 is formed on the semiconductor substrate. In this example, a deposited oxide film having a thickness of 50 nm was formed, and oxynitriding was performed at 1300 ° C. for 30 minutes.

  Subsequently, as shown in FIG. 2 (i), a gate material film 41 made of an n-type polycrystalline silicon film having a thickness of 200 nm was deposited.

  Subsequently, as shown in FIG. 2 (j), the gate material film 41 was etched using the resist as a mask to form the gate electrode 42 of the MOS transistor.

  Subsequently, as shown in FIG. 2 (k), through holes are formed in the gate material film located on the source region 23, the drain region 24, and the base contact region 25, and the source region 23, the drain region 24, and the base contact are formed. A step of forming a contact of the source electrode 51, the drain electrode 52, and the base contact electrode 53 (including a silicidation step) and a step of forming a wiring are performed on the region 25, thereby completing the semiconductor device of FIG.

[Device evaluation of SiC-MOSFET]
3 to 5, a specification using plasma oxidation for sacrificial oxidation (hereinafter abbreviated as plasma oxidation specification) and a specification using conventional thermal oxidation method for sacrificial oxidation (hereinafter abbreviated as thermal oxidation specification). ) SiC-MOSFET device evaluation results are shown.

FIG. 3 shows the gate voltage dependency (I _d V _g characteristic) of the drain current of the silicon carbide semiconductor device in Example 1. When “Thermal Oxidation” uses a thermal oxide film, “Plasma Oxidation” is a characteristic line when a plasma oxide film is used. As shown in FIG. 3, the _{Vth of the} plasma oxidation specification was higher than the thermal oxidation specification. Specifically, the thermal oxidation specification is V _th = 4.3 V, and the plasma oxidation specification is V _th = 6.6 V, which is about 2.3 V higher than the plasma oxidation specification.

FIG. 4 shows the gate voltage dependence of the channel mobility μ of the silicon carbide semiconductor device in Example 1. When “Thermal Oxidation” uses a thermal oxide film, “Plasma Oxidation” is a characteristic line when a plasma oxide film is used. The horizontal axis of FIG. 4 is a value obtained by subtracting the gate threshold voltage _Vth from the gate voltage Vg. As shown in FIG. 4, the maximum value of channel mobility is μ = 21.8 cm2 / V · s in the thermal oxidation specification, and μ = 21.1 cm2 / V · s in the plasma oxidation specification, which is the difference between the two specifications. There is almost no.

FIG. 5 shows a table summarizing the values of _Vth and channel mobility μ. “Thermal Oxidation” is data when a thermal oxide film is used, and “Plasma Oxidation” is data when a plasma oxide film is used. As can be seen from FIG. 5, in the plasma oxidation specification, the channel mobility is almost the same as in the thermal oxidation specification, and V _th is about 2.3 V higher. In this manner, in the process of manufacturing a normal MOS transistor, the conventional sacrificial oxide film by thermal oxidation is replaced with a plasma oxide film without changing the channel mobility of the SiC-MOSFET (same as the thermal oxide film). It can be seen that _Vth can be increased by maintaining a certain degree of mobility.

  In the first embodiment, an n-type silicon carbide single crystal semiconductor substrate is used, but a p-type silicon carbide substrate may be used. In this case, the MOS structure can be formed by reversing the polarity of impurity ion implantation into each region for forming the MOS structure.

  The following describes application to the vertical MOS structure shown in FIG. However, repeated description of the same members as those shown in the first embodiment is omitted.

[Vertical MOS structure]
In FIG. 6, silicon carbide MOSFET which is a silicon carbide semiconductor device is formed on silicon carbide substrate 10, back contact region 26 which is an ion implantation region formed inside silicon carbide substrate 10, and back contact region 26. The drain electrode 54, the drain electrode 54 and the silicon carbide layer 20 formed on the silicon carbide substrate 10, the insulating film 32 formed on the silicon carbide layer 20, and the gate electrode 42 formed on the insulating film 32. And a source-base contact common electrode 55 formed on the silicon carbide layer 20. Silicon carbide layer 20 is formed of a silicon carbide epitaxial layer 21, a base region 22 that is an ion implantation region, and a source region 23.

  Here, for example, nitrogen (N) ions are used as an impurity to be implanted into a region desired to be n-type, and boron (B) or aluminum (Al) ions are used as an impurity to be implanted into a region desired to be p-type. For example, in the figure, a p + -type back contact region 26 is formed inside the silicon carbide substrate 10 and an n + -type source region 23 is formed as in the first embodiment.

  On the surface of silicon carbide layer 20, gate insulating film 32 and source-base contact common electrode 55 are formed. A drain electrode 54 is formed on the back surface of the silicon carbide layer 20.

  The source base contact common electrode 55 is connected to the base region 22 and the source region 23. The drain electrode 54 is connected to the back contact region 26.

  A gate electrode 40 is formed so as to cover a part of n-type source region 23 through gate insulating film 32 on silicon carbide layer 20.

[Manufacturing method of vertical MOS structure]
Next, a method for manufacturing the vertical MOS structure will be described. However, detailed description of the same manufacturing method as the manufacturing method shown in Example 1 is omitted. FIG. 7A to FIG. 7J are cross-sectional views in each step when manufacturing the vertical MOS transistor of the second embodiment. In addition, in order to avoid complexity, the cross-sectional view shows only the configuration of the main part in the process, and does not correspond to an accurate cross-sectional view.
First, as shown in FIG. 7A, a silicon carbide epitaxial layer 21 was stacked.

  Next, as shown in FIGS. 7B, 7C, and 7D, ions were implanted into the p-type base region 22, the n-type source region 23, and the back contact region. The ion species used for implantation is Al ion implantation in the back contact region 26, and the p-type base region 22 and the n-type source region 23 are the same as in the first embodiment. The ions implanted into the back contact region 26 may be B ions.

  Subsequently, as shown in FIG. 7 (e), after carbon film 60 is deposited on the surfaces of silicon carbide substrate 10 and silicon carbide layer 20, annealing for impurity activation is performed at a temperature of 1600 to 1800 ° C., for example. It was.

  Next, the carbon layer of the cap material was removed by oxygen plasma ashing. At this time, since the carbon compound formed by the reaction between the carbon of the cap material and the substrate could not be completely removed, sacrificial oxidation by plasma oxidation was performed as shown in FIG. Specifically, after performing predetermined cleaning, the surface of the silicon carbide layer 20 is subjected to plasma oxidation to form an oxide film 31, and the oxide film 31 is removed with diluted hydrofluoric acid. When sacrificial oxidation by thermal oxidation is used, the front surface is oxidized and the back surface is also oxidized. Therefore, the ion implantation has to be performed in consideration of the thickness removed by the sacrificial oxidation when the ion implantation is performed on the back contact region 26. When sacrificial oxidation by the plasma oxidation is used, there is almost no oxidation on the back surface. Therefore, there is no need to consider removal by sacrificial oxidation when ion implantation is performed on the back contact region 26, and it is sufficient to perform ion implantation at a concentration at which contact with the electrode is desired in the vicinity of the outermost surface of the back surface. This effect facilitates making good contact with the electrode.

  Next, as shown in FIG. 7G, a gate oxide film 32 is formed on the semiconductor substrate. In this example, a deposited oxide film having a thickness of 50 nm was formed, and oxynitriding was performed at 1300 ° C. for 30 minutes.

  Subsequently, as shown in FIGS. 7H and 7I, a gate material film 41 was deposited, and the gate material film 41 was etched to form a gate electrode 42 of the MOS transistor.

  Subsequently, as shown in FIG. 7 (j), a through hole is formed at the boundary between the base region 22 and the source region 23, and the source base contact is made to the boundary between the base region 22 and the source region 23 and the back contact region 26, respectively. A process for forming a contact for the common electrode 55 and the drain electrode 54 (including a silicidation process) and a process for forming a wiring are performed to complete the semiconductor device of FIG.

Also according to the configuration and the manufacturing method of the second embodiment, as in the first embodiment, by changing only the method for forming the lower portion of the gate insulating film in the MOS transistor having the vertical MOS structure, V _th can be _achieved without changing the mobility. Can be raised.

  DESCRIPTION OF SYMBOLS 10 ... Silicon carbide substrate, 20 ... Silicon carbide layer, 21 ... Silicon carbide epitaxial layer, 22 ... Base region, 23 ... Source region, 24 ... Drain region, 25 ... Base contact region, 26 ... Back contact region, 31 ... Sacrificial oxidation Films 32... Gate insulating film 41. Gate material film 42. Gate electrode 51. Source electrode 52. Drain electrode 53. Base contact electrode 54. Drain electrode 55 55 Source-base contact common electrode 60. Carbon film

Claims (6)

In a method for manufacturing a silicon carbide semiconductor device including a gate oxide film on a silicon carbide layer,
Annealing after forming a cap material on the silicon carbide layer;
Forming a sacrificial oxide film by an oxidation method at a temperature lower than the thermal oxidation temperature after removing the cap material;
And a step of forming a gate oxide film after removing the sacrificial oxide film. In claim 1,
The method for manufacturing a silicon carbide semiconductor device, wherein the cap material is a carbon film. In claim 2,
A step of implanting impurity ions before forming the cap material;
The method of manufacturing a silicon carbide semiconductor device, wherein the annealing is performed at a temperature higher than the temperature at which the impurity ions are activated. In claim 3,
The impurity ions are implanted so that the impurity concentration of the source region is different from the impurity concentration of the base region,
A method for manufacturing a silicon carbide semiconductor device, wherein the sacrificial oxide film has a thickness of 3 nm to 30 nm. In claim 2,
The method of manufacturing a silicon carbide semiconductor device, wherein the sacrificial oxide film is formed at 500 degrees or less. In claim 5,
The method of manufacturing a silicon carbide semiconductor device, wherein the sacrificial oxide film is formed by plasma oxidation.

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