JP5995701B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  In order to save energy in power electronics equipment such as inverters, semiconductors such as insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field effect transistors (MOSFETs) It is necessary to reduce the loss of the switching element.

  Since the loss of the semiconductor switching element is determined by the conduction loss and switching loss of the element, development using a wide band gap semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN) has been advanced to reduce these losses. Yes.

  On the other hand, high power control requires improvement and stabilization of element reliability. In particular, SiC-MOSFETs have a higher dielectric breakdown resistance than Si-MOSFETs, so that the drift concentration can be increased. In this case, however, a large electric field is applied to the gate oxide film when a high voltage is applied to the drain. This causes deterioration and destruction of the gate oxide film.

  Patent Document 1 discloses a structure (see FIG. 15) for improving the reliability of an SiC-MOSFET. In this SiC-MOSFET, the p-type electric field relaxation region 30 is formed in the n-type epitaxial layer 12 in contact with the gate oxide film 21, thereby relaxing the electric field strength applied to the gate oxide film 21.

JP 2011-60930 A

  However, according to the above structure, the drain-source current when the MOSFET is on is hindered by the depletion layer that spreads from the electric field relaxation region 30. That is, the resistance value between the well regions 13, that is, the so-called JFET resistance value increases. In particular, in the SiC-MOSFET, since the epitaxial layer 12 that is the drift region can be made thin and the carrier density can be increased, the drift resistance is small, and most of the on-resistance of the entire MOSFET is the JFET resistance. And channel resistance. Therefore, in the configuration of the SiC-MOSFET proposed in Patent Document 1, although the reliability of the gate oxide film 21 is improved, there is a problem in that the on-resistance is significantly increased.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device that achieves both a reduction in on-resistance and the reliability of a gate oxide film, and a method for manufacturing the same.

A silicon carbide semiconductor device of the present invention includes a first conductivity type SiC substrate, a first conductivity type epitaxial layer formed on the SiC substrate, and a second conductivity type selectively formed on a surface layer of the epitaxial layer. A well region; a source region of a first conductivity type selectively formed on a surface layer of the well region; and a surface of the well region sandwiched between the source region and the epitaxial layer and the surface of the epitaxial layer. a gate oxide film, and a gate electrode formed on the gate oxide film, have a negative fixed charge at the interface of the gate oxide film and the epitaxial layer, the negative fixed charge in the gate oxide film on the surface of the well region Is less than the density of negative fixed charges in the gate oxide film on the surface of the epitaxial layer .

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes (a) a step of forming a first conductivity type epitaxial layer on a first conductivity type SiC substrate, and (b) a second conductivity on a surface layer of the epitaxial layer. A step of selectively forming a well region of a mold, (c) a source region of a first conductivity type selectively formed in a surface layer of the well region, and (d) a well region sandwiched between the source region and the epitaxial layer Forming a gate oxide film over the surface of the epitaxial layer from the surface of (a) forming a gate electrode on the gate oxide film; (f) applying a positive voltage to the gate electrode; Forming a negative fixed charge at the interface between the gate oxide film and the epitaxial layer.

A silicon carbide semiconductor device of the present invention includes a first conductivity type SiC substrate, a first conductivity type epitaxial layer formed on the SiC substrate, and a second conductivity type selectively formed on a surface layer of the epitaxial layer. A well region; a source region of a first conductivity type selectively formed on a surface layer of the well region; and a surface of the well region sandwiched between the source region and the epitaxial layer and the surface of the epitaxial layer. It has a gate oxide film and a gate electrode formed on the gate oxide film, and has a negative fixed charge at the interface between the gate oxide film and the epitaxial layer. Therefore, the electric field applied to the gate oxide film at the off time can be relaxed without increasing the JFET resistance at the on time. In addition, by making the negative fixed charge density in the gate oxide film on the surface of the well region smaller than the negative fixed charge density in the gate oxide film on the surface of the epitaxial layer, the negative fixed charge is channel characteristics. Can be reduced.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes (a) a step of forming a first conductivity type epitaxial layer on a first conductivity type SiC substrate, and (b) a second conductivity on a surface layer of the epitaxial layer. A step of selectively forming a well region of a mold, (c) a source region of a first conductivity type selectively formed in a surface layer of the well region, and (d) a well region sandwiched between the source region and the epitaxial layer Forming a gate oxide film over the surface of the epitaxial layer from the surface of (a) forming a gate electrode on the gate oxide film; (f) applying a positive voltage to the gate electrode; Forming a negative fixed charge at the interface between the gate oxide film and the epitaxial layer. Therefore, it is possible to manufacture a silicon carbide semiconductor device in which the electric field applied to the gate oxide film at the off time is relaxed without increasing the JFET resistance at the on time.

1 is a cross sectional view of a silicon carbide semiconductor device according to a first embodiment. 5 is a cross sectional view showing a manufacturing step of the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a manufacturing step of the silicon carbide semiconductor device according to the first embodiment. FIG. It is a figure which shows the electric field strength of a gate oxide film. It is a figure which shows the electric field strength of a gate oxide film. It is a figure which shows the electric field strength of a gate oxide film. It is a figure which shows the electric field strength of a gate oxide film. It is a figure which shows the drain voltage characteristic of JFET resistance. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device according to a second embodiment. FIG. 10 is a cross sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 11 is a cross sectional view showing a process for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 14 is a cross sectional view showing a manufacturing step of a silicon carbide semiconductor device according to a variation of Embodiment 3. It is sectional drawing which shows the manufacturing process of the silicon carbide semiconductor device which concerns on a prior art.

<A. Embodiment 1>
In this specification, the first conductivity type is n-type and the second conductivity type is p-type as the semiconductor conductivity type, but the opposite conductivity type may be used.

<A-1. Configuration>
FIG. 1 shows a cross-sectional view of n-channel SiC-MOSFET 101 which is the silicon carbide semiconductor device of the first embodiment.

  The SiC-MOSFET 101 includes an n-type SiC substrate 11, an n-type epitaxial layer 12, a p-type well region 13, an n-type source region 14, a p-type well contact region 15, a gate oxide film 21, a gate electrode 22, An interlayer insulating film 23, a source electrode 24, and a drain electrode 25 are provided.

  Epitaxial layer 12 is formed on SiC substrate 11, and a plurality of well regions 13 are selectively formed on the surface of epitaxial layer 12. A source region 14 and a well contact region 15 are selectively formed adjacent to each other on the surface of the well region 13. The well contact region 15 is for suppressing the operation of the parasitic transistor by making the potentials of the source region 14 and the well region 13 the same. A gate electrode 22 is formed via a gate oxide film 21 from the surface of the well region 13 sandwiched between the source region 14 and the epitaxial layer 12 to the surface of the epitaxial layer 12 (JFET portion 41). A negative fixed charge 31 introduced by the gate voltage is formed at the interface between the gate oxide film 21 and the epitaxial layer 12 (hereinafter also simply referred to as the gate oxide film 21 interface). An interlayer insulating film 23 for separating the gate electrode 22 and the source electrode 24 is formed on the gate electrode 22, and a source electrode 24 in contact with the source region 14 and the well contact region 15 is formed thereon. A drain electrode 25 is formed below the SiC substrate 11.

<A-2. Operation>
Next, the operation of the SiC-MOSFET 101 will be described.

  When a positive voltage is applied to the gate electrode 22, a channel that is a current path is formed in the surface layer of the well region 13. When a positive voltage is applied to the drain electrode 25 in this state, a current flows from the drain electrode 25 to the source electrode 24 through the SiC substrate 11, the epitaxial layer 12, the surface layer (channel) of the well region 13, and the source region 14. In particular, in an element using a wide band gap semiconductor material such as SiC, the epitaxial layer 12 can be highly concentrated or thinned and has a low resistance, so that the current path between the opposing well regions 13 (JFET portion 41). Reducing the resistance (JFET resistance) and the resistance of the channel portion (channel resistance) is very effective for reducing the conduction loss of the device.

  On the other hand, when the positive voltage of the gate electrode 22 is removed or a negative voltage is applied, the channel is removed. As a result, even when a high voltage is applied to the drain electrode 25, the drain-source current can be cut off. At this time, although the gate oxide film 21 is exposed to a high electric field, a negative fixed charge 31 is formed by the gate bias at the interface between the JFET portion 41 and the gate oxide film 21 where the electric field is most concentrated. The electric field strength applied to the film 21 is relaxed, and the reliability of the gate oxide film 21 is ensured. In particular, when SiC is used as a semiconductor material, the dielectric breakdown electric field is large, so that it is often designed so that a high electric field is applied to the epitaxial layer 12, and the electric field strength applied to the gate oxide film 21 is increased accordingly. The structure of the present invention in which the electric field is relaxed by the charge 31 is very effective.

  Although the p-type electric field relaxation region is formed in the center of the JFET portion 41 as in the SiC-MOSFET 100 of FIG. 15, the electric field strength of the gate oxide film 21 can be suppressed and its reliability can be ensured. Since the JFET resistance is greatly increased, the conduction loss of the element becomes very large. However, since the SiC-MOSFET 101 forms a negative fixed charge at the interface of the gate oxide film 21 instead of the electric field relaxation region, the reliability of the gate oxide film 21 can be improved without increasing the conduction loss of the element. it can.

  With these operations, the SiC-MOSFET 101 functions as a switching element.

<A-3. Manufacturing method>
Next, a method for manufacturing the SiC-MOSFET 101 will be described with reference to FIGS.

First, an n-type and low-resistance SiC substrate 11 is prepared, and an n-type epitaxial layer 12 is formed on the SiC substrate 11 by epitaxial growth (FIG. 2). In the epitaxial layer 12, the n-type impurity concentration is appropriately set to, for example, 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is, for example, 4 μm to 200 μm according to the breakdown voltage required for the SiC-MOSFET 101. .

Next, the p-type well region 13 is formed on the surface of the epitaxial layer 12 and the n-type source region 14 and the p-type well are formed on the surface of the well region 13 by using a known lithography technique, etching technique, ion implantation technique, or the like. Contact regions 15 are respectively formed (FIG. 3). Each region is formed, for example, by implanting N ions in the n-type region and Al ions in the p-type region using a resist or oxide film processed by photolithography as a mask. In the well region 13, the impurity concentration is, for example, 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the implantation depth is, for example, 0.3 μm to 2.0 μm. The source region 14 is formed so that the bottom surface thereof does not exceed the bottom surface of the well region 13, and the impurity concentration exceeds the impurity concentration of the well region 13, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ^−3. To the extent. The well contact region 15 is desirably formed at a substrate temperature of 150 ° C. or higher, and its impurity concentration is set to exceed the impurity concentration of the well region 13.

  Next, annealing is performed in an inert gas atmosphere such as Ar gas by a heat treatment apparatus. Annealing is performed at a temperature of 1300 ° C. to 1900 ° C. for 30 seconds to 1 hour, for example. This activates n-type impurities such as N and p-type impurities such as Al implanted in the previous step.

  Next, the gate oxide film 21 and the gate electrode 22 are formed (FIG. 4). The gate oxide film 21 is formed through heat treatment in a nitrogen or ammonia atmosphere after using, for example, a thermal oxidation method or a deposition method. The gate electrode 22 is formed by etching using, for example, polysilicon deposited by CVD and using a resist processed by photolithography as a mask. Polysilicon may contain impurities such as phosphorus and boron, thereby realizing low sheet resistance.

  Next, after forming the interlayer insulating film 23, the source electrode 24 and the drain electrode 25 are formed (FIG. 5). The interlayer insulating film 23 is deposited by, for example, a CVD method, and is etched so as to expose at least a part of the gate electrode 22, the source region 14, and the well contact region 15 in order to separate and take out the gate and the source. Go and form. Although the wiring of the gate electrode 22 is not shown in FIG. 5, the interlayer insulating film 23 is exposed at the outer periphery of the MOSFET, and the source electrode 24 and the gate electrode 22 are formed separately. Thereafter, in order to bring the source electrode 24 into ohmic contact with the source region 14 and the well contact region 15 exposed by etching, for example, Ni is formed on the entire surface of the substrate and heat treatment is performed at 600 to 1000 ° C. to form silicide. (Not shown). Note that Ni remaining on the interlayer insulating film 23 is removed by wet etching. Similarly, silicide is also formed on the back surface of the substrate. Thereby, good ohmic contact between SiC substrate 11 and drain electrode 25 can be realized. The wiring for taking out the gate electrode 22 and the source electrode 24 are formed by sputtering or vapor deposition of metals such as Al, Cu, Ti, Ni, Mo, W, Ta, nitrides thereof, laminated films thereof, and alloy layers thereof. It is formed by depositing by patterning and patterning. The drain electrode 25 is formed of a metal film such as Ti, Ni, Ag, or Au by a sputtering method or a vapor deposition method.

  Finally, by applying a positive voltage (gate bias) to the gate for a long time in the state of FIG. 5, a negative fixed charge 31 is formed at the interface of the gate oxide film 21, and the SiC-MOSFET shown in FIG. 1 is completed. . The application of the gate voltage for forming the negative fixed charge 31 may be performed at any time such as the state of the wafer or chip or after the module is formed.

<A-4. Fixed charge>
FIG. 6 shows the result of calculating the relationship between the negative fixed charge density introduced by the gate bias and the electric field strength applied to the gate oxide film 21 on the center of the JFET portion 41 (JFET central portion) by the drain voltage. Show. Assuming an element having a breakdown voltage characteristic of about 1200 V, the thickness of the epitaxial layer 12 is set to 12 μm, and the impurity concentration is set to about 1 × 10 ¹⁶ cm ⁻³ . Further, it is assumed that the distance between the opposing p-wells 13, the so-called JFET length, is 2 μm to 3 μm. The value of the electric field strength is a calculated value when 1200 V is applied to the drain electrode 25, and is represented by a relative value where the electric field strength in a state where the fixed charge 31 is not introduced is 100%. In FIG. 6, since the y-axis is a relative value, this calculation result is applied even when the negative fixed charge 31 is formed at the interface of the gate oxide film 21 regardless of the gate bias in the thermal oxidation process or the like. Is possible. Various models have been proposed for deterioration and destruction of the gate oxide film 21 due to electric field stress, and since it varies greatly depending on the applied electric field in actual use, it cannot be described in general. By suppressing about 1 to 10%, the lifetime of the element can be improved from several times to several tens of times. Thereby, reliability is improved and a device design margin is improved.

  The applicant has also clarified that the fixed charge density introduced by the gate bias has time, temperature, and electric field strength dependence through experiments using bias application and gate characteristic evaluation. As each parameter increases, the fixed charge density introduced also increases.

  FIG. 7 shows the result of calculating the relationship between the gate bias application time and the electric field strength applied to the gate oxide film 21 on the JFET central portion when the drain voltage is applied after the gate bias is applied. The calculation method of the electric field strength is based on FIG. 6 and is calculated from the introduced fixed charge density. It is assumed that the temperature at the time of applying the gate bias is 300 K, and the electric field strength is 4 MV / cm. Usually, in a test process such as a wafer test, a gate bias is often applied under conditions of a temperature of 300 K and an electric field strength of about 4 MV / cm. However, since the application time is about several μs to several s, the effect of the present invention is expected. I understand that I can't. According to the figure, electric field relaxation of about 1 to 3% is possible by applying a gate bias for about 1 to 30 hours under the above conditions. However, in order to shorten the bias application time and realize further electric field relaxation, it is necessary to optimize the temperature and electric field strength at the time of bias application.

  FIG. 8 shows the result of calculating the relationship between the temperature at the time of applying the gate bias and the electric field strength applied to the gate oxide film 21 on the JFET central portion when the drain voltage is applied after the gate bias is applied. The calculation method of the electric field strength is based on FIG. 6 and is calculated from the introduced fixed charge density. It is assumed that the gate bias application time is 5 hours and the electric field strength is 4 MV / cm. According to the figure, the electric field strength of the gate oxide film 21 when the drain voltage is applied is reduced as the temperature when the gate bias is applied is increased. However, when a gate bias is applied in the state of the wafer, there is a concern that the wettability of the electrode may be deteriorated, so that it is desirable to set it to 450K or less. However, after the module is formed, the gate bias may be applied at a temperature exceeding 450K and not higher than the heat resistance temperature of the module. According to the figure, the electric field relaxation of about 1 to 10% is possible by setting the temperature at the time of applying the gate bias to 300 to 600 K under the above-described conditions. However, in order to reduce the temperature at the time of gate bias and realize further electric field relaxation, it is necessary to optimize the gate bias application time and the electric field strength at the time of application.

  FIG. 9 shows the result of calculating the relationship between the electric field strength when the gate bias is applied and the electric field strength applied to the gate oxide film 21 on the JFET central portion when the drain voltage is applied after the gate bias is applied. . The calculation method of the electric field strength is based on FIG. 6 and is calculated from the introduced fixed charge density. It is assumed that the gate bias application time is 5 hours and the temperature is 300K. According to the figure, the electric field strength of the gate oxide film 21 when the drain voltage is applied is reduced as the electric field strength when the gate bias is applied is increased. However, when the electric field applied to the gate electrode 22 exceeds 6 MV / cm, an FN (Fowler-Nordheim) current rises and the gate oxide film 21 may be deteriorated. According to the figure, electric field relaxation of about 1 to 8% is possible by applying a gate bias of 1 to 6 MV / cm under the above-described conditions. However, it is necessary to optimize the gate bias application time and the gate bias temperature in order to reduce the electric field strength during the gate bias and to further reduce the electric field.

  From the relationship between the fixed charge density and the gate bias condition shown in FIGS. 6 to 9, for example, the gate bias application time is several tens of minutes to several tens of hours, the temperature is 300 to 450 K, and the electric field strength is 3 to 5.5 MV / cm. By doing so, the electric field strength applied to the gate oxide film 21 on the center of the JFET when the drain rated voltage is applied after the fixed charge is introduced can be suppressed by 1 to 10%. Therefore, although depending on the design and the driving method, the device life can be improved from several times to several tens of times.

FIG. 10 is a graph in which the relationship between the drain voltage and the JFET resistance at the time of ON is derived by calculation. In the SiC-MOSFET 101, the calculation is performed before the gate bias is applied and after the gate bias is applied and a fixed charge of about 5 × 10 ¹¹ cm ⁻² is introduced, and the SiC− described in the prior document 1 shown in FIG. The calculation result of the MOSFET 100 was compared. According to the figure, it can be seen that the SiC-MOSFET 101 does not increase the JFET resistance even when a gate bias is applied. On the other hand, it can be seen that the SiC-MOSFET 100 described in the prior art document has a JFET resistance that is significantly increased as compared with the SiC-MOSFET 101.

  6 to 10 that the SiC-MOSFET 101 ensures the reliability of the gate oxide film 21 without significantly increasing the ON resistance of the element.

<A-5. Effect>
SiC-MOSFET 101 which is the silicon carbide semiconductor device of the present embodiment includes a first conductivity type SiC substrate 11, a first conductivity type epitaxial layer 12 formed on SiC substrate 11, and a surface layer of epitaxial layer 12. A well region 13 of a second conductivity type formed selectively, a source region 14 of a first conductivity type selectively formed on the surface layer of the well region 13, and a well sandwiched between the source region 14 and the epitaxial layer 12 A gate oxide film 21 formed from the surface of region 13 to the surface of epitaxial layer 12 and a gate electrode 22 formed on gate oxide film 21, and an interface between gate oxide film 21 and epitaxial layer 12 Have a negative fixed charge 31. Therefore, the electric field applied to the gate oxide film 21 at the off time can be relaxed without increasing the JFET resistance at the on time.

  The manufacturing method of SiC-MOSFET 101 according to the present embodiment includes (a) a step of forming first conductivity type epitaxial layer 12 on first conductivity type SiC substrate 11, and (b) a first layer on the surface of epitaxial layer 12. A step of selectively forming a well region 13 of two conductivity type, (c) a source region 14 of a first conductivity type selectively formed on a surface layer of the well region 13, and (d) a source region 14 and an epitaxial layer. A step of forming a gate oxide film 21 over the surface of the well region 13 sandwiched between 12 and the surface of the epitaxial layer 12; (e) a step of forming a gate electrode 22 on the gate oxide film 21; f) applying a positive voltage to the gate electrode 22 to form a negative fixed charge 31 at the interface between the gate oxide film 21 and the epitaxial layer 12. By introducing negative fixed charges into the interface between the epitaxial layer surface and the gate oxide film, the electric field applied to the gate oxide film at the off time can be relaxed without increasing the JFET resistance at the on time.

<B. Second Embodiment>
<B-1. Configuration>
FIG. 11 is a cross-sectional view of n-channel SiC-MOSFET 102 which is the silicon carbide semiconductor device of the second embodiment.

  The SiC-MOSFET 102 is different from the SiC-MOSFET 101 in that the gate oxide film 21 on the surface of the well region 13 is formed thicker than the gate oxide film 21 on the surface of the JFET portion 41 (epitaxial layer 12). As shown in the first embodiment, the fixed charge density introduced into the SiC interface of the gate oxide film 21 has an electric field strength dependency, and a large amount of fixed charges can be formed by increasing the gate bias. is there. On the other hand, since the fixed charge 31 is also formed at the interface of the gate oxide film 21 of the well region 13 where the channel is formed when the channel is turned on, channel characteristics such as channel resistance and threshold voltage change.

  The channel characteristics can be freely designed by adjusting the concentration of the well region 13 and the like. Naturally, the channel characteristics can also be designed in the first embodiment assuming that the fixed charge 31 is formed. Is obtained. However, by changing the film thickness of the gate oxide film 21 between the JFET portion 41 and the channel portion as in the second embodiment, the channel portion has a greater strength than the electric field strength applied to the gate oxide film 21 on the JFET portion 41 when a bias is applied. It is possible to reduce the electric field strength applied to the gate oxide film 21. Accordingly, the fixed charge 31 is relatively difficult to be formed at the interface of the gate oxide film 21 in the channel portion, so that desired channel characteristics can be easily realized.

<B-2. Manufacturing process>
The manufacturing method of the SiC-MOSFET 102 differs from the SiC-MOSFET 101 of the first embodiment in the formation process of the gate oxide film 21. The process up to the step of forming the gate oxide film 21 is the same as that of the SiC-MOSFET 101 shown in FIGS.

  2 and 3 as in the first embodiment, after that, as shown in FIG. 12, a gate oxide film 21 (first gate oxide film) is formed on the entire surface of the substrate by using, for example, a thermal oxidation method or a deposition method. Form. When the gate oxide film 21 on the JFET portion 41 reaches a desired film thickness, a silicon nitride film 26 is formed in that portion, and the gate oxide film 21 (second film) is formed on the surface of the well region 13 by using a thermal oxidation method. A gate oxide film) is formed. Thereafter, the silicon nitride film 26 is removed, and the SiC-MOSFET 102 shown in FIG. 11 is completed through the steps of forming the gate electrode 22, the interlayer insulating film 23, the source electrode 24, and the drain electrode as in the first embodiment.

  6 to 9 can be applied to the gate bias condition characteristics of the relative electric field strength of the gate oxide film 21 on the JFET central portion in the SiC-MOSFET 102. However, in the calculation of the electric field strength, the film thickness on the JFET portion 41 is used as the film thickness of the gate oxide film 21.

<B-3. Effect>
In SiC-MOSFET 102 that is the silicon carbide semiconductor device of the second embodiment, the gate oxide film on the surface of well region 13 is thicker than gate oxide film 21 on the surface of epitaxial layer 12. The thicker the gate oxide film 21, the weaker the electric field applied when applying the gate bias, and the smaller the amount of fixed charge 31 introduced, so that the fixed charge 31 is channeled while the fixed charge 31 is mainly introduced into the interface on the JFET portion 41. Can be suppressed.

  In the method for manufacturing SiC-MOSFET 102 of the second embodiment, in the step of forming gate oxide film 21, gate oxide film 21 on the surface of well region 13 is formed thicker than gate oxide film 21 on the surface of epitaxial layer 12. To do. The thicker the gate oxide film 21, the weaker the electric field applied when applying the gate bias, and the smaller the amount of fixed charge 31 introduced, so that the fixed charge 31 is channeled while the fixed charge 31 is mainly introduced into the interface on the JFET portion 41. Can be suppressed.

  The step of forming the gate oxide film 21 includes (d1) forming the first gate oxide film 21 from the surface of the well region 13 sandwiched between the source region 14 and the epitaxial layer 12 to the surface of the epitaxial layer 12. (D2) a step of forming a silicon nitride film 26 on a portion of the first gate oxide film 21 on the epitaxial layer 12; and (d3) a well region 13 of the first gate oxide film 21. Forming a second gate oxide film 21 on the upper portion by a thermal oxidation method. As a result, the gate oxide film 21 on the well region 13 where the source region 14 is not formed can be formed thicker than other portions.

<C. Embodiment 3>
<C-1. Configuration>
FIG. 13 shows a cross-sectional view of n-channel SiC-MOSFET 103 which is the silicon carbide semiconductor device of the third embodiment.

SiC-MOSFET 103 differs from SiC-MOSFET 102 of the second embodiment in that n-type channel doped region 16 is formed in the surface layer portion of well region 13. The impurity concentration of the channel dope region 16 exceeds the impurity concentration of the epitaxial layer 12 and is equal to or lower than the impurity concentration of the source region 14, for example, about 1 × 10 ¹³ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

<C-2. Manufacturing process>
The channel dope region 16 is formed, for example, by ion implantation using a mask when forming the well region 13. When the gate oxide film 21 is formed by the thermal oxidation method after the channel dope region 16 is formed, the channel dope region 16 and the source region 14 are oxidized at a higher concentration than the epitaxial layer 12, and the gates at these locations are increased. The oxide film 21 is formed thicker than on the JFET portion 41. Through the above manufacturing process, the thickness control of the gate oxide film 21 similar to the SiC-MOSFET 102 shown in FIG. 11 can be easily performed based on the channel dope region 16, and the SiC-MOSFET 103 shown in FIG. 13 is completed.

  Further, the channel doped region 16 is formed to be very shallow, for example, at a depth of several nm to several hundred nm, so that the channel doped region 16 is completely consumed in the process of forming the gate oxide film 21 by the thermal oxidation method. For example, the SiC-MOSFET 102 shown in FIG. 11 can be manufactured.

<C-3. Modification>
FIG. 14 is a cross-sectional view of SiC-MOSFET 104 according to a modification of the third embodiment. The SiC-MOSFET 104 is different from the SiC-MOSFET 103 shown in FIG. 13 in that the channel dope region 16 is formed not only on the surface layer of the well region 13 but also on a part of the epitaxial layer 12. According to this structure, the JFET resistance is further reduced. In association with this, a portion where the thickness of the gate oxide film 21 is increased is also formed in a part of the JFET portion 41, and the fixed charge density introduced into the portion by the gate bias is reduced. However, since the thickness of the gate oxide film 21 and the fixed charge density introduced by the gate bias in the central portion of the JFET where the electric field concentration is most concerned are the same as the SiC-MOSFET 103 shown in FIG. Have.

  In the first to third embodiments, the SiC-MOSFET has been described as an example of the silicon carbide semiconductor device. However, the semiconductor device is not limited to the MOSFET, and even if it is an insulated gate bipolar transistor, for example, the same effect as in this embodiment can be obtained.

<C-4. Effect>
In SiC-MOSFETs 103 and 104 which are silicon carbide semiconductor devices according to the third embodiment and the modification thereof, the surface layer of well region 13 sandwiched between source region 14 and epitaxial layer 12, or the surface layer and an epitaxial layer adjacent thereto The first conductivity type channel dope region 16 having a higher impurity concentration than that of the epitaxial layer 12 is formed in the 12 surface layers. When the SiC layer is oxidized by the thermal oxidation method, the higher the impurity concentration, the faster the oxidation rate. Therefore, the gate oxide film 21 on the well region 13 is formed thicker, and the amount of the fixed charge 31 introduced when applying the gate bias is reduced. Is possible.

  In the method of manufacturing SiC-MOSFETs 103 and 104 which are silicon carbide semiconductor devices according to the third embodiment and its modification, a plurality of well regions 13 are selectively formed on the surface layer of epitaxial layer 12 to form gate oxide film 21. (D1) A step of forming a channel doped layer 16 of the first conductivity type having an impurity concentration higher than that of the epitaxial layer 12 on the surface layer of the well region 13 or the surface layer of the surface layer and the epitaxial layer 12 adjacent thereto. And (d2) forming a gate oxide film 21 on the channel dope layer 16 and the epitaxial layer 12 by a thermal oxidation method. In the thermal oxidation process, the higher the impurity concentration, the faster the oxidation rate. Therefore, the gate oxide film 21 on the well region 13 is formed thicker than the other portions, and the amount of the fixed charge 31 introduced when applying the gate bias is reduced.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  11 SiC substrate, 12 epitaxial layer, 13 well region, 14 source region, 15 well contact region, 21 gate oxide film, 22 gate electrode, 23 interlayer insulating film, 24 source electrode, 25 drain electrode, 30 electric field relaxation region, 31 fixed Charge, 41 JFET, 100, 101, 102, 103, 104 SiC-MOSFET.

Claims (7)

A first conductivity type SiC substrate;
An epitaxial layer of a first conductivity type formed on the SiC substrate;
A well region of a second conductivity type selectively formed on a surface layer of the epitaxial layer;
A first conductivity type source region selectively formed on a surface layer of the well region;
A gate oxide film formed from the surface of the well region sandwiched between the source region and the epitaxial layer to the surface of the epitaxial layer;
A gate electrode formed on the gate oxide film,
Have a negative fixed charge at the interface of the gate oxide film and the epitaxial layer,
The density of the negative fixed charge in the gate oxide film on the surface of the well region is smaller than the density of the negative fixed charge in the gate oxide film on the surface of the epitaxial layer ,
Silicon carbide semiconductor device. The gate oxide on the surface of the well region is thicker than the gate oxide on the surface of the epitaxial layer;
The silicon carbide semiconductor device according to claim 1. A channel of the first conductivity type having a higher impurity concentration than the epitaxial layer, formed in the surface layer of the well region sandwiched between the source region and the epitaxial layer, or in the surface layer of the epitaxial layer adjacent to the surface layer. Further comprising a doped region;
The silicon carbide semiconductor device according to claim 1 or 2. (A) forming a first conductivity type epitaxial layer on a first conductivity type SiC substrate;
(B) selectively forming a second conductivity type well region on a surface layer of the epitaxial layer;
(C) a first conductivity type source region selectively formed on a surface layer of the well region;
(D) forming a gate oxide film from the surface of the well region sandwiched between the source region and the epitaxial layer to the surface of the epitaxial layer;
(E) forming a gate electrode on the gate oxide film;
(F) applying a positive voltage to the gate electrode to form a negative fixed charge at the interface between the gate oxide film and the epitaxial layer,
A method for manufacturing a silicon carbide semiconductor device. The step (d) is a step of forming the gate oxide film on the surface of the well region to be thicker than the gate oxide film on the surface of the epitaxial layer.
A method for manufacturing a silicon carbide semiconductor device according to claim 4. The step (d)
(D1) forming a first gate oxide film from the surface of the well region sandwiched between the source region and the epitaxial layer to the surface of the epitaxial layer;
(D2) forming a silicon nitride film on a portion of the first gate oxide film on the epitaxial layer;
(D3) including a step of forming a second gate oxide film by thermal oxidation on a portion of the first gate oxide film on the well region.
A method for manufacturing a silicon carbide semiconductor device according to claim 5. The step (d)
(D1) forming a first conductivity type channel dope layer having an impurity concentration higher than that of the epitaxial layer on the surface of the well region or on the surface of the epitaxial layer adjacent to the surface layer;
(D2) forming a gate oxide film on the channel dope layer and the epitaxial layer by a thermal oxidation method,
A method for manufacturing a silicon carbide semiconductor device according to claim 5.

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